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be518018 TK |
1 | /* |
2 | * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver | |
3 | * | |
4 | * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de> | |
5 | * | |
08c55e22 | 6 | * Current driver maintained by Ben Dooks and Simtec Electronics |
7 | * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org> | |
8 | * | |
be518018 TK |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/mmc/host.h> | |
18 | #include <linux/platform_device.h> | |
f87e6d00 | 19 | #include <linux/cpufreq.h> |
ec976d6e | 20 | #include <linux/gpio.h> |
be518018 TK |
21 | #include <linux/irq.h> |
22 | #include <linux/io.h> | |
23 | ||
7ad14f83 | 24 | #include <mach/dma.h> |
be518018 | 25 | |
a09e64fb RK |
26 | #include <mach/regs-sdi.h> |
27 | #include <mach/regs-gpio.h> | |
be518018 | 28 | |
e3bd9ec5 | 29 | #include <plat/mci.h> |
edb5a98e | 30 | |
be518018 TK |
31 | #include "s3cmci.h" |
32 | ||
33 | #define DRIVER_NAME "s3c-mci" | |
34 | ||
35 | enum dbg_channels { | |
36 | dbg_err = (1 << 0), | |
37 | dbg_debug = (1 << 1), | |
38 | dbg_info = (1 << 2), | |
39 | dbg_irq = (1 << 3), | |
40 | dbg_sg = (1 << 4), | |
41 | dbg_dma = (1 << 5), | |
42 | dbg_pio = (1 << 6), | |
43 | dbg_fail = (1 << 7), | |
44 | dbg_conf = (1 << 8), | |
45 | }; | |
46 | ||
9c2e7e40 | 47 | static const int dbgmap_err = dbg_fail; |
be518018 | 48 | static const int dbgmap_info = dbg_info | dbg_conf; |
9c2e7e40 | 49 | static const int dbgmap_debug = dbg_err | dbg_debug; |
be518018 TK |
50 | |
51 | #define dbg(host, channels, args...) \ | |
52 | do { \ | |
53 | if (dbgmap_err & channels) \ | |
54 | dev_err(&host->pdev->dev, args); \ | |
55 | else if (dbgmap_info & channels) \ | |
56 | dev_info(&host->pdev->dev, args); \ | |
57 | else if (dbgmap_debug & channels) \ | |
58 | dev_dbg(&host->pdev->dev, args); \ | |
59 | } while (0) | |
60 | ||
61 | #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1) | |
62 | ||
63 | static struct s3c2410_dma_client s3cmci_dma_client = { | |
64 | .name = "s3c-mci", | |
65 | }; | |
66 | ||
67 | static void finalize_request(struct s3cmci_host *host); | |
68 | static void s3cmci_send_request(struct mmc_host *mmc); | |
69 | static void s3cmci_reset(struct s3cmci_host *host); | |
70 | ||
71 | #ifdef CONFIG_MMC_DEBUG | |
72 | ||
73 | static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) | |
74 | { | |
75 | u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize; | |
76 | u32 datcon, datcnt, datsta, fsta, imask; | |
77 | ||
78 | con = readl(host->base + S3C2410_SDICON); | |
79 | pre = readl(host->base + S3C2410_SDIPRE); | |
80 | cmdarg = readl(host->base + S3C2410_SDICMDARG); | |
81 | cmdcon = readl(host->base + S3C2410_SDICMDCON); | |
82 | cmdsta = readl(host->base + S3C2410_SDICMDSTAT); | |
83 | r0 = readl(host->base + S3C2410_SDIRSP0); | |
84 | r1 = readl(host->base + S3C2410_SDIRSP1); | |
85 | r2 = readl(host->base + S3C2410_SDIRSP2); | |
86 | r3 = readl(host->base + S3C2410_SDIRSP3); | |
87 | timer = readl(host->base + S3C2410_SDITIMER); | |
88 | bsize = readl(host->base + S3C2410_SDIBSIZE); | |
89 | datcon = readl(host->base + S3C2410_SDIDCON); | |
90 | datcnt = readl(host->base + S3C2410_SDIDCNT); | |
91 | datsta = readl(host->base + S3C2410_SDIDSTA); | |
92 | fsta = readl(host->base + S3C2410_SDIFSTA); | |
93 | imask = readl(host->base + host->sdiimsk); | |
94 | ||
95 | dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n", | |
96 | prefix, con, pre, timer); | |
97 | ||
98 | dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n", | |
99 | prefix, cmdcon, cmdarg, cmdsta); | |
100 | ||
101 | dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]" | |
102 | " DSTA:[%08x] DCNT:[%08x]\n", | |
103 | prefix, datcon, fsta, datsta, datcnt); | |
104 | ||
105 | dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]" | |
106 | " R2:[%08x] R3:[%08x]\n", | |
107 | prefix, r0, r1, r2, r3); | |
108 | } | |
109 | ||
110 | static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd, | |
111 | int stop) | |
112 | { | |
113 | snprintf(host->dbgmsg_cmd, 300, | |
114 | "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u", | |
115 | host->ccnt, (stop ? " (STOP)" : ""), | |
116 | cmd->opcode, cmd->arg, cmd->flags, cmd->retries); | |
117 | ||
118 | if (cmd->data) { | |
119 | snprintf(host->dbgmsg_dat, 300, | |
120 | "#%u bsize:%u blocks:%u bytes:%u", | |
121 | host->dcnt, cmd->data->blksz, | |
122 | cmd->data->blocks, | |
123 | cmd->data->blocks * cmd->data->blksz); | |
124 | } else { | |
125 | host->dbgmsg_dat[0] = '\0'; | |
126 | } | |
127 | } | |
128 | ||
129 | static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd, | |
130 | int fail) | |
131 | { | |
132 | unsigned int dbglvl = fail ? dbg_fail : dbg_debug; | |
133 | ||
134 | if (!cmd) | |
135 | return; | |
136 | ||
137 | if (cmd->error == 0) { | |
138 | dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n", | |
139 | host->dbgmsg_cmd, cmd->resp[0]); | |
140 | } else { | |
141 | dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n", | |
142 | cmd->error, host->dbgmsg_cmd, host->status); | |
143 | } | |
144 | ||
145 | if (!cmd->data) | |
146 | return; | |
147 | ||
148 | if (cmd->data->error == 0) { | |
149 | dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat); | |
150 | } else { | |
151 | dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n", | |
152 | cmd->data->error, host->dbgmsg_dat, | |
153 | readl(host->base + S3C2410_SDIDCNT)); | |
154 | } | |
155 | } | |
156 | #else | |
157 | static void dbg_dumpcmd(struct s3cmci_host *host, | |
158 | struct mmc_command *cmd, int fail) { } | |
159 | ||
160 | static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd, | |
161 | int stop) { } | |
162 | ||
163 | static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { } | |
164 | ||
165 | #endif /* CONFIG_MMC_DEBUG */ | |
166 | ||
167 | static inline u32 enable_imask(struct s3cmci_host *host, u32 imask) | |
168 | { | |
169 | u32 newmask; | |
170 | ||
171 | newmask = readl(host->base + host->sdiimsk); | |
172 | newmask |= imask; | |
173 | ||
174 | writel(newmask, host->base + host->sdiimsk); | |
175 | ||
176 | return newmask; | |
177 | } | |
178 | ||
179 | static inline u32 disable_imask(struct s3cmci_host *host, u32 imask) | |
180 | { | |
181 | u32 newmask; | |
182 | ||
183 | newmask = readl(host->base + host->sdiimsk); | |
184 | newmask &= ~imask; | |
185 | ||
186 | writel(newmask, host->base + host->sdiimsk); | |
187 | ||
188 | return newmask; | |
189 | } | |
190 | ||
191 | static inline void clear_imask(struct s3cmci_host *host) | |
192 | { | |
193 | writel(0, host->base + host->sdiimsk); | |
194 | } | |
195 | ||
196 | static inline int get_data_buffer(struct s3cmci_host *host, | |
088a78af | 197 | u32 *bytes, u32 **pointer) |
be518018 TK |
198 | { |
199 | struct scatterlist *sg; | |
200 | ||
201 | if (host->pio_active == XFER_NONE) | |
202 | return -EINVAL; | |
203 | ||
204 | if ((!host->mrq) || (!host->mrq->data)) | |
205 | return -EINVAL; | |
206 | ||
207 | if (host->pio_sgptr >= host->mrq->data->sg_len) { | |
208 | dbg(host, dbg_debug, "no more buffers (%i/%i)\n", | |
209 | host->pio_sgptr, host->mrq->data->sg_len); | |
210 | return -EBUSY; | |
211 | } | |
212 | sg = &host->mrq->data->sg[host->pio_sgptr]; | |
213 | ||
088a78af | 214 | *bytes = sg->length; |
be518018 TK |
215 | *pointer = sg_virt(sg); |
216 | ||
217 | host->pio_sgptr++; | |
218 | ||
219 | dbg(host, dbg_sg, "new buffer (%i/%i)\n", | |
220 | host->pio_sgptr, host->mrq->data->sg_len); | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | static inline u32 fifo_count(struct s3cmci_host *host) | |
226 | { | |
227 | u32 fifostat = readl(host->base + S3C2410_SDIFSTA); | |
228 | ||
229 | fifostat &= S3C2410_SDIFSTA_COUNTMASK; | |
088a78af | 230 | return fifostat; |
be518018 TK |
231 | } |
232 | ||
233 | static inline u32 fifo_free(struct s3cmci_host *host) | |
234 | { | |
235 | u32 fifostat = readl(host->base + S3C2410_SDIFSTA); | |
236 | ||
237 | fifostat &= S3C2410_SDIFSTA_COUNTMASK; | |
088a78af | 238 | return 63 - fifostat; |
be518018 TK |
239 | } |
240 | ||
241 | static void do_pio_read(struct s3cmci_host *host) | |
242 | { | |
243 | int res; | |
244 | u32 fifo; | |
18280fff | 245 | u32 *ptr; |
088a78af | 246 | u32 fifo_words; |
be518018 TK |
247 | void __iomem *from_ptr; |
248 | ||
249 | /* write real prescaler to host, it might be set slow to fix */ | |
250 | writel(host->prescaler, host->base + S3C2410_SDIPRE); | |
251 | ||
252 | from_ptr = host->base + host->sdidata; | |
253 | ||
254 | while ((fifo = fifo_count(host))) { | |
088a78af CW |
255 | if (!host->pio_bytes) { |
256 | res = get_data_buffer(host, &host->pio_bytes, | |
be518018 TK |
257 | &host->pio_ptr); |
258 | if (res) { | |
259 | host->pio_active = XFER_NONE; | |
260 | host->complete_what = COMPLETION_FINALIZE; | |
261 | ||
262 | dbg(host, dbg_pio, "pio_read(): " | |
263 | "complete (no more data).\n"); | |
264 | return; | |
265 | } | |
266 | ||
267 | dbg(host, dbg_pio, | |
268 | "pio_read(): new target: [%i]@[%p]\n", | |
088a78af | 269 | host->pio_bytes, host->pio_ptr); |
be518018 TK |
270 | } |
271 | ||
272 | dbg(host, dbg_pio, | |
273 | "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n", | |
088a78af | 274 | fifo, host->pio_bytes, |
be518018 TK |
275 | readl(host->base + S3C2410_SDIDCNT)); |
276 | ||
088a78af CW |
277 | /* If we have reached the end of the block, we can |
278 | * read a word and get 1 to 3 bytes. If we in the | |
279 | * middle of the block, we have to read full words, | |
280 | * otherwise we will write garbage, so round down to | |
281 | * an even multiple of 4. */ | |
282 | if (fifo >= host->pio_bytes) | |
283 | fifo = host->pio_bytes; | |
284 | else | |
285 | fifo -= fifo & 3; | |
286 | ||
287 | host->pio_bytes -= fifo; | |
be518018 TK |
288 | host->pio_count += fifo; |
289 | ||
088a78af | 290 | fifo_words = fifo >> 2; |
18280fff | 291 | ptr = host->pio_ptr; |
088a78af | 292 | while (fifo_words--) |
18280fff | 293 | *ptr++ = readl(from_ptr); |
294 | host->pio_ptr = ptr; | |
088a78af CW |
295 | |
296 | if (fifo & 3) { | |
297 | u32 n = fifo & 3; | |
298 | u32 data = readl(from_ptr); | |
299 | u8 *p = (u8 *)host->pio_ptr; | |
300 | ||
301 | while (n--) { | |
302 | *p++ = data; | |
303 | data >>= 8; | |
304 | } | |
305 | } | |
be518018 TK |
306 | } |
307 | ||
088a78af CW |
308 | if (!host->pio_bytes) { |
309 | res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr); | |
be518018 TK |
310 | if (res) { |
311 | dbg(host, dbg_pio, | |
312 | "pio_read(): complete (no more buffers).\n"); | |
313 | host->pio_active = XFER_NONE; | |
314 | host->complete_what = COMPLETION_FINALIZE; | |
315 | ||
316 | return; | |
317 | } | |
318 | } | |
319 | ||
320 | enable_imask(host, | |
321 | S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST); | |
322 | } | |
323 | ||
324 | static void do_pio_write(struct s3cmci_host *host) | |
325 | { | |
326 | void __iomem *to_ptr; | |
327 | int res; | |
328 | u32 fifo; | |
18280fff | 329 | u32 *ptr; |
be518018 TK |
330 | |
331 | to_ptr = host->base + host->sdidata; | |
332 | ||
99424488 | 333 | while ((fifo = fifo_free(host)) > 3) { |
088a78af CW |
334 | if (!host->pio_bytes) { |
335 | res = get_data_buffer(host, &host->pio_bytes, | |
be518018 TK |
336 | &host->pio_ptr); |
337 | if (res) { | |
338 | dbg(host, dbg_pio, | |
339 | "pio_write(): complete (no more data).\n"); | |
340 | host->pio_active = XFER_NONE; | |
341 | ||
342 | return; | |
343 | } | |
344 | ||
345 | dbg(host, dbg_pio, | |
346 | "pio_write(): new source: [%i]@[%p]\n", | |
088a78af | 347 | host->pio_bytes, host->pio_ptr); |
be518018 TK |
348 | |
349 | } | |
350 | ||
088a78af CW |
351 | /* If we have reached the end of the block, we have to |
352 | * write exactly the remaining number of bytes. If we | |
353 | * in the middle of the block, we have to write full | |
354 | * words, so round down to an even multiple of 4. */ | |
355 | if (fifo >= host->pio_bytes) | |
356 | fifo = host->pio_bytes; | |
357 | else | |
358 | fifo -= fifo & 3; | |
be518018 | 359 | |
088a78af | 360 | host->pio_bytes -= fifo; |
be518018 TK |
361 | host->pio_count += fifo; |
362 | ||
088a78af | 363 | fifo = (fifo + 3) >> 2; |
18280fff | 364 | ptr = host->pio_ptr; |
be518018 | 365 | while (fifo--) |
18280fff | 366 | writel(*ptr++, to_ptr); |
367 | host->pio_ptr = ptr; | |
be518018 TK |
368 | } |
369 | ||
370 | enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); | |
371 | } | |
372 | ||
373 | static void pio_tasklet(unsigned long data) | |
374 | { | |
375 | struct s3cmci_host *host = (struct s3cmci_host *) data; | |
376 | ||
377 | ||
d643b5f7 RM |
378 | disable_irq(host->irq); |
379 | ||
be518018 TK |
380 | if (host->pio_active == XFER_WRITE) |
381 | do_pio_write(host); | |
382 | ||
383 | if (host->pio_active == XFER_READ) | |
384 | do_pio_read(host); | |
385 | ||
386 | if (host->complete_what == COMPLETION_FINALIZE) { | |
387 | clear_imask(host); | |
388 | if (host->pio_active != XFER_NONE) { | |
389 | dbg(host, dbg_err, "unfinished %s " | |
088a78af | 390 | "- pio_count:[%u] pio_bytes:[%u]\n", |
be518018 | 391 | (host->pio_active == XFER_READ) ? "read" : "write", |
088a78af | 392 | host->pio_count, host->pio_bytes); |
be518018 | 393 | |
7c14450e BD |
394 | if (host->mrq->data) |
395 | host->mrq->data->error = -EINVAL; | |
be518018 TK |
396 | } |
397 | ||
be518018 | 398 | finalize_request(host); |
d643b5f7 RM |
399 | } else |
400 | enable_irq(host->irq); | |
be518018 TK |
401 | } |
402 | ||
403 | /* | |
404 | * ISR for SDI Interface IRQ | |
405 | * Communication between driver and ISR works as follows: | |
406 | * host->mrq points to current request | |
407 | * host->complete_what Indicates when the request is considered done | |
408 | * COMPLETION_CMDSENT when the command was sent | |
409 | * COMPLETION_RSPFIN when a response was received | |
410 | * COMPLETION_XFERFINISH when the data transfer is finished | |
411 | * COMPLETION_XFERFINISH_RSPFIN both of the above. | |
412 | * host->complete_request is the completion-object the driver waits for | |
413 | * | |
414 | * 1) Driver sets up host->mrq and host->complete_what | |
415 | * 2) Driver prepares the transfer | |
416 | * 3) Driver enables interrupts | |
417 | * 4) Driver starts transfer | |
418 | * 5) Driver waits for host->complete_rquest | |
419 | * 6) ISR checks for request status (errors and success) | |
420 | * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error | |
421 | * 7) ISR completes host->complete_request | |
422 | * 8) ISR disables interrupts | |
423 | * 9) Driver wakes up and takes care of the request | |
424 | * | |
425 | * Note: "->error"-fields are expected to be set to 0 before the request | |
426 | * was issued by mmc.c - therefore they are only set, when an error | |
427 | * contition comes up | |
428 | */ | |
429 | ||
430 | static irqreturn_t s3cmci_irq(int irq, void *dev_id) | |
431 | { | |
432 | struct s3cmci_host *host = dev_id; | |
433 | struct mmc_command *cmd; | |
434 | u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk; | |
435 | u32 mci_cclear, mci_dclear; | |
436 | unsigned long iflags; | |
437 | ||
438 | spin_lock_irqsave(&host->complete_lock, iflags); | |
439 | ||
440 | mci_csta = readl(host->base + S3C2410_SDICMDSTAT); | |
441 | mci_dsta = readl(host->base + S3C2410_SDIDSTA); | |
442 | mci_dcnt = readl(host->base + S3C2410_SDIDCNT); | |
443 | mci_fsta = readl(host->base + S3C2410_SDIFSTA); | |
444 | mci_imsk = readl(host->base + host->sdiimsk); | |
445 | mci_cclear = 0; | |
446 | mci_dclear = 0; | |
447 | ||
448 | if ((host->complete_what == COMPLETION_NONE) || | |
449 | (host->complete_what == COMPLETION_FINALIZE)) { | |
450 | host->status = "nothing to complete"; | |
451 | clear_imask(host); | |
452 | goto irq_out; | |
453 | } | |
454 | ||
455 | if (!host->mrq) { | |
456 | host->status = "no active mrq"; | |
457 | clear_imask(host); | |
458 | goto irq_out; | |
459 | } | |
460 | ||
461 | cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd; | |
462 | ||
463 | if (!cmd) { | |
464 | host->status = "no active cmd"; | |
465 | clear_imask(host); | |
466 | goto irq_out; | |
467 | } | |
468 | ||
469 | if (!host->dodma) { | |
470 | if ((host->pio_active == XFER_WRITE) && | |
471 | (mci_fsta & S3C2410_SDIFSTA_TFDET)) { | |
472 | ||
473 | disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); | |
474 | tasklet_schedule(&host->pio_tasklet); | |
475 | host->status = "pio tx"; | |
476 | } | |
477 | ||
478 | if ((host->pio_active == XFER_READ) && | |
479 | (mci_fsta & S3C2410_SDIFSTA_RFDET)) { | |
480 | ||
481 | disable_imask(host, | |
482 | S3C2410_SDIIMSK_RXFIFOHALF | | |
483 | S3C2410_SDIIMSK_RXFIFOLAST); | |
484 | ||
485 | tasklet_schedule(&host->pio_tasklet); | |
486 | host->status = "pio rx"; | |
487 | } | |
488 | } | |
489 | ||
490 | if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) { | |
ff8c804f | 491 | dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n"); |
be518018 TK |
492 | cmd->error = -ETIMEDOUT; |
493 | host->status = "error: command timeout"; | |
494 | goto fail_transfer; | |
495 | } | |
496 | ||
497 | if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) { | |
498 | if (host->complete_what == COMPLETION_CMDSENT) { | |
499 | host->status = "ok: command sent"; | |
500 | goto close_transfer; | |
501 | } | |
502 | ||
503 | mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT; | |
504 | } | |
505 | ||
506 | if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) { | |
507 | if (cmd->flags & MMC_RSP_CRC) { | |
679f0f8a HW |
508 | if (host->mrq->cmd->flags & MMC_RSP_136) { |
509 | dbg(host, dbg_irq, | |
510 | "fixup: ignore CRC fail with long rsp\n"); | |
511 | } else { | |
512 | /* note, we used to fail the transfer | |
513 | * here, but it seems that this is just | |
514 | * the hardware getting it wrong. | |
515 | * | |
516 | * cmd->error = -EILSEQ; | |
517 | * host->status = "error: bad command crc"; | |
518 | * goto fail_transfer; | |
519 | */ | |
520 | } | |
be518018 TK |
521 | } |
522 | ||
523 | mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL; | |
524 | } | |
525 | ||
526 | if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) { | |
527 | if (host->complete_what == COMPLETION_RSPFIN) { | |
528 | host->status = "ok: command response received"; | |
529 | goto close_transfer; | |
530 | } | |
531 | ||
532 | if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN) | |
533 | host->complete_what = COMPLETION_XFERFINISH; | |
534 | ||
535 | mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN; | |
536 | } | |
537 | ||
538 | /* errors handled after this point are only relevant | |
539 | when a data transfer is in progress */ | |
540 | ||
541 | if (!cmd->data) | |
542 | goto clear_status_bits; | |
543 | ||
544 | /* Check for FIFO failure */ | |
545 | if (host->is2440) { | |
546 | if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) { | |
ff8c804f | 547 | dbg(host, dbg_err, "FIFO failure\n"); |
be518018 TK |
548 | host->mrq->data->error = -EILSEQ; |
549 | host->status = "error: 2440 fifo failure"; | |
550 | goto fail_transfer; | |
551 | } | |
552 | } else { | |
553 | if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) { | |
ff8c804f | 554 | dbg(host, dbg_err, "FIFO failure\n"); |
be518018 TK |
555 | cmd->data->error = -EILSEQ; |
556 | host->status = "error: fifo failure"; | |
557 | goto fail_transfer; | |
558 | } | |
559 | } | |
560 | ||
561 | if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) { | |
ff8c804f | 562 | dbg(host, dbg_err, "bad data crc (outgoing)\n"); |
be518018 TK |
563 | cmd->data->error = -EILSEQ; |
564 | host->status = "error: bad data crc (outgoing)"; | |
565 | goto fail_transfer; | |
566 | } | |
567 | ||
568 | if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) { | |
ff8c804f | 569 | dbg(host, dbg_err, "bad data crc (incoming)\n"); |
be518018 TK |
570 | cmd->data->error = -EILSEQ; |
571 | host->status = "error: bad data crc (incoming)"; | |
572 | goto fail_transfer; | |
573 | } | |
574 | ||
575 | if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) { | |
ff8c804f | 576 | dbg(host, dbg_err, "data timeout\n"); |
be518018 TK |
577 | cmd->data->error = -ETIMEDOUT; |
578 | host->status = "error: data timeout"; | |
579 | goto fail_transfer; | |
580 | } | |
581 | ||
582 | if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) { | |
583 | if (host->complete_what == COMPLETION_XFERFINISH) { | |
584 | host->status = "ok: data transfer completed"; | |
585 | goto close_transfer; | |
586 | } | |
587 | ||
588 | if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN) | |
589 | host->complete_what = COMPLETION_RSPFIN; | |
590 | ||
591 | mci_dclear |= S3C2410_SDIDSTA_XFERFINISH; | |
592 | } | |
593 | ||
594 | clear_status_bits: | |
595 | writel(mci_cclear, host->base + S3C2410_SDICMDSTAT); | |
596 | writel(mci_dclear, host->base + S3C2410_SDIDSTA); | |
597 | ||
598 | goto irq_out; | |
599 | ||
600 | fail_transfer: | |
601 | host->pio_active = XFER_NONE; | |
602 | ||
603 | close_transfer: | |
604 | host->complete_what = COMPLETION_FINALIZE; | |
605 | ||
606 | clear_imask(host); | |
607 | tasklet_schedule(&host->pio_tasklet); | |
608 | ||
609 | goto irq_out; | |
610 | ||
611 | irq_out: | |
612 | dbg(host, dbg_irq, | |
613 | "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n", | |
614 | mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status); | |
615 | ||
616 | spin_unlock_irqrestore(&host->complete_lock, iflags); | |
617 | return IRQ_HANDLED; | |
618 | ||
619 | } | |
620 | ||
621 | /* | |
622 | * ISR for the CardDetect Pin | |
623 | */ | |
624 | ||
625 | static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id) | |
626 | { | |
627 | struct s3cmci_host *host = (struct s3cmci_host *)dev_id; | |
628 | ||
629 | dbg(host, dbg_irq, "card detect\n"); | |
630 | ||
2de5f79d | 631 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); |
be518018 TK |
632 | |
633 | return IRQ_HANDLED; | |
634 | } | |
635 | ||
5d304400 BD |
636 | static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch, |
637 | void *buf_id, int size, | |
638 | enum s3c2410_dma_buffresult result) | |
be518018 TK |
639 | { |
640 | struct s3cmci_host *host = buf_id; | |
641 | unsigned long iflags; | |
642 | u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt; | |
643 | ||
644 | mci_csta = readl(host->base + S3C2410_SDICMDSTAT); | |
645 | mci_dsta = readl(host->base + S3C2410_SDIDSTA); | |
646 | mci_fsta = readl(host->base + S3C2410_SDIFSTA); | |
647 | mci_dcnt = readl(host->base + S3C2410_SDIDCNT); | |
648 | ||
649 | BUG_ON(!host->mrq); | |
650 | BUG_ON(!host->mrq->data); | |
651 | BUG_ON(!host->dmatogo); | |
652 | ||
653 | spin_lock_irqsave(&host->complete_lock, iflags); | |
654 | ||
655 | if (result != S3C2410_RES_OK) { | |
656 | dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x " | |
657 | "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n", | |
658 | mci_csta, mci_dsta, mci_fsta, | |
659 | mci_dcnt, result, host->dmatogo); | |
660 | ||
661 | goto fail_request; | |
662 | } | |
663 | ||
664 | host->dmatogo--; | |
665 | if (host->dmatogo) { | |
666 | dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] " | |
667 | "DCNT:[%08x] toGo:%u\n", | |
668 | size, mci_dsta, mci_dcnt, host->dmatogo); | |
669 | ||
670 | goto out; | |
671 | } | |
672 | ||
673 | dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n", | |
674 | size, mci_dsta, mci_dcnt); | |
675 | ||
676 | host->complete_what = COMPLETION_FINALIZE; | |
677 | ||
678 | out: | |
679 | tasklet_schedule(&host->pio_tasklet); | |
680 | spin_unlock_irqrestore(&host->complete_lock, iflags); | |
681 | return; | |
682 | ||
be518018 TK |
683 | fail_request: |
684 | host->mrq->data->error = -EINVAL; | |
685 | host->complete_what = COMPLETION_FINALIZE; | |
686 | writel(0, host->base + host->sdiimsk); | |
687 | goto out; | |
688 | ||
689 | } | |
690 | ||
691 | static void finalize_request(struct s3cmci_host *host) | |
692 | { | |
693 | struct mmc_request *mrq = host->mrq; | |
694 | struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; | |
695 | int debug_as_failure = 0; | |
696 | ||
697 | if (host->complete_what != COMPLETION_FINALIZE) | |
698 | return; | |
699 | ||
700 | if (!mrq) | |
701 | return; | |
702 | ||
703 | if (cmd->data && (cmd->error == 0) && | |
704 | (cmd->data->error == 0)) { | |
705 | if (host->dodma && (!host->dma_complete)) { | |
706 | dbg(host, dbg_dma, "DMA Missing!\n"); | |
707 | return; | |
708 | } | |
709 | } | |
710 | ||
711 | /* Read response from controller. */ | |
712 | cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0); | |
713 | cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1); | |
714 | cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2); | |
715 | cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3); | |
716 | ||
717 | writel(host->prescaler, host->base + S3C2410_SDIPRE); | |
718 | ||
719 | if (cmd->error) | |
720 | debug_as_failure = 1; | |
721 | ||
722 | if (cmd->data && cmd->data->error) | |
723 | debug_as_failure = 1; | |
724 | ||
725 | dbg_dumpcmd(host, cmd, debug_as_failure); | |
726 | ||
727 | /* Cleanup controller */ | |
728 | writel(0, host->base + S3C2410_SDICMDARG); | |
bdbc9c3a | 729 | writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON); |
be518018 TK |
730 | writel(0, host->base + S3C2410_SDICMDCON); |
731 | writel(0, host->base + host->sdiimsk); | |
732 | ||
733 | if (cmd->data && cmd->error) | |
734 | cmd->data->error = cmd->error; | |
735 | ||
736 | if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) { | |
737 | host->cmd_is_stop = 1; | |
738 | s3cmci_send_request(host->mmc); | |
739 | return; | |
740 | } | |
741 | ||
742 | /* If we have no data transfer we are finished here */ | |
743 | if (!mrq->data) | |
744 | goto request_done; | |
745 | ||
746 | /* Calulate the amout of bytes transfer if there was no error */ | |
747 | if (mrq->data->error == 0) { | |
748 | mrq->data->bytes_xfered = | |
749 | (mrq->data->blocks * mrq->data->blksz); | |
750 | } else { | |
751 | mrq->data->bytes_xfered = 0; | |
752 | } | |
753 | ||
754 | /* If we had an error while transfering data we flush the | |
755 | * DMA channel and the fifo to clear out any garbage. */ | |
756 | if (mrq->data->error != 0) { | |
757 | if (host->dodma) | |
758 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); | |
759 | ||
760 | if (host->is2440) { | |
761 | /* Clear failure register and reset fifo. */ | |
762 | writel(S3C2440_SDIFSTA_FIFORESET | | |
763 | S3C2440_SDIFSTA_FIFOFAIL, | |
764 | host->base + S3C2410_SDIFSTA); | |
765 | } else { | |
766 | u32 mci_con; | |
767 | ||
768 | /* reset fifo */ | |
769 | mci_con = readl(host->base + S3C2410_SDICON); | |
770 | mci_con |= S3C2410_SDICON_FIFORESET; | |
771 | ||
772 | writel(mci_con, host->base + S3C2410_SDICON); | |
773 | } | |
774 | } | |
775 | ||
776 | request_done: | |
777 | host->complete_what = COMPLETION_NONE; | |
778 | host->mrq = NULL; | |
779 | mmc_request_done(host->mmc, mrq); | |
780 | } | |
781 | ||
5d304400 BD |
782 | static void s3cmci_dma_setup(struct s3cmci_host *host, |
783 | enum s3c2410_dmasrc source) | |
be518018 TK |
784 | { |
785 | static enum s3c2410_dmasrc last_source = -1; | |
786 | static int setup_ok; | |
787 | ||
788 | if (last_source == source) | |
789 | return; | |
790 | ||
791 | last_source = source; | |
792 | ||
8970ef47 | 793 | s3c2410_dma_devconfig(host->dma, source, |
be518018 TK |
794 | host->mem->start + host->sdidata); |
795 | ||
796 | if (!setup_ok) { | |
fe9db6cb | 797 | s3c2410_dma_config(host->dma, 4); |
be518018 TK |
798 | s3c2410_dma_set_buffdone_fn(host->dma, |
799 | s3cmci_dma_done_callback); | |
800 | s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART); | |
801 | setup_ok = 1; | |
802 | } | |
803 | } | |
804 | ||
805 | static void s3cmci_send_command(struct s3cmci_host *host, | |
806 | struct mmc_command *cmd) | |
807 | { | |
808 | u32 ccon, imsk; | |
809 | ||
810 | imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT | | |
811 | S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT | | |
812 | S3C2410_SDIIMSK_RESPONSECRC; | |
813 | ||
814 | enable_imask(host, imsk); | |
815 | ||
816 | if (cmd->data) | |
817 | host->complete_what = COMPLETION_XFERFINISH_RSPFIN; | |
818 | else if (cmd->flags & MMC_RSP_PRESENT) | |
819 | host->complete_what = COMPLETION_RSPFIN; | |
820 | else | |
821 | host->complete_what = COMPLETION_CMDSENT; | |
822 | ||
823 | writel(cmd->arg, host->base + S3C2410_SDICMDARG); | |
824 | ||
825 | ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX; | |
826 | ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART; | |
827 | ||
828 | if (cmd->flags & MMC_RSP_PRESENT) | |
829 | ccon |= S3C2410_SDICMDCON_WAITRSP; | |
830 | ||
831 | if (cmd->flags & MMC_RSP_136) | |
832 | ccon |= S3C2410_SDICMDCON_LONGRSP; | |
833 | ||
834 | writel(ccon, host->base + S3C2410_SDICMDCON); | |
835 | } | |
836 | ||
837 | static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data) | |
838 | { | |
839 | u32 dcon, imsk, stoptries = 3; | |
840 | ||
841 | /* write DCON register */ | |
842 | ||
843 | if (!data) { | |
844 | writel(0, host->base + S3C2410_SDIDCON); | |
845 | return 0; | |
846 | } | |
847 | ||
7e9c7b64 BD |
848 | if ((data->blksz & 3) != 0) { |
849 | /* We cannot deal with unaligned blocks with more than | |
850 | * one block being transfered. */ | |
851 | ||
088a78af CW |
852 | if (data->blocks > 1) { |
853 | pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz); | |
7e9c7b64 | 854 | return -EINVAL; |
088a78af | 855 | } |
7e9c7b64 BD |
856 | } |
857 | ||
be518018 TK |
858 | while (readl(host->base + S3C2410_SDIDSTA) & |
859 | (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) { | |
860 | ||
861 | dbg(host, dbg_err, | |
862 | "mci_setup_data() transfer stillin progress.\n"); | |
863 | ||
bdbc9c3a | 864 | writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON); |
be518018 TK |
865 | s3cmci_reset(host); |
866 | ||
867 | if ((stoptries--) == 0) { | |
868 | dbg_dumpregs(host, "DRF"); | |
869 | return -EINVAL; | |
870 | } | |
871 | } | |
872 | ||
873 | dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK; | |
874 | ||
875 | if (host->dodma) | |
876 | dcon |= S3C2410_SDIDCON_DMAEN; | |
877 | ||
878 | if (host->bus_width == MMC_BUS_WIDTH_4) | |
879 | dcon |= S3C2410_SDIDCON_WIDEBUS; | |
880 | ||
881 | if (!(data->flags & MMC_DATA_STREAM)) | |
882 | dcon |= S3C2410_SDIDCON_BLOCKMODE; | |
883 | ||
884 | if (data->flags & MMC_DATA_WRITE) { | |
885 | dcon |= S3C2410_SDIDCON_TXAFTERRESP; | |
886 | dcon |= S3C2410_SDIDCON_XFER_TXSTART; | |
887 | } | |
888 | ||
889 | if (data->flags & MMC_DATA_READ) { | |
890 | dcon |= S3C2410_SDIDCON_RXAFTERCMD; | |
891 | dcon |= S3C2410_SDIDCON_XFER_RXSTART; | |
892 | } | |
893 | ||
894 | if (host->is2440) { | |
895 | dcon |= S3C2440_SDIDCON_DS_WORD; | |
896 | dcon |= S3C2440_SDIDCON_DATSTART; | |
897 | } | |
898 | ||
899 | writel(dcon, host->base + S3C2410_SDIDCON); | |
900 | ||
901 | /* write BSIZE register */ | |
902 | ||
903 | writel(data->blksz, host->base + S3C2410_SDIBSIZE); | |
904 | ||
905 | /* add to IMASK register */ | |
906 | imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC | | |
907 | S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH; | |
908 | ||
909 | enable_imask(host, imsk); | |
910 | ||
911 | /* write TIMER register */ | |
912 | ||
913 | if (host->is2440) { | |
914 | writel(0x007FFFFF, host->base + S3C2410_SDITIMER); | |
915 | } else { | |
916 | writel(0x0000FFFF, host->base + S3C2410_SDITIMER); | |
917 | ||
918 | /* FIX: set slow clock to prevent timeouts on read */ | |
919 | if (data->flags & MMC_DATA_READ) | |
920 | writel(0xFF, host->base + S3C2410_SDIPRE); | |
921 | } | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
926 | #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ) | |
927 | ||
928 | static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data) | |
929 | { | |
930 | int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; | |
931 | ||
932 | BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR); | |
933 | ||
934 | host->pio_sgptr = 0; | |
088a78af | 935 | host->pio_bytes = 0; |
be518018 TK |
936 | host->pio_count = 0; |
937 | host->pio_active = rw ? XFER_WRITE : XFER_READ; | |
938 | ||
939 | if (rw) { | |
940 | do_pio_write(host); | |
941 | enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); | |
942 | } else { | |
943 | enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF | |
944 | | S3C2410_SDIIMSK_RXFIFOLAST); | |
945 | } | |
946 | ||
947 | return 0; | |
948 | } | |
949 | ||
950 | static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data) | |
951 | { | |
952 | int dma_len, i; | |
953 | int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; | |
954 | ||
955 | BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR); | |
956 | ||
957 | s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW); | |
958 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); | |
959 | ||
960 | dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
961 | (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
962 | ||
963 | if (dma_len == 0) | |
964 | return -ENOMEM; | |
965 | ||
966 | host->dma_complete = 0; | |
967 | host->dmatogo = dma_len; | |
968 | ||
969 | for (i = 0; i < dma_len; i++) { | |
970 | int res; | |
971 | ||
972 | dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i, | |
973 | sg_dma_address(&data->sg[i]), | |
974 | sg_dma_len(&data->sg[i])); | |
975 | ||
976 | res = s3c2410_dma_enqueue(host->dma, (void *) host, | |
977 | sg_dma_address(&data->sg[i]), | |
978 | sg_dma_len(&data->sg[i])); | |
979 | ||
980 | if (res) { | |
981 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); | |
982 | return -EBUSY; | |
983 | } | |
984 | } | |
985 | ||
986 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START); | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
991 | static void s3cmci_send_request(struct mmc_host *mmc) | |
992 | { | |
993 | struct s3cmci_host *host = mmc_priv(mmc); | |
994 | struct mmc_request *mrq = host->mrq; | |
995 | struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; | |
996 | ||
997 | host->ccnt++; | |
998 | prepare_dbgmsg(host, cmd, host->cmd_is_stop); | |
999 | ||
1000 | /* Clear command, data and fifo status registers | |
1001 | Fifo clear only necessary on 2440, but doesn't hurt on 2410 | |
1002 | */ | |
1003 | writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT); | |
1004 | writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA); | |
1005 | writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA); | |
1006 | ||
1007 | if (cmd->data) { | |
1008 | int res = s3cmci_setup_data(host, cmd->data); | |
1009 | ||
1010 | host->dcnt++; | |
1011 | ||
1012 | if (res) { | |
ff8c804f BD |
1013 | dbg(host, dbg_err, "setup data error %d\n", res); |
1014 | cmd->error = res; | |
1015 | cmd->data->error = res; | |
be518018 TK |
1016 | |
1017 | mmc_request_done(mmc, mrq); | |
1018 | return; | |
1019 | } | |
1020 | ||
1021 | if (host->dodma) | |
1022 | res = s3cmci_prepare_dma(host, cmd->data); | |
1023 | else | |
1024 | res = s3cmci_prepare_pio(host, cmd->data); | |
1025 | ||
1026 | if (res) { | |
ff8c804f | 1027 | dbg(host, dbg_err, "data prepare error %d\n", res); |
be518018 TK |
1028 | cmd->error = res; |
1029 | cmd->data->error = res; | |
1030 | ||
1031 | mmc_request_done(mmc, mrq); | |
1032 | return; | |
1033 | } | |
1034 | } | |
1035 | ||
1036 | /* Send command */ | |
1037 | s3cmci_send_command(host, cmd); | |
1038 | ||
1039 | /* Enable Interrupt */ | |
1040 | enable_irq(host->irq); | |
1041 | } | |
1042 | ||
87dd9803 | 1043 | static int s3cmci_card_present(struct mmc_host *mmc) |
50a84570 | 1044 | { |
87dd9803 | 1045 | struct s3cmci_host *host = mmc_priv(mmc); |
50a84570 BD |
1046 | struct s3c24xx_mci_pdata *pdata = host->pdata; |
1047 | int ret; | |
1048 | ||
1049 | if (pdata->gpio_detect == 0) | |
1050 | return -ENOSYS; | |
1051 | ||
1052 | ret = s3c2410_gpio_getpin(pdata->gpio_detect) ? 0 : 1; | |
1053 | return ret ^ pdata->detect_invert; | |
1054 | } | |
1055 | ||
be518018 TK |
1056 | static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
1057 | { | |
1058 | struct s3cmci_host *host = mmc_priv(mmc); | |
1059 | ||
1060 | host->status = "mmc request"; | |
1061 | host->cmd_is_stop = 0; | |
1062 | host->mrq = mrq; | |
1063 | ||
87dd9803 | 1064 | if (s3cmci_card_present(mmc) == 0) { |
50a84570 BD |
1065 | dbg(host, dbg_err, "%s: no medium present\n", __func__); |
1066 | host->mrq->cmd->error = -ENOMEDIUM; | |
1067 | mmc_request_done(mmc, mrq); | |
1068 | } else | |
1069 | s3cmci_send_request(mmc); | |
be518018 TK |
1070 | } |
1071 | ||
f87e6d00 | 1072 | static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios) |
1073 | { | |
1074 | u32 mci_psc; | |
1075 | ||
1076 | /* Set clock */ | |
1077 | for (mci_psc = 0; mci_psc < 255; mci_psc++) { | |
1078 | host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1)); | |
1079 | ||
1080 | if (host->real_rate <= ios->clock) | |
1081 | break; | |
1082 | } | |
1083 | ||
1084 | if (mci_psc > 255) | |
1085 | mci_psc = 255; | |
1086 | ||
1087 | host->prescaler = mci_psc; | |
1088 | writel(host->prescaler, host->base + S3C2410_SDIPRE); | |
1089 | ||
1090 | /* If requested clock is 0, real_rate will be 0, too */ | |
1091 | if (ios->clock == 0) | |
1092 | host->real_rate = 0; | |
1093 | } | |
1094 | ||
be518018 TK |
1095 | static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1096 | { | |
1097 | struct s3cmci_host *host = mmc_priv(mmc); | |
f87e6d00 | 1098 | u32 mci_con; |
be518018 TK |
1099 | |
1100 | /* Set the power state */ | |
1101 | ||
1102 | mci_con = readl(host->base + S3C2410_SDICON); | |
1103 | ||
1104 | switch (ios->power_mode) { | |
1105 | case MMC_POWER_ON: | |
1106 | case MMC_POWER_UP: | |
1107 | s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_SDCLK); | |
1108 | s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2410_GPE6_SDCMD); | |
1109 | s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2410_GPE7_SDDAT0); | |
1110 | s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); | |
1111 | s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_SDDAT2); | |
1112 | s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_SDDAT3); | |
1113 | ||
edb5a98e BD |
1114 | if (host->pdata->set_power) |
1115 | host->pdata->set_power(ios->power_mode, ios->vdd); | |
1116 | ||
be518018 TK |
1117 | if (!host->is2440) |
1118 | mci_con |= S3C2410_SDICON_FIFORESET; | |
1119 | ||
1120 | break; | |
1121 | ||
1122 | case MMC_POWER_OFF: | |
1123 | default: | |
1124 | s3c2410_gpio_setpin(S3C2410_GPE5, 0); | |
ec976d6e | 1125 | s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPIO_OUTPUT); |
be518018 TK |
1126 | |
1127 | if (host->is2440) | |
1128 | mci_con |= S3C2440_SDICON_SDRESET; | |
1129 | ||
edb5a98e BD |
1130 | if (host->pdata->set_power) |
1131 | host->pdata->set_power(ios->power_mode, ios->vdd); | |
1132 | ||
be518018 TK |
1133 | break; |
1134 | } | |
1135 | ||
f87e6d00 | 1136 | s3cmci_set_clk(host, ios); |
be518018 TK |
1137 | |
1138 | /* Set CLOCK_ENABLE */ | |
1139 | if (ios->clock) | |
1140 | mci_con |= S3C2410_SDICON_CLOCKTYPE; | |
1141 | else | |
1142 | mci_con &= ~S3C2410_SDICON_CLOCKTYPE; | |
1143 | ||
1144 | writel(mci_con, host->base + S3C2410_SDICON); | |
1145 | ||
1146 | if ((ios->power_mode == MMC_POWER_ON) || | |
1147 | (ios->power_mode == MMC_POWER_UP)) { | |
1148 | dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n", | |
1149 | host->real_rate/1000, ios->clock/1000); | |
1150 | } else { | |
1151 | dbg(host, dbg_conf, "powered down.\n"); | |
1152 | } | |
1153 | ||
1154 | host->bus_width = ios->bus_width; | |
1155 | } | |
1156 | ||
1157 | static void s3cmci_reset(struct s3cmci_host *host) | |
1158 | { | |
1159 | u32 con = readl(host->base + S3C2410_SDICON); | |
1160 | ||
1161 | con |= S3C2440_SDICON_SDRESET; | |
1162 | writel(con, host->base + S3C2410_SDICON); | |
1163 | } | |
1164 | ||
edb5a98e BD |
1165 | static int s3cmci_get_ro(struct mmc_host *mmc) |
1166 | { | |
1167 | struct s3cmci_host *host = mmc_priv(mmc); | |
cf0984c8 BD |
1168 | struct s3c24xx_mci_pdata *pdata = host->pdata; |
1169 | int ret; | |
edb5a98e | 1170 | |
cf0984c8 | 1171 | if (pdata->gpio_wprotect == 0) |
edb5a98e BD |
1172 | return 0; |
1173 | ||
cf0984c8 BD |
1174 | ret = s3c2410_gpio_getpin(pdata->gpio_wprotect); |
1175 | ||
1176 | if (pdata->wprotect_invert) | |
1177 | ret = !ret; | |
1178 | ||
1179 | return ret; | |
edb5a98e BD |
1180 | } |
1181 | ||
be518018 TK |
1182 | static struct mmc_host_ops s3cmci_ops = { |
1183 | .request = s3cmci_request, | |
1184 | .set_ios = s3cmci_set_ios, | |
edb5a98e | 1185 | .get_ro = s3cmci_get_ro, |
87dd9803 | 1186 | .get_cd = s3cmci_card_present, |
edb5a98e BD |
1187 | }; |
1188 | ||
1189 | static struct s3c24xx_mci_pdata s3cmci_def_pdata = { | |
1190 | /* This is currently here to avoid a number of if (host->pdata) | |
1191 | * checks. Any zero fields to ensure reaonable defaults are picked. */ | |
be518018 TK |
1192 | }; |
1193 | ||
f87e6d00 | 1194 | #ifdef CONFIG_CPU_FREQ |
1195 | ||
1196 | static int s3cmci_cpufreq_transition(struct notifier_block *nb, | |
1197 | unsigned long val, void *data) | |
1198 | { | |
1199 | struct s3cmci_host *host; | |
1200 | struct mmc_host *mmc; | |
1201 | unsigned long newclk; | |
1202 | unsigned long flags; | |
1203 | ||
1204 | host = container_of(nb, struct s3cmci_host, freq_transition); | |
1205 | newclk = clk_get_rate(host->clk); | |
1206 | mmc = host->mmc; | |
1207 | ||
1208 | if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) || | |
1209 | (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) { | |
1210 | spin_lock_irqsave(&mmc->lock, flags); | |
1211 | ||
1212 | host->clk_rate = newclk; | |
1213 | ||
1214 | if (mmc->ios.power_mode != MMC_POWER_OFF && | |
1215 | mmc->ios.clock != 0) | |
1216 | s3cmci_set_clk(host, &mmc->ios); | |
1217 | ||
1218 | spin_unlock_irqrestore(&mmc->lock, flags); | |
1219 | } | |
1220 | ||
1221 | return 0; | |
1222 | } | |
1223 | ||
1224 | static inline int s3cmci_cpufreq_register(struct s3cmci_host *host) | |
1225 | { | |
1226 | host->freq_transition.notifier_call = s3cmci_cpufreq_transition; | |
1227 | ||
1228 | return cpufreq_register_notifier(&host->freq_transition, | |
1229 | CPUFREQ_TRANSITION_NOTIFIER); | |
1230 | } | |
1231 | ||
1232 | static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host) | |
1233 | { | |
1234 | cpufreq_unregister_notifier(&host->freq_transition, | |
1235 | CPUFREQ_TRANSITION_NOTIFIER); | |
1236 | } | |
1237 | ||
1238 | #else | |
1239 | static inline int s3cmci_cpufreq_register(struct s3cmci_host *host) | |
1240 | { | |
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host) | |
1245 | { | |
1246 | } | |
1247 | #endif | |
1248 | ||
be518018 TK |
1249 | static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) |
1250 | { | |
1251 | struct s3cmci_host *host; | |
1252 | struct mmc_host *mmc; | |
1253 | int ret; | |
1254 | ||
1255 | mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev); | |
1256 | if (!mmc) { | |
1257 | ret = -ENOMEM; | |
1258 | goto probe_out; | |
1259 | } | |
1260 | ||
1261 | host = mmc_priv(mmc); | |
1262 | host->mmc = mmc; | |
1263 | host->pdev = pdev; | |
1264 | host->is2440 = is2440; | |
1265 | ||
edb5a98e BD |
1266 | host->pdata = pdev->dev.platform_data; |
1267 | if (!host->pdata) { | |
1268 | pdev->dev.platform_data = &s3cmci_def_pdata; | |
1269 | host->pdata = &s3cmci_def_pdata; | |
1270 | } | |
1271 | ||
be518018 TK |
1272 | spin_lock_init(&host->complete_lock); |
1273 | tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host); | |
1274 | ||
1275 | if (is2440) { | |
1276 | host->sdiimsk = S3C2440_SDIIMSK; | |
1277 | host->sdidata = S3C2440_SDIDATA; | |
1278 | host->clk_div = 1; | |
1279 | } else { | |
1280 | host->sdiimsk = S3C2410_SDIIMSK; | |
1281 | host->sdidata = S3C2410_SDIDATA; | |
1282 | host->clk_div = 2; | |
1283 | } | |
1284 | ||
1285 | host->dodma = 0; | |
1286 | host->complete_what = COMPLETION_NONE; | |
1287 | host->pio_active = XFER_NONE; | |
1288 | ||
1289 | host->dma = S3CMCI_DMA; | |
be518018 TK |
1290 | |
1291 | host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1292 | if (!host->mem) { | |
1293 | dev_err(&pdev->dev, | |
1294 | "failed to get io memory region resouce.\n"); | |
1295 | ||
1296 | ret = -ENOENT; | |
1297 | goto probe_free_host; | |
1298 | } | |
1299 | ||
1300 | host->mem = request_mem_region(host->mem->start, | |
1301 | RESSIZE(host->mem), pdev->name); | |
1302 | ||
1303 | if (!host->mem) { | |
1304 | dev_err(&pdev->dev, "failed to request io memory region.\n"); | |
1305 | ret = -ENOENT; | |
1306 | goto probe_free_host; | |
1307 | } | |
1308 | ||
1309 | host->base = ioremap(host->mem->start, RESSIZE(host->mem)); | |
5d304400 | 1310 | if (!host->base) { |
be518018 TK |
1311 | dev_err(&pdev->dev, "failed to ioremap() io memory region.\n"); |
1312 | ret = -EINVAL; | |
1313 | goto probe_free_mem_region; | |
1314 | } | |
1315 | ||
1316 | host->irq = platform_get_irq(pdev, 0); | |
1317 | if (host->irq == 0) { | |
1318 | dev_err(&pdev->dev, "failed to get interrupt resouce.\n"); | |
1319 | ret = -EINVAL; | |
1320 | goto probe_iounmap; | |
1321 | } | |
1322 | ||
1323 | if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) { | |
1324 | dev_err(&pdev->dev, "failed to request mci interrupt.\n"); | |
1325 | ret = -ENOENT; | |
1326 | goto probe_iounmap; | |
1327 | } | |
1328 | ||
1329 | /* We get spurious interrupts even when we have set the IMSK | |
1330 | * register to ignore everything, so use disable_irq() to make | |
1331 | * ensure we don't lock the system with un-serviceable requests. */ | |
1332 | ||
1333 | disable_irq(host->irq); | |
1334 | ||
55d70f5a | 1335 | host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect); |
be518018 | 1336 | |
55d70f5a BD |
1337 | if (host->irq_cd >= 0) { |
1338 | if (request_irq(host->irq_cd, s3cmci_irq_cd, | |
1339 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | |
1340 | DRIVER_NAME, host)) { | |
1341 | dev_err(&pdev->dev, "can't get card detect irq.\n"); | |
1342 | ret = -ENOENT; | |
1343 | goto probe_free_irq; | |
1344 | } | |
1345 | } else { | |
1346 | dev_warn(&pdev->dev, "host detect has no irq available\n"); | |
1347 | s3c2410_gpio_cfgpin(host->pdata->gpio_detect, | |
1348 | S3C2410_GPIO_INPUT); | |
be518018 TK |
1349 | } |
1350 | ||
edb5a98e BD |
1351 | if (host->pdata->gpio_wprotect) |
1352 | s3c2410_gpio_cfgpin(host->pdata->gpio_wprotect, | |
1353 | S3C2410_GPIO_INPUT); | |
1354 | ||
3886ff5f | 1355 | if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL) < 0) { |
be518018 TK |
1356 | dev_err(&pdev->dev, "unable to get DMA channel.\n"); |
1357 | ret = -EBUSY; | |
1358 | goto probe_free_irq_cd; | |
1359 | } | |
1360 | ||
1361 | host->clk = clk_get(&pdev->dev, "sdi"); | |
1362 | if (IS_ERR(host->clk)) { | |
1363 | dev_err(&pdev->dev, "failed to find clock source.\n"); | |
1364 | ret = PTR_ERR(host->clk); | |
1365 | host->clk = NULL; | |
1366 | goto probe_free_host; | |
1367 | } | |
1368 | ||
1369 | ret = clk_enable(host->clk); | |
1370 | if (ret) { | |
1371 | dev_err(&pdev->dev, "failed to enable clock source.\n"); | |
1372 | goto clk_free; | |
1373 | } | |
1374 | ||
1375 | host->clk_rate = clk_get_rate(host->clk); | |
1376 | ||
1377 | mmc->ops = &s3cmci_ops; | |
edb5a98e | 1378 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
be518018 TK |
1379 | mmc->caps = MMC_CAP_4_BIT_DATA; |
1380 | mmc->f_min = host->clk_rate / (host->clk_div * 256); | |
1381 | mmc->f_max = host->clk_rate / host->clk_div; | |
1382 | ||
edb5a98e BD |
1383 | if (host->pdata->ocr_avail) |
1384 | mmc->ocr_avail = host->pdata->ocr_avail; | |
1385 | ||
be518018 TK |
1386 | mmc->max_blk_count = 4095; |
1387 | mmc->max_blk_size = 4095; | |
1388 | mmc->max_req_size = 4095 * 512; | |
1389 | mmc->max_seg_size = mmc->max_req_size; | |
1390 | ||
1391 | mmc->max_phys_segs = 128; | |
1392 | mmc->max_hw_segs = 128; | |
1393 | ||
1394 | dbg(host, dbg_debug, | |
1395 | "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n", | |
1396 | (host->is2440?"2440":""), | |
1397 | host->base, host->irq, host->irq_cd, host->dma); | |
1398 | ||
f87e6d00 | 1399 | ret = s3cmci_cpufreq_register(host); |
1400 | if (ret) { | |
1401 | dev_err(&pdev->dev, "failed to register cpufreq\n"); | |
1402 | goto free_dmabuf; | |
1403 | } | |
1404 | ||
be518018 TK |
1405 | ret = mmc_add_host(mmc); |
1406 | if (ret) { | |
1407 | dev_err(&pdev->dev, "failed to add mmc host.\n"); | |
f87e6d00 | 1408 | goto free_cpufreq; |
be518018 TK |
1409 | } |
1410 | ||
1411 | platform_set_drvdata(pdev, mmc); | |
1412 | dev_info(&pdev->dev, "initialisation done.\n"); | |
1413 | ||
1414 | return 0; | |
1415 | ||
f87e6d00 | 1416 | free_cpufreq: |
1417 | s3cmci_cpufreq_deregister(host); | |
1418 | ||
be518018 TK |
1419 | free_dmabuf: |
1420 | clk_disable(host->clk); | |
1421 | ||
1422 | clk_free: | |
1423 | clk_put(host->clk); | |
1424 | ||
1425 | probe_free_irq_cd: | |
55d70f5a BD |
1426 | if (host->irq_cd >= 0) |
1427 | free_irq(host->irq_cd, host); | |
be518018 TK |
1428 | |
1429 | probe_free_irq: | |
1430 | free_irq(host->irq, host); | |
1431 | ||
1432 | probe_iounmap: | |
1433 | iounmap(host->base); | |
1434 | ||
1435 | probe_free_mem_region: | |
1436 | release_mem_region(host->mem->start, RESSIZE(host->mem)); | |
1437 | ||
1438 | probe_free_host: | |
1439 | mmc_free_host(mmc); | |
1440 | probe_out: | |
1441 | return ret; | |
1442 | } | |
1443 | ||
907b2cd6 BD |
1444 | static void s3cmci_shutdown(struct platform_device *pdev) |
1445 | { | |
1446 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1447 | struct s3cmci_host *host = mmc_priv(mmc); | |
1448 | ||
1449 | if (host->irq_cd >= 0) | |
1450 | free_irq(host->irq_cd, host); | |
1451 | ||
f87e6d00 | 1452 | s3cmci_cpufreq_deregister(host); |
907b2cd6 BD |
1453 | mmc_remove_host(mmc); |
1454 | clk_disable(host->clk); | |
1455 | } | |
1456 | ||
be518018 TK |
1457 | static int __devexit s3cmci_remove(struct platform_device *pdev) |
1458 | { | |
1459 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1460 | struct s3cmci_host *host = mmc_priv(mmc); | |
1461 | ||
907b2cd6 | 1462 | s3cmci_shutdown(pdev); |
be518018 | 1463 | |
be518018 TK |
1464 | clk_put(host->clk); |
1465 | ||
1466 | tasklet_disable(&host->pio_tasklet); | |
ceb3ac25 | 1467 | s3c2410_dma_free(S3CMCI_DMA, &s3cmci_dma_client); |
be518018 | 1468 | |
be518018 TK |
1469 | free_irq(host->irq, host); |
1470 | ||
1471 | iounmap(host->base); | |
1472 | release_mem_region(host->mem->start, RESSIZE(host->mem)); | |
1473 | ||
1474 | mmc_free_host(mmc); | |
1475 | return 0; | |
1476 | } | |
1477 | ||
d2f2761b | 1478 | static int __devinit s3cmci_2410_probe(struct platform_device *dev) |
be518018 TK |
1479 | { |
1480 | return s3cmci_probe(dev, 0); | |
1481 | } | |
1482 | ||
d2f2761b | 1483 | static int __devinit s3cmci_2412_probe(struct platform_device *dev) |
be518018 TK |
1484 | { |
1485 | return s3cmci_probe(dev, 1); | |
1486 | } | |
1487 | ||
d2f2761b | 1488 | static int __devinit s3cmci_2440_probe(struct platform_device *dev) |
be518018 TK |
1489 | { |
1490 | return s3cmci_probe(dev, 1); | |
1491 | } | |
1492 | ||
1493 | #ifdef CONFIG_PM | |
1494 | ||
1495 | static int s3cmci_suspend(struct platform_device *dev, pm_message_t state) | |
1496 | { | |
1497 | struct mmc_host *mmc = platform_get_drvdata(dev); | |
1498 | ||
1499 | return mmc_suspend_host(mmc, state); | |
1500 | } | |
1501 | ||
1502 | static int s3cmci_resume(struct platform_device *dev) | |
1503 | { | |
1504 | struct mmc_host *mmc = platform_get_drvdata(dev); | |
1505 | ||
1506 | return mmc_resume_host(mmc); | |
1507 | } | |
1508 | ||
1509 | #else /* CONFIG_PM */ | |
1510 | #define s3cmci_suspend NULL | |
1511 | #define s3cmci_resume NULL | |
1512 | #endif /* CONFIG_PM */ | |
1513 | ||
1514 | ||
d2f2761b | 1515 | static struct platform_driver s3cmci_2410_driver = { |
be518018 TK |
1516 | .driver.name = "s3c2410-sdi", |
1517 | .driver.owner = THIS_MODULE, | |
d2f2761b | 1518 | .probe = s3cmci_2410_probe, |
be518018 | 1519 | .remove = __devexit_p(s3cmci_remove), |
907b2cd6 | 1520 | .shutdown = s3cmci_shutdown, |
be518018 TK |
1521 | .suspend = s3cmci_suspend, |
1522 | .resume = s3cmci_resume, | |
1523 | }; | |
1524 | ||
d2f2761b | 1525 | static struct platform_driver s3cmci_2412_driver = { |
be518018 TK |
1526 | .driver.name = "s3c2412-sdi", |
1527 | .driver.owner = THIS_MODULE, | |
d2f2761b | 1528 | .probe = s3cmci_2412_probe, |
be518018 | 1529 | .remove = __devexit_p(s3cmci_remove), |
907b2cd6 | 1530 | .shutdown = s3cmci_shutdown, |
be518018 TK |
1531 | .suspend = s3cmci_suspend, |
1532 | .resume = s3cmci_resume, | |
1533 | }; | |
1534 | ||
d2f2761b | 1535 | static struct platform_driver s3cmci_2440_driver = { |
be518018 TK |
1536 | .driver.name = "s3c2440-sdi", |
1537 | .driver.owner = THIS_MODULE, | |
d2f2761b | 1538 | .probe = s3cmci_2440_probe, |
be518018 | 1539 | .remove = __devexit_p(s3cmci_remove), |
907b2cd6 | 1540 | .shutdown = s3cmci_shutdown, |
be518018 TK |
1541 | .suspend = s3cmci_suspend, |
1542 | .resume = s3cmci_resume, | |
1543 | }; | |
1544 | ||
1545 | ||
1546 | static int __init s3cmci_init(void) | |
1547 | { | |
d2f2761b BD |
1548 | platform_driver_register(&s3cmci_2410_driver); |
1549 | platform_driver_register(&s3cmci_2412_driver); | |
1550 | platform_driver_register(&s3cmci_2440_driver); | |
be518018 TK |
1551 | return 0; |
1552 | } | |
1553 | ||
1554 | static void __exit s3cmci_exit(void) | |
1555 | { | |
d2f2761b BD |
1556 | platform_driver_unregister(&s3cmci_2410_driver); |
1557 | platform_driver_unregister(&s3cmci_2412_driver); | |
1558 | platform_driver_unregister(&s3cmci_2440_driver); | |
be518018 TK |
1559 | } |
1560 | ||
1561 | module_init(s3cmci_init); | |
1562 | module_exit(s3cmci_exit); | |
1563 | ||
1564 | MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver"); | |
1565 | MODULE_LICENSE("GPL v2"); | |
08c55e22 | 1566 | MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>"); |
318f905f BD |
1567 | MODULE_ALIAS("platform:s3c2410-sdi"); |
1568 | MODULE_ALIAS("platform:s3c2412-sdi"); | |
1569 | MODULE_ALIAS("platform:s3c2440-sdi"); |