[deliverable/linux.git] / drivers / mmc / host / sdhci-esdhc-imx.c

/*
 * Freescale eSDHC i.MX controller driver for the platform bus.
 *
 * derived from the OF-version.
 *
 * Copyright (c) 2010 Pengutronix e.K.
 *   Author: Wolfram Sang <w.sang@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */

#include <linux/io.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sdhci-pltfm.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/sdio.h>
#include <mach/hardware.h>
#include <mach/esdhc.h>
#include "sdhci.h"
#include "sdhci-pltfm.h"
#include "sdhci-esdhc.h"

/* VENDOR SPEC register */
#define SDHCI_VENDOR_SPEC		0xC0
#define  SDHCI_VENDOR_SPEC_SDIO_QUIRK	0x00000002

#define ESDHC_FLAG_GPIO_FOR_CD_WP	(1 << 0)
/*
 * The CMDTYPE of the CMD register (offset 0xE) should be set to
 * "11" when the STOP CMD12 is issued on imx53 to abort one
 * open ended multi-blk IO. Otherwise the TC INT wouldn't
 * be generated.
 * In exact block transfer, the controller doesn't complete the
 * operations automatically as required at the end of the
 * transfer and remains on hold if the abort command is not sent.
 * As a result, the TC flag is not asserted and SW  received timeout
 * exeception. Bit1 of Vendor Spec registor is used to fix it.
 */
#define ESDHC_FLAG_MULTIBLK_NO_INT	(1 << 1)

struct pltfm_imx_data {
	int flags;
	u32 scratchpad;
};

static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
{
	void __iomem *base = host->ioaddr + (reg & ~0x3);
	u32 shift = (reg & 0x3) * 8;

	writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
}

static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct pltfm_imx_data *imx_data = pltfm_host->priv;

	/* fake CARD_PRESENT flag on mx25/35 */
	u32 val = readl(host->ioaddr + reg);

	if (unlikely((reg == SDHCI_PRESENT_STATE)
			&& (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP))) {
		struct esdhc_platform_data *boarddata =
				host->mmc->parent->platform_data;

		if (boarddata && gpio_is_valid(boarddata->cd_gpio)
				&& gpio_get_value(boarddata->cd_gpio))
			/* no card, if a valid gpio says so... */
			val &= SDHCI_CARD_PRESENT;
		else
			/* ... in all other cases assume card is present */
			val |= SDHCI_CARD_PRESENT;
	}

	return val;
}

static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct pltfm_imx_data *imx_data = pltfm_host->priv;

	if (unlikely((reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)
			&& (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP)))
		/*
		 * these interrupts won't work with a custom card_detect gpio
		 * (only applied to mx25/35)
		 */
		val &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);

	if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
				&& (reg == SDHCI_INT_STATUS)
				&& (val & SDHCI_INT_DATA_END))) {
			u32 v;
			v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
			v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK;
			writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
	}

	writel(val, host->ioaddr + reg);
}

static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
{
	if (unlikely(reg == SDHCI_HOST_VERSION))
		reg ^= 2;

	return readw(host->ioaddr + reg);
}

static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct pltfm_imx_data *imx_data = pltfm_host->priv;

	switch (reg) {
	case SDHCI_TRANSFER_MODE:
		/*
		 * Postpone this write, we must do it together with a
		 * command write that is down below.
		 */
		if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
				&& (host->cmd->opcode == SD_IO_RW_EXTENDED)
				&& (host->cmd->data->blocks > 1)
				&& (host->cmd->data->flags & MMC_DATA_READ)) {
			u32 v;
			v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
			v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK;
			writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
		}
		imx_data->scratchpad = val;
		return;
	case SDHCI_COMMAND:
		if ((host->cmd->opcode == MMC_STOP_TRANSMISSION)
			&& (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
			val |= SDHCI_CMD_ABORTCMD;
		writel(val << 16 | imx_data->scratchpad,
			host->ioaddr + SDHCI_TRANSFER_MODE);
		return;
	case SDHCI_BLOCK_SIZE:
		val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
		break;
	}
	esdhc_clrset_le(host, 0xffff, val, reg);
}

static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
{
	u32 new_val;

	switch (reg) {
	case SDHCI_POWER_CONTROL:
		/*
		 * FSL put some DMA bits here
		 * If your board has a regulator, code should be here
		 */
		return;
	case SDHCI_HOST_CONTROL:
		/* FSL messed up here, so we can just keep those two */
		new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS);
		/* ensure the endianess */
		new_val |= ESDHC_HOST_CONTROL_LE;
		/* DMA mode bits are shifted */
		new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;

		esdhc_clrset_le(host, 0xffff, new_val, reg);
		return;
	}
	esdhc_clrset_le(host, 0xff, val, reg);
}

static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	return clk_get_rate(pltfm_host->clk);
}

static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	return clk_get_rate(pltfm_host->clk) / 256 / 16;
}

static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
{
	struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;

	if (boarddata && gpio_is_valid(boarddata->wp_gpio))
		return gpio_get_value(boarddata->wp_gpio);
	else
		return -ENOSYS;
}

static struct sdhci_ops sdhci_esdhc_ops = {
	.read_l = esdhc_readl_le,
	.read_w = esdhc_readw_le,
	.write_l = esdhc_writel_le,
	.write_w = esdhc_writew_le,
	.write_b = esdhc_writeb_le,
	.set_clock = esdhc_set_clock,
	.get_max_clock = esdhc_pltfm_get_max_clock,
	.get_min_clock = esdhc_pltfm_get_min_clock,
};

static irqreturn_t cd_irq(int irq, void *data)
{
	struct sdhci_host *sdhost = (struct sdhci_host *)data;

	tasklet_schedule(&sdhost->card_tasklet);
	return IRQ_HANDLED;
};

static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pdata)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;
	struct clk *clk;
	int err;
	struct pltfm_imx_data *imx_data;

	clk = clk_get(mmc_dev(host->mmc), NULL);
	if (IS_ERR(clk)) {
		dev_err(mmc_dev(host->mmc), "clk err\n");
		return PTR_ERR(clk);
	}
	clk_enable(clk);
	pltfm_host->clk = clk;

	imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL);
	if (!imx_data) {
		clk_disable(pltfm_host->clk);
		clk_put(pltfm_host->clk);
		return -ENOMEM;
	}
	pltfm_host->priv = imx_data;

	if (!cpu_is_mx25())
		host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;

	if (cpu_is_mx25() || cpu_is_mx35()) {
		/* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
		host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
		/* write_protect can't be routed to controller, use gpio */
		sdhci_esdhc_ops.get_ro = esdhc_pltfm_get_ro;
	}

	if (!(cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51()))
		imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;

	if (boarddata) {
		err = gpio_request_one(boarddata->wp_gpio, GPIOF_IN, "ESDHC_WP");
		if (err) {
			dev_warn(mmc_dev(host->mmc),
				"no write-protect pin available!\n");
			boarddata->wp_gpio = err;
		}

		err = gpio_request_one(boarddata->cd_gpio, GPIOF_IN, "ESDHC_CD");
		if (err) {
			dev_warn(mmc_dev(host->mmc),
				"no card-detect pin available!\n");
			goto no_card_detect_pin;
		}

		/* i.MX5x has issues to be researched */
		if (!cpu_is_mx25() && !cpu_is_mx35())
			goto not_supported;

		err = request_irq(gpio_to_irq(boarddata->cd_gpio), cd_irq,
				 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
				 mmc_hostname(host->mmc), host);
		if (err) {
			dev_warn(mmc_dev(host->mmc), "request irq error\n");
			goto no_card_detect_irq;
		}

		imx_data->flags |= ESDHC_FLAG_GPIO_FOR_CD_WP;
		/* Now we have a working card_detect again */
		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
	}

	return 0;

 no_card_detect_irq:
	gpio_free(boarddata->cd_gpio);
 no_card_detect_pin:
	boarddata->cd_gpio = err;
 not_supported:
	kfree(imx_data);
	return 0;
}

static void esdhc_pltfm_exit(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;
	struct pltfm_imx_data *imx_data = pltfm_host->priv;

	if (boarddata && gpio_is_valid(boarddata->wp_gpio))
		gpio_free(boarddata->wp_gpio);

	if (boarddata && gpio_is_valid(boarddata->cd_gpio)) {
		gpio_free(boarddata->cd_gpio);

		if (!(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION))
			free_irq(gpio_to_irq(boarddata->cd_gpio), host);
	}

	clk_disable(pltfm_host->clk);
	clk_put(pltfm_host->clk);
	kfree(imx_data);
}

struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA
			| SDHCI_QUIRK_BROKEN_CARD_DETECTION,
	/* ADMA has issues. Might be fixable */
	.ops = &sdhci_esdhc_ops,
	.init = esdhc_pltfm_init,
	.exit = esdhc_pltfm_exit,
};
Commit	Line	Data
95f25efe WS	1	/*
	2	* Freescale eSDHC i.MX controller driver for the platform bus.
	3	*
	4	* derived from the OF-version.
	5	*
	6	* Copyright (c) 2010 Pengutronix e.K.
	7	* Author: Wolfram Sang <w.sang@pengutronix.de>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License.
	12	*/
	13
	14	#include <linux/io.h>
	15	#include <linux/delay.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
0c6d49ce	18	#include <linux/gpio.h>
e149860d	19	#include <linux/slab.h>
95f25efe WS	20	#include <linux/mmc/host.h>
95f25efe WS	21	#include <linux/mmc/sdhci-pltfm.h>
58ac8177 RZ	22	#include <linux/mmc/mmc.h>
58ac8177 RZ	23	#include <linux/mmc/sdio.h>
37865fe9	24	#include <mach/hardware.h>
0c6d49ce	25	#include <mach/esdhc.h>
95f25efe WS	26	#include "sdhci.h"
	27	#include "sdhci-pltfm.h"
	28	#include "sdhci-esdhc.h"
	29
58ac8177 RZ	30	/* VENDOR SPEC register */
	31	#define SDHCI_VENDOR_SPEC 0xC0
	32	#define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002
	33
e149860d	34	#define ESDHC_FLAG_GPIO_FOR_CD_WP (1 << 0)
58ac8177 RZ	35	/*
	36	* The CMDTYPE of the CMD register (offset 0xE) should be set to
	37	* "11" when the STOP CMD12 is issued on imx53 to abort one
	38	* open ended multi-blk IO. Otherwise the TC INT wouldn't
	39	* be generated.
	40	* In exact block transfer, the controller doesn't complete the
	41	* operations automatically as required at the end of the
	42	* transfer and remains on hold if the abort command is not sent.
	43	* As a result, the TC flag is not asserted and SW received timeout
	44	* exeception. Bit1 of Vendor Spec registor is used to fix it.
	45	*/
	46	#define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1)
e149860d RZ	47
	48	struct pltfm_imx_data {
	49	int flags;
	50	u32 scratchpad;
	51	};
	52
95f25efe WS	53	static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
	54	{
	55	void __iomem *base = host->ioaddr + (reg & ~0x3);
	56	u32 shift = (reg & 0x3) * 8;
	57
	58	writel(((readl(base) & ~(mask << shift)) \| (val << shift)), base);
	59	}
	60
7e29c306 WS	61	static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
7e29c306 WS	62	{
e149860d RZ	63	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	64	struct pltfm_imx_data *imx_data = pltfm_host->priv;
	65
7e29c306 WS	66	/* fake CARD_PRESENT flag on mx25/35 */
	67	u32 val = readl(host->ioaddr + reg);
	68
e149860d RZ	69	if (unlikely((reg == SDHCI_PRESENT_STATE)
e149860d RZ	70	&& (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP))) {
7e29c306 WS	71	struct esdhc_platform_data *boarddata =
	72	host->mmc->parent->platform_data;
	73
	74	if (boarddata && gpio_is_valid(boarddata->cd_gpio)
	75	&& gpio_get_value(boarddata->cd_gpio))
	76	/* no card, if a valid gpio says so... */
	77	val &= SDHCI_CARD_PRESENT;
	78	else
	79	/* ... in all other cases assume card is present */
	80	val \|= SDHCI_CARD_PRESENT;
	81	}
	82
	83	return val;
	84	}
	85
	86	static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
	87	{
e149860d RZ	88	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	89	struct pltfm_imx_data *imx_data = pltfm_host->priv;
	90
	91	if (unlikely((reg == SDHCI_INT_ENABLE \|\| reg == SDHCI_SIGNAL_ENABLE)
	92	&& (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP)))
7e29c306 WS	93	/*
	94	* these interrupts won't work with a custom card_detect gpio
	95	* (only applied to mx25/35)
	96	*/
	97	val &= ~(SDHCI_INT_CARD_REMOVE \| SDHCI_INT_CARD_INSERT);
	98
58ac8177 RZ	99	if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
	100	&& (reg == SDHCI_INT_STATUS)
	101	&& (val & SDHCI_INT_DATA_END))) {
	102	u32 v;
	103	v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
	104	v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK;
	105	writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
	106	}
	107
7e29c306 WS	108	writel(val, host->ioaddr + reg);
	109	}
	110
95f25efe WS	111	static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
	112	{
	113	if (unlikely(reg == SDHCI_HOST_VERSION))
	114	reg ^= 2;
	115
	116	return readw(host->ioaddr + reg);
	117	}
	118
	119	static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
	120	{
	121	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
e149860d	122	struct pltfm_imx_data *imx_data = pltfm_host->priv;
95f25efe WS	123
	124	switch (reg) {
	125	case SDHCI_TRANSFER_MODE:
	126	/*
	127	* Postpone this write, we must do it together with a
	128	* command write that is down below.
	129	*/
58ac8177 RZ	130	if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
	131	&& (host->cmd->opcode == SD_IO_RW_EXTENDED)
	132	&& (host->cmd->data->blocks > 1)
	133	&& (host->cmd->data->flags & MMC_DATA_READ)) {
	134	u32 v;
	135	v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
	136	v \|= SDHCI_VENDOR_SPEC_SDIO_QUIRK;
	137	writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
	138	}
e149860d	139	imx_data->scratchpad = val;
95f25efe WS	140	return;
95f25efe WS	141	case SDHCI_COMMAND:
58ac8177 RZ	142	if ((host->cmd->opcode == MMC_STOP_TRANSMISSION)
	143	&& (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
	144	val \|= SDHCI_CMD_ABORTCMD;
e149860d	145	writel(val << 16 \| imx_data->scratchpad,
95f25efe WS	146	host->ioaddr + SDHCI_TRANSFER_MODE);
	147	return;
	148	case SDHCI_BLOCK_SIZE:
	149	val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
	150	break;
	151	}
	152	esdhc_clrset_le(host, 0xffff, val, reg);
	153	}
	154
	155	static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
	156	{
	157	u32 new_val;
	158
	159	switch (reg) {
	160	case SDHCI_POWER_CONTROL:
	161	/*
	162	* FSL put some DMA bits here
	163	* If your board has a regulator, code should be here
	164	*/
	165	return;
	166	case SDHCI_HOST_CONTROL:
	167	/* FSL messed up here, so we can just keep those two */
	168	new_val = val & (SDHCI_CTRL_LED \| SDHCI_CTRL_4BITBUS);
	169	/* ensure the endianess */
	170	new_val \|= ESDHC_HOST_CONTROL_LE;
	171	/* DMA mode bits are shifted */
	172	new_val \|= (val & SDHCI_CTRL_DMA_MASK) << 5;
	173
	174	esdhc_clrset_le(host, 0xffff, new_val, reg);
	175	return;
	176	}
	177	esdhc_clrset_le(host, 0xff, val, reg);
	178	}
	179
	180	static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
	181	{
	182	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	183
	184	return clk_get_rate(pltfm_host->clk);
	185	}
	186
	187	static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
	188	{
	189	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	190
	191	return clk_get_rate(pltfm_host->clk) / 256 / 16;
	192	}
	193
0c6d49ce WS	194	static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
	195	{
	196	struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;
	197
	198	if (boarddata && gpio_is_valid(boarddata->wp_gpio))
	199	return gpio_get_value(boarddata->wp_gpio);
	200	else
	201	return -ENOSYS;
	202	}
	203
	204	static struct sdhci_ops sdhci_esdhc_ops = {
e149860d	205	.read_l = esdhc_readl_le,
0c6d49ce	206	.read_w = esdhc_readw_le,
e149860d	207	.write_l = esdhc_writel_le,
0c6d49ce WS	208	.write_w = esdhc_writew_le,
	209	.write_b = esdhc_writeb_le,
	210	.set_clock = esdhc_set_clock,
	211	.get_max_clock = esdhc_pltfm_get_max_clock,
	212	.get_min_clock = esdhc_pltfm_get_min_clock,
	213	};
	214
7e29c306 WS	215	static irqreturn_t cd_irq(int irq, void *data)
	216	{
	217	struct sdhci_host sdhost = (struct sdhci_host )data;
	218
	219	tasklet_schedule(&sdhost->card_tasklet);
	220	return IRQ_HANDLED;
	221	};
	222
95f25efe WS	223	static int esdhc_pltfm_init(struct sdhci_host host, struct sdhci_pltfm_data pdata)
	224	{
	225	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0c6d49ce	226	struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;
95f25efe	227	struct clk *clk;
0c6d49ce	228	int err;
e149860d	229	struct pltfm_imx_data *imx_data;
95f25efe WS	230
	231	clk = clk_get(mmc_dev(host->mmc), NULL);
	232	if (IS_ERR(clk)) {
	233	dev_err(mmc_dev(host->mmc), "clk err\n");
	234	return PTR_ERR(clk);
	235	}
	236	clk_enable(clk);
	237	pltfm_host->clk = clk;
	238
e149860d RZ	239	imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL);
	240	if (!imx_data) {
	241	clk_disable(pltfm_host->clk);
	242	clk_put(pltfm_host->clk);
	243	return -ENOMEM;
	244	}
	245	pltfm_host->priv = imx_data;
	246
	247	if (!cpu_is_mx25())
37865fe9 EB	248	host->quirks \|= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
37865fe9 EB	249
0c6d49ce WS	250	if (cpu_is_mx25() \|\| cpu_is_mx35()) {
0c6d49ce WS	251	/* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
16a790bc	252	host->quirks \|= SDHCI_QUIRK_NO_MULTIBLOCK;
0c6d49ce WS	253	/* write_protect can't be routed to controller, use gpio */
	254	sdhci_esdhc_ops.get_ro = esdhc_pltfm_get_ro;
	255	}
	256
58ac8177 RZ	257	if (!(cpu_is_mx25() \|\| cpu_is_mx35() \|\| cpu_is_mx51()))
	258	imx_data->flags \|= ESDHC_FLAG_MULTIBLK_NO_INT;
	259
0c6d49ce WS	260	if (boarddata) {
	261	err = gpio_request_one(boarddata->wp_gpio, GPIOF_IN, "ESDHC_WP");
	262	if (err) {
	263	dev_warn(mmc_dev(host->mmc),
	264	"no write-protect pin available!\n");
	265	boarddata->wp_gpio = err;
	266	}
7e29c306 WS	267
	268	err = gpio_request_one(boarddata->cd_gpio, GPIOF_IN, "ESDHC_CD");
	269	if (err) {
	270	dev_warn(mmc_dev(host->mmc),
	271	"no card-detect pin available!\n");
	272	goto no_card_detect_pin;
	273	}
	274
	275	/* i.MX5x has issues to be researched */
	276	if (!cpu_is_mx25() && !cpu_is_mx35())
	277	goto not_supported;
	278
	279	err = request_irq(gpio_to_irq(boarddata->cd_gpio), cd_irq,
	280	IRQF_TRIGGER_FALLING \| IRQF_TRIGGER_RISING,
	281	mmc_hostname(host->mmc), host);
	282	if (err) {
	283	dev_warn(mmc_dev(host->mmc), "request irq error\n");
	284	goto no_card_detect_irq;
	285	}
	286
e149860d	287	imx_data->flags \|= ESDHC_FLAG_GPIO_FOR_CD_WP;
7e29c306 WS	288	/* Now we have a working card_detect again */
7e29c306 WS	289	host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
0c6d49ce	290	}
16a790bc	291
95f25efe	292	return 0;
7e29c306 WS	293
	294	no_card_detect_irq:
	295	gpio_free(boarddata->cd_gpio);
	296	no_card_detect_pin:
	297	boarddata->cd_gpio = err;
	298	not_supported:
e149860d	299	kfree(imx_data);
7e29c306	300	return 0;
95f25efe WS	301	}
	302
	303	static void esdhc_pltfm_exit(struct sdhci_host *host)
	304	{
	305	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0c6d49ce	306	struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;
e149860d	307	struct pltfm_imx_data *imx_data = pltfm_host->priv;
0c6d49ce WS	308
	309	if (boarddata && gpio_is_valid(boarddata->wp_gpio))
	310	gpio_free(boarddata->wp_gpio);
95f25efe	311
7e29c306 WS	312	if (boarddata && gpio_is_valid(boarddata->cd_gpio)) {
	313	gpio_free(boarddata->cd_gpio);
	314
	315	if (!(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION))
	316	free_irq(gpio_to_irq(boarddata->cd_gpio), host);
	317	}
	318
95f25efe WS	319	clk_disable(pltfm_host->clk);
95f25efe WS	320	clk_put(pltfm_host->clk);
e149860d	321	kfree(imx_data);
95f25efe WS	322	}
95f25efe WS	323
95f25efe	324	struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
3bb2a9f6 WS	325	.quirks = ESDHC_DEFAULT_QUIRKS \| SDHCI_QUIRK_BROKEN_ADMA
3bb2a9f6 WS	326	\| SDHCI_QUIRK_BROKEN_CARD_DETECTION,
95f25efe	327	/* ADMA has issues. Might be fixable */
95f25efe WS	328	.ops = &sdhci_esdhc_ops,
	329	.init = esdhc_pltfm_init,
	330	.exit = esdhc_pltfm_exit,
	331	};