Commit | Line | Data |
---|---|---|
95f25efe WS |
1 | /* |
2 | * Freescale eSDHC i.MX controller driver for the platform bus. | |
3 | * | |
4 | * derived from the OF-version. | |
5 | * | |
6 | * Copyright (c) 2010 Pengutronix e.K. | |
035ff831 | 7 | * Author: Wolfram Sang <kernel@pengutronix.de> |
95f25efe WS |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/clk.h> | |
0c6d49ce | 18 | #include <linux/gpio.h> |
66506f76 | 19 | #include <linux/module.h> |
e149860d | 20 | #include <linux/slab.h> |
95f25efe | 21 | #include <linux/mmc/host.h> |
58ac8177 RZ |
22 | #include <linux/mmc/mmc.h> |
23 | #include <linux/mmc/sdio.h> | |
fbe5fdd1 | 24 | #include <linux/mmc/slot-gpio.h> |
abfafc2d SG |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/of_gpio.h> | |
e62d8b8f | 28 | #include <linux/pinctrl/consumer.h> |
82906b13 | 29 | #include <linux/platform_data/mmc-esdhc-imx.h> |
89d7e5c1 | 30 | #include <linux/pm_runtime.h> |
95f25efe WS |
31 | #include "sdhci-pltfm.h" |
32 | #include "sdhci-esdhc.h" | |
33 | ||
60bf6396 | 34 | #define ESDHC_CTRL_D3CD 0x08 |
fd44954e | 35 | #define ESDHC_BURST_LEN_EN_INCR (1 << 27) |
58ac8177 | 36 | /* VENDOR SPEC register */ |
60bf6396 SG |
37 | #define ESDHC_VENDOR_SPEC 0xc0 |
38 | #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) | |
0322191e | 39 | #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) |
fed2f6e2 | 40 | #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) |
60bf6396 | 41 | #define ESDHC_WTMK_LVL 0x44 |
cc17e129 | 42 | #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 |
60bf6396 | 43 | #define ESDHC_MIX_CTRL 0x48 |
de5bdbff | 44 | #define ESDHC_MIX_CTRL_DDREN (1 << 3) |
2a15f981 | 45 | #define ESDHC_MIX_CTRL_AC23EN (1 << 7) |
0322191e DA |
46 | #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) |
47 | #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) | |
0b330e38 | 48 | #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) |
0322191e | 49 | #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) |
28b07674 | 50 | #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) |
2a15f981 SG |
51 | /* Bits 3 and 6 are not SDHCI standard definitions */ |
52 | #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 | |
d131a71c DA |
53 | /* Tuning bits */ |
54 | #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 | |
58ac8177 | 55 | |
602519b2 DA |
56 | /* dll control register */ |
57 | #define ESDHC_DLL_CTRL 0x60 | |
58 | #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 | |
59 | #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 | |
60 | ||
0322191e DA |
61 | /* tune control register */ |
62 | #define ESDHC_TUNE_CTRL_STATUS 0x68 | |
63 | #define ESDHC_TUNE_CTRL_STEP 1 | |
64 | #define ESDHC_TUNE_CTRL_MIN 0 | |
65 | #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) | |
66 | ||
28b07674 HC |
67 | /* strobe dll register */ |
68 | #define ESDHC_STROBE_DLL_CTRL 0x70 | |
69 | #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) | |
70 | #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) | |
71 | #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 | |
72 | ||
73 | #define ESDHC_STROBE_DLL_STATUS 0x74 | |
74 | #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) | |
75 | #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 | |
76 | ||
6e9fd28e DA |
77 | #define ESDHC_TUNING_CTRL 0xcc |
78 | #define ESDHC_STD_TUNING_EN (1 << 24) | |
79 | /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ | |
d87fc966 DA |
80 | #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 |
81 | #define ESDHC_TUNING_START_TAP_MASK 0xff | |
260ecb3c | 82 | #define ESDHC_TUNING_STEP_MASK 0x00070000 |
d407e30b | 83 | #define ESDHC_TUNING_STEP_SHIFT 16 |
6e9fd28e | 84 | |
ad93220d DA |
85 | /* pinctrl state */ |
86 | #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" | |
87 | #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" | |
88 | ||
af51079e SH |
89 | /* |
90 | * Our interpretation of the SDHCI_HOST_CONTROL register | |
91 | */ | |
92 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) | |
93 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) | |
94 | #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) | |
95 | ||
97e4ba6a RZ |
96 | /* |
97 | * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: | |
98 | * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, | |
99 | * but bit28 is used as the INT DMA ERR in fsl eSDHC design. | |
100 | * Define this macro DMA error INT for fsl eSDHC | |
101 | */ | |
60bf6396 | 102 | #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) |
97e4ba6a | 103 | |
58ac8177 RZ |
104 | /* |
105 | * The CMDTYPE of the CMD register (offset 0xE) should be set to | |
106 | * "11" when the STOP CMD12 is issued on imx53 to abort one | |
107 | * open ended multi-blk IO. Otherwise the TC INT wouldn't | |
108 | * be generated. | |
109 | * In exact block transfer, the controller doesn't complete the | |
110 | * operations automatically as required at the end of the | |
111 | * transfer and remains on hold if the abort command is not sent. | |
112 | * As a result, the TC flag is not asserted and SW received timeout | |
113 | * exeception. Bit1 of Vendor Spec registor is used to fix it. | |
114 | */ | |
31fbb301 SG |
115 | #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) |
116 | /* | |
117 | * The flag enables the workaround for ESDHC errata ENGcm07207 which | |
118 | * affects i.MX25 and i.MX35. | |
119 | */ | |
120 | #define ESDHC_FLAG_ENGCM07207 BIT(2) | |
9d61c009 SG |
121 | /* |
122 | * The flag tells that the ESDHC controller is an USDHC block that is | |
123 | * integrated on the i.MX6 series. | |
124 | */ | |
125 | #define ESDHC_FLAG_USDHC BIT(3) | |
6e9fd28e DA |
126 | /* The IP supports manual tuning process */ |
127 | #define ESDHC_FLAG_MAN_TUNING BIT(4) | |
128 | /* The IP supports standard tuning process */ | |
129 | #define ESDHC_FLAG_STD_TUNING BIT(5) | |
130 | /* The IP has SDHCI_CAPABILITIES_1 register */ | |
131 | #define ESDHC_FLAG_HAVE_CAP1 BIT(6) | |
18094430 DA |
132 | /* |
133 | * The IP has errata ERR004536 | |
134 | * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, | |
135 | * when reading data from the card | |
136 | */ | |
137 | #define ESDHC_FLAG_ERR004536 BIT(7) | |
4245afff DA |
138 | /* The IP supports HS200 mode */ |
139 | #define ESDHC_FLAG_HS200 BIT(8) | |
28b07674 HC |
140 | /* The IP supports HS400 mode */ |
141 | #define ESDHC_FLAG_HS400 BIT(9) | |
142 | ||
143 | /* A higher clock ferquency than this rate requires strobell dll control */ | |
144 | #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 | |
e149860d | 145 | |
f47c4bbf SG |
146 | struct esdhc_soc_data { |
147 | u32 flags; | |
148 | }; | |
149 | ||
150 | static struct esdhc_soc_data esdhc_imx25_data = { | |
151 | .flags = ESDHC_FLAG_ENGCM07207, | |
152 | }; | |
153 | ||
154 | static struct esdhc_soc_data esdhc_imx35_data = { | |
155 | .flags = ESDHC_FLAG_ENGCM07207, | |
156 | }; | |
157 | ||
158 | static struct esdhc_soc_data esdhc_imx51_data = { | |
159 | .flags = 0, | |
160 | }; | |
161 | ||
162 | static struct esdhc_soc_data esdhc_imx53_data = { | |
163 | .flags = ESDHC_FLAG_MULTIBLK_NO_INT, | |
164 | }; | |
165 | ||
166 | static struct esdhc_soc_data usdhc_imx6q_data = { | |
6e9fd28e DA |
167 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, |
168 | }; | |
169 | ||
170 | static struct esdhc_soc_data usdhc_imx6sl_data = { | |
171 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
4245afff DA |
172 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 |
173 | | ESDHC_FLAG_HS200, | |
57ed3314 SG |
174 | }; |
175 | ||
913d4951 DA |
176 | static struct esdhc_soc_data usdhc_imx6sx_data = { |
177 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
4245afff | 178 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, |
913d4951 DA |
179 | }; |
180 | ||
28b07674 HC |
181 | static struct esdhc_soc_data usdhc_imx7d_data = { |
182 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
183 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 | |
184 | | ESDHC_FLAG_HS400, | |
185 | }; | |
186 | ||
e149860d | 187 | struct pltfm_imx_data { |
e149860d | 188 | u32 scratchpad; |
e62d8b8f | 189 | struct pinctrl *pinctrl; |
ad93220d DA |
190 | struct pinctrl_state *pins_default; |
191 | struct pinctrl_state *pins_100mhz; | |
192 | struct pinctrl_state *pins_200mhz; | |
f47c4bbf | 193 | const struct esdhc_soc_data *socdata; |
842afc02 | 194 | struct esdhc_platform_data boarddata; |
52dac615 SH |
195 | struct clk *clk_ipg; |
196 | struct clk *clk_ahb; | |
197 | struct clk *clk_per; | |
361b8482 LS |
198 | enum { |
199 | NO_CMD_PENDING, /* no multiblock command pending*/ | |
200 | MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ | |
201 | WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ | |
202 | } multiblock_status; | |
de5bdbff | 203 | u32 is_ddr; |
e149860d RZ |
204 | }; |
205 | ||
f8cbf461 | 206 | static const struct platform_device_id imx_esdhc_devtype[] = { |
57ed3314 SG |
207 | { |
208 | .name = "sdhci-esdhc-imx25", | |
f47c4bbf | 209 | .driver_data = (kernel_ulong_t) &esdhc_imx25_data, |
57ed3314 SG |
210 | }, { |
211 | .name = "sdhci-esdhc-imx35", | |
f47c4bbf | 212 | .driver_data = (kernel_ulong_t) &esdhc_imx35_data, |
57ed3314 SG |
213 | }, { |
214 | .name = "sdhci-esdhc-imx51", | |
f47c4bbf | 215 | .driver_data = (kernel_ulong_t) &esdhc_imx51_data, |
57ed3314 SG |
216 | }, { |
217 | /* sentinel */ | |
218 | } | |
219 | }; | |
220 | MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); | |
221 | ||
abfafc2d | 222 | static const struct of_device_id imx_esdhc_dt_ids[] = { |
f47c4bbf SG |
223 | { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, |
224 | { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, | |
225 | { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, | |
226 | { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, | |
913d4951 | 227 | { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, |
6e9fd28e | 228 | { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, |
f47c4bbf | 229 | { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, |
28b07674 | 230 | { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, |
abfafc2d SG |
231 | { /* sentinel */ } |
232 | }; | |
233 | MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); | |
234 | ||
57ed3314 SG |
235 | static inline int is_imx25_esdhc(struct pltfm_imx_data *data) |
236 | { | |
f47c4bbf | 237 | return data->socdata == &esdhc_imx25_data; |
57ed3314 SG |
238 | } |
239 | ||
240 | static inline int is_imx53_esdhc(struct pltfm_imx_data *data) | |
241 | { | |
f47c4bbf | 242 | return data->socdata == &esdhc_imx53_data; |
57ed3314 SG |
243 | } |
244 | ||
95a2482a SG |
245 | static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) |
246 | { | |
f47c4bbf | 247 | return data->socdata == &usdhc_imx6q_data; |
95a2482a SG |
248 | } |
249 | ||
9d61c009 SG |
250 | static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) |
251 | { | |
f47c4bbf | 252 | return !!(data->socdata->flags & ESDHC_FLAG_USDHC); |
9d61c009 SG |
253 | } |
254 | ||
95f25efe WS |
255 | static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) |
256 | { | |
257 | void __iomem *base = host->ioaddr + (reg & ~0x3); | |
258 | u32 shift = (reg & 0x3) * 8; | |
259 | ||
260 | writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); | |
261 | } | |
262 | ||
7e29c306 WS |
263 | static u32 esdhc_readl_le(struct sdhci_host *host, int reg) |
264 | { | |
361b8482 | 265 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 266 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
7e29c306 WS |
267 | u32 val = readl(host->ioaddr + reg); |
268 | ||
0322191e DA |
269 | if (unlikely(reg == SDHCI_PRESENT_STATE)) { |
270 | u32 fsl_prss = val; | |
271 | /* save the least 20 bits */ | |
272 | val = fsl_prss & 0x000FFFFF; | |
273 | /* move dat[0-3] bits */ | |
274 | val |= (fsl_prss & 0x0F000000) >> 4; | |
275 | /* move cmd line bit */ | |
276 | val |= (fsl_prss & 0x00800000) << 1; | |
277 | } | |
278 | ||
97e4ba6a | 279 | if (unlikely(reg == SDHCI_CAPABILITIES)) { |
6b4fb671 DA |
280 | /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ |
281 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
282 | val &= 0xffff0000; | |
283 | ||
97e4ba6a RZ |
284 | /* In FSL esdhc IC module, only bit20 is used to indicate the |
285 | * ADMA2 capability of esdhc, but this bit is messed up on | |
286 | * some SOCs (e.g. on MX25, MX35 this bit is set, but they | |
287 | * don't actually support ADMA2). So set the BROKEN_ADMA | |
288 | * uirk on MX25/35 platforms. | |
289 | */ | |
290 | ||
291 | if (val & SDHCI_CAN_DO_ADMA1) { | |
292 | val &= ~SDHCI_CAN_DO_ADMA1; | |
293 | val |= SDHCI_CAN_DO_ADMA2; | |
294 | } | |
295 | } | |
296 | ||
6e9fd28e DA |
297 | if (unlikely(reg == SDHCI_CAPABILITIES_1)) { |
298 | if (esdhc_is_usdhc(imx_data)) { | |
299 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
300 | val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; | |
301 | else | |
302 | /* imx6q/dl does not have cap_1 register, fake one */ | |
303 | val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 | |
888824bb | 304 | | SDHCI_SUPPORT_SDR50 |
da0295ff DA |
305 | | SDHCI_USE_SDR50_TUNING |
306 | | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); | |
28b07674 HC |
307 | |
308 | if (imx_data->socdata->flags & ESDHC_FLAG_HS400) | |
309 | val |= SDHCI_SUPPORT_HS400; | |
6e9fd28e DA |
310 | } |
311 | } | |
0322191e | 312 | |
9d61c009 | 313 | if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { |
0322191e DA |
314 | val = 0; |
315 | val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; | |
316 | val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; | |
317 | val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; | |
318 | } | |
319 | ||
97e4ba6a | 320 | if (unlikely(reg == SDHCI_INT_STATUS)) { |
60bf6396 SG |
321 | if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { |
322 | val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; | |
97e4ba6a RZ |
323 | val |= SDHCI_INT_ADMA_ERROR; |
324 | } | |
361b8482 LS |
325 | |
326 | /* | |
327 | * mask off the interrupt we get in response to the manually | |
328 | * sent CMD12 | |
329 | */ | |
330 | if ((imx_data->multiblock_status == WAIT_FOR_INT) && | |
331 | ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { | |
332 | val &= ~SDHCI_INT_RESPONSE; | |
333 | writel(SDHCI_INT_RESPONSE, host->ioaddr + | |
334 | SDHCI_INT_STATUS); | |
335 | imx_data->multiblock_status = NO_CMD_PENDING; | |
336 | } | |
97e4ba6a RZ |
337 | } |
338 | ||
7e29c306 WS |
339 | return val; |
340 | } | |
341 | ||
342 | static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) | |
343 | { | |
e149860d | 344 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 345 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
0d58864b TL |
346 | u32 data; |
347 | ||
348 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { | |
b7321042 | 349 | if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { |
0d58864b TL |
350 | /* |
351 | * Clear and then set D3CD bit to avoid missing the | |
352 | * card interrupt. This is a eSDHC controller problem | |
353 | * so we need to apply the following workaround: clear | |
354 | * and set D3CD bit will make eSDHC re-sample the card | |
355 | * interrupt. In case a card interrupt was lost, | |
356 | * re-sample it by the following steps. | |
357 | */ | |
358 | data = readl(host->ioaddr + SDHCI_HOST_CONTROL); | |
60bf6396 | 359 | data &= ~ESDHC_CTRL_D3CD; |
0d58864b | 360 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
60bf6396 | 361 | data |= ESDHC_CTRL_D3CD; |
0d58864b TL |
362 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
363 | } | |
915be485 DA |
364 | |
365 | if (val & SDHCI_INT_ADMA_ERROR) { | |
366 | val &= ~SDHCI_INT_ADMA_ERROR; | |
367 | val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; | |
368 | } | |
0d58864b | 369 | } |
7e29c306 | 370 | |
f47c4bbf | 371 | if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
372 | && (reg == SDHCI_INT_STATUS) |
373 | && (val & SDHCI_INT_DATA_END))) { | |
374 | u32 v; | |
60bf6396 SG |
375 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
376 | v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
377 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
361b8482 LS |
378 | |
379 | if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) | |
380 | { | |
381 | /* send a manual CMD12 with RESPTYP=none */ | |
382 | data = MMC_STOP_TRANSMISSION << 24 | | |
383 | SDHCI_CMD_ABORTCMD << 16; | |
384 | writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); | |
385 | imx_data->multiblock_status = WAIT_FOR_INT; | |
386 | } | |
58ac8177 RZ |
387 | } |
388 | ||
7e29c306 WS |
389 | writel(val, host->ioaddr + reg); |
390 | } | |
391 | ||
95f25efe WS |
392 | static u16 esdhc_readw_le(struct sdhci_host *host, int reg) |
393 | { | |
ef4d0888 | 394 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 395 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
0322191e DA |
396 | u16 ret = 0; |
397 | u32 val; | |
ef4d0888 | 398 | |
95a2482a | 399 | if (unlikely(reg == SDHCI_HOST_VERSION)) { |
ef4d0888 | 400 | reg ^= 2; |
9d61c009 | 401 | if (esdhc_is_usdhc(imx_data)) { |
ef4d0888 SG |
402 | /* |
403 | * The usdhc register returns a wrong host version. | |
404 | * Correct it here. | |
405 | */ | |
406 | return SDHCI_SPEC_300; | |
407 | } | |
95a2482a | 408 | } |
95f25efe | 409 | |
0322191e DA |
410 | if (unlikely(reg == SDHCI_HOST_CONTROL2)) { |
411 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
412 | if (val & ESDHC_VENDOR_SPEC_VSELECT) | |
413 | ret |= SDHCI_CTRL_VDD_180; | |
414 | ||
9d61c009 | 415 | if (esdhc_is_usdhc(imx_data)) { |
6e9fd28e DA |
416 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
417 | val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
418 | else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) | |
419 | /* the std tuning bits is in ACMD12_ERR for imx6sl */ | |
420 | val = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
0322191e DA |
421 | } |
422 | ||
6e9fd28e DA |
423 | if (val & ESDHC_MIX_CTRL_EXE_TUNE) |
424 | ret |= SDHCI_CTRL_EXEC_TUNING; | |
425 | if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) | |
426 | ret |= SDHCI_CTRL_TUNED_CLK; | |
427 | ||
0322191e DA |
428 | ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
429 | ||
430 | return ret; | |
431 | } | |
432 | ||
7dd109ef DA |
433 | if (unlikely(reg == SDHCI_TRANSFER_MODE)) { |
434 | if (esdhc_is_usdhc(imx_data)) { | |
435 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
436 | ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; | |
437 | /* Swap AC23 bit */ | |
438 | if (m & ESDHC_MIX_CTRL_AC23EN) { | |
439 | ret &= ~ESDHC_MIX_CTRL_AC23EN; | |
440 | ret |= SDHCI_TRNS_AUTO_CMD23; | |
441 | } | |
442 | } else { | |
443 | ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); | |
444 | } | |
445 | ||
446 | return ret; | |
447 | } | |
448 | ||
95f25efe WS |
449 | return readw(host->ioaddr + reg); |
450 | } | |
451 | ||
452 | static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) | |
453 | { | |
454 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 455 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
0322191e | 456 | u32 new_val = 0; |
95f25efe WS |
457 | |
458 | switch (reg) { | |
0322191e DA |
459 | case SDHCI_CLOCK_CONTROL: |
460 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
461 | if (val & SDHCI_CLOCK_CARD_EN) | |
462 | new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
463 | else | |
464 | new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
eeed7026 | 465 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); |
0322191e DA |
466 | return; |
467 | case SDHCI_HOST_CONTROL2: | |
468 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
469 | if (val & SDHCI_CTRL_VDD_180) | |
470 | new_val |= ESDHC_VENDOR_SPEC_VSELECT; | |
471 | else | |
472 | new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; | |
473 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); | |
6e9fd28e DA |
474 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { |
475 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
da0295ff | 476 | if (val & SDHCI_CTRL_TUNED_CLK) { |
6e9fd28e | 477 | new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; |
da0295ff DA |
478 | new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; |
479 | } else { | |
6e9fd28e | 480 | new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; |
da0295ff DA |
481 | new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; |
482 | } | |
6e9fd28e DA |
483 | writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); |
484 | } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { | |
485 | u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
486 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
8b2bb0ad DA |
487 | if (val & SDHCI_CTRL_TUNED_CLK) { |
488 | v |= ESDHC_MIX_CTRL_SMPCLK_SEL; | |
489 | } else { | |
490 | v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
491 | m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; | |
0b330e38 | 492 | m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; |
8b2bb0ad DA |
493 | } |
494 | ||
6e9fd28e | 495 | if (val & SDHCI_CTRL_EXEC_TUNING) { |
6e9fd28e DA |
496 | v |= ESDHC_MIX_CTRL_EXE_TUNE; |
497 | m |= ESDHC_MIX_CTRL_FBCLK_SEL; | |
0b330e38 | 498 | m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; |
6e9fd28e | 499 | } else { |
6e9fd28e | 500 | v &= ~ESDHC_MIX_CTRL_EXE_TUNE; |
6e9fd28e DA |
501 | } |
502 | ||
6e9fd28e DA |
503 | writel(v, host->ioaddr + SDHCI_ACMD12_ERR); |
504 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | |
505 | } | |
0322191e | 506 | return; |
95f25efe | 507 | case SDHCI_TRANSFER_MODE: |
f47c4bbf | 508 | if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
509 | && (host->cmd->opcode == SD_IO_RW_EXTENDED) |
510 | && (host->cmd->data->blocks > 1) | |
511 | && (host->cmd->data->flags & MMC_DATA_READ)) { | |
512 | u32 v; | |
60bf6396 SG |
513 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
514 | v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
515 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
58ac8177 | 516 | } |
69f54698 | 517 | |
9d61c009 | 518 | if (esdhc_is_usdhc(imx_data)) { |
69f54698 | 519 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
2a15f981 SG |
520 | /* Swap AC23 bit */ |
521 | if (val & SDHCI_TRNS_AUTO_CMD23) { | |
522 | val &= ~SDHCI_TRNS_AUTO_CMD23; | |
523 | val |= ESDHC_MIX_CTRL_AC23EN; | |
524 | } | |
525 | m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); | |
69f54698 SG |
526 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
527 | } else { | |
528 | /* | |
529 | * Postpone this write, we must do it together with a | |
530 | * command write that is down below. | |
531 | */ | |
532 | imx_data->scratchpad = val; | |
533 | } | |
95f25efe WS |
534 | return; |
535 | case SDHCI_COMMAND: | |
361b8482 | 536 | if (host->cmd->opcode == MMC_STOP_TRANSMISSION) |
58ac8177 | 537 | val |= SDHCI_CMD_ABORTCMD; |
95a2482a | 538 | |
361b8482 | 539 | if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && |
f47c4bbf | 540 | (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) |
361b8482 LS |
541 | imx_data->multiblock_status = MULTIBLK_IN_PROCESS; |
542 | ||
9d61c009 | 543 | if (esdhc_is_usdhc(imx_data)) |
95a2482a SG |
544 | writel(val << 16, |
545 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
69f54698 | 546 | else |
95a2482a SG |
547 | writel(val << 16 | imx_data->scratchpad, |
548 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
95f25efe WS |
549 | return; |
550 | case SDHCI_BLOCK_SIZE: | |
551 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); | |
552 | break; | |
553 | } | |
554 | esdhc_clrset_le(host, 0xffff, val, reg); | |
555 | } | |
556 | ||
557 | static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) | |
558 | { | |
9a0985b7 | 559 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 560 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
95f25efe | 561 | u32 new_val; |
af51079e | 562 | u32 mask; |
95f25efe WS |
563 | |
564 | switch (reg) { | |
565 | case SDHCI_POWER_CONTROL: | |
566 | /* | |
567 | * FSL put some DMA bits here | |
568 | * If your board has a regulator, code should be here | |
569 | */ | |
570 | return; | |
571 | case SDHCI_HOST_CONTROL: | |
6b40d182 | 572 | /* FSL messed up here, so we need to manually compose it. */ |
af51079e | 573 | new_val = val & SDHCI_CTRL_LED; |
7122bbb0 | 574 | /* ensure the endianness */ |
95f25efe | 575 | new_val |= ESDHC_HOST_CONTROL_LE; |
9a0985b7 WC |
576 | /* bits 8&9 are reserved on mx25 */ |
577 | if (!is_imx25_esdhc(imx_data)) { | |
578 | /* DMA mode bits are shifted */ | |
579 | new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; | |
580 | } | |
95f25efe | 581 | |
af51079e SH |
582 | /* |
583 | * Do not touch buswidth bits here. This is done in | |
584 | * esdhc_pltfm_bus_width. | |
f6825748 MF |
585 | * Do not touch the D3CD bit either which is used for the |
586 | * SDIO interrupt errata workaround. | |
af51079e | 587 | */ |
f6825748 | 588 | mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); |
af51079e SH |
589 | |
590 | esdhc_clrset_le(host, mask, new_val, reg); | |
95f25efe WS |
591 | return; |
592 | } | |
593 | esdhc_clrset_le(host, 0xff, val, reg); | |
913413c3 SG |
594 | |
595 | /* | |
596 | * The esdhc has a design violation to SDHC spec which tells | |
597 | * that software reset should not affect card detection circuit. | |
598 | * But esdhc clears its SYSCTL register bits [0..2] during the | |
599 | * software reset. This will stop those clocks that card detection | |
600 | * circuit relies on. To work around it, we turn the clocks on back | |
601 | * to keep card detection circuit functional. | |
602 | */ | |
58c8c4fb | 603 | if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { |
913413c3 | 604 | esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); |
58c8c4fb SG |
605 | /* |
606 | * The reset on usdhc fails to clear MIX_CTRL register. | |
607 | * Do it manually here. | |
608 | */ | |
de5bdbff | 609 | if (esdhc_is_usdhc(imx_data)) { |
d131a71c DA |
610 | /* the tuning bits should be kept during reset */ |
611 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
612 | writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, | |
613 | host->ioaddr + ESDHC_MIX_CTRL); | |
de5bdbff DA |
614 | imx_data->is_ddr = 0; |
615 | } | |
58c8c4fb | 616 | } |
95f25efe WS |
617 | } |
618 | ||
0ddf03c9 LS |
619 | static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) |
620 | { | |
621 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
0ddf03c9 | 622 | |
a3bd4f98 | 623 | return pltfm_host->clock; |
0ddf03c9 LS |
624 | } |
625 | ||
95f25efe WS |
626 | static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) |
627 | { | |
628 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
629 | ||
a974862f | 630 | return pltfm_host->clock / 256 / 16; |
95f25efe WS |
631 | } |
632 | ||
8ba9580a LS |
633 | static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, |
634 | unsigned int clock) | |
635 | { | |
636 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 637 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
a974862f | 638 | unsigned int host_clock = pltfm_host->clock; |
d31fc00a DA |
639 | int pre_div = 2; |
640 | int div = 1; | |
fed2f6e2 | 641 | u32 temp, val; |
d31fc00a | 642 | |
fed2f6e2 | 643 | if (clock == 0) { |
1650d0c7 RK |
644 | host->mmc->actual_clock = 0; |
645 | ||
9d61c009 | 646 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
647 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
648 | writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
649 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
650 | } | |
373073ef | 651 | return; |
fed2f6e2 | 652 | } |
d31fc00a | 653 | |
de5bdbff | 654 | if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) |
5f7886c5 DA |
655 | pre_div = 1; |
656 | ||
d31fc00a DA |
657 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
658 | temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
659 | | ESDHC_CLOCK_MASK); | |
660 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
661 | ||
662 | while (host_clock / pre_div / 16 > clock && pre_div < 256) | |
663 | pre_div *= 2; | |
664 | ||
665 | while (host_clock / pre_div / div > clock && div < 16) | |
666 | div++; | |
667 | ||
e76b8559 | 668 | host->mmc->actual_clock = host_clock / pre_div / div; |
d31fc00a | 669 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", |
e76b8559 | 670 | clock, host->mmc->actual_clock); |
d31fc00a | 671 | |
de5bdbff DA |
672 | if (imx_data->is_ddr) |
673 | pre_div >>= 2; | |
674 | else | |
675 | pre_div >>= 1; | |
d31fc00a DA |
676 | div--; |
677 | ||
678 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); | |
679 | temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
680 | | (div << ESDHC_DIVIDER_SHIFT) | |
681 | | (pre_div << ESDHC_PREDIV_SHIFT)); | |
682 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
fed2f6e2 | 683 | |
9d61c009 | 684 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
685 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
686 | writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
687 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
688 | } | |
689 | ||
d31fc00a | 690 | mdelay(1); |
8ba9580a LS |
691 | } |
692 | ||
913413c3 SG |
693 | static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) |
694 | { | |
842afc02 | 695 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 696 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
842afc02 | 697 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
913413c3 SG |
698 | |
699 | switch (boarddata->wp_type) { | |
700 | case ESDHC_WP_GPIO: | |
fbe5fdd1 | 701 | return mmc_gpio_get_ro(host->mmc); |
913413c3 SG |
702 | case ESDHC_WP_CONTROLLER: |
703 | return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & | |
704 | SDHCI_WRITE_PROTECT); | |
705 | case ESDHC_WP_NONE: | |
706 | break; | |
707 | } | |
708 | ||
709 | return -ENOSYS; | |
710 | } | |
711 | ||
2317f56c | 712 | static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) |
af51079e SH |
713 | { |
714 | u32 ctrl; | |
715 | ||
716 | switch (width) { | |
717 | case MMC_BUS_WIDTH_8: | |
718 | ctrl = ESDHC_CTRL_8BITBUS; | |
719 | break; | |
720 | case MMC_BUS_WIDTH_4: | |
721 | ctrl = ESDHC_CTRL_4BITBUS; | |
722 | break; | |
723 | default: | |
724 | ctrl = 0; | |
725 | break; | |
726 | } | |
727 | ||
728 | esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, | |
729 | SDHCI_HOST_CONTROL); | |
af51079e SH |
730 | } |
731 | ||
0322191e DA |
732 | static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) |
733 | { | |
734 | u32 reg; | |
735 | ||
736 | /* FIXME: delay a bit for card to be ready for next tuning due to errors */ | |
737 | mdelay(1); | |
738 | ||
739 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
740 | reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | | |
741 | ESDHC_MIX_CTRL_FBCLK_SEL; | |
742 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); | |
743 | writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); | |
744 | dev_dbg(mmc_dev(host->mmc), | |
745 | "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", | |
746 | val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); | |
747 | } | |
748 | ||
0322191e DA |
749 | static void esdhc_post_tuning(struct sdhci_host *host) |
750 | { | |
751 | u32 reg; | |
752 | ||
753 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
754 | reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; | |
da0295ff | 755 | reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; |
0322191e DA |
756 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); |
757 | } | |
758 | ||
759 | static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) | |
760 | { | |
761 | int min, max, avg, ret; | |
762 | ||
763 | /* find the mininum delay first which can pass tuning */ | |
764 | min = ESDHC_TUNE_CTRL_MIN; | |
765 | while (min < ESDHC_TUNE_CTRL_MAX) { | |
766 | esdhc_prepare_tuning(host, min); | |
9979dbe5 | 767 | if (!mmc_send_tuning(host->mmc, opcode, NULL)) |
0322191e DA |
768 | break; |
769 | min += ESDHC_TUNE_CTRL_STEP; | |
770 | } | |
771 | ||
772 | /* find the maxinum delay which can not pass tuning */ | |
773 | max = min + ESDHC_TUNE_CTRL_STEP; | |
774 | while (max < ESDHC_TUNE_CTRL_MAX) { | |
775 | esdhc_prepare_tuning(host, max); | |
9979dbe5 | 776 | if (mmc_send_tuning(host->mmc, opcode, NULL)) { |
0322191e DA |
777 | max -= ESDHC_TUNE_CTRL_STEP; |
778 | break; | |
779 | } | |
780 | max += ESDHC_TUNE_CTRL_STEP; | |
781 | } | |
782 | ||
783 | /* use average delay to get the best timing */ | |
784 | avg = (min + max) / 2; | |
785 | esdhc_prepare_tuning(host, avg); | |
9979dbe5 | 786 | ret = mmc_send_tuning(host->mmc, opcode, NULL); |
0322191e DA |
787 | esdhc_post_tuning(host); |
788 | ||
789 | dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", | |
790 | ret ? "failed" : "passed", avg, ret); | |
791 | ||
792 | return ret; | |
793 | } | |
794 | ||
ad93220d DA |
795 | static int esdhc_change_pinstate(struct sdhci_host *host, |
796 | unsigned int uhs) | |
797 | { | |
798 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 799 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
ad93220d DA |
800 | struct pinctrl_state *pinctrl; |
801 | ||
802 | dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); | |
803 | ||
804 | if (IS_ERR(imx_data->pinctrl) || | |
805 | IS_ERR(imx_data->pins_default) || | |
806 | IS_ERR(imx_data->pins_100mhz) || | |
807 | IS_ERR(imx_data->pins_200mhz)) | |
808 | return -EINVAL; | |
809 | ||
810 | switch (uhs) { | |
811 | case MMC_TIMING_UHS_SDR50: | |
812 | pinctrl = imx_data->pins_100mhz; | |
813 | break; | |
814 | case MMC_TIMING_UHS_SDR104: | |
429a5b45 | 815 | case MMC_TIMING_MMC_HS200: |
28b07674 | 816 | case MMC_TIMING_MMC_HS400: |
ad93220d DA |
817 | pinctrl = imx_data->pins_200mhz; |
818 | break; | |
819 | default: | |
820 | /* back to default state for other legacy timing */ | |
821 | pinctrl = imx_data->pins_default; | |
822 | } | |
823 | ||
824 | return pinctrl_select_state(imx_data->pinctrl, pinctrl); | |
825 | } | |
826 | ||
28b07674 HC |
827 | /* |
828 | * For HS400 eMMC, there is a data_strobe line, this signal is generated | |
829 | * by the device and used for data output and CRC status response output | |
830 | * in HS400 mode. The frequency of this signal follows the frequency of | |
831 | * CLK generated by host. Host receive the data which is aligned to the | |
832 | * edge of data_strobe line. Due to the time delay between CLK line and | |
833 | * data_strobe line, if the delay time is larger than one clock cycle, | |
834 | * then CLK and data_strobe line will misaligned, read error shows up. | |
835 | * So when the CLK is higher than 100MHz, each clock cycle is short enough, | |
836 | * host should config the delay target. | |
837 | */ | |
838 | static void esdhc_set_strobe_dll(struct sdhci_host *host) | |
839 | { | |
840 | u32 v; | |
841 | ||
842 | if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { | |
7ac6da26 DA |
843 | /* disable clock before enabling strobe dll */ |
844 | writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & | |
845 | ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
846 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
847 | ||
28b07674 HC |
848 | /* force a reset on strobe dll */ |
849 | writel(ESDHC_STROBE_DLL_CTRL_RESET, | |
850 | host->ioaddr + ESDHC_STROBE_DLL_CTRL); | |
851 | /* | |
852 | * enable strobe dll ctrl and adjust the delay target | |
853 | * for the uSDHC loopback read clock | |
854 | */ | |
855 | v = ESDHC_STROBE_DLL_CTRL_ENABLE | | |
856 | (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); | |
857 | writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); | |
858 | /* wait 1us to make sure strobe dll status register stable */ | |
859 | udelay(1); | |
860 | v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); | |
861 | if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) | |
862 | dev_warn(mmc_dev(host->mmc), | |
863 | "warning! HS400 strobe DLL status REF not lock!\n"); | |
864 | if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) | |
865 | dev_warn(mmc_dev(host->mmc), | |
866 | "warning! HS400 strobe DLL status SLV not lock!\n"); | |
867 | } | |
868 | } | |
869 | ||
850a29b8 | 870 | static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
ad93220d | 871 | { |
28b07674 | 872 | u32 m; |
ad93220d | 873 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 874 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
602519b2 | 875 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
ad93220d | 876 | |
28b07674 HC |
877 | /* disable ddr mode and disable HS400 mode */ |
878 | m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
879 | m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); | |
880 | imx_data->is_ddr = 0; | |
881 | ||
850a29b8 | 882 | switch (timing) { |
ad93220d | 883 | case MMC_TIMING_UHS_SDR12: |
ad93220d | 884 | case MMC_TIMING_UHS_SDR25: |
ad93220d | 885 | case MMC_TIMING_UHS_SDR50: |
ad93220d | 886 | case MMC_TIMING_UHS_SDR104: |
429a5b45 | 887 | case MMC_TIMING_MMC_HS200: |
28b07674 | 888 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
ad93220d DA |
889 | break; |
890 | case MMC_TIMING_UHS_DDR50: | |
69f5bf38 | 891 | case MMC_TIMING_MMC_DDR52: |
28b07674 HC |
892 | m |= ESDHC_MIX_CTRL_DDREN; |
893 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | |
de5bdbff | 894 | imx_data->is_ddr = 1; |
602519b2 DA |
895 | if (boarddata->delay_line) { |
896 | u32 v; | |
897 | v = boarddata->delay_line << | |
898 | ESDHC_DLL_OVERRIDE_VAL_SHIFT | | |
899 | (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); | |
900 | if (is_imx53_esdhc(imx_data)) | |
901 | v <<= 1; | |
902 | writel(v, host->ioaddr + ESDHC_DLL_CTRL); | |
903 | } | |
ad93220d | 904 | break; |
28b07674 HC |
905 | case MMC_TIMING_MMC_HS400: |
906 | m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; | |
907 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | |
908 | imx_data->is_ddr = 1; | |
7ac6da26 DA |
909 | /* update clock after enable DDR for strobe DLL lock */ |
910 | host->ops->set_clock(host, host->clock); | |
28b07674 HC |
911 | esdhc_set_strobe_dll(host); |
912 | break; | |
ad93220d DA |
913 | } |
914 | ||
850a29b8 | 915 | esdhc_change_pinstate(host, timing); |
ad93220d DA |
916 | } |
917 | ||
0718e59a RK |
918 | static void esdhc_reset(struct sdhci_host *host, u8 mask) |
919 | { | |
920 | sdhci_reset(host, mask); | |
921 | ||
922 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
923 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
924 | } | |
925 | ||
10fd0ad9 AD |
926 | static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) |
927 | { | |
928 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 929 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
10fd0ad9 AD |
930 | |
931 | return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; | |
932 | } | |
933 | ||
e33eb8e2 AD |
934 | static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
935 | { | |
936 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 937 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
e33eb8e2 AD |
938 | |
939 | /* use maximum timeout counter */ | |
940 | sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, | |
941 | SDHCI_TIMEOUT_CONTROL); | |
942 | } | |
943 | ||
6e9fd28e | 944 | static struct sdhci_ops sdhci_esdhc_ops = { |
e149860d | 945 | .read_l = esdhc_readl_le, |
0c6d49ce | 946 | .read_w = esdhc_readw_le, |
e149860d | 947 | .write_l = esdhc_writel_le, |
0c6d49ce WS |
948 | .write_w = esdhc_writew_le, |
949 | .write_b = esdhc_writeb_le, | |
8ba9580a | 950 | .set_clock = esdhc_pltfm_set_clock, |
0ddf03c9 | 951 | .get_max_clock = esdhc_pltfm_get_max_clock, |
0c6d49ce | 952 | .get_min_clock = esdhc_pltfm_get_min_clock, |
10fd0ad9 | 953 | .get_max_timeout_count = esdhc_get_max_timeout_count, |
913413c3 | 954 | .get_ro = esdhc_pltfm_get_ro, |
e33eb8e2 | 955 | .set_timeout = esdhc_set_timeout, |
2317f56c | 956 | .set_bus_width = esdhc_pltfm_set_bus_width, |
ad93220d | 957 | .set_uhs_signaling = esdhc_set_uhs_signaling, |
0718e59a | 958 | .reset = esdhc_reset, |
0c6d49ce WS |
959 | }; |
960 | ||
1db5eebf | 961 | static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { |
97e4ba6a RZ |
962 | .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT |
963 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | |
964 | | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
85d6509d | 965 | | SDHCI_QUIRK_BROKEN_CARD_DETECTION, |
85d6509d SG |
966 | .ops = &sdhci_esdhc_ops, |
967 | }; | |
968 | ||
f3f5cf3d DA |
969 | static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) |
970 | { | |
971 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
972 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); | |
2b16cf32 | 973 | int tmp; |
f3f5cf3d DA |
974 | |
975 | if (esdhc_is_usdhc(imx_data)) { | |
976 | /* | |
977 | * The imx6q ROM code will change the default watermark | |
978 | * level setting to something insane. Change it back here. | |
979 | */ | |
980 | writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); | |
981 | ||
982 | /* | |
983 | * ROM code will change the bit burst_length_enable setting | |
984 | * to zero if this usdhc is choosed to boot system. Change | |
985 | * it back here, otherwise it will impact the performance a | |
986 | * lot. This bit is used to enable/disable the burst length | |
987 | * for the external AHB2AXI bridge, it's usefully especially | |
988 | * for INCR transfer because without burst length indicator, | |
989 | * the AHB2AXI bridge does not know the burst length in | |
990 | * advance. And without burst length indicator, AHB INCR | |
991 | * transfer can only be converted to singles on the AXI side. | |
992 | */ | |
993 | writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) | |
994 | | ESDHC_BURST_LEN_EN_INCR, | |
995 | host->ioaddr + SDHCI_HOST_CONTROL); | |
996 | /* | |
997 | * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL | |
998 | * TO1.1, it's harmless for MX6SL | |
999 | */ | |
1000 | writel(readl(host->ioaddr + 0x6c) | BIT(7), | |
1001 | host->ioaddr + 0x6c); | |
1002 | ||
1003 | /* disable DLL_CTRL delay line settings */ | |
1004 | writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); | |
2b16cf32 DA |
1005 | |
1006 | if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { | |
1007 | tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); | |
1008 | tmp |= ESDHC_STD_TUNING_EN | | |
1009 | ESDHC_TUNING_START_TAP_DEFAULT; | |
1010 | if (imx_data->boarddata.tuning_start_tap) { | |
1011 | tmp &= ~ESDHC_TUNING_START_TAP_MASK; | |
1012 | tmp |= imx_data->boarddata.tuning_start_tap; | |
1013 | } | |
1014 | ||
1015 | if (imx_data->boarddata.tuning_step) { | |
1016 | tmp &= ~ESDHC_TUNING_STEP_MASK; | |
1017 | tmp |= imx_data->boarddata.tuning_step | |
1018 | << ESDHC_TUNING_STEP_SHIFT; | |
1019 | } | |
1020 | writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); | |
1021 | } | |
f3f5cf3d DA |
1022 | } |
1023 | } | |
1024 | ||
abfafc2d | 1025 | #ifdef CONFIG_OF |
c3be1efd | 1026 | static int |
abfafc2d | 1027 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, |
07bf2b54 | 1028 | struct sdhci_host *host, |
91fa4252 | 1029 | struct pltfm_imx_data *imx_data) |
abfafc2d SG |
1030 | { |
1031 | struct device_node *np = pdev->dev.of_node; | |
91fa4252 | 1032 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
4800e87a | 1033 | int ret; |
abfafc2d | 1034 | |
abfafc2d SG |
1035 | if (of_get_property(np, "fsl,wp-controller", NULL)) |
1036 | boarddata->wp_type = ESDHC_WP_CONTROLLER; | |
1037 | ||
abfafc2d SG |
1038 | boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); |
1039 | if (gpio_is_valid(boarddata->wp_gpio)) | |
1040 | boarddata->wp_type = ESDHC_WP_GPIO; | |
1041 | ||
d407e30b | 1042 | of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); |
d87fc966 DA |
1043 | of_property_read_u32(np, "fsl,tuning-start-tap", |
1044 | &boarddata->tuning_start_tap); | |
d407e30b | 1045 | |
ad93220d DA |
1046 | if (of_find_property(np, "no-1-8-v", NULL)) |
1047 | boarddata->support_vsel = false; | |
1048 | else | |
1049 | boarddata->support_vsel = true; | |
1050 | ||
602519b2 DA |
1051 | if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) |
1052 | boarddata->delay_line = 0; | |
1053 | ||
07bf2b54 SH |
1054 | mmc_of_parse_voltage(np, &host->ocr_mask); |
1055 | ||
91fa4252 DA |
1056 | /* sdr50 and sdr104 needs work on 1.8v signal voltage */ |
1057 | if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && | |
1058 | !IS_ERR(imx_data->pins_default)) { | |
1059 | imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, | |
1060 | ESDHC_PINCTRL_STATE_100MHZ); | |
1061 | imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, | |
1062 | ESDHC_PINCTRL_STATE_200MHZ); | |
1063 | if (IS_ERR(imx_data->pins_100mhz) || | |
1064 | IS_ERR(imx_data->pins_200mhz)) { | |
1065 | dev_warn(mmc_dev(host->mmc), | |
1066 | "could not get ultra high speed state, work on normal mode\n"); | |
1067 | /* | |
1068 | * fall back to not support uhs by specify no 1.8v quirk | |
1069 | */ | |
1070 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
1071 | } | |
1072 | } else { | |
1073 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
1074 | } | |
1075 | ||
15064119 | 1076 | /* call to generic mmc_of_parse to support additional capabilities */ |
4800e87a DA |
1077 | ret = mmc_of_parse(host->mmc); |
1078 | if (ret) | |
1079 | return ret; | |
1080 | ||
287980e4 | 1081 | if (mmc_gpio_get_cd(host->mmc) >= 0) |
4800e87a DA |
1082 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
1083 | ||
1084 | return 0; | |
abfafc2d SG |
1085 | } |
1086 | #else | |
1087 | static inline int | |
1088 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, | |
07bf2b54 | 1089 | struct sdhci_host *host, |
91fa4252 | 1090 | struct pltfm_imx_data *imx_data) |
abfafc2d SG |
1091 | { |
1092 | return -ENODEV; | |
1093 | } | |
1094 | #endif | |
1095 | ||
91fa4252 DA |
1096 | static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, |
1097 | struct sdhci_host *host, | |
1098 | struct pltfm_imx_data *imx_data) | |
1099 | { | |
1100 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | |
1101 | int err; | |
1102 | ||
1103 | if (!host->mmc->parent->platform_data) { | |
1104 | dev_err(mmc_dev(host->mmc), "no board data!\n"); | |
1105 | return -EINVAL; | |
1106 | } | |
1107 | ||
1108 | imx_data->boarddata = *((struct esdhc_platform_data *) | |
1109 | host->mmc->parent->platform_data); | |
1110 | /* write_protect */ | |
1111 | if (boarddata->wp_type == ESDHC_WP_GPIO) { | |
1112 | err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); | |
1113 | if (err) { | |
1114 | dev_err(mmc_dev(host->mmc), | |
1115 | "failed to request write-protect gpio!\n"); | |
1116 | return err; | |
1117 | } | |
1118 | host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; | |
1119 | } | |
1120 | ||
1121 | /* card_detect */ | |
1122 | switch (boarddata->cd_type) { | |
1123 | case ESDHC_CD_GPIO: | |
1124 | err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); | |
1125 | if (err) { | |
1126 | dev_err(mmc_dev(host->mmc), | |
1127 | "failed to request card-detect gpio!\n"); | |
1128 | return err; | |
1129 | } | |
1130 | /* fall through */ | |
1131 | ||
1132 | case ESDHC_CD_CONTROLLER: | |
1133 | /* we have a working card_detect back */ | |
1134 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
1135 | break; | |
1136 | ||
1137 | case ESDHC_CD_PERMANENT: | |
1138 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; | |
1139 | break; | |
1140 | ||
1141 | case ESDHC_CD_NONE: | |
1142 | break; | |
1143 | } | |
1144 | ||
1145 | switch (boarddata->max_bus_width) { | |
1146 | case 8: | |
1147 | host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; | |
1148 | break; | |
1149 | case 4: | |
1150 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1151 | break; | |
1152 | case 1: | |
1153 | default: | |
1154 | host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; | |
1155 | break; | |
1156 | } | |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | ||
c3be1efd | 1161 | static int sdhci_esdhc_imx_probe(struct platform_device *pdev) |
95f25efe | 1162 | { |
abfafc2d SG |
1163 | const struct of_device_id *of_id = |
1164 | of_match_device(imx_esdhc_dt_ids, &pdev->dev); | |
85d6509d SG |
1165 | struct sdhci_pltfm_host *pltfm_host; |
1166 | struct sdhci_host *host; | |
0c6d49ce | 1167 | int err; |
e149860d | 1168 | struct pltfm_imx_data *imx_data; |
95f25efe | 1169 | |
070e6d3f JZ |
1170 | host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, |
1171 | sizeof(*imx_data)); | |
85d6509d SG |
1172 | if (IS_ERR(host)) |
1173 | return PTR_ERR(host); | |
1174 | ||
1175 | pltfm_host = sdhci_priv(host); | |
1176 | ||
070e6d3f | 1177 | imx_data = sdhci_pltfm_priv(pltfm_host); |
57ed3314 | 1178 | |
f47c4bbf SG |
1179 | imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) |
1180 | pdev->id_entry->driver_data; | |
85d6509d | 1181 | |
52dac615 SH |
1182 | imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1183 | if (IS_ERR(imx_data->clk_ipg)) { | |
1184 | err = PTR_ERR(imx_data->clk_ipg); | |
e3af31c6 | 1185 | goto free_sdhci; |
95f25efe | 1186 | } |
52dac615 SH |
1187 | |
1188 | imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
1189 | if (IS_ERR(imx_data->clk_ahb)) { | |
1190 | err = PTR_ERR(imx_data->clk_ahb); | |
e3af31c6 | 1191 | goto free_sdhci; |
52dac615 SH |
1192 | } |
1193 | ||
1194 | imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); | |
1195 | if (IS_ERR(imx_data->clk_per)) { | |
1196 | err = PTR_ERR(imx_data->clk_per); | |
e3af31c6 | 1197 | goto free_sdhci; |
52dac615 SH |
1198 | } |
1199 | ||
1200 | pltfm_host->clk = imx_data->clk_per; | |
a974862f | 1201 | pltfm_host->clock = clk_get_rate(pltfm_host->clk); |
52dac615 SH |
1202 | clk_prepare_enable(imx_data->clk_per); |
1203 | clk_prepare_enable(imx_data->clk_ipg); | |
1204 | clk_prepare_enable(imx_data->clk_ahb); | |
95f25efe | 1205 | |
ad93220d | 1206 | imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); |
e62d8b8f DA |
1207 | if (IS_ERR(imx_data->pinctrl)) { |
1208 | err = PTR_ERR(imx_data->pinctrl); | |
e3af31c6 | 1209 | goto disable_clk; |
e62d8b8f DA |
1210 | } |
1211 | ||
ad93220d DA |
1212 | imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, |
1213 | PINCTRL_STATE_DEFAULT); | |
cd529af7 DB |
1214 | if (IS_ERR(imx_data->pins_default)) |
1215 | dev_warn(mmc_dev(host->mmc), "could not get default state\n"); | |
ad93220d | 1216 | |
f47c4bbf | 1217 | if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) |
0c6d49ce | 1218 | /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ |
97e4ba6a RZ |
1219 | host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK |
1220 | | SDHCI_QUIRK_BROKEN_ADMA; | |
0c6d49ce | 1221 | |
69ed60e0 | 1222 | if (esdhc_is_usdhc(imx_data)) { |
69ed60e0 | 1223 | host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; |
e2997c94 | 1224 | host->mmc->caps |= MMC_CAP_1_8V_DDR; |
4245afff DA |
1225 | if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) |
1226 | host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; | |
a75dcbf4 DA |
1227 | |
1228 | /* clear tuning bits in case ROM has set it already */ | |
1229 | writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); | |
1230 | writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR); | |
1231 | writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); | |
69ed60e0 | 1232 | } |
f750ba9b | 1233 | |
6e9fd28e DA |
1234 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
1235 | sdhci_esdhc_ops.platform_execute_tuning = | |
1236 | esdhc_executing_tuning; | |
8b2bb0ad | 1237 | |
18094430 DA |
1238 | if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) |
1239 | host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; | |
1240 | ||
28b07674 HC |
1241 | if (imx_data->socdata->flags & ESDHC_FLAG_HS400) |
1242 | host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; | |
1243 | ||
91fa4252 DA |
1244 | if (of_id) |
1245 | err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); | |
1246 | else | |
1247 | err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); | |
1248 | if (err) | |
1249 | goto disable_clk; | |
ad93220d | 1250 | |
f3f5cf3d DA |
1251 | sdhci_esdhc_imx_hwinit(host); |
1252 | ||
85d6509d SG |
1253 | err = sdhci_add_host(host); |
1254 | if (err) | |
e3af31c6 | 1255 | goto disable_clk; |
85d6509d | 1256 | |
89d7e5c1 | 1257 | pm_runtime_set_active(&pdev->dev); |
89d7e5c1 DA |
1258 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1259 | pm_runtime_use_autosuspend(&pdev->dev); | |
1260 | pm_suspend_ignore_children(&pdev->dev, 1); | |
77903c01 | 1261 | pm_runtime_enable(&pdev->dev); |
89d7e5c1 | 1262 | |
95f25efe | 1263 | return 0; |
7e29c306 | 1264 | |
e3af31c6 | 1265 | disable_clk: |
52dac615 SH |
1266 | clk_disable_unprepare(imx_data->clk_per); |
1267 | clk_disable_unprepare(imx_data->clk_ipg); | |
1268 | clk_disable_unprepare(imx_data->clk_ahb); | |
e3af31c6 | 1269 | free_sdhci: |
85d6509d SG |
1270 | sdhci_pltfm_free(pdev); |
1271 | return err; | |
95f25efe WS |
1272 | } |
1273 | ||
6e0ee714 | 1274 | static int sdhci_esdhc_imx_remove(struct platform_device *pdev) |
95f25efe | 1275 | { |
85d6509d | 1276 | struct sdhci_host *host = platform_get_drvdata(pdev); |
95f25efe | 1277 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 1278 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
85d6509d SG |
1279 | int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
1280 | ||
0b414368 | 1281 | pm_runtime_get_sync(&pdev->dev); |
89d7e5c1 | 1282 | pm_runtime_disable(&pdev->dev); |
0b414368 | 1283 | pm_runtime_put_noidle(&pdev->dev); |
89d7e5c1 | 1284 | |
0b414368 UH |
1285 | sdhci_remove_host(host, dead); |
1286 | ||
1287 | clk_disable_unprepare(imx_data->clk_per); | |
1288 | clk_disable_unprepare(imx_data->clk_ipg); | |
1289 | clk_disable_unprepare(imx_data->clk_ahb); | |
52dac615 | 1290 | |
85d6509d SG |
1291 | sdhci_pltfm_free(pdev); |
1292 | ||
1293 | return 0; | |
95f25efe WS |
1294 | } |
1295 | ||
2788ed42 | 1296 | #ifdef CONFIG_PM_SLEEP |
04143fba DA |
1297 | static int sdhci_esdhc_suspend(struct device *dev) |
1298 | { | |
3e3274ab UH |
1299 | struct sdhci_host *host = dev_get_drvdata(dev); |
1300 | ||
1301 | return sdhci_suspend_host(host); | |
04143fba DA |
1302 | } |
1303 | ||
1304 | static int sdhci_esdhc_resume(struct device *dev) | |
1305 | { | |
cc17e129 | 1306 | struct sdhci_host *host = dev_get_drvdata(dev); |
cc17e129 | 1307 | |
19dbfdd3 DA |
1308 | /* re-initialize hw state in case it's lost in low power mode */ |
1309 | sdhci_esdhc_imx_hwinit(host); | |
cc17e129 | 1310 | |
3e3274ab | 1311 | return sdhci_resume_host(host); |
04143fba | 1312 | } |
2788ed42 | 1313 | #endif |
04143fba | 1314 | |
2788ed42 | 1315 | #ifdef CONFIG_PM |
89d7e5c1 DA |
1316 | static int sdhci_esdhc_runtime_suspend(struct device *dev) |
1317 | { | |
1318 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1319 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 1320 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
89d7e5c1 DA |
1321 | int ret; |
1322 | ||
1323 | ret = sdhci_runtime_suspend_host(host); | |
1324 | ||
be138554 RK |
1325 | if (!sdhci_sdio_irq_enabled(host)) { |
1326 | clk_disable_unprepare(imx_data->clk_per); | |
1327 | clk_disable_unprepare(imx_data->clk_ipg); | |
1328 | } | |
89d7e5c1 DA |
1329 | clk_disable_unprepare(imx_data->clk_ahb); |
1330 | ||
1331 | return ret; | |
1332 | } | |
1333 | ||
1334 | static int sdhci_esdhc_runtime_resume(struct device *dev) | |
1335 | { | |
1336 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1337 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 1338 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
89d7e5c1 | 1339 | |
be138554 RK |
1340 | if (!sdhci_sdio_irq_enabled(host)) { |
1341 | clk_prepare_enable(imx_data->clk_per); | |
1342 | clk_prepare_enable(imx_data->clk_ipg); | |
1343 | } | |
89d7e5c1 DA |
1344 | clk_prepare_enable(imx_data->clk_ahb); |
1345 | ||
1346 | return sdhci_runtime_resume_host(host); | |
1347 | } | |
1348 | #endif | |
1349 | ||
1350 | static const struct dev_pm_ops sdhci_esdhc_pmops = { | |
04143fba | 1351 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) |
89d7e5c1 DA |
1352 | SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, |
1353 | sdhci_esdhc_runtime_resume, NULL) | |
1354 | }; | |
1355 | ||
85d6509d SG |
1356 | static struct platform_driver sdhci_esdhc_imx_driver = { |
1357 | .driver = { | |
1358 | .name = "sdhci-esdhc-imx", | |
abfafc2d | 1359 | .of_match_table = imx_esdhc_dt_ids, |
89d7e5c1 | 1360 | .pm = &sdhci_esdhc_pmops, |
85d6509d | 1361 | }, |
57ed3314 | 1362 | .id_table = imx_esdhc_devtype, |
85d6509d | 1363 | .probe = sdhci_esdhc_imx_probe, |
0433c143 | 1364 | .remove = sdhci_esdhc_imx_remove, |
95f25efe | 1365 | }; |
85d6509d | 1366 | |
d1f81a64 | 1367 | module_platform_driver(sdhci_esdhc_imx_driver); |
85d6509d SG |
1368 | |
1369 | MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); | |
035ff831 | 1370 | MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); |
85d6509d | 1371 | MODULE_LICENSE("GPL v2"); |