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b580c52d SB |
1 | /* |
2 | * Copyright (C) 2014 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation version 2. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | /* | |
15 | * iProc SDHCI platform driver | |
16 | */ | |
17 | ||
18 | #include <linux/delay.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/mmc/host.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_device.h> | |
23 | #include "sdhci-pltfm.h" | |
24 | ||
25 | struct sdhci_iproc_data { | |
26 | const struct sdhci_pltfm_data *pdata; | |
27 | u32 caps; | |
28 | u32 caps1; | |
b17b4ab8 | 29 | u32 mmc_caps; |
b580c52d SB |
30 | }; |
31 | ||
32 | struct sdhci_iproc_host { | |
33 | const struct sdhci_iproc_data *data; | |
34 | u32 shadow_cmd; | |
35 | u32 shadow_blk; | |
36 | }; | |
37 | ||
38 | #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) | |
39 | ||
40 | static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg) | |
41 | { | |
42 | u32 val = readl(host->ioaddr + reg); | |
43 | ||
44 | pr_debug("%s: readl [0x%02x] 0x%08x\n", | |
45 | mmc_hostname(host->mmc), reg, val); | |
46 | return val; | |
47 | } | |
48 | ||
49 | static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg) | |
50 | { | |
51 | u32 val = sdhci_iproc_readl(host, (reg & ~3)); | |
52 | u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff; | |
53 | return word; | |
54 | } | |
55 | ||
56 | static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg) | |
57 | { | |
58 | u32 val = sdhci_iproc_readl(host, (reg & ~3)); | |
59 | u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff; | |
60 | return byte; | |
61 | } | |
62 | ||
63 | static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg) | |
64 | { | |
65 | pr_debug("%s: writel [0x%02x] 0x%08x\n", | |
66 | mmc_hostname(host->mmc), reg, val); | |
67 | ||
68 | writel(val, host->ioaddr + reg); | |
69 | ||
70 | if (host->clock <= 400000) { | |
71 | /* Round up to micro-second four SD clock delay */ | |
72 | if (host->clock) | |
73 | udelay((4 * 1000000 + host->clock - 1) / host->clock); | |
74 | else | |
75 | udelay(10); | |
76 | } | |
77 | } | |
78 | ||
79 | /* | |
80 | * The Arasan has a bugette whereby it may lose the content of successive | |
81 | * writes to the same register that are within two SD-card clock cycles of | |
82 | * each other (a clock domain crossing problem). The data | |
83 | * register does not have this problem, which is just as well - otherwise we'd | |
84 | * have to nobble the DMA engine too. | |
85 | * | |
86 | * This wouldn't be a problem with the code except that we can only write the | |
87 | * controller with 32-bit writes. So two different 16-bit registers are | |
88 | * written back to back creates the problem. | |
89 | * | |
90 | * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT | |
91 | * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND. | |
92 | * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so | |
93 | * the work around can be further optimized. We can keep shadow values of | |
94 | * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued. | |
95 | * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed | |
96 | * by the TRANSFER+COMMAND in another 32-bit write. | |
97 | */ | |
98 | static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg) | |
99 | { | |
100 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
b1ddaa3d | 101 | struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host); |
b580c52d SB |
102 | u32 word_shift = REG_OFFSET_IN_BITS(reg); |
103 | u32 mask = 0xffff << word_shift; | |
104 | u32 oldval, newval; | |
105 | ||
106 | if (reg == SDHCI_COMMAND) { | |
107 | /* Write the block now as we are issuing a command */ | |
108 | if (iproc_host->shadow_blk != 0) { | |
109 | sdhci_iproc_writel(host, iproc_host->shadow_blk, | |
110 | SDHCI_BLOCK_SIZE); | |
111 | iproc_host->shadow_blk = 0; | |
112 | } | |
113 | oldval = iproc_host->shadow_cmd; | |
114 | } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) { | |
115 | /* Block size and count are stored in shadow reg */ | |
116 | oldval = iproc_host->shadow_blk; | |
117 | } else { | |
118 | /* Read reg, all other registers are not shadowed */ | |
119 | oldval = sdhci_iproc_readl(host, (reg & ~3)); | |
120 | } | |
121 | newval = (oldval & ~mask) | (val << word_shift); | |
122 | ||
123 | if (reg == SDHCI_TRANSFER_MODE) { | |
124 | /* Save the transfer mode until the command is issued */ | |
125 | iproc_host->shadow_cmd = newval; | |
126 | } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) { | |
127 | /* Save the block info until the command is issued */ | |
128 | iproc_host->shadow_blk = newval; | |
129 | } else { | |
130 | /* Command or other regular 32-bit write */ | |
131 | sdhci_iproc_writel(host, newval, reg & ~3); | |
132 | } | |
133 | } | |
134 | ||
135 | static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg) | |
136 | { | |
137 | u32 oldval = sdhci_iproc_readl(host, (reg & ~3)); | |
138 | u32 byte_shift = REG_OFFSET_IN_BITS(reg); | |
139 | u32 mask = 0xff << byte_shift; | |
140 | u32 newval = (oldval & ~mask) | (val << byte_shift); | |
141 | ||
142 | sdhci_iproc_writel(host, newval, reg & ~3); | |
143 | } | |
144 | ||
145 | static const struct sdhci_ops sdhci_iproc_ops = { | |
146 | .read_l = sdhci_iproc_readl, | |
147 | .read_w = sdhci_iproc_readw, | |
148 | .read_b = sdhci_iproc_readb, | |
149 | .write_l = sdhci_iproc_writel, | |
150 | .write_w = sdhci_iproc_writew, | |
151 | .write_b = sdhci_iproc_writeb, | |
152 | .set_clock = sdhci_set_clock, | |
153 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | |
154 | .set_bus_width = sdhci_set_bus_width, | |
155 | .reset = sdhci_reset, | |
156 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
157 | }; | |
158 | ||
159 | static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = { | |
160 | .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, | |
161 | .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN, | |
162 | .ops = &sdhci_iproc_ops, | |
163 | }; | |
164 | ||
165 | static const struct sdhci_iproc_data iproc_data = { | |
166 | .pdata = &sdhci_iproc_pltfm_data, | |
167 | .caps = 0x05E90000, | |
168 | .caps1 = 0x00000064, | |
b17b4ab8 | 169 | .mmc_caps = MMC_CAP_1_8V_DDR, |
b580c52d SB |
170 | }; |
171 | ||
77cb7d3a SW |
172 | static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = { |
173 | .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | | |
174 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | | |
175 | SDHCI_QUIRK_MISSING_CAPS, | |
176 | .ops = &sdhci_iproc_ops, | |
177 | }; | |
178 | ||
179 | static const struct sdhci_iproc_data bcm2835_data = { | |
180 | .pdata = &sdhci_bcm2835_pltfm_data, | |
181 | .caps = SDHCI_CAN_VDD_330, | |
182 | .caps1 = 0x00000000, | |
183 | .mmc_caps = 0x00000000, | |
184 | }; | |
185 | ||
b580c52d | 186 | static const struct of_device_id sdhci_iproc_of_match[] = { |
77cb7d3a | 187 | { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data }, |
b580c52d SB |
188 | { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_data }, |
189 | { } | |
190 | }; | |
191 | MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match); | |
192 | ||
193 | static int sdhci_iproc_probe(struct platform_device *pdev) | |
194 | { | |
195 | const struct of_device_id *match; | |
196 | const struct sdhci_iproc_data *iproc_data; | |
197 | struct sdhci_host *host; | |
198 | struct sdhci_iproc_host *iproc_host; | |
199 | struct sdhci_pltfm_host *pltfm_host; | |
200 | int ret; | |
201 | ||
202 | match = of_match_device(sdhci_iproc_of_match, &pdev->dev); | |
203 | if (!match) | |
204 | return -EINVAL; | |
205 | iproc_data = match->data; | |
206 | ||
207 | host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host)); | |
208 | if (IS_ERR(host)) | |
209 | return PTR_ERR(host); | |
210 | ||
211 | pltfm_host = sdhci_priv(host); | |
212 | iproc_host = sdhci_pltfm_priv(pltfm_host); | |
213 | ||
214 | iproc_host->data = iproc_data; | |
215 | ||
216 | mmc_of_parse(host->mmc); | |
217 | sdhci_get_of_property(pdev); | |
218 | ||
b17b4ab8 | 219 | host->mmc->caps |= iproc_host->data->mmc_caps; |
b580c52d SB |
220 | |
221 | pltfm_host->clk = devm_clk_get(&pdev->dev, NULL); | |
222 | if (IS_ERR(pltfm_host->clk)) { | |
223 | ret = PTR_ERR(pltfm_host->clk); | |
224 | goto err; | |
225 | } | |
9f24b0f2 SW |
226 | ret = clk_prepare_enable(pltfm_host->clk); |
227 | if (ret) { | |
228 | dev_err(&pdev->dev, "failed to enable host clk\n"); | |
229 | goto err; | |
230 | } | |
b580c52d SB |
231 | |
232 | if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) { | |
233 | host->caps = iproc_host->data->caps; | |
234 | host->caps1 = iproc_host->data->caps1; | |
235 | } | |
236 | ||
1d6ad057 SW |
237 | ret = sdhci_add_host(host); |
238 | if (ret) | |
9f24b0f2 | 239 | goto err_clk; |
1d6ad057 SW |
240 | |
241 | return 0; | |
b580c52d | 242 | |
9f24b0f2 SW |
243 | err_clk: |
244 | clk_disable_unprepare(pltfm_host->clk); | |
b580c52d SB |
245 | err: |
246 | sdhci_pltfm_free(pdev); | |
247 | return ret; | |
248 | } | |
249 | ||
b580c52d SB |
250 | static struct platform_driver sdhci_iproc_driver = { |
251 | .driver = { | |
252 | .name = "sdhci-iproc", | |
253 | .of_match_table = sdhci_iproc_of_match, | |
254 | .pm = SDHCI_PLTFM_PMOPS, | |
255 | }, | |
256 | .probe = sdhci_iproc_probe, | |
d1a13c5e | 257 | .remove = sdhci_pltfm_unregister, |
b580c52d SB |
258 | }; |
259 | module_platform_driver(sdhci_iproc_driver); | |
260 | ||
261 | MODULE_AUTHOR("Broadcom"); | |
262 | MODULE_DESCRIPTION("IPROC SDHCI driver"); | |
263 | MODULE_LICENSE("GPL v2"); |