Commit | Line | Data |
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e3ec3a3d SB |
1 | /* |
2 | * Arasan Secure Digital Host Controller Interface. | |
3 | * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> | |
4 | * Copyright (c) 2012 Wind River Systems, Inc. | |
5 | * Copyright (C) 2013 Pengutronix e.K. | |
6 | * Copyright (C) 2013 Xilinx Inc. | |
7 | * | |
8 | * Based on sdhci-of-esdhc.c | |
9 | * | |
10 | * Copyright (c) 2007 Freescale Semiconductor, Inc. | |
11 | * Copyright (c) 2009 MontaVista Software, Inc. | |
12 | * | |
13 | * Authors: Xiaobo Xie <X.Xie@freescale.com> | |
14 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or (at | |
19 | * your option) any later version. | |
20 | */ | |
21 | ||
c390f211 | 22 | #include <linux/clk-provider.h> |
3ea4666e | 23 | #include <linux/mfd/syscon.h> |
e3ec3a3d | 24 | #include <linux/module.h> |
308f3f8d | 25 | #include <linux/of_device.h> |
91aa3661 | 26 | #include <linux/phy/phy.h> |
3ea4666e | 27 | #include <linux/regmap.h> |
e3ec3a3d SB |
28 | #include "sdhci-pltfm.h" |
29 | ||
30 | #define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c | |
a05c8465 | 31 | #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 |
e3ec3a3d | 32 | |
a05c8465 | 33 | #define VENDOR_ENHANCED_STROBE BIT(0) |
e3ec3a3d SB |
34 | #define CLK_CTRL_TIMEOUT_SHIFT 16 |
35 | #define CLK_CTRL_TIMEOUT_MASK (0xf << CLK_CTRL_TIMEOUT_SHIFT) | |
36 | #define CLK_CTRL_TIMEOUT_MIN_EXP 13 | |
37 | ||
3ea4666e DA |
38 | /* |
39 | * On some SoCs the syscon area has a feature where the upper 16-bits of | |
40 | * each 32-bit register act as a write mask for the lower 16-bits. This allows | |
41 | * atomic updates of the register without locking. This macro is used on SoCs | |
42 | * that have that feature. | |
43 | */ | |
44 | #define HIWORD_UPDATE(val, mask, shift) \ | |
45 | ((val) << (shift) | (mask) << ((shift) + 16)) | |
46 | ||
47 | /** | |
48 | * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map | |
49 | * | |
50 | * @reg: Offset within the syscon of the register containing this field | |
51 | * @width: Number of bits for this field | |
52 | * @shift: Bit offset within @reg of this field (or -1 if not avail) | |
53 | */ | |
54 | struct sdhci_arasan_soc_ctl_field { | |
55 | u32 reg; | |
56 | u16 width; | |
57 | s16 shift; | |
58 | }; | |
59 | ||
60 | /** | |
61 | * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers | |
62 | * | |
63 | * It's up to the licensee of the Arsan IP block to make these available | |
64 | * somewhere if needed. Presumably these will be scattered somewhere that's | |
65 | * accessible via the syscon API. | |
66 | * | |
67 | * @baseclkfreq: Where to find corecfg_baseclkfreq | |
68 | * @hiword_update: If true, use HIWORD_UPDATE to access the syscon | |
69 | */ | |
70 | struct sdhci_arasan_soc_ctl_map { | |
71 | struct sdhci_arasan_soc_ctl_field baseclkfreq; | |
72 | bool hiword_update; | |
73 | }; | |
74 | ||
e3ec3a3d SB |
75 | /** |
76 | * struct sdhci_arasan_data | |
c390f211 | 77 | * @host: Pointer to the main SDHCI host structure. |
3ea4666e DA |
78 | * @clk_ahb: Pointer to the AHB clock |
79 | * @phy: Pointer to the generic phy | |
c390f211 DA |
80 | * @sdcardclk_hw: Struct for the clock we might provide to a PHY. |
81 | * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. | |
3ea4666e DA |
82 | * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. |
83 | * @soc_ctl_map: Map to get offsets into soc_ctl registers. | |
e3ec3a3d SB |
84 | */ |
85 | struct sdhci_arasan_data { | |
c390f211 | 86 | struct sdhci_host *host; |
e3ec3a3d | 87 | struct clk *clk_ahb; |
91aa3661 | 88 | struct phy *phy; |
3ea4666e | 89 | |
c390f211 DA |
90 | struct clk_hw sdcardclk_hw; |
91 | struct clk *sdcardclk; | |
92 | ||
3ea4666e DA |
93 | struct regmap *soc_ctl_base; |
94 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; | |
95 | }; | |
96 | ||
97 | static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { | |
98 | .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, | |
99 | .hiword_update = true, | |
e3ec3a3d SB |
100 | }; |
101 | ||
3ea4666e DA |
102 | /** |
103 | * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers | |
104 | * | |
105 | * This function allows writing to fields in sdhci_arasan_soc_ctl_map. | |
106 | * Note that if a field is specified as not available (shift < 0) then | |
107 | * this function will silently return an error code. It will be noisy | |
108 | * and print errors for any other (unexpected) errors. | |
109 | * | |
110 | * @host: The sdhci_host | |
111 | * @fld: The field to write to | |
112 | * @val: The value to write | |
113 | */ | |
114 | static int sdhci_arasan_syscon_write(struct sdhci_host *host, | |
115 | const struct sdhci_arasan_soc_ctl_field *fld, | |
116 | u32 val) | |
117 | { | |
118 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
119 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
120 | struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; | |
121 | u32 reg = fld->reg; | |
122 | u16 width = fld->width; | |
123 | s16 shift = fld->shift; | |
124 | int ret; | |
125 | ||
126 | /* | |
127 | * Silently return errors for shift < 0 so caller doesn't have | |
128 | * to check for fields which are optional. For fields that | |
129 | * are required then caller needs to do something special | |
130 | * anyway. | |
131 | */ | |
132 | if (shift < 0) | |
133 | return -EINVAL; | |
134 | ||
135 | if (sdhci_arasan->soc_ctl_map->hiword_update) | |
136 | ret = regmap_write(soc_ctl_base, reg, | |
137 | HIWORD_UPDATE(val, GENMASK(width, 0), | |
138 | shift)); | |
139 | else | |
140 | ret = regmap_update_bits(soc_ctl_base, reg, | |
141 | GENMASK(shift + width, shift), | |
142 | val << shift); | |
143 | ||
144 | /* Yell about (unexpected) regmap errors */ | |
145 | if (ret) | |
146 | pr_warn("%s: Regmap write fail: %d\n", | |
147 | mmc_hostname(host->mmc), ret); | |
148 | ||
149 | return ret; | |
150 | } | |
151 | ||
e3ec3a3d SB |
152 | static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host) |
153 | { | |
154 | u32 div; | |
155 | unsigned long freq; | |
156 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
157 | ||
158 | div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET); | |
159 | div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT; | |
160 | ||
161 | freq = clk_get_rate(pltfm_host->clk); | |
162 | freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div); | |
163 | ||
164 | return freq; | |
165 | } | |
166 | ||
802ac39a SL |
167 | static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) |
168 | { | |
169 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
170 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
6fc09244 | 171 | bool ctrl_phy = false; |
802ac39a | 172 | |
6fc09244 DA |
173 | if (clock > MMC_HIGH_52_MAX_DTR && (!IS_ERR(sdhci_arasan->phy))) |
174 | ctrl_phy = true; | |
802ac39a | 175 | |
6fc09244 | 176 | if (ctrl_phy) { |
802ac39a SL |
177 | spin_unlock_irq(&host->lock); |
178 | phy_power_off(sdhci_arasan->phy); | |
179 | spin_lock_irq(&host->lock); | |
180 | } | |
181 | ||
182 | sdhci_set_clock(host, clock); | |
183 | ||
6fc09244 | 184 | if (ctrl_phy) { |
802ac39a SL |
185 | spin_unlock_irq(&host->lock); |
186 | phy_power_on(sdhci_arasan->phy); | |
187 | spin_lock_irq(&host->lock); | |
188 | } | |
189 | } | |
190 | ||
a05c8465 SL |
191 | static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, |
192 | struct mmc_ios *ios) | |
193 | { | |
194 | u32 vendor; | |
195 | struct sdhci_host *host = mmc_priv(mmc); | |
196 | ||
197 | vendor = readl(host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER); | |
198 | if (ios->enhanced_strobe) | |
199 | vendor |= VENDOR_ENHANCED_STROBE; | |
200 | else | |
201 | vendor &= ~VENDOR_ENHANCED_STROBE; | |
202 | ||
203 | writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER); | |
204 | } | |
205 | ||
e3ec3a3d | 206 | static struct sdhci_ops sdhci_arasan_ops = { |
802ac39a | 207 | .set_clock = sdhci_arasan_set_clock, |
e3ec3a3d SB |
208 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
209 | .get_timeout_clock = sdhci_arasan_get_timeout_clock, | |
2317f56c | 210 | .set_bus_width = sdhci_set_bus_width, |
03231f9b | 211 | .reset = sdhci_reset, |
96d7b78c | 212 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
e3ec3a3d SB |
213 | }; |
214 | ||
215 | static struct sdhci_pltfm_data sdhci_arasan_pdata = { | |
216 | .ops = &sdhci_arasan_ops, | |
2d532d45 SG |
217 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
218 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
219 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, | |
e3ec3a3d SB |
220 | }; |
221 | ||
222 | #ifdef CONFIG_PM_SLEEP | |
223 | /** | |
224 | * sdhci_arasan_suspend - Suspend method for the driver | |
225 | * @dev: Address of the device structure | |
226 | * Returns 0 on success and error value on error | |
227 | * | |
228 | * Put the device in a low power state. | |
229 | */ | |
230 | static int sdhci_arasan_suspend(struct device *dev) | |
231 | { | |
232 | struct platform_device *pdev = to_platform_device(dev); | |
233 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
234 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
89211418 | 235 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
236 | int ret; |
237 | ||
238 | ret = sdhci_suspend_host(host); | |
239 | if (ret) | |
240 | return ret; | |
241 | ||
91aa3661 SL |
242 | if (!IS_ERR(sdhci_arasan->phy)) { |
243 | ret = phy_power_off(sdhci_arasan->phy); | |
244 | if (ret) { | |
245 | dev_err(dev, "Cannot power off phy.\n"); | |
246 | sdhci_resume_host(host); | |
247 | return ret; | |
248 | } | |
249 | } | |
250 | ||
e3ec3a3d SB |
251 | clk_disable(pltfm_host->clk); |
252 | clk_disable(sdhci_arasan->clk_ahb); | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
257 | /** | |
258 | * sdhci_arasan_resume - Resume method for the driver | |
259 | * @dev: Address of the device structure | |
260 | * Returns 0 on success and error value on error | |
261 | * | |
262 | * Resume operation after suspend | |
263 | */ | |
264 | static int sdhci_arasan_resume(struct device *dev) | |
265 | { | |
266 | struct platform_device *pdev = to_platform_device(dev); | |
267 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
268 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
89211418 | 269 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
270 | int ret; |
271 | ||
272 | ret = clk_enable(sdhci_arasan->clk_ahb); | |
273 | if (ret) { | |
274 | dev_err(dev, "Cannot enable AHB clock.\n"); | |
275 | return ret; | |
276 | } | |
277 | ||
278 | ret = clk_enable(pltfm_host->clk); | |
279 | if (ret) { | |
280 | dev_err(dev, "Cannot enable SD clock.\n"); | |
e3ec3a3d SB |
281 | return ret; |
282 | } | |
283 | ||
91aa3661 SL |
284 | if (!IS_ERR(sdhci_arasan->phy)) { |
285 | ret = phy_power_on(sdhci_arasan->phy); | |
286 | if (ret) { | |
287 | dev_err(dev, "Cannot power on phy.\n"); | |
288 | return ret; | |
289 | } | |
290 | } | |
291 | ||
e3ec3a3d SB |
292 | return sdhci_resume_host(host); |
293 | } | |
294 | #endif /* ! CONFIG_PM_SLEEP */ | |
295 | ||
296 | static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, | |
297 | sdhci_arasan_resume); | |
298 | ||
3ea4666e DA |
299 | static const struct of_device_id sdhci_arasan_of_match[] = { |
300 | /* SoC-specific compatible strings w/ soc_ctl_map */ | |
301 | { | |
302 | .compatible = "rockchip,rk3399-sdhci-5.1", | |
303 | .data = &rk3399_soc_ctl_map, | |
304 | }, | |
305 | ||
306 | /* Generic compatible below here */ | |
307 | { .compatible = "arasan,sdhci-8.9a" }, | |
308 | { .compatible = "arasan,sdhci-5.1" }, | |
309 | { .compatible = "arasan,sdhci-4.9a" }, | |
310 | ||
311 | { /* sentinel */ } | |
312 | }; | |
313 | MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); | |
314 | ||
c390f211 DA |
315 | /** |
316 | * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate | |
317 | * | |
318 | * Return the current actual rate of the SD card clock. This can be used | |
319 | * to communicate with out PHY. | |
320 | * | |
321 | * @hw: Pointer to the hardware clock structure. | |
322 | * @parent_rate The parent rate (should be rate of clk_xin). | |
323 | * Returns the card clock rate. | |
324 | */ | |
325 | static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, | |
326 | unsigned long parent_rate) | |
327 | ||
328 | { | |
329 | struct sdhci_arasan_data *sdhci_arasan = | |
330 | container_of(hw, struct sdhci_arasan_data, sdcardclk_hw); | |
331 | struct sdhci_host *host = sdhci_arasan->host; | |
332 | ||
333 | return host->mmc->actual_clock; | |
334 | } | |
335 | ||
336 | static const struct clk_ops arasan_sdcardclk_ops = { | |
337 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
338 | }; | |
339 | ||
3ea4666e DA |
340 | /** |
341 | * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq | |
342 | * | |
343 | * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This | |
344 | * function can be used to make that happen. | |
345 | * | |
346 | * NOTES: | |
347 | * - Many existing devices don't seem to do this and work fine. To keep | |
348 | * compatibility for old hardware where the device tree doesn't provide a | |
349 | * register map, this function is a noop if a soc_ctl_map hasn't been provided | |
350 | * for this platform. | |
351 | * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider | |
352 | * to achieve lower clock rates. That means that this function is called once | |
353 | * at probe time and never called again. | |
354 | * | |
355 | * @host: The sdhci_host | |
356 | */ | |
357 | static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) | |
358 | { | |
359 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
360 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
361 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
362 | sdhci_arasan->soc_ctl_map; | |
363 | u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); | |
364 | ||
365 | /* Having a map is optional */ | |
366 | if (!soc_ctl_map) | |
367 | return; | |
368 | ||
369 | /* If we have a map, we expect to have a syscon */ | |
370 | if (!sdhci_arasan->soc_ctl_base) { | |
371 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
372 | mmc_hostname(host->mmc)); | |
373 | return; | |
374 | } | |
375 | ||
376 | sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); | |
377 | } | |
378 | ||
c390f211 DA |
379 | /** |
380 | * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use | |
381 | * | |
382 | * Some PHY devices need to know what the actual card clock is. In order for | |
383 | * them to find out, we'll provide a clock through the common clock framework | |
384 | * for them to query. | |
385 | * | |
386 | * Note: without seriously re-architecting SDHCI's clock code and testing on | |
387 | * all platforms, there's no way to create a totally beautiful clock here | |
388 | * with all clock ops implemented. Instead, we'll just create a clock that can | |
389 | * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock | |
390 | * framework that we're doing things behind its back. This should be sufficient | |
391 | * to create nice clean device tree bindings and later (if needed) we can try | |
392 | * re-architecting SDHCI if we see some benefit to it. | |
393 | * | |
394 | * @sdhci_arasan: Our private data structure. | |
395 | * @clk_xin: Pointer to the functional clock | |
396 | * @dev: Pointer to our struct device. | |
397 | * Returns 0 on success and error value on error | |
398 | */ | |
399 | static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, | |
400 | struct clk *clk_xin, | |
401 | struct device *dev) | |
402 | { | |
403 | struct device_node *np = dev->of_node; | |
404 | struct clk_init_data sdcardclk_init; | |
405 | const char *parent_clk_name; | |
406 | int ret; | |
407 | ||
408 | /* Providing a clock to the PHY is optional; no error if missing */ | |
409 | if (!of_find_property(np, "#clock-cells", NULL)) | |
410 | return 0; | |
411 | ||
412 | ret = of_property_read_string_index(np, "clock-output-names", 0, | |
413 | &sdcardclk_init.name); | |
414 | if (ret) { | |
415 | dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); | |
416 | return ret; | |
417 | } | |
418 | ||
419 | parent_clk_name = __clk_get_name(clk_xin); | |
420 | sdcardclk_init.parent_names = &parent_clk_name; | |
421 | sdcardclk_init.num_parents = 1; | |
422 | sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; | |
423 | sdcardclk_init.ops = &arasan_sdcardclk_ops; | |
424 | ||
425 | sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init; | |
426 | sdhci_arasan->sdcardclk = | |
427 | devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw); | |
428 | sdhci_arasan->sdcardclk_hw.init = NULL; | |
429 | ||
430 | ret = of_clk_add_provider(np, of_clk_src_simple_get, | |
431 | sdhci_arasan->sdcardclk); | |
432 | if (ret) | |
433 | dev_err(dev, "Failed to add clock provider\n"); | |
434 | ||
435 | return ret; | |
436 | } | |
437 | ||
438 | /** | |
439 | * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() | |
440 | * | |
441 | * Should be called any time we're exiting and sdhci_arasan_register_sdclk() | |
442 | * returned success. | |
443 | * | |
444 | * @dev: Pointer to our struct device. | |
445 | */ | |
446 | static void sdhci_arasan_unregister_sdclk(struct device *dev) | |
447 | { | |
448 | struct device_node *np = dev->of_node; | |
449 | ||
450 | if (!of_find_property(np, "#clock-cells", NULL)) | |
451 | return; | |
452 | ||
453 | of_clk_del_provider(dev->of_node); | |
454 | } | |
455 | ||
e3ec3a3d SB |
456 | static int sdhci_arasan_probe(struct platform_device *pdev) |
457 | { | |
458 | int ret; | |
3ea4666e DA |
459 | const struct of_device_id *match; |
460 | struct device_node *node; | |
e3ec3a3d SB |
461 | struct clk *clk_xin; |
462 | struct sdhci_host *host; | |
463 | struct sdhci_pltfm_host *pltfm_host; | |
464 | struct sdhci_arasan_data *sdhci_arasan; | |
465 | ||
89211418 JZ |
466 | host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata, |
467 | sizeof(*sdhci_arasan)); | |
468 | if (IS_ERR(host)) | |
469 | return PTR_ERR(host); | |
470 | ||
471 | pltfm_host = sdhci_priv(host); | |
472 | sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
c390f211 | 473 | sdhci_arasan->host = host; |
e3ec3a3d | 474 | |
3ea4666e DA |
475 | match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); |
476 | sdhci_arasan->soc_ctl_map = match->data; | |
477 | ||
478 | node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); | |
479 | if (node) { | |
480 | sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); | |
481 | of_node_put(node); | |
482 | ||
483 | if (IS_ERR(sdhci_arasan->soc_ctl_base)) { | |
484 | ret = PTR_ERR(sdhci_arasan->soc_ctl_base); | |
485 | if (ret != -EPROBE_DEFER) | |
486 | dev_err(&pdev->dev, "Can't get syscon: %d\n", | |
487 | ret); | |
488 | goto err_pltfm_free; | |
489 | } | |
490 | } | |
491 | ||
e3ec3a3d SB |
492 | sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); |
493 | if (IS_ERR(sdhci_arasan->clk_ahb)) { | |
494 | dev_err(&pdev->dev, "clk_ahb clock not found.\n"); | |
278d0962 SL |
495 | ret = PTR_ERR(sdhci_arasan->clk_ahb); |
496 | goto err_pltfm_free; | |
e3ec3a3d SB |
497 | } |
498 | ||
499 | clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); | |
500 | if (IS_ERR(clk_xin)) { | |
501 | dev_err(&pdev->dev, "clk_xin clock not found.\n"); | |
278d0962 SL |
502 | ret = PTR_ERR(clk_xin); |
503 | goto err_pltfm_free; | |
e3ec3a3d SB |
504 | } |
505 | ||
506 | ret = clk_prepare_enable(sdhci_arasan->clk_ahb); | |
507 | if (ret) { | |
508 | dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); | |
278d0962 | 509 | goto err_pltfm_free; |
e3ec3a3d SB |
510 | } |
511 | ||
512 | ret = clk_prepare_enable(clk_xin); | |
513 | if (ret) { | |
514 | dev_err(&pdev->dev, "Unable to enable SD clock.\n"); | |
515 | goto clk_dis_ahb; | |
516 | } | |
517 | ||
e3ec3a3d | 518 | sdhci_get_of_property(pdev); |
e3ec3a3d SB |
519 | pltfm_host->clk = clk_xin; |
520 | ||
3ea4666e DA |
521 | sdhci_arasan_update_baseclkfreq(host); |
522 | ||
c390f211 DA |
523 | ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); |
524 | if (ret) | |
525 | goto clk_disable_all; | |
526 | ||
16b23787 MS |
527 | ret = mmc_of_parse(host->mmc); |
528 | if (ret) { | |
529 | dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret); | |
c390f211 | 530 | goto unreg_clk; |
16b23787 MS |
531 | } |
532 | ||
91aa3661 SL |
533 | sdhci_arasan->phy = ERR_PTR(-ENODEV); |
534 | if (of_device_is_compatible(pdev->dev.of_node, | |
535 | "arasan,sdhci-5.1")) { | |
536 | sdhci_arasan->phy = devm_phy_get(&pdev->dev, | |
537 | "phy_arasan"); | |
538 | if (IS_ERR(sdhci_arasan->phy)) { | |
539 | ret = PTR_ERR(sdhci_arasan->phy); | |
540 | dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); | |
c390f211 | 541 | goto unreg_clk; |
91aa3661 SL |
542 | } |
543 | ||
544 | ret = phy_init(sdhci_arasan->phy); | |
545 | if (ret < 0) { | |
546 | dev_err(&pdev->dev, "phy_init err.\n"); | |
c390f211 | 547 | goto unreg_clk; |
91aa3661 SL |
548 | } |
549 | ||
6fc09244 DA |
550 | ret = phy_power_on(sdhci_arasan->phy); |
551 | if (ret < 0) { | |
552 | dev_err(&pdev->dev, "phy_power_on err.\n"); | |
553 | goto err_phy_power; | |
554 | } | |
555 | ||
a05c8465 SL |
556 | host->mmc_host_ops.hs400_enhanced_strobe = |
557 | sdhci_arasan_hs400_enhanced_strobe; | |
91aa3661 SL |
558 | } |
559 | ||
e3ec3a3d | 560 | ret = sdhci_add_host(host); |
b1df9de7 | 561 | if (ret) |
91aa3661 | 562 | goto err_add_host; |
e3ec3a3d SB |
563 | |
564 | return 0; | |
565 | ||
91aa3661 | 566 | err_add_host: |
6fc09244 DA |
567 | if (!IS_ERR(sdhci_arasan->phy)) |
568 | phy_power_off(sdhci_arasan->phy); | |
569 | err_phy_power: | |
91aa3661 SL |
570 | if (!IS_ERR(sdhci_arasan->phy)) |
571 | phy_exit(sdhci_arasan->phy); | |
c390f211 DA |
572 | unreg_clk: |
573 | sdhci_arasan_unregister_sdclk(&pdev->dev); | |
e3ec3a3d SB |
574 | clk_disable_all: |
575 | clk_disable_unprepare(clk_xin); | |
576 | clk_dis_ahb: | |
577 | clk_disable_unprepare(sdhci_arasan->clk_ahb); | |
278d0962 SL |
578 | err_pltfm_free: |
579 | sdhci_pltfm_free(pdev); | |
e3ec3a3d SB |
580 | return ret; |
581 | } | |
582 | ||
583 | static int sdhci_arasan_remove(struct platform_device *pdev) | |
584 | { | |
0c7fe32e | 585 | int ret; |
e3ec3a3d SB |
586 | struct sdhci_host *host = platform_get_drvdata(pdev); |
587 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
89211418 JZ |
588 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
589 | struct clk *clk_ahb = sdhci_arasan->clk_ahb; | |
e3ec3a3d | 590 | |
91aa3661 SL |
591 | if (!IS_ERR(sdhci_arasan->phy)) { |
592 | phy_power_off(sdhci_arasan->phy); | |
593 | phy_exit(sdhci_arasan->phy); | |
594 | } | |
595 | ||
c390f211 DA |
596 | sdhci_arasan_unregister_sdclk(&pdev->dev); |
597 | ||
0c7fe32e JZ |
598 | ret = sdhci_pltfm_unregister(pdev); |
599 | ||
89211418 | 600 | clk_disable_unprepare(clk_ahb); |
e3ec3a3d | 601 | |
0c7fe32e | 602 | return ret; |
e3ec3a3d SB |
603 | } |
604 | ||
e3ec3a3d SB |
605 | static struct platform_driver sdhci_arasan_driver = { |
606 | .driver = { | |
607 | .name = "sdhci-arasan", | |
e3ec3a3d SB |
608 | .of_match_table = sdhci_arasan_of_match, |
609 | .pm = &sdhci_arasan_dev_pm_ops, | |
610 | }, | |
611 | .probe = sdhci_arasan_probe, | |
612 | .remove = sdhci_arasan_remove, | |
613 | }; | |
614 | ||
615 | module_platform_driver(sdhci_arasan_driver); | |
616 | ||
617 | MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); | |
618 | MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); | |
619 | MODULE_LICENSE("GPL"); |