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bb5f8ea4 | 1 | /* |
2 | * Atmel SDMMC controller driver. | |
3 | * | |
4 | * Copyright (C) 2015 Atmel, | |
5 | * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
4e289a7d | 18 | #include <linux/delay.h> |
bb5f8ea4 | 19 | #include <linux/err.h> |
20 | #include <linux/io.h> | |
21 | #include <linux/mmc/host.h> | |
64e5cd72 | 22 | #include <linux/mmc/slot-gpio.h> |
bb5f8ea4 | 23 | #include <linux/module.h> |
24 | #include <linux/of.h> | |
25 | #include <linux/of_device.h> | |
f5f17813 | 26 | #include <linux/pm.h> |
27 | #include <linux/pm_runtime.h> | |
bb5f8ea4 | 28 | |
29 | #include "sdhci-pltfm.h" | |
30 | ||
31 | #define SDMMC_CACR 0x230 | |
32 | #define SDMMC_CACR_CAPWREN BIT(0) | |
33 | #define SDMMC_CACR_KEY (0x46 << 8) | |
34 | ||
35 | struct sdhci_at91_priv { | |
36 | struct clk *hclock; | |
37 | struct clk *gck; | |
38 | struct clk *mainck; | |
39 | }; | |
40 | ||
4e289a7d LD |
41 | static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) |
42 | { | |
43 | u16 clk; | |
44 | unsigned long timeout; | |
45 | ||
46 | host->mmc->actual_clock = 0; | |
47 | ||
48 | /* | |
49 | * There is no requirement to disable the internal clock before | |
50 | * changing the SD clock configuration. Moreover, disabling the | |
51 | * internal clock, changing the configuration and re-enabling the | |
52 | * internal clock causes some bugs. It can prevent to get the internal | |
53 | * clock stable flag ready and an unexpected switch to the base clock | |
54 | * when using presets. | |
55 | */ | |
56 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
57 | clk &= SDHCI_CLOCK_INT_EN; | |
58 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
59 | ||
60 | if (clock == 0) | |
61 | return; | |
62 | ||
63 | clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); | |
64 | ||
65 | clk |= SDHCI_CLOCK_INT_EN; | |
66 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
67 | ||
68 | /* Wait max 20 ms */ | |
69 | timeout = 20; | |
70 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) | |
71 | & SDHCI_CLOCK_INT_STABLE)) { | |
72 | if (timeout == 0) { | |
73 | pr_err("%s: Internal clock never stabilised.\n", | |
74 | mmc_hostname(host->mmc)); | |
75 | return; | |
76 | } | |
77 | timeout--; | |
78 | mdelay(1); | |
79 | } | |
80 | ||
81 | clk |= SDHCI_CLOCK_CARD_EN; | |
82 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
83 | } | |
84 | ||
bb5f8ea4 | 85 | static const struct sdhci_ops sdhci_at91_sama5d2_ops = { |
4e289a7d | 86 | .set_clock = sdhci_at91_set_clock, |
bb5f8ea4 | 87 | .set_bus_width = sdhci_set_bus_width, |
88 | .reset = sdhci_reset, | |
89 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
90 | }; | |
91 | ||
92 | static const struct sdhci_pltfm_data soc_data_sama5d2 = { | |
93 | .ops = &sdhci_at91_sama5d2_ops, | |
94 | }; | |
95 | ||
96 | static const struct of_device_id sdhci_at91_dt_match[] = { | |
97 | { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, | |
98 | {} | |
99 | }; | |
100 | ||
f5f17813 | 101 | #ifdef CONFIG_PM |
102 | static int sdhci_at91_runtime_suspend(struct device *dev) | |
103 | { | |
104 | struct sdhci_host *host = dev_get_drvdata(dev); | |
105 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
10f1c135 | 106 | struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); |
f5f17813 | 107 | int ret; |
108 | ||
109 | ret = sdhci_runtime_suspend_host(host); | |
110 | ||
111 | clk_disable_unprepare(priv->gck); | |
112 | clk_disable_unprepare(priv->hclock); | |
113 | clk_disable_unprepare(priv->mainck); | |
114 | ||
115 | return ret; | |
116 | } | |
117 | ||
118 | static int sdhci_at91_runtime_resume(struct device *dev) | |
119 | { | |
120 | struct sdhci_host *host = dev_get_drvdata(dev); | |
121 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
10f1c135 | 122 | struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); |
f5f17813 | 123 | int ret; |
124 | ||
125 | ret = clk_prepare_enable(priv->mainck); | |
126 | if (ret) { | |
127 | dev_err(dev, "can't enable mainck\n"); | |
128 | return ret; | |
129 | } | |
130 | ||
131 | ret = clk_prepare_enable(priv->hclock); | |
132 | if (ret) { | |
133 | dev_err(dev, "can't enable hclock\n"); | |
134 | return ret; | |
135 | } | |
136 | ||
137 | ret = clk_prepare_enable(priv->gck); | |
138 | if (ret) { | |
139 | dev_err(dev, "can't enable gck\n"); | |
140 | return ret; | |
141 | } | |
142 | ||
143 | return sdhci_runtime_resume_host(host); | |
144 | } | |
145 | #endif /* CONFIG_PM */ | |
146 | ||
147 | static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { | |
148 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
149 | pm_runtime_force_resume) | |
150 | SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, | |
151 | sdhci_at91_runtime_resume, | |
152 | NULL) | |
153 | }; | |
154 | ||
bb5f8ea4 | 155 | static int sdhci_at91_probe(struct platform_device *pdev) |
156 | { | |
157 | const struct of_device_id *match; | |
158 | const struct sdhci_pltfm_data *soc_data; | |
159 | struct sdhci_host *host; | |
160 | struct sdhci_pltfm_host *pltfm_host; | |
161 | struct sdhci_at91_priv *priv; | |
162 | unsigned int caps0, caps1; | |
163 | unsigned int clk_base, clk_mul; | |
164 | unsigned int gck_rate, real_gck_rate; | |
165 | int ret; | |
166 | ||
167 | match = of_match_device(sdhci_at91_dt_match, &pdev->dev); | |
168 | if (!match) | |
169 | return -EINVAL; | |
170 | soc_data = match->data; | |
171 | ||
10f1c135 JZ |
172 | host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv)); |
173 | if (IS_ERR(host)) | |
174 | return PTR_ERR(host); | |
175 | ||
176 | pltfm_host = sdhci_priv(host); | |
177 | priv = sdhci_pltfm_priv(pltfm_host); | |
bb5f8ea4 | 178 | |
179 | priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); | |
180 | if (IS_ERR(priv->mainck)) { | |
181 | dev_err(&pdev->dev, "failed to get baseclk\n"); | |
182 | return PTR_ERR(priv->mainck); | |
183 | } | |
184 | ||
185 | priv->hclock = devm_clk_get(&pdev->dev, "hclock"); | |
186 | if (IS_ERR(priv->hclock)) { | |
187 | dev_err(&pdev->dev, "failed to get hclock\n"); | |
188 | return PTR_ERR(priv->hclock); | |
189 | } | |
190 | ||
191 | priv->gck = devm_clk_get(&pdev->dev, "multclk"); | |
192 | if (IS_ERR(priv->gck)) { | |
193 | dev_err(&pdev->dev, "failed to get multclk\n"); | |
194 | return PTR_ERR(priv->gck); | |
195 | } | |
196 | ||
bb5f8ea4 | 197 | /* |
198 | * The mult clock is provided by as a generated clock by the PMC | |
199 | * controller. In order to set the rate of gck, we have to get the | |
200 | * base clock rate and the clock mult from capabilities. | |
201 | */ | |
202 | clk_prepare_enable(priv->hclock); | |
203 | caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); | |
204 | caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); | |
205 | clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; | |
206 | clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; | |
207 | gck_rate = clk_base * 1000000 * (clk_mul + 1); | |
208 | ret = clk_set_rate(priv->gck, gck_rate); | |
209 | if (ret < 0) { | |
210 | dev_err(&pdev->dev, "failed to set gck"); | |
211 | goto hclock_disable_unprepare; | |
bb5f8ea4 | 212 | } |
213 | /* | |
214 | * We need to check if we have the requested rate for gck because in | |
215 | * some cases this rate could be not supported. If it happens, the rate | |
216 | * is the closest one gck can provide. We have to update the value | |
217 | * of clk mul. | |
218 | */ | |
219 | real_gck_rate = clk_get_rate(priv->gck); | |
220 | if (real_gck_rate != gck_rate) { | |
221 | clk_mul = real_gck_rate / (clk_base * 1000000) - 1; | |
222 | caps1 &= (~SDHCI_CLOCK_MUL_MASK); | |
223 | caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK); | |
224 | /* Set capabilities in r/w mode. */ | |
225 | writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); | |
226 | writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); | |
227 | /* Set capabilities in ro mode. */ | |
228 | writel(0, host->ioaddr + SDMMC_CACR); | |
229 | dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n", | |
230 | clk_mul, real_gck_rate); | |
231 | } | |
232 | ||
233 | clk_prepare_enable(priv->mainck); | |
234 | clk_prepare_enable(priv->gck); | |
235 | ||
bb5f8ea4 | 236 | ret = mmc_of_parse(host->mmc); |
237 | if (ret) | |
238 | goto clocks_disable_unprepare; | |
239 | ||
240 | sdhci_get_of_property(pdev); | |
241 | ||
f5f17813 | 242 | pm_runtime_get_noresume(&pdev->dev); |
243 | pm_runtime_set_active(&pdev->dev); | |
244 | pm_runtime_enable(&pdev->dev); | |
245 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
246 | pm_runtime_use_autosuspend(&pdev->dev); | |
247 | ||
bb5f8ea4 | 248 | ret = sdhci_add_host(host); |
249 | if (ret) | |
f5f17813 | 250 | goto pm_runtime_disable; |
251 | ||
64e5cd72 | 252 | /* |
253 | * When calling sdhci_runtime_suspend_host(), the sdhci layer makes | |
254 | * the assumption that all the clocks of the controller are disabled. | |
255 | * It means we can't get irq from it when it is runtime suspended. | |
256 | * For that reason, it is not planned to wake-up on a card detect irq | |
257 | * from the controller. | |
258 | * If we want to use runtime PM and to be able to wake-up on card | |
259 | * insertion, we have to use a GPIO for the card detection or we can | |
260 | * use polling. Be aware that using polling will resume/suspend the | |
261 | * controller between each attempt. | |
262 | * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries | |
263 | * to enable polling via device tree with broken-cd property. | |
264 | */ | |
265 | if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE) && | |
266 | IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc))) { | |
267 | host->mmc->caps |= MMC_CAP_NEEDS_POLL; | |
268 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
269 | } | |
270 | ||
f5f17813 | 271 | pm_runtime_put_autosuspend(&pdev->dev); |
bb5f8ea4 | 272 | |
273 | return 0; | |
274 | ||
f5f17813 | 275 | pm_runtime_disable: |
276 | pm_runtime_disable(&pdev->dev); | |
277 | pm_runtime_set_suspended(&pdev->dev); | |
2df9d58f | 278 | pm_runtime_put_noidle(&pdev->dev); |
bb5f8ea4 | 279 | clocks_disable_unprepare: |
280 | clk_disable_unprepare(priv->gck); | |
281 | clk_disable_unprepare(priv->mainck); | |
282 | hclock_disable_unprepare: | |
283 | clk_disable_unprepare(priv->hclock); | |
284 | sdhci_pltfm_free(pdev); | |
285 | return ret; | |
286 | } | |
287 | ||
288 | static int sdhci_at91_remove(struct platform_device *pdev) | |
289 | { | |
290 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
291 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
10f1c135 JZ |
292 | struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); |
293 | struct clk *gck = priv->gck; | |
294 | struct clk *hclock = priv->hclock; | |
295 | struct clk *mainck = priv->mainck; | |
bb5f8ea4 | 296 | |
f5f17813 | 297 | pm_runtime_get_sync(&pdev->dev); |
298 | pm_runtime_disable(&pdev->dev); | |
299 | pm_runtime_put_noidle(&pdev->dev); | |
300 | ||
bb5f8ea4 | 301 | sdhci_pltfm_unregister(pdev); |
302 | ||
10f1c135 JZ |
303 | clk_disable_unprepare(gck); |
304 | clk_disable_unprepare(hclock); | |
305 | clk_disable_unprepare(mainck); | |
bb5f8ea4 | 306 | |
307 | return 0; | |
308 | } | |
309 | ||
310 | static struct platform_driver sdhci_at91_driver = { | |
311 | .driver = { | |
312 | .name = "sdhci-at91", | |
bb5f8ea4 | 313 | .of_match_table = sdhci_at91_dt_match, |
f5f17813 | 314 | .pm = &sdhci_at91_dev_pm_ops, |
bb5f8ea4 | 315 | }, |
316 | .probe = sdhci_at91_probe, | |
317 | .remove = sdhci_at91_remove, | |
318 | }; | |
319 | ||
320 | module_platform_driver(sdhci_at91_driver); | |
321 | ||
322 | MODULE_DESCRIPTION("SDHCI driver for at91"); | |
323 | MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); | |
324 | MODULE_LICENSE("GPL v2"); |