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bb5f8ea4 | 1 | /* |
2 | * Atmel SDMMC controller driver. | |
3 | * | |
4 | * Copyright (C) 2015 Atmel, | |
5 | * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/mmc/host.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_device.h> | |
f5f17813 | 24 | #include <linux/pm.h> |
25 | #include <linux/pm_runtime.h> | |
bb5f8ea4 | 26 | |
27 | #include "sdhci-pltfm.h" | |
28 | ||
29 | #define SDMMC_CACR 0x230 | |
30 | #define SDMMC_CACR_CAPWREN BIT(0) | |
31 | #define SDMMC_CACR_KEY (0x46 << 8) | |
32 | ||
33 | struct sdhci_at91_priv { | |
34 | struct clk *hclock; | |
35 | struct clk *gck; | |
36 | struct clk *mainck; | |
37 | }; | |
38 | ||
39 | static const struct sdhci_ops sdhci_at91_sama5d2_ops = { | |
40 | .set_clock = sdhci_set_clock, | |
41 | .set_bus_width = sdhci_set_bus_width, | |
42 | .reset = sdhci_reset, | |
43 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
44 | }; | |
45 | ||
46 | static const struct sdhci_pltfm_data soc_data_sama5d2 = { | |
47 | .ops = &sdhci_at91_sama5d2_ops, | |
88c6eb0e | 48 | .quirks2 = SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST, |
bb5f8ea4 | 49 | }; |
50 | ||
51 | static const struct of_device_id sdhci_at91_dt_match[] = { | |
52 | { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, | |
53 | {} | |
54 | }; | |
55 | ||
f5f17813 | 56 | #ifdef CONFIG_PM |
57 | static int sdhci_at91_runtime_suspend(struct device *dev) | |
58 | { | |
59 | struct sdhci_host *host = dev_get_drvdata(dev); | |
60 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
10f1c135 | 61 | struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); |
f5f17813 | 62 | int ret; |
63 | ||
64 | ret = sdhci_runtime_suspend_host(host); | |
65 | ||
66 | clk_disable_unprepare(priv->gck); | |
67 | clk_disable_unprepare(priv->hclock); | |
68 | clk_disable_unprepare(priv->mainck); | |
69 | ||
70 | return ret; | |
71 | } | |
72 | ||
73 | static int sdhci_at91_runtime_resume(struct device *dev) | |
74 | { | |
75 | struct sdhci_host *host = dev_get_drvdata(dev); | |
76 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
10f1c135 | 77 | struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); |
f5f17813 | 78 | int ret; |
79 | ||
80 | ret = clk_prepare_enable(priv->mainck); | |
81 | if (ret) { | |
82 | dev_err(dev, "can't enable mainck\n"); | |
83 | return ret; | |
84 | } | |
85 | ||
86 | ret = clk_prepare_enable(priv->hclock); | |
87 | if (ret) { | |
88 | dev_err(dev, "can't enable hclock\n"); | |
89 | return ret; | |
90 | } | |
91 | ||
92 | ret = clk_prepare_enable(priv->gck); | |
93 | if (ret) { | |
94 | dev_err(dev, "can't enable gck\n"); | |
95 | return ret; | |
96 | } | |
97 | ||
98 | return sdhci_runtime_resume_host(host); | |
99 | } | |
100 | #endif /* CONFIG_PM */ | |
101 | ||
102 | static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { | |
103 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
104 | pm_runtime_force_resume) | |
105 | SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, | |
106 | sdhci_at91_runtime_resume, | |
107 | NULL) | |
108 | }; | |
109 | ||
bb5f8ea4 | 110 | static int sdhci_at91_probe(struct platform_device *pdev) |
111 | { | |
112 | const struct of_device_id *match; | |
113 | const struct sdhci_pltfm_data *soc_data; | |
114 | struct sdhci_host *host; | |
115 | struct sdhci_pltfm_host *pltfm_host; | |
116 | struct sdhci_at91_priv *priv; | |
117 | unsigned int caps0, caps1; | |
118 | unsigned int clk_base, clk_mul; | |
119 | unsigned int gck_rate, real_gck_rate; | |
120 | int ret; | |
121 | ||
122 | match = of_match_device(sdhci_at91_dt_match, &pdev->dev); | |
123 | if (!match) | |
124 | return -EINVAL; | |
125 | soc_data = match->data; | |
126 | ||
10f1c135 JZ |
127 | host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv)); |
128 | if (IS_ERR(host)) | |
129 | return PTR_ERR(host); | |
130 | ||
131 | pltfm_host = sdhci_priv(host); | |
132 | priv = sdhci_pltfm_priv(pltfm_host); | |
bb5f8ea4 | 133 | |
134 | priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); | |
135 | if (IS_ERR(priv->mainck)) { | |
136 | dev_err(&pdev->dev, "failed to get baseclk\n"); | |
137 | return PTR_ERR(priv->mainck); | |
138 | } | |
139 | ||
140 | priv->hclock = devm_clk_get(&pdev->dev, "hclock"); | |
141 | if (IS_ERR(priv->hclock)) { | |
142 | dev_err(&pdev->dev, "failed to get hclock\n"); | |
143 | return PTR_ERR(priv->hclock); | |
144 | } | |
145 | ||
146 | priv->gck = devm_clk_get(&pdev->dev, "multclk"); | |
147 | if (IS_ERR(priv->gck)) { | |
148 | dev_err(&pdev->dev, "failed to get multclk\n"); | |
149 | return PTR_ERR(priv->gck); | |
150 | } | |
151 | ||
bb5f8ea4 | 152 | /* |
153 | * The mult clock is provided by as a generated clock by the PMC | |
154 | * controller. In order to set the rate of gck, we have to get the | |
155 | * base clock rate and the clock mult from capabilities. | |
156 | */ | |
157 | clk_prepare_enable(priv->hclock); | |
158 | caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); | |
159 | caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); | |
160 | clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; | |
161 | clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; | |
162 | gck_rate = clk_base * 1000000 * (clk_mul + 1); | |
163 | ret = clk_set_rate(priv->gck, gck_rate); | |
164 | if (ret < 0) { | |
165 | dev_err(&pdev->dev, "failed to set gck"); | |
166 | goto hclock_disable_unprepare; | |
bb5f8ea4 | 167 | } |
168 | /* | |
169 | * We need to check if we have the requested rate for gck because in | |
170 | * some cases this rate could be not supported. If it happens, the rate | |
171 | * is the closest one gck can provide. We have to update the value | |
172 | * of clk mul. | |
173 | */ | |
174 | real_gck_rate = clk_get_rate(priv->gck); | |
175 | if (real_gck_rate != gck_rate) { | |
176 | clk_mul = real_gck_rate / (clk_base * 1000000) - 1; | |
177 | caps1 &= (~SDHCI_CLOCK_MUL_MASK); | |
178 | caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK); | |
179 | /* Set capabilities in r/w mode. */ | |
180 | writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); | |
181 | writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); | |
182 | /* Set capabilities in ro mode. */ | |
183 | writel(0, host->ioaddr + SDMMC_CACR); | |
184 | dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n", | |
185 | clk_mul, real_gck_rate); | |
186 | } | |
187 | ||
188 | clk_prepare_enable(priv->mainck); | |
189 | clk_prepare_enable(priv->gck); | |
190 | ||
bb5f8ea4 | 191 | ret = mmc_of_parse(host->mmc); |
192 | if (ret) | |
193 | goto clocks_disable_unprepare; | |
194 | ||
195 | sdhci_get_of_property(pdev); | |
196 | ||
f5f17813 | 197 | pm_runtime_get_noresume(&pdev->dev); |
198 | pm_runtime_set_active(&pdev->dev); | |
199 | pm_runtime_enable(&pdev->dev); | |
200 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
201 | pm_runtime_use_autosuspend(&pdev->dev); | |
202 | ||
bb5f8ea4 | 203 | ret = sdhci_add_host(host); |
204 | if (ret) | |
f5f17813 | 205 | goto pm_runtime_disable; |
206 | ||
207 | pm_runtime_put_autosuspend(&pdev->dev); | |
bb5f8ea4 | 208 | |
209 | return 0; | |
210 | ||
f5f17813 | 211 | pm_runtime_disable: |
212 | pm_runtime_disable(&pdev->dev); | |
213 | pm_runtime_set_suspended(&pdev->dev); | |
2df9d58f | 214 | pm_runtime_put_noidle(&pdev->dev); |
bb5f8ea4 | 215 | clocks_disable_unprepare: |
216 | clk_disable_unprepare(priv->gck); | |
217 | clk_disable_unprepare(priv->mainck); | |
218 | hclock_disable_unprepare: | |
219 | clk_disable_unprepare(priv->hclock); | |
220 | sdhci_pltfm_free(pdev); | |
221 | return ret; | |
222 | } | |
223 | ||
224 | static int sdhci_at91_remove(struct platform_device *pdev) | |
225 | { | |
226 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
227 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
10f1c135 JZ |
228 | struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); |
229 | struct clk *gck = priv->gck; | |
230 | struct clk *hclock = priv->hclock; | |
231 | struct clk *mainck = priv->mainck; | |
bb5f8ea4 | 232 | |
f5f17813 | 233 | pm_runtime_get_sync(&pdev->dev); |
234 | pm_runtime_disable(&pdev->dev); | |
235 | pm_runtime_put_noidle(&pdev->dev); | |
236 | ||
bb5f8ea4 | 237 | sdhci_pltfm_unregister(pdev); |
238 | ||
10f1c135 JZ |
239 | clk_disable_unprepare(gck); |
240 | clk_disable_unprepare(hclock); | |
241 | clk_disable_unprepare(mainck); | |
bb5f8ea4 | 242 | |
243 | return 0; | |
244 | } | |
245 | ||
246 | static struct platform_driver sdhci_at91_driver = { | |
247 | .driver = { | |
248 | .name = "sdhci-at91", | |
bb5f8ea4 | 249 | .of_match_table = sdhci_at91_dt_match, |
f5f17813 | 250 | .pm = &sdhci_at91_dev_pm_ops, |
bb5f8ea4 | 251 | }, |
252 | .probe = sdhci_at91_probe, | |
253 | .remove = sdhci_at91_remove, | |
254 | }; | |
255 | ||
256 | module_platform_driver(sdhci_at91_driver); | |
257 | ||
258 | MODULE_DESCRIPTION("SDHCI driver for at91"); | |
259 | MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); | |
260 | MODULE_LICENSE("GPL v2"); |