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7657c3a7 AH |
1 | /* |
2 | * Freescale eSDHC controller driver. | |
3 | * | |
4 | * Copyright (c) 2007 Freescale Semiconductor, Inc. | |
5 | * Copyright (c) 2009 MontaVista Software, Inc. | |
6 | * | |
7 | * Authors: Xiaobo Xie <X.Xie@freescale.com> | |
8 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or (at | |
13 | * your option) any later version. | |
14 | */ | |
15 | ||
16 | #include <linux/io.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/mmc/host.h> | |
19 | #include "sdhci-of.h" | |
20 | #include "sdhci.h" | |
21 | ||
22 | /* | |
23 | * Ops and quirks for the Freescale eSDHC controller. | |
24 | */ | |
25 | ||
26 | #define ESDHC_DMA_SYSCTL 0x40c | |
27 | #define ESDHC_DMA_SNOOP 0x00000040 | |
28 | ||
29 | #define ESDHC_SYSTEM_CONTROL 0x2c | |
30 | #define ESDHC_CLOCK_MASK 0x0000fff0 | |
31 | #define ESDHC_PREDIV_SHIFT 8 | |
32 | #define ESDHC_DIVIDER_SHIFT 4 | |
33 | #define ESDHC_CLOCK_PEREN 0x00000004 | |
34 | #define ESDHC_CLOCK_HCKEN 0x00000002 | |
35 | #define ESDHC_CLOCK_IPGEN 0x00000001 | |
36 | ||
37 | #define ESDHC_HOST_CONTROL_RES 0x05 | |
38 | ||
39 | static u16 esdhc_readw(struct sdhci_host *host, int reg) | |
40 | { | |
41 | u16 ret; | |
42 | ||
43 | if (unlikely(reg == SDHCI_HOST_VERSION)) | |
44 | ret = in_be16(host->ioaddr + reg); | |
45 | else | |
46 | ret = sdhci_be32bs_readw(host, reg); | |
47 | return ret; | |
48 | } | |
49 | ||
50 | static void esdhc_writew(struct sdhci_host *host, u16 val, int reg) | |
51 | { | |
52 | if (reg == SDHCI_BLOCK_SIZE) { | |
53 | /* | |
54 | * Two last DMA bits are reserved, and first one is used for | |
55 | * non-standard blksz of 4096 bytes that we don't support | |
56 | * yet. So clear the DMA boundary bits. | |
57 | */ | |
58 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); | |
59 | } | |
60 | sdhci_be32bs_writew(host, val, reg); | |
61 | } | |
62 | ||
63 | static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg) | |
64 | { | |
65 | /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */ | |
66 | if (reg == SDHCI_HOST_CONTROL) | |
67 | val &= ~ESDHC_HOST_CONTROL_RES; | |
68 | sdhci_be32bs_writeb(host, val, reg); | |
69 | } | |
70 | ||
71 | static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock) | |
72 | { | |
73 | int pre_div = 2; | |
74 | int div = 1; | |
75 | ||
76 | clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN | | |
77 | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); | |
78 | ||
79 | if (clock == 0) | |
80 | goto out; | |
81 | ||
82 | while (host->max_clk / pre_div / 16 > clock && pre_div < 256) | |
83 | pre_div *= 2; | |
84 | ||
85 | while (host->max_clk / pre_div / div > clock && div < 16) | |
86 | div++; | |
87 | ||
88 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", | |
89 | clock, host->max_clk / pre_div / div); | |
90 | ||
91 | pre_div >>= 1; | |
92 | div--; | |
93 | ||
94 | setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN | | |
95 | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | | |
96 | div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT); | |
97 | mdelay(100); | |
98 | out: | |
99 | host->clock = clock; | |
100 | } | |
101 | ||
102 | static int esdhc_enable_dma(struct sdhci_host *host) | |
103 | { | |
104 | setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP); | |
105 | return 0; | |
106 | } | |
107 | ||
108 | static unsigned int esdhc_get_max_clock(struct sdhci_host *host) | |
109 | { | |
110 | struct sdhci_of_host *of_host = sdhci_priv(host); | |
111 | ||
112 | return of_host->clock; | |
113 | } | |
114 | ||
115 | static unsigned int esdhc_get_min_clock(struct sdhci_host *host) | |
116 | { | |
117 | struct sdhci_of_host *of_host = sdhci_priv(host); | |
118 | ||
119 | return of_host->clock / 256 / 16; | |
120 | } | |
121 | ||
122 | struct sdhci_of_data sdhci_esdhc = { | |
123 | .quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 | | |
124 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | | |
125 | SDHCI_QUIRK_NO_BUSY_IRQ | | |
126 | SDHCI_QUIRK_NONSTANDARD_CLOCK | | |
127 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | | |
128 | SDHCI_QUIRK_PIO_NEEDS_DELAY | | |
129 | SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET | | |
130 | SDHCI_QUIRK_NO_CARD_NO_RESET, | |
131 | .ops = { | |
dc297c92 MF |
132 | .read_l = sdhci_be32bs_readl, |
133 | .read_w = esdhc_readw, | |
134 | .read_b = sdhci_be32bs_readb, | |
135 | .write_l = sdhci_be32bs_writel, | |
136 | .write_w = esdhc_writew, | |
137 | .write_b = esdhc_writeb, | |
7657c3a7 AH |
138 | .set_clock = esdhc_set_clock, |
139 | .enable_dma = esdhc_enable_dma, | |
140 | .get_max_clock = esdhc_get_max_clock, | |
141 | .get_min_clock = esdhc_get_min_clock, | |
142 | }, | |
143 | }; |