projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc
[deliverable/linux.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
17#include <linux/pci.h>
18#include <linux/dma-mapping.h>
5a0e3ad6 19#include <linux/slab.h>
ccc92c23 20#include <linux/device.h>
b8c86fc5
PO		 21
22#include <linux/mmc/host.h>
23
24#include <asm/scatterlist.h>
25#include <asm/io.h>
26
27#include "sdhci.h"
28
29/*
30 * PCI registers
31 */
32
33#define PCI_SDHCI_IFPIO 0x00
34#define PCI_SDHCI_IFDMA 0x01
35#define PCI_SDHCI_IFVENDOR 0x02
36
37#define PCI_SLOT_INFO 0x40 /* 8 bits */
38#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
39#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
40
41#define MAX_SLOTS 8
42
22606405 43struct sdhci_pci_chip;
4489428a 44struct sdhci_pci_slot;
22606405
PO		 45
46struct sdhci_pci_fixes {
47 unsigned int quirks;
48
49 int (*probe)(struct sdhci_pci_chip*);
45211e21 50
4489428a 51 int (*probe_slot)(struct sdhci_pci_slot*);
1e72859e 52 void (*remove_slot)(struct sdhci_pci_slot*, int);
4489428a
PO		 53
54 int (*suspend)(struct sdhci_pci_chip*,
55 pm_message_t);
45211e21 56 int (*resume)(struct sdhci_pci_chip*);
22606405
PO		 57};
58
59struct sdhci_pci_slot {
60 struct sdhci_pci_chip *chip;
61 struct sdhci_host *host;
b8c86fc5 62
22606405
PO		 63 int pci_bar;
64};
65
66struct sdhci_pci_chip {
67 struct pci_dev *pdev;
68
69 unsigned int quirks;
70 const struct sdhci_pci_fixes *fixes;
71
72 int num_slots; /* Slots on controller */
73 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
74};
75
76
77/*****************************************************************************\
78 * *
79 * Hardware specific quirk handling *
80 * *
81\*****************************************************************************/
82
83static int ricoh_probe(struct sdhci_pci_chip *chip)
84{
c99436fb
CB		 85 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
86 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 87 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 88 return 0;
89}
90
91static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
92{
93 slot->host->caps =
94 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
95 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 96
ccc92c23
ML		 97 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
98 & SDHCI_CLOCK_BASE_MASK) |
99
100 SDHCI_TIMEOUT_CLK_UNIT |
101 SDHCI_CAN_VDD_330 |
102 SDHCI_CAN_DO_SDMA;
103 return 0;
104}
105
106static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
107{
108 /* Apply a delay to allow controller to settle */
109 /* Otherwise it becomes confused if card state changed
110 during suspend */
111 msleep(500);
22606405
PO		 112 return 0;
113}
114
115static const struct sdhci_pci_fixes sdhci_ricoh = {
116 .probe = ricoh_probe,
84938294
VK		 117 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
118 SDHCI_QUIRK_FORCE_DMA |
119 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 120};
121
ccc92c23
ML		 122static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
123 .probe_slot = ricoh_mmc_probe_slot,
124 .resume = ricoh_mmc_resume,
125 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
126 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
127 SDHCI_QUIRK_NO_CARD_NO_RESET |
128 SDHCI_QUIRK_MISSING_CAPS
129};
130
22606405
PO		 131static const struct sdhci_pci_fixes sdhci_ene_712 = {
132 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
133 SDHCI_QUIRK_BROKEN_DMA,
134};
135
136static const struct sdhci_pci_fixes sdhci_ene_714 = {
137 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
138 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
139 SDHCI_QUIRK_BROKEN_DMA,
140};
141
142static const struct sdhci_pci_fixes sdhci_cafe = {
143 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 144 SDHCI_QUIRK_NO_BUSY_IRQ |
ee53ab5d 145 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 146};
147
f9ee3eab
AC		 148/*
149 * ADMA operation is disabled for Moorestown platform due to
150 * hardware bugs.
151 */
152static int mrst_hc1_probe(struct sdhci_pci_chip *chip)
153{
154 /*
155 * slots number is fixed here for MRST as SDIO3 is never used and has
156 * hardware bugs.
157 */
158 chip->num_slots = 1;
159 return 0;
160}
161
162static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
163 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
164};
165
166static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1 = {
167 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
168 .probe = mrst_hc1_probe,
169};
170
29229052
XS		 171static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
172 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
173};
174
175static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc_sdio = {
176 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
177};
178
45211e21
PO		 179static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
180{
181 u8 scratch;
182 int ret;
183
184 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
185 if (ret)
186 return ret;
187
188 /*
189 * Turn PMOS on [bit 0], set over current detection to 2.4 V
190 * [bit 1:2] and enable over current debouncing [bit 6].
191 */
192 if (on)
193 scratch |= 0x47;
194 else
195 scratch &= ~0x47;
196
197 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
198 if (ret)
199 return ret;
200
201 return 0;
202}
203
204static int jmicron_probe(struct sdhci_pci_chip *chip)
205{
206 int ret;
207
93fc48c7
PO		 208 if (chip->pdev->revision == 0) {
209 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
210 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 211 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 212 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 213 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 214 }
215
4489428a
PO		 216 /*
217 * JMicron chips can have two interfaces to the same hardware
218 * in order to work around limitations in Microsoft's driver.
219 * We need to make sure we only bind to one of them.
220 *
221 * This code assumes two things:
222 *
223 * 1. The PCI code adds subfunctions in order.
224 *
225 * 2. The MMC interface has a lower subfunction number
226 * than the SD interface.
227 */
228 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) {
229 struct pci_dev *sd_dev;
230
231 sd_dev = NULL;
232 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
233 PCI_DEVICE_ID_JMICRON_JMB38X_MMC, sd_dev)) != NULL) {
234 if ((PCI_SLOT(chip->pdev->devfn) ==
235 PCI_SLOT(sd_dev->devfn)) &&
236 (chip->pdev->bus == sd_dev->bus))
237 break;
238 }
239
240 if (sd_dev) {
241 pci_dev_put(sd_dev);
242 dev_info(&chip->pdev->dev, "Refusing to bind to "
243 "secondary interface.\n");
244 return -ENODEV;
245 }
246 }
247
45211e21
PO		 248 /*
249 * JMicron chips need a bit of a nudge to enable the power
250 * output pins.
251 */
252 ret = jmicron_pmos(chip, 1);
253 if (ret) {
254 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
255 return ret;
256 }
257
258 return 0;
259}
260
4489428a
PO		 261static void jmicron_enable_mmc(struct sdhci_host *host, int on)
262{
263 u8 scratch;
264
265 scratch = readb(host->ioaddr + 0xC0);
266
267 if (on)
268 scratch |= 0x01;
269 else
270 scratch &= ~0x01;
271
272 writeb(scratch, host->ioaddr + 0xC0);
273}
274
275static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
276{
2134a922
PO		 277 if (slot->chip->pdev->revision == 0) {
278 u16 version;
279
280 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
281 version = (version & SDHCI_VENDOR_VER_MASK) >>
282 SDHCI_VENDOR_VER_SHIFT;
283
284 /*
285 * Older versions of the chip have lots of nasty glitches
286 * in the ADMA engine. It's best just to avoid it
287 * completely.
288 */
289 if (version < 0xAC)
290 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
291 }
292
4489428a
PO		 293 /*
294 * The secondary interface requires a bit set to get the
295 * interrupts.
296 */
297 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC)
298 jmicron_enable_mmc(slot->host, 1);
299
300 return 0;
301}
302
1e72859e 303static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 304{
1e72859e
PO		 305 if (dead)
306 return;
307
4489428a
PO		 308 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC)
309 jmicron_enable_mmc(slot->host, 0);
310}
311
312static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
313{
314 int i;
315
316 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) {
317 for (i = 0;i < chip->num_slots;i++)
318 jmicron_enable_mmc(chip->slots[i]->host, 0);
319 }
320
321 return 0;
322}
323
45211e21
PO		 324static int jmicron_resume(struct sdhci_pci_chip *chip)
325{
4489428a
PO		 326 int ret, i;
327
328 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) {
329 for (i = 0;i < chip->num_slots;i++)
330 jmicron_enable_mmc(chip->slots[i]->host, 1);
331 }
45211e21
PO		 332
333 ret = jmicron_pmos(chip, 1);
334 if (ret) {
335 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
336 return ret;
337 }
338
339 return 0;
340}
341
22606405 342static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 343 .probe = jmicron_probe,
344
4489428a
PO		 345 .probe_slot = jmicron_probe_slot,
346 .remove_slot = jmicron_remove_slot,
347
348 .suspend = jmicron_suspend,
45211e21 349 .resume = jmicron_resume,
22606405
PO		 350};
351
a7a6186c
NP		 352/* SysKonnect CardBus2SDIO extra registers */
353#define SYSKT_CTRL 0x200
354#define SYSKT_RDFIFO_STAT 0x204
355#define SYSKT_WRFIFO_STAT 0x208
356#define SYSKT_POWER_DATA 0x20c
357#define SYSKT_POWER_330 0xef
358#define SYSKT_POWER_300 0xf8
359#define SYSKT_POWER_184 0xcc
360#define SYSKT_POWER_CMD 0x20d
361#define SYSKT_POWER_START (1 << 7)
362#define SYSKT_POWER_STATUS 0x20e
363#define SYSKT_POWER_STATUS_OK (1 << 0)
364#define SYSKT_BOARD_REV 0x210
365#define SYSKT_CHIP_REV 0x211
366#define SYSKT_CONF_DATA 0x212
367#define SYSKT_CONF_DATA_1V8 (1 << 2)
368#define SYSKT_CONF_DATA_2V5 (1 << 1)
369#define SYSKT_CONF_DATA_3V3 (1 << 0)
370
371static int syskt_probe(struct sdhci_pci_chip *chip)
372{
373 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
374 chip->pdev->class &= ~0x0000FF;
375 chip->pdev->class |= PCI_SDHCI_IFDMA;
376 }
377 return 0;
378}
379
380static int syskt_probe_slot(struct sdhci_pci_slot *slot)
381{
382 int tm, ps;
383
384 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
385 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
386 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
387 "board rev %d.%d, chip rev %d.%d\n",
388 board_rev >> 4, board_rev & 0xf,
389 chip_rev >> 4, chip_rev & 0xf);
390 if (chip_rev >= 0x20)
391 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
392
393 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
394 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
395 udelay(50);
396 tm = 10; /* Wait max 1 ms */
397 do {
398 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
399 if (ps & SYSKT_POWER_STATUS_OK)
400 break;
401 udelay(100);
402 } while (--tm);
403 if (!tm) {
404 dev_err(&slot->chip->pdev->dev,
405 "power regulator never stabilized");
406 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
407 return -ENODEV;
408 }
409
410 return 0;
411}
412
413static const struct sdhci_pci_fixes sdhci_syskt = {
414 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
415 .probe = syskt_probe,
416 .probe_slot = syskt_probe_slot,
417};
418
557b0697
HW		 419static int via_probe(struct sdhci_pci_chip *chip)
420{
421 if (chip->pdev->revision == 0x10)
422 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
423
424 return 0;
425}
426
427static const struct sdhci_pci_fixes sdhci_via = {
428 .probe = via_probe,
429};
430
22606405 431static const struct pci_device_id pci_ids[] __devinitdata = {
b8c86fc5
PO		 432 {
433 .vendor = PCI_VENDOR_ID_RICOH,
434 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 435 .subvendor = PCI_ANY_ID,
b8c86fc5 436 .subdevice = PCI_ANY_ID,
22606405 437 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 438 },
439
ccc92c23
ML		 440 {
441 .vendor = PCI_VENDOR_ID_RICOH,
442 .device = 0x843,
443 .subvendor = PCI_ANY_ID,
444 .subdevice = PCI_ANY_ID,
445 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
446 },
447
568133eb
PC		 448 {
449 .vendor = PCI_VENDOR_ID_RICOH,
450 .device = 0xe822,
451 .subvendor = PCI_ANY_ID,
452 .subdevice = PCI_ANY_ID,
453 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
454 },
455
b8c86fc5
PO		 456 {
457 .vendor = PCI_VENDOR_ID_ENE,
458 .device = PCI_DEVICE_ID_ENE_CB712_SD,
459 .subvendor = PCI_ANY_ID,
460 .subdevice = PCI_ANY_ID,
22606405 461 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 462 },
463
464 {
465 .vendor = PCI_VENDOR_ID_ENE,
466 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
467 .subvendor = PCI_ANY_ID,
468 .subdevice = PCI_ANY_ID,
22606405 469 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 470 },
471
472 {
473 .vendor = PCI_VENDOR_ID_ENE,
474 .device = PCI_DEVICE_ID_ENE_CB714_SD,
475 .subvendor = PCI_ANY_ID,
476 .subdevice = PCI_ANY_ID,
22606405 477 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 478 },
479
480 {
481 .vendor = PCI_VENDOR_ID_ENE,
482 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
483 .subvendor = PCI_ANY_ID,
484 .subdevice = PCI_ANY_ID,
22606405 485 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 486 },
487
488 {
489 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 490 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 491 .subvendor = PCI_ANY_ID,
492 .subdevice = PCI_ANY_ID,
22606405 493 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 494 },
495
496 {
497 .vendor = PCI_VENDOR_ID_JMICRON,
498 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
499 .subvendor = PCI_ANY_ID,
500 .subdevice = PCI_ANY_ID,
22606405 501 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 502 },
503
4489428a
PO		 504 {
505 .vendor = PCI_VENDOR_ID_JMICRON,
506 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
507 .subvendor = PCI_ANY_ID,
508 .subdevice = PCI_ANY_ID,
509 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
510 },
511
a7a6186c
NP		 512 {
513 .vendor = PCI_VENDOR_ID_SYSKONNECT,
514 .device = 0x8000,
515 .subvendor = PCI_ANY_ID,
516 .subdevice = PCI_ANY_ID,
517 .driver_data = (kernel_ulong_t)&sdhci_syskt,
518 },
519
557b0697
HW		 520 {
521 .vendor = PCI_VENDOR_ID_VIA,
522 .device = 0x95d0,
523 .subvendor = PCI_ANY_ID,
524 .subdevice = PCI_ANY_ID,
525 .driver_data = (kernel_ulong_t)&sdhci_via,
526 },
527
29229052
XS		 528 {
529 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 530 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
531 .subvendor = PCI_ANY_ID,
532 .subdevice = PCI_ANY_ID,
533 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
534 },
535
536 {
537 .vendor = PCI_VENDOR_ID_INTEL,
538 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
539 .subvendor = PCI_ANY_ID,
540 .subdevice = PCI_ANY_ID,
541 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1,
542 },
543
544 {
545 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 546 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
547 .subvendor = PCI_ANY_ID,
548 .subdevice = PCI_ANY_ID,
549 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
550 },
551
552 {
553 .vendor = PCI_VENDOR_ID_INTEL,
554 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
555 .subvendor = PCI_ANY_ID,
556 .subdevice = PCI_ANY_ID,
557 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
558 },
559
560 {
561 .vendor = PCI_VENDOR_ID_INTEL,
562 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
563 .subvendor = PCI_ANY_ID,
564 .subdevice = PCI_ANY_ID,
565 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
566 },
567
568 {
569 .vendor = PCI_VENDOR_ID_INTEL,
570 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
571 .subvendor = PCI_ANY_ID,
572 .subdevice = PCI_ANY_ID,
573 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
574 },
575
576 {
577 .vendor = PCI_VENDOR_ID_INTEL,
578 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
579 .subvendor = PCI_ANY_ID,
580 .subdevice = PCI_ANY_ID,
581 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
582 },
583
b8c86fc5
PO		 584 { /* Generic SD host controller */
585 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
586 },
587
588 { /* end: all zeroes */ },
589};
590
591MODULE_DEVICE_TABLE(pci, pci_ids);
592
b8c86fc5
PO		 593/*****************************************************************************\
594 * *
595 * SDHCI core callbacks *
596 * *
597\*****************************************************************************/
598
599static int sdhci_pci_enable_dma(struct sdhci_host *host)
600{
601 struct sdhci_pci_slot *slot;
602 struct pci_dev *pdev;
603 int ret;
604
605 slot = sdhci_priv(host);
606 pdev = slot->chip->pdev;
607
608 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
609 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 610 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 611 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
612 "doesn't fully claim to support it.\n");
613 }
614
284901a9 615 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 616 if (ret)
617 return ret;
618
619 pci_set_master(pdev);
620
621 return 0;
622}
623
624static struct sdhci_ops sdhci_pci_ops = {
625 .enable_dma = sdhci_pci_enable_dma,
626};
627
628/*****************************************************************************\
629 * *
630 * Suspend/resume *
631 * *
632\*****************************************************************************/
633
634#ifdef CONFIG_PM
635
636static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state)
637{
638 struct sdhci_pci_chip *chip;
639 struct sdhci_pci_slot *slot;
2f4cbb3d 640 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 641 int i, ret;
642
643 chip = pci_get_drvdata(pdev);
644 if (!chip)
645 return 0;
646
647 for (i = 0;i < chip->num_slots;i++) {
648 slot = chip->slots[i];
649 if (!slot)
650 continue;
651
652 ret = sdhci_suspend_host(slot->host, state);
653
654 if (ret) {
655 for (i--;i >= 0;i--)
656 sdhci_resume_host(chip->slots[i]->host);
657 return ret;
658 }
2f4cbb3d
NP		 659
660 pm_flags |= slot->host->mmc->pm_flags;
b8c86fc5
PO		 661 }
662
4489428a
PO		 663 if (chip->fixes && chip->fixes->suspend) {
664 ret = chip->fixes->suspend(chip, state);
665 if (ret) {
666 for (i = chip->num_slots - 1;i >= 0;i--)
667 sdhci_resume_host(chip->slots[i]->host);
668 return ret;
669 }
670 }
671
b8c86fc5 672 pci_save_state(pdev);
2f4cbb3d
NP		 673 if (pm_flags & MMC_PM_KEEP_POWER) {
674 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
675 pci_enable_wake(pdev, PCI_D3hot, 1);
676 pci_set_power_state(pdev, PCI_D3hot);
677 } else {
678 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
679 pci_disable_device(pdev);
680 pci_set_power_state(pdev, pci_choose_state(pdev, state));
681 }
b8c86fc5
PO		 682
683 return 0;
684}
685
686static int sdhci_pci_resume (struct pci_dev *pdev)
687{
688 struct sdhci_pci_chip *chip;
689 struct sdhci_pci_slot *slot;
690 int i, ret;
691
692 chip = pci_get_drvdata(pdev);
693 if (!chip)
694 return 0;
695
696 pci_set_power_state(pdev, PCI_D0);
697 pci_restore_state(pdev);
698 ret = pci_enable_device(pdev);
699 if (ret)
700 return ret;
701
45211e21
PO		 702 if (chip->fixes && chip->fixes->resume) {
703 ret = chip->fixes->resume(chip);
704 if (ret)
705 return ret;
706 }
707
b8c86fc5
PO		 708 for (i = 0;i < chip->num_slots;i++) {
709 slot = chip->slots[i];
710 if (!slot)
711 continue;
712
713 ret = sdhci_resume_host(slot->host);
714 if (ret)
715 return ret;
716 }
717
718 return 0;
719}
720
721#else /* CONFIG_PM */
722
723#define sdhci_pci_suspend NULL
724#define sdhci_pci_resume NULL
725
726#endif /* CONFIG_PM */
727
728/*****************************************************************************\
729 * *
730 * Device probing/removal *
731 * *
732\*****************************************************************************/
733
734static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
735 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
736{
737 struct sdhci_pci_slot *slot;
738 struct sdhci_host *host;
739
740 resource_size_t addr;
741
742 int ret;
743
744 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
745 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
746 return ERR_PTR(-ENODEV);
747 }
748
749 if (pci_resource_len(pdev, bar) != 0x100) {
750 dev_err(&pdev->dev, "Invalid iomem size. You may "
751 "experience problems.\n");
752 }
753
754 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
755 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
756 return ERR_PTR(-ENODEV);
757 }
758
759 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
760 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
761 return ERR_PTR(-ENODEV);
762 }
763
764 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
765 if (IS_ERR(host)) {
c60a32cd 766 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 767 return ERR_CAST(host);
b8c86fc5
PO		 768 }
769
770 slot = sdhci_priv(host);
771
772 slot->chip = chip;
773 slot->host = host;
774 slot->pci_bar = bar;
775
776 host->hw_name = "PCI";
777 host->ops = &sdhci_pci_ops;
778 host->quirks = chip->quirks;
779
780 host->irq = pdev->irq;
781
782 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
783 if (ret) {
784 dev_err(&pdev->dev, "cannot request region\n");
c60a32cd 785 goto free;
b8c86fc5
PO		 786 }
787
788 addr = pci_resource_start(pdev, bar);
092f82ed 789 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 790 if (!host->ioaddr) {
791 dev_err(&pdev->dev, "failed to remap registers\n");
792 goto release;
793 }
794
4489428a
PO		 795 if (chip->fixes && chip->fixes->probe_slot) {
796 ret = chip->fixes->probe_slot(slot);
797 if (ret)
798 goto unmap;
799 }
800
2f4cbb3d
NP		 801 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
802
b8c86fc5
PO		 803 ret = sdhci_add_host(host);
804 if (ret)
4489428a 805 goto remove;
b8c86fc5
PO		 806
807 return slot;
808
4489428a
PO		 809remove:
810 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 811 chip->fixes->remove_slot(slot, 0);
4489428a 812
b8c86fc5
PO		 813unmap:
814 iounmap(host->ioaddr);
815
816release:
817 pci_release_region(pdev, bar);
c60a32cd
DC		 818
819free:
b8c86fc5
PO		 820 sdhci_free_host(host);
821
822 return ERR_PTR(ret);
823}
824
825static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
826{
1e72859e
PO		 827 int dead;
828 u32 scratch;
829
830 dead = 0;
831 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
832 if (scratch == (u32)-1)
833 dead = 1;
834
835 sdhci_remove_host(slot->host, dead);
4489428a
PO		 836
837 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 838 slot->chip->fixes->remove_slot(slot, dead);
4489428a 839
b8c86fc5 840 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 841
b8c86fc5
PO		 842 sdhci_free_host(slot->host);
843}
844
845static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
846 const struct pci_device_id *ent)
847{
848 struct sdhci_pci_chip *chip;
849 struct sdhci_pci_slot *slot;
850
851 u8 slots, rev, first_bar;
852 int ret, i;
853
854 BUG_ON(pdev == NULL);
855 BUG_ON(ent == NULL);
856
857 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
858
859 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
860 (int)pdev->vendor, (int)pdev->device, (int)rev);
861
862 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
863 if (ret)
864 return ret;
865
866 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
867 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
868 if (slots == 0)
869 return -ENODEV;
870
871 BUG_ON(slots > MAX_SLOTS);
872
873 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
874 if (ret)
875 return ret;
876
877 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
878
879 if (first_bar > 5) {
880 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
881 return -ENODEV;
882 }
883
884 ret = pci_enable_device(pdev);
885 if (ret)
886 return ret;
887
888 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
889 if (!chip) {
890 ret = -ENOMEM;
891 goto err;
892 }
893
894 chip->pdev = pdev;
22606405
PO		 895 chip->fixes = (const struct sdhci_pci_fixes*)ent->driver_data;
896 if (chip->fixes)
897 chip->quirks = chip->fixes->quirks;
b8c86fc5
PO		 898 chip->num_slots = slots;
899
900 pci_set_drvdata(pdev, chip);
901
22606405
PO		 902 if (chip->fixes && chip->fixes->probe) {
903 ret = chip->fixes->probe(chip);
904 if (ret)
905 goto free;
906 }
907
225d85fe
AC		 908 slots = chip->num_slots; /* Quirk may have changed this */
909
b8c86fc5
PO		 910 for (i = 0;i < slots;i++) {
911 slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
912 if (IS_ERR(slot)) {
913 for (i--;i >= 0;i--)
914 sdhci_pci_remove_slot(chip->slots[i]);
915 ret = PTR_ERR(slot);
916 goto free;
917 }
918
919 chip->slots[i] = slot;
920 }
921
922 return 0;
923
924free:
925 pci_set_drvdata(pdev, NULL);
926 kfree(chip);
927
928err:
929 pci_disable_device(pdev);
930 return ret;
931}
932
933static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
934{
935 int i;
936 struct sdhci_pci_chip *chip;
937
938 chip = pci_get_drvdata(pdev);
939
940 if (chip) {
941 for (i = 0;i < chip->num_slots; i++)
942 sdhci_pci_remove_slot(chip->slots[i]);
943
944 pci_set_drvdata(pdev, NULL);
945 kfree(chip);
946 }
947
948 pci_disable_device(pdev);
949}
950
951static struct pci_driver sdhci_driver = {
952 .name = "sdhci-pci",
953 .id_table = pci_ids,
954 .probe = sdhci_pci_probe,
955 .remove = __devexit_p(sdhci_pci_remove),
956 .suspend = sdhci_pci_suspend,
957 .resume = sdhci_pci_resume,
958};
959
960/*****************************************************************************\
961 * *
962 * Driver init/exit *
963 * *
964\*****************************************************************************/
965
966static int __init sdhci_drv_init(void)
967{
968 return pci_register_driver(&sdhci_driver);
969}
970
971static void __exit sdhci_drv_exit(void)
972{
973 pci_unregister_driver(&sdhci_driver);
974}
975
976module_init(sdhci_drv_init);
977module_exit(sdhci_drv_exit);
978
32710e8f 979MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 980MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
981MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.36765 seconds and 5 git commands to generate.