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mmc: sdhci-pci: add flag for devices that can support runtime PM
[deliverable/linux.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
b177bc91
AP		 23#include <linux/scatterlist.h>
24#include <linux/io.h>
0f201655
AH		 25#include <linux/gpio.h>
26#include <linux/sfi.h>
66fd8ad5 27#include <linux/pm_runtime.h>
b8c86fc5
PO		 28
29#include "sdhci.h"
30
31/*
32 * PCI registers
33 */
34
35#define PCI_SDHCI_IFPIO 0x00
36#define PCI_SDHCI_IFDMA 0x01
37#define PCI_SDHCI_IFVENDOR 0x02
38
39#define PCI_SLOT_INFO 0x40 /* 8 bits */
40#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
41#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
42
43#define MAX_SLOTS 8
44
22606405 45struct sdhci_pci_chip;
4489428a 46struct sdhci_pci_slot;
22606405
PO		 47
48struct sdhci_pci_fixes {
49 unsigned int quirks;
c43fd774 50 bool allow_runtime_pm;
22606405 51
b177bc91 52 int (*probe) (struct sdhci_pci_chip *);
45211e21 53
b177bc91
AP		 54 int (*probe_slot) (struct sdhci_pci_slot *);
55 void (*remove_slot) (struct sdhci_pci_slot *, int);
4489428a 56
b177bc91 57 int (*suspend) (struct sdhci_pci_chip *,
4489428a 58 pm_message_t);
b177bc91 59 int (*resume) (struct sdhci_pci_chip *);
22606405
PO		 60};
61
62struct sdhci_pci_slot {
63 struct sdhci_pci_chip *chip;
64 struct sdhci_host *host;
b8c86fc5 65
22606405 66 int pci_bar;
0f201655 67 int rst_n_gpio;
66fd8ad5
AH		 68 int cd_gpio;
69 int cd_irq;
22606405
PO		 70};
71
72struct sdhci_pci_chip {
73 struct pci_dev *pdev;
74
75 unsigned int quirks;
c43fd774 76 bool allow_runtime_pm;
22606405
PO		 77 const struct sdhci_pci_fixes *fixes;
78
79 int num_slots; /* Slots on controller */
80 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
81};
82
83
84/*****************************************************************************\
85 * *
86 * Hardware specific quirk handling *
87 * *
88\*****************************************************************************/
89
90static int ricoh_probe(struct sdhci_pci_chip *chip)
91{
c99436fb
CB		 92 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
93 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 94 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 95 return 0;
96}
97
98static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
99{
100 slot->host->caps =
101 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
102 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 103
ccc92c23
ML		 104 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
105 & SDHCI_CLOCK_BASE_MASK) |
106
107 SDHCI_TIMEOUT_CLK_UNIT |
108 SDHCI_CAN_VDD_330 |
109 SDHCI_CAN_DO_SDMA;
110 return 0;
111}
112
113static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
114{
115 /* Apply a delay to allow controller to settle */
116 /* Otherwise it becomes confused if card state changed
117 during suspend */
118 msleep(500);
22606405
PO		 119 return 0;
120}
121
122static const struct sdhci_pci_fixes sdhci_ricoh = {
123 .probe = ricoh_probe,
84938294
VK		 124 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
125 SDHCI_QUIRK_FORCE_DMA |
126 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 127};
128
ccc92c23
ML		 129static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
130 .probe_slot = ricoh_mmc_probe_slot,
131 .resume = ricoh_mmc_resume,
132 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
133 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
134 SDHCI_QUIRK_NO_CARD_NO_RESET |
135 SDHCI_QUIRK_MISSING_CAPS
136};
137
22606405
PO		 138static const struct sdhci_pci_fixes sdhci_ene_712 = {
139 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
140 SDHCI_QUIRK_BROKEN_DMA,
141};
142
143static const struct sdhci_pci_fixes sdhci_ene_714 = {
144 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
145 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
146 SDHCI_QUIRK_BROKEN_DMA,
147};
148
149static const struct sdhci_pci_fixes sdhci_cafe = {
150 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 151 SDHCI_QUIRK_NO_BUSY_IRQ |
ee53ab5d 152 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 153};
154
68077b02
ML		 155static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
156{
157 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
158 return 0;
159}
160
f9ee3eab
AC		 161/*
162 * ADMA operation is disabled for Moorestown platform due to
163 * hardware bugs.
164 */
35ac6f08 165static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 166{
167 /*
35ac6f08
JP		 168 * slots number is fixed here for MRST as SDIO3/5 are never used and
169 * have hardware bugs.
f9ee3eab
AC		 170 */
171 chip->num_slots = 1;
172 return 0;
173}
174
0f201655
AH		 175/* Medfield eMMC hardware reset GPIOs */
176static int mfd_emmc0_rst_gpio = -EINVAL;
177static int mfd_emmc1_rst_gpio = -EINVAL;
178
179static int mfd_emmc_gpio_parse(struct sfi_table_header *table)
180{
181 struct sfi_table_simple *sb = (struct sfi_table_simple *)table;
182 struct sfi_gpio_table_entry *entry;
183 int i, num;
184
185 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
186 entry = (struct sfi_gpio_table_entry *)sb->pentry;
187
188 for (i = 0; i < num; i++, entry++) {
189 if (!strncmp(entry->pin_name, "emmc0_rst", SFI_NAME_LEN))
190 mfd_emmc0_rst_gpio = entry->pin_no;
191 else if (!strncmp(entry->pin_name, "emmc1_rst", SFI_NAME_LEN))
192 mfd_emmc1_rst_gpio = entry->pin_no;
193 }
194
195 return 0;
196}
197
66fd8ad5
AH		 198#ifdef CONFIG_PM_RUNTIME
199
200static irqreturn_t mfd_sd_cd(int irq, void *dev_id)
201{
202 struct sdhci_pci_slot *slot = dev_id;
203 struct sdhci_host *host = slot->host;
204
205 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
206 return IRQ_HANDLED;
207}
208
209#define MFLD_SD_CD_PIN 69
210
211static int mfd_sd_probe_slot(struct sdhci_pci_slot *slot)
212{
213 int err, irq, gpio = MFLD_SD_CD_PIN;
214
215 slot->cd_gpio = -EINVAL;
216 slot->cd_irq = -EINVAL;
217
218 err = gpio_request(gpio, "sd_cd");
219 if (err < 0)
220 goto out;
221
222 err = gpio_direction_input(gpio);
223 if (err < 0)
224 goto out_free;
225
226 irq = gpio_to_irq(gpio);
227 if (irq < 0)
228 goto out_free;
229
230 err = request_irq(irq, mfd_sd_cd, IRQF_TRIGGER_RISING |
231 IRQF_TRIGGER_FALLING, "sd_cd", slot);
232 if (err)
233 goto out_free;
234
235 slot->cd_gpio = gpio;
236 slot->cd_irq = irq;
237 slot->host->quirks2 |= SDHCI_QUIRK2_OWN_CARD_DETECTION;
238
239 return 0;
240
241out_free:
242 gpio_free(gpio);
243out:
244 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
245 return 0;
246}
247
248static void mfd_sd_remove_slot(struct sdhci_pci_slot *slot, int dead)
249{
250 if (slot->cd_irq >= 0)
251 free_irq(slot->cd_irq, slot);
252 gpio_free(slot->cd_gpio);
253}
254
255#else
256
257#define mfd_sd_probe_slot NULL
258#define mfd_sd_remove_slot NULL
259
260#endif
261
0d013bcf
AH		 262static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
263{
0f201655
AH		 264 const char *name = NULL;
265 int gpio = -EINVAL;
266
267 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, mfd_emmc_gpio_parse);
268
269 switch (slot->chip->pdev->device) {
270 case PCI_DEVICE_ID_INTEL_MFD_EMMC0:
271 gpio = mfd_emmc0_rst_gpio;
272 name = "eMMC0_reset";
273 break;
274 case PCI_DEVICE_ID_INTEL_MFD_EMMC1:
275 gpio = mfd_emmc1_rst_gpio;
276 name = "eMMC1_reset";
277 break;
278 }
279
280 if (!gpio_request(gpio, name)) {
281 gpio_direction_output(gpio, 1);
282 slot->rst_n_gpio = gpio;
283 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
284 }
285
66fd8ad5 286 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
0f201655 287
f7c56ef2
AH		 288 slot->host->mmc->caps2 = MMC_CAP2_BOOTPART_NOACC;
289
0d013bcf
AH		 290 return 0;
291}
292
0f201655
AH		 293static void mfd_emmc_remove_slot(struct sdhci_pci_slot *slot, int dead)
294{
295 gpio_free(slot->rst_n_gpio);
296}
297
f9ee3eab
AC		 298static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
299 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 300 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 301};
302
35ac6f08 303static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 304 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 305 .probe = mrst_hc_probe,
f9ee3eab
AC		 306};
307
29229052
XS		 308static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
309 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 310 .allow_runtime_pm = true,
66fd8ad5
AH		 311 .probe_slot = mfd_sd_probe_slot,
312 .remove_slot = mfd_sd_remove_slot,
29229052
XS		 313};
314
0d013bcf
AH		 315static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
316 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 317 .allow_runtime_pm = true,
0d013bcf
AH		 318};
319
320static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 321 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 322 .allow_runtime_pm = true,
0d013bcf 323 .probe_slot = mfd_emmc_probe_slot,
0f201655 324 .remove_slot = mfd_emmc_remove_slot,
29229052
XS		 325};
326
26daa1ed
JL		 327/* O2Micro extra registers */
328#define O2_SD_LOCK_WP 0xD3
329#define O2_SD_MULTI_VCC3V 0xEE
330#define O2_SD_CLKREQ 0xEC
331#define O2_SD_CAPS 0xE0
332#define O2_SD_ADMA1 0xE2
333#define O2_SD_ADMA2 0xE7
334#define O2_SD_INF_MOD 0xF1
335
336static int o2_probe(struct sdhci_pci_chip *chip)
337{
338 int ret;
339 u8 scratch;
340
341 switch (chip->pdev->device) {
342 case PCI_DEVICE_ID_O2_8220:
343 case PCI_DEVICE_ID_O2_8221:
344 case PCI_DEVICE_ID_O2_8320:
345 case PCI_DEVICE_ID_O2_8321:
346 /* This extra setup is required due to broken ADMA. */
347 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
348 if (ret)
349 return ret;
350 scratch &= 0x7f;
351 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
352
353 /* Set Multi 3 to VCC3V# */
354 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
355
356 /* Disable CLK_REQ# support after media DET */
357 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
358 if (ret)
359 return ret;
360 scratch |= 0x20;
361 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
362
363 /* Choose capabilities, enable SDMA. We have to write 0x01
364 * to the capabilities register first to unlock it.
365 */
366 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
367 if (ret)
368 return ret;
369 scratch |= 0x01;
370 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
371 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
372
373 /* Disable ADMA1/2 */
374 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
375 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
376
377 /* Disable the infinite transfer mode */
378 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
379 if (ret)
380 return ret;
381 scratch |= 0x08;
382 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
383
384 /* Lock WP */
385 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
386 if (ret)
387 return ret;
388 scratch |= 0x80;
389 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
390 }
391
392 return 0;
393}
394
45211e21
PO		 395static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
396{
397 u8 scratch;
398 int ret;
399
400 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
401 if (ret)
402 return ret;
403
404 /*
405 * Turn PMOS on [bit 0], set over current detection to 2.4 V
406 * [bit 1:2] and enable over current debouncing [bit 6].
407 */
408 if (on)
409 scratch |= 0x47;
410 else
411 scratch &= ~0x47;
412
413 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
414 if (ret)
415 return ret;
416
417 return 0;
418}
419
420static int jmicron_probe(struct sdhci_pci_chip *chip)
421{
422 int ret;
8f230f45 423 u16 mmcdev = 0;
45211e21 424
93fc48c7
PO		 425 if (chip->pdev->revision == 0) {
426 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
427 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 428 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 429 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 430 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 431 }
432
4489428a
PO		 433 /*
434 * JMicron chips can have two interfaces to the same hardware
435 * in order to work around limitations in Microsoft's driver.
436 * We need to make sure we only bind to one of them.
437 *
438 * This code assumes two things:
439 *
440 * 1. The PCI code adds subfunctions in order.
441 *
442 * 2. The MMC interface has a lower subfunction number
443 * than the SD interface.
444 */
8f230f45
TI		 445 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
446 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
447 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
448 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
449
450 if (mmcdev) {
4489428a
PO		 451 struct pci_dev *sd_dev;
452
453 sd_dev = NULL;
454 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 455 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 456 if ((PCI_SLOT(chip->pdev->devfn) ==
457 PCI_SLOT(sd_dev->devfn)) &&
458 (chip->pdev->bus == sd_dev->bus))
459 break;
460 }
461
462 if (sd_dev) {
463 pci_dev_put(sd_dev);
464 dev_info(&chip->pdev->dev, "Refusing to bind to "
465 "secondary interface.\n");
466 return -ENODEV;
467 }
468 }
469
45211e21
PO		 470 /*
471 * JMicron chips need a bit of a nudge to enable the power
472 * output pins.
473 */
474 ret = jmicron_pmos(chip, 1);
475 if (ret) {
476 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
477 return ret;
478 }
479
82b0e23a
TI		 480 /* quirk for unsable RO-detection on JM388 chips */
481 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
482 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
483 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
484
45211e21
PO		 485 return 0;
486}
487
4489428a
PO		 488static void jmicron_enable_mmc(struct sdhci_host *host, int on)
489{
490 u8 scratch;
491
492 scratch = readb(host->ioaddr + 0xC0);
493
494 if (on)
495 scratch |= 0x01;
496 else
497 scratch &= ~0x01;
498
499 writeb(scratch, host->ioaddr + 0xC0);
500}
501
502static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
503{
2134a922
PO		 504 if (slot->chip->pdev->revision == 0) {
505 u16 version;
506
507 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
508 version = (version & SDHCI_VENDOR_VER_MASK) >>
509 SDHCI_VENDOR_VER_SHIFT;
510
511 /*
512 * Older versions of the chip have lots of nasty glitches
513 * in the ADMA engine. It's best just to avoid it
514 * completely.
515 */
516 if (version < 0xAC)
517 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
518 }
519
8f230f45
TI		 520 /* JM388 MMC doesn't support 1.8V while SD supports it */
521 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
522 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
523 MMC_VDD_29_30 | MMC_VDD_30_31 |
524 MMC_VDD_165_195; /* allow 1.8V */
525 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
526 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
527 }
528
4489428a
PO		 529 /*
530 * The secondary interface requires a bit set to get the
531 * interrupts.
532 */
8f230f45
TI		 533 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
534 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 535 jmicron_enable_mmc(slot->host, 1);
536
d75c1084
TI		 537 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
538
4489428a
PO		 539 return 0;
540}
541
1e72859e 542static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 543{
1e72859e
PO		 544 if (dead)
545 return;
546
8f230f45
TI		 547 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
548 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 549 jmicron_enable_mmc(slot->host, 0);
550}
551
552static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
553{
554 int i;
555
8f230f45
TI		 556 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
557 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 558 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 559 jmicron_enable_mmc(chip->slots[i]->host, 0);
560 }
561
562 return 0;
563}
564
45211e21
PO		 565static int jmicron_resume(struct sdhci_pci_chip *chip)
566{
4489428a
PO		 567 int ret, i;
568
8f230f45
TI		 569 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
570 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 571 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 572 jmicron_enable_mmc(chip->slots[i]->host, 1);
573 }
45211e21
PO		 574
575 ret = jmicron_pmos(chip, 1);
576 if (ret) {
577 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
578 return ret;
579 }
580
581 return 0;
582}
583
26daa1ed
JL		 584static const struct sdhci_pci_fixes sdhci_o2 = {
585 .probe = o2_probe,
586};
587
22606405 588static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 589 .probe = jmicron_probe,
590
4489428a
PO		 591 .probe_slot = jmicron_probe_slot,
592 .remove_slot = jmicron_remove_slot,
593
594 .suspend = jmicron_suspend,
45211e21 595 .resume = jmicron_resume,
22606405
PO		 596};
597
a7a6186c
NP		 598/* SysKonnect CardBus2SDIO extra registers */
599#define SYSKT_CTRL 0x200
600#define SYSKT_RDFIFO_STAT 0x204
601#define SYSKT_WRFIFO_STAT 0x208
602#define SYSKT_POWER_DATA 0x20c
603#define SYSKT_POWER_330 0xef
604#define SYSKT_POWER_300 0xf8
605#define SYSKT_POWER_184 0xcc
606#define SYSKT_POWER_CMD 0x20d
607#define SYSKT_POWER_START (1 << 7)
608#define SYSKT_POWER_STATUS 0x20e
609#define SYSKT_POWER_STATUS_OK (1 << 0)
610#define SYSKT_BOARD_REV 0x210
611#define SYSKT_CHIP_REV 0x211
612#define SYSKT_CONF_DATA 0x212
613#define SYSKT_CONF_DATA_1V8 (1 << 2)
614#define SYSKT_CONF_DATA_2V5 (1 << 1)
615#define SYSKT_CONF_DATA_3V3 (1 << 0)
616
617static int syskt_probe(struct sdhci_pci_chip *chip)
618{
619 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
620 chip->pdev->class &= ~0x0000FF;
621 chip->pdev->class |= PCI_SDHCI_IFDMA;
622 }
623 return 0;
624}
625
626static int syskt_probe_slot(struct sdhci_pci_slot *slot)
627{
628 int tm, ps;
629
630 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
631 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
632 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
633 "board rev %d.%d, chip rev %d.%d\n",
634 board_rev >> 4, board_rev & 0xf,
635 chip_rev >> 4, chip_rev & 0xf);
636 if (chip_rev >= 0x20)
637 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
638
639 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
640 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
641 udelay(50);
642 tm = 10; /* Wait max 1 ms */
643 do {
644 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
645 if (ps & SYSKT_POWER_STATUS_OK)
646 break;
647 udelay(100);
648 } while (--tm);
649 if (!tm) {
650 dev_err(&slot->chip->pdev->dev,
651 "power regulator never stabilized");
652 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
653 return -ENODEV;
654 }
655
656 return 0;
657}
658
659static const struct sdhci_pci_fixes sdhci_syskt = {
660 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
661 .probe = syskt_probe,
662 .probe_slot = syskt_probe_slot,
663};
664
557b0697
HW		 665static int via_probe(struct sdhci_pci_chip *chip)
666{
667 if (chip->pdev->revision == 0x10)
668 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
669
670 return 0;
671}
672
673static const struct sdhci_pci_fixes sdhci_via = {
674 .probe = via_probe,
675};
676
22606405 677static const struct pci_device_id pci_ids[] __devinitdata = {
b8c86fc5
PO		 678 {
679 .vendor = PCI_VENDOR_ID_RICOH,
680 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 681 .subvendor = PCI_ANY_ID,
b8c86fc5 682 .subdevice = PCI_ANY_ID,
22606405 683 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 684 },
685
ccc92c23
ML		 686 {
687 .vendor = PCI_VENDOR_ID_RICOH,
688 .device = 0x843,
689 .subvendor = PCI_ANY_ID,
690 .subdevice = PCI_ANY_ID,
691 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
692 },
693
568133eb
PC		 694 {
695 .vendor = PCI_VENDOR_ID_RICOH,
696 .device = 0xe822,
697 .subvendor = PCI_ANY_ID,
698 .subdevice = PCI_ANY_ID,
699 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
700 },
701
5fd11c07
MI		 702 {
703 .vendor = PCI_VENDOR_ID_RICOH,
704 .device = 0xe823,
705 .subvendor = PCI_ANY_ID,
706 .subdevice = PCI_ANY_ID,
707 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
708 },
709
b8c86fc5
PO		 710 {
711 .vendor = PCI_VENDOR_ID_ENE,
712 .device = PCI_DEVICE_ID_ENE_CB712_SD,
713 .subvendor = PCI_ANY_ID,
714 .subdevice = PCI_ANY_ID,
22606405 715 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 716 },
717
718 {
719 .vendor = PCI_VENDOR_ID_ENE,
720 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
721 .subvendor = PCI_ANY_ID,
722 .subdevice = PCI_ANY_ID,
22606405 723 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 724 },
725
726 {
727 .vendor = PCI_VENDOR_ID_ENE,
728 .device = PCI_DEVICE_ID_ENE_CB714_SD,
729 .subvendor = PCI_ANY_ID,
730 .subdevice = PCI_ANY_ID,
22606405 731 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 732 },
733
734 {
735 .vendor = PCI_VENDOR_ID_ENE,
736 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
737 .subvendor = PCI_ANY_ID,
738 .subdevice = PCI_ANY_ID,
22606405 739 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 740 },
741
742 {
743 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 744 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 745 .subvendor = PCI_ANY_ID,
746 .subdevice = PCI_ANY_ID,
22606405 747 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 748 },
749
750 {
751 .vendor = PCI_VENDOR_ID_JMICRON,
752 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
753 .subvendor = PCI_ANY_ID,
754 .subdevice = PCI_ANY_ID,
22606405 755 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 756 },
757
4489428a
PO		 758 {
759 .vendor = PCI_VENDOR_ID_JMICRON,
760 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
761 .subvendor = PCI_ANY_ID,
762 .subdevice = PCI_ANY_ID,
763 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 764 },
765
766 {
767 .vendor = PCI_VENDOR_ID_JMICRON,
768 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
769 .subvendor = PCI_ANY_ID,
770 .subdevice = PCI_ANY_ID,
771 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
772 },
773
774 {
775 .vendor = PCI_VENDOR_ID_JMICRON,
776 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
777 .subvendor = PCI_ANY_ID,
778 .subdevice = PCI_ANY_ID,
779 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 780 },
781
a7a6186c
NP		 782 {
783 .vendor = PCI_VENDOR_ID_SYSKONNECT,
784 .device = 0x8000,
785 .subvendor = PCI_ANY_ID,
786 .subdevice = PCI_ANY_ID,
787 .driver_data = (kernel_ulong_t)&sdhci_syskt,
788 },
789
557b0697
HW		 790 {
791 .vendor = PCI_VENDOR_ID_VIA,
792 .device = 0x95d0,
793 .subvendor = PCI_ANY_ID,
794 .subdevice = PCI_ANY_ID,
795 .driver_data = (kernel_ulong_t)&sdhci_via,
796 },
797
29229052
XS		 798 {
799 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 800 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
801 .subvendor = PCI_ANY_ID,
802 .subdevice = PCI_ANY_ID,
803 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
804 },
805
806 {
807 .vendor = PCI_VENDOR_ID_INTEL,
808 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
809 .subvendor = PCI_ANY_ID,
810 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 811 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
812 },
813
814 {
815 .vendor = PCI_VENDOR_ID_INTEL,
816 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
817 .subvendor = PCI_ANY_ID,
818 .subdevice = PCI_ANY_ID,
819 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 820 },
821
822 {
823 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 824 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
825 .subvendor = PCI_ANY_ID,
826 .subdevice = PCI_ANY_ID,
827 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
828 },
829
830 {
831 .vendor = PCI_VENDOR_ID_INTEL,
832 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
833 .subvendor = PCI_ANY_ID,
834 .subdevice = PCI_ANY_ID,
0d013bcf 835 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 836 },
837
838 {
839 .vendor = PCI_VENDOR_ID_INTEL,
840 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
841 .subvendor = PCI_ANY_ID,
842 .subdevice = PCI_ANY_ID,
0d013bcf 843 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 844 },
845
846 {
847 .vendor = PCI_VENDOR_ID_INTEL,
848 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
849 .subvendor = PCI_ANY_ID,
850 .subdevice = PCI_ANY_ID,
0d013bcf 851 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 852 },
853
854 {
855 .vendor = PCI_VENDOR_ID_INTEL,
856 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
857 .subvendor = PCI_ANY_ID,
858 .subdevice = PCI_ANY_ID,
0d013bcf 859 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 860 },
861
26daa1ed
JL		 862 {
863 .vendor = PCI_VENDOR_ID_O2,
864 .device = PCI_DEVICE_ID_O2_8120,
865 .subvendor = PCI_ANY_ID,
866 .subdevice = PCI_ANY_ID,
867 .driver_data = (kernel_ulong_t)&sdhci_o2,
868 },
869
870 {
871 .vendor = PCI_VENDOR_ID_O2,
872 .device = PCI_DEVICE_ID_O2_8220,
873 .subvendor = PCI_ANY_ID,
874 .subdevice = PCI_ANY_ID,
875 .driver_data = (kernel_ulong_t)&sdhci_o2,
876 },
877
878 {
879 .vendor = PCI_VENDOR_ID_O2,
880 .device = PCI_DEVICE_ID_O2_8221,
881 .subvendor = PCI_ANY_ID,
882 .subdevice = PCI_ANY_ID,
883 .driver_data = (kernel_ulong_t)&sdhci_o2,
884 },
885
886 {
887 .vendor = PCI_VENDOR_ID_O2,
888 .device = PCI_DEVICE_ID_O2_8320,
889 .subvendor = PCI_ANY_ID,
890 .subdevice = PCI_ANY_ID,
891 .driver_data = (kernel_ulong_t)&sdhci_o2,
892 },
893
894 {
895 .vendor = PCI_VENDOR_ID_O2,
896 .device = PCI_DEVICE_ID_O2_8321,
897 .subvendor = PCI_ANY_ID,
898 .subdevice = PCI_ANY_ID,
899 .driver_data = (kernel_ulong_t)&sdhci_o2,
900 },
901
b8c86fc5
PO		 902 { /* Generic SD host controller */
903 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
904 },
905
906 { /* end: all zeroes */ },
907};
908
909MODULE_DEVICE_TABLE(pci, pci_ids);
910
b8c86fc5
PO		 911/*****************************************************************************\
912 * *
913 * SDHCI core callbacks *
914 * *
915\*****************************************************************************/
916
917static int sdhci_pci_enable_dma(struct sdhci_host *host)
918{
919 struct sdhci_pci_slot *slot;
920 struct pci_dev *pdev;
921 int ret;
922
923 slot = sdhci_priv(host);
924 pdev = slot->chip->pdev;
925
926 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
927 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 928 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 929 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
930 "doesn't fully claim to support it.\n");
931 }
932
284901a9 933 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 934 if (ret)
935 return ret;
936
937 pci_set_master(pdev);
938
939 return 0;
940}
941
68077b02
ML		 942static int sdhci_pci_8bit_width(struct sdhci_host *host, int width)
943{
944 u8 ctrl;
945
946 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
947
948 switch (width) {
949 case MMC_BUS_WIDTH_8:
950 ctrl |= SDHCI_CTRL_8BITBUS;
951 ctrl &= ~SDHCI_CTRL_4BITBUS;
952 break;
953 case MMC_BUS_WIDTH_4:
954 ctrl |= SDHCI_CTRL_4BITBUS;
955 ctrl &= ~SDHCI_CTRL_8BITBUS;
956 break;
957 default:
958 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
959 break;
960 }
961
962 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
963
964 return 0;
965}
966
0f201655
AH		 967static void sdhci_pci_hw_reset(struct sdhci_host *host)
968{
969 struct sdhci_pci_slot *slot = sdhci_priv(host);
970 int rst_n_gpio = slot->rst_n_gpio;
971
972 if (!gpio_is_valid(rst_n_gpio))
973 return;
974 gpio_set_value_cansleep(rst_n_gpio, 0);
975 /* For eMMC, minimum is 1us but give it 10us for good measure */
976 udelay(10);
977 gpio_set_value_cansleep(rst_n_gpio, 1);
978 /* For eMMC, minimum is 200us but give it 300us for good measure */
979 usleep_range(300, 1000);
980}
981
b8c86fc5
PO		 982static struct sdhci_ops sdhci_pci_ops = {
983 .enable_dma = sdhci_pci_enable_dma,
68077b02 984 .platform_8bit_width = sdhci_pci_8bit_width,
0f201655 985 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 986};
987
988/*****************************************************************************\
989 * *
990 * Suspend/resume *
991 * *
992\*****************************************************************************/
993
994#ifdef CONFIG_PM
995
b177bc91 996static int sdhci_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b8c86fc5
PO		 997{
998 struct sdhci_pci_chip *chip;
999 struct sdhci_pci_slot *slot;
5f619704 1000 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 1001 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 1002 int i, ret;
1003
1004 chip = pci_get_drvdata(pdev);
1005 if (!chip)
1006 return 0;
1007
b177bc91 1008 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1009 slot = chip->slots[i];
1010 if (!slot)
1011 continue;
1012
1013 ret = sdhci_suspend_host(slot->host, state);
1014
1015 if (ret) {
b177bc91 1016 for (i--; i >= 0; i--)
b8c86fc5
PO		 1017 sdhci_resume_host(chip->slots[i]->host);
1018 return ret;
1019 }
2f4cbb3d 1020
5f619704
DD		 1021 slot_pm_flags = slot->host->mmc->pm_flags;
1022 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1023 sdhci_enable_irq_wakeups(slot->host);
1024
1025 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1026 }
1027
4489428a
PO		 1028 if (chip->fixes && chip->fixes->suspend) {
1029 ret = chip->fixes->suspend(chip, state);
1030 if (ret) {
b177bc91 1031 for (i = chip->num_slots - 1; i >= 0; i--)
4489428a
PO		 1032 sdhci_resume_host(chip->slots[i]->host);
1033 return ret;
1034 }
1035 }
1036
b8c86fc5 1037 pci_save_state(pdev);
2f4cbb3d 1038 if (pm_flags & MMC_PM_KEEP_POWER) {
5f619704
DD		 1039 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
1040 pci_pme_active(pdev, true);
2f4cbb3d 1041 pci_enable_wake(pdev, PCI_D3hot, 1);
5f619704 1042 }
2f4cbb3d
NP		 1043 pci_set_power_state(pdev, PCI_D3hot);
1044 } else {
1045 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1046 pci_disable_device(pdev);
1047 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1048 }
b8c86fc5
PO		 1049
1050 return 0;
1051}
1052
b177bc91 1053static int sdhci_pci_resume(struct pci_dev *pdev)
b8c86fc5
PO		 1054{
1055 struct sdhci_pci_chip *chip;
1056 struct sdhci_pci_slot *slot;
1057 int i, ret;
1058
1059 chip = pci_get_drvdata(pdev);
1060 if (!chip)
1061 return 0;
1062
1063 pci_set_power_state(pdev, PCI_D0);
1064 pci_restore_state(pdev);
1065 ret = pci_enable_device(pdev);
1066 if (ret)
1067 return ret;
1068
45211e21
PO		 1069 if (chip->fixes && chip->fixes->resume) {
1070 ret = chip->fixes->resume(chip);
1071 if (ret)
1072 return ret;
1073 }
1074
b177bc91 1075 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1076 slot = chip->slots[i];
1077 if (!slot)
1078 continue;
1079
1080 ret = sdhci_resume_host(slot->host);
1081 if (ret)
1082 return ret;
1083 }
1084
1085 return 0;
1086}
1087
1088#else /* CONFIG_PM */
1089
1090#define sdhci_pci_suspend NULL
1091#define sdhci_pci_resume NULL
1092
1093#endif /* CONFIG_PM */
1094
66fd8ad5
AH		 1095#ifdef CONFIG_PM_RUNTIME
1096
1097static int sdhci_pci_runtime_suspend(struct device *dev)
1098{
1099 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1100 struct sdhci_pci_chip *chip;
1101 struct sdhci_pci_slot *slot;
1102 pm_message_t state = { .event = PM_EVENT_SUSPEND };
1103 int i, ret;
1104
1105 chip = pci_get_drvdata(pdev);
1106 if (!chip)
1107 return 0;
1108
1109 for (i = 0; i < chip->num_slots; i++) {
1110 slot = chip->slots[i];
1111 if (!slot)
1112 continue;
1113
1114 ret = sdhci_runtime_suspend_host(slot->host);
1115
1116 if (ret) {
1117 for (i--; i >= 0; i--)
1118 sdhci_runtime_resume_host(chip->slots[i]->host);
1119 return ret;
1120 }
1121 }
1122
1123 if (chip->fixes && chip->fixes->suspend) {
1124 ret = chip->fixes->suspend(chip, state);
1125 if (ret) {
1126 for (i = chip->num_slots - 1; i >= 0; i--)
1127 sdhci_runtime_resume_host(chip->slots[i]->host);
1128 return ret;
1129 }
1130 }
1131
1132 return 0;
1133}
1134
1135static int sdhci_pci_runtime_resume(struct device *dev)
1136{
1137 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1138 struct sdhci_pci_chip *chip;
1139 struct sdhci_pci_slot *slot;
1140 int i, ret;
1141
1142 chip = pci_get_drvdata(pdev);
1143 if (!chip)
1144 return 0;
1145
1146 if (chip->fixes && chip->fixes->resume) {
1147 ret = chip->fixes->resume(chip);
1148 if (ret)
1149 return ret;
1150 }
1151
1152 for (i = 0; i < chip->num_slots; i++) {
1153 slot = chip->slots[i];
1154 if (!slot)
1155 continue;
1156
1157 ret = sdhci_runtime_resume_host(slot->host);
1158 if (ret)
1159 return ret;
1160 }
1161
1162 return 0;
1163}
1164
1165static int sdhci_pci_runtime_idle(struct device *dev)
1166{
1167 return 0;
1168}
1169
1170#else
1171
1172#define sdhci_pci_runtime_suspend NULL
1173#define sdhci_pci_runtime_resume NULL
1174#define sdhci_pci_runtime_idle NULL
1175
1176#endif
1177
1178static const struct dev_pm_ops sdhci_pci_pm_ops = {
1179 .runtime_suspend = sdhci_pci_runtime_suspend,
1180 .runtime_resume = sdhci_pci_runtime_resume,
1181 .runtime_idle = sdhci_pci_runtime_idle,
1182};
1183
b8c86fc5
PO		 1184/*****************************************************************************\
1185 * *
1186 * Device probing/removal *
1187 * *
1188\*****************************************************************************/
1189
1190static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
1191 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
1192{
1193 struct sdhci_pci_slot *slot;
1194 struct sdhci_host *host;
b8c86fc5
PO		 1195 int ret;
1196
1197 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1198 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1199 return ERR_PTR(-ENODEV);
1200 }
1201
1202 if (pci_resource_len(pdev, bar) != 0x100) {
1203 dev_err(&pdev->dev, "Invalid iomem size. You may "
1204 "experience problems.\n");
1205 }
1206
1207 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1208 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1209 return ERR_PTR(-ENODEV);
1210 }
1211
1212 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1213 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1214 return ERR_PTR(-ENODEV);
1215 }
1216
1217 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1218 if (IS_ERR(host)) {
c60a32cd 1219 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1220 return ERR_CAST(host);
b8c86fc5
PO		 1221 }
1222
1223 slot = sdhci_priv(host);
1224
1225 slot->chip = chip;
1226 slot->host = host;
1227 slot->pci_bar = bar;
0f201655 1228 slot->rst_n_gpio = -EINVAL;
b8c86fc5
PO		 1229
1230 host->hw_name = "PCI";
1231 host->ops = &sdhci_pci_ops;
1232 host->quirks = chip->quirks;
1233
1234 host->irq = pdev->irq;
1235
1236 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1237 if (ret) {
1238 dev_err(&pdev->dev, "cannot request region\n");
c60a32cd 1239 goto free;
b8c86fc5
PO		 1240 }
1241
092f82ed 1242 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 1243 if (!host->ioaddr) {
1244 dev_err(&pdev->dev, "failed to remap registers\n");
9fdcdbb0 1245 ret = -ENOMEM;
b8c86fc5
PO		 1246 goto release;
1247 }
1248
4489428a
PO		 1249 if (chip->fixes && chip->fixes->probe_slot) {
1250 ret = chip->fixes->probe_slot(slot);
1251 if (ret)
1252 goto unmap;
1253 }
1254
2f4cbb3d
NP		 1255 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1256
b8c86fc5
PO		 1257 ret = sdhci_add_host(host);
1258 if (ret)
4489428a 1259 goto remove;
b8c86fc5
PO		 1260
1261 return slot;
1262
4489428a
PO		 1263remove:
1264 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1265 chip->fixes->remove_slot(slot, 0);
4489428a 1266
b8c86fc5
PO		 1267unmap:
1268 iounmap(host->ioaddr);
1269
1270release:
1271 pci_release_region(pdev, bar);
c60a32cd
DC		 1272
1273free:
b8c86fc5
PO		 1274 sdhci_free_host(host);
1275
1276 return ERR_PTR(ret);
1277}
1278
1279static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1280{
1e72859e
PO		 1281 int dead;
1282 u32 scratch;
1283
1284 dead = 0;
1285 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1286 if (scratch == (u32)-1)
1287 dead = 1;
1288
1289 sdhci_remove_host(slot->host, dead);
4489428a
PO		 1290
1291 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1292 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1293
b8c86fc5 1294 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 1295
b8c86fc5
PO		 1296 sdhci_free_host(slot->host);
1297}
1298
66fd8ad5
AH		 1299static void __devinit sdhci_pci_runtime_pm_allow(struct device *dev)
1300{
1301 pm_runtime_put_noidle(dev);
1302 pm_runtime_allow(dev);
1303 pm_runtime_set_autosuspend_delay(dev, 50);
1304 pm_runtime_use_autosuspend(dev);
1305 pm_suspend_ignore_children(dev, 1);
1306}
1307
1308static void __devexit sdhci_pci_runtime_pm_forbid(struct device *dev)
1309{
1310 pm_runtime_forbid(dev);
1311 pm_runtime_get_noresume(dev);
1312}
1313
b8c86fc5
PO		 1314static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
1315 const struct pci_device_id *ent)
1316{
1317 struct sdhci_pci_chip *chip;
1318 struct sdhci_pci_slot *slot;
1319
cf5e23e1 1320 u8 slots, first_bar;
b8c86fc5
PO		 1321 int ret, i;
1322
1323 BUG_ON(pdev == NULL);
1324 BUG_ON(ent == NULL);
1325
b8c86fc5 1326 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1327 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1328
1329 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1330 if (ret)
1331 return ret;
1332
1333 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1334 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1335 if (slots == 0)
1336 return -ENODEV;
1337
1338 BUG_ON(slots > MAX_SLOTS);
1339
1340 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1341 if (ret)
1342 return ret;
1343
1344 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1345
1346 if (first_bar > 5) {
1347 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1348 return -ENODEV;
1349 }
1350
1351 ret = pci_enable_device(pdev);
1352 if (ret)
1353 return ret;
1354
1355 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1356 if (!chip) {
1357 ret = -ENOMEM;
1358 goto err;
1359 }
1360
1361 chip->pdev = pdev;
b177bc91 1362 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1363 if (chip->fixes) {
22606405 1364 chip->quirks = chip->fixes->quirks;
c43fd774
AH		 1365 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1366 }
b8c86fc5
PO		 1367 chip->num_slots = slots;
1368
1369 pci_set_drvdata(pdev, chip);
1370
22606405
PO		 1371 if (chip->fixes && chip->fixes->probe) {
1372 ret = chip->fixes->probe(chip);
1373 if (ret)
1374 goto free;
1375 }
1376
225d85fe
AC		 1377 slots = chip->num_slots; /* Quirk may have changed this */
1378
b177bc91 1379 for (i = 0; i < slots; i++) {
b8c86fc5
PO		 1380 slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
1381 if (IS_ERR(slot)) {
b177bc91 1382 for (i--; i >= 0; i--)
b8c86fc5
PO		 1383 sdhci_pci_remove_slot(chip->slots[i]);
1384 ret = PTR_ERR(slot);
1385 goto free;
1386 }
1387
1388 chip->slots[i] = slot;
1389 }
1390
c43fd774
AH		 1391 if (chip->allow_runtime_pm)
1392 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1393
b8c86fc5
PO		 1394 return 0;
1395
1396free:
1397 pci_set_drvdata(pdev, NULL);
1398 kfree(chip);
1399
1400err:
1401 pci_disable_device(pdev);
1402 return ret;
1403}
1404
1405static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
1406{
1407 int i;
1408 struct sdhci_pci_chip *chip;
1409
1410 chip = pci_get_drvdata(pdev);
1411
1412 if (chip) {
c43fd774
AH		 1413 if (chip->allow_runtime_pm)
1414 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1415
b177bc91 1416 for (i = 0; i < chip->num_slots; i++)
b8c86fc5
PO		 1417 sdhci_pci_remove_slot(chip->slots[i]);
1418
1419 pci_set_drvdata(pdev, NULL);
1420 kfree(chip);
1421 }
1422
1423 pci_disable_device(pdev);
1424}
1425
1426static struct pci_driver sdhci_driver = {
b177bc91 1427 .name = "sdhci-pci",
b8c86fc5 1428 .id_table = pci_ids,
b177bc91 1429 .probe = sdhci_pci_probe,
b8c86fc5
PO		 1430 .remove = __devexit_p(sdhci_pci_remove),
1431 .suspend = sdhci_pci_suspend,
1432 .resume = sdhci_pci_resume,
66fd8ad5
AH		 1433 .driver = {
1434 .pm = &sdhci_pci_pm_ops
1435 },
b8c86fc5
PO		 1436};
1437
1438/*****************************************************************************\
1439 * *
1440 * Driver init/exit *
1441 * *
1442\*****************************************************************************/
1443
1444static int __init sdhci_drv_init(void)
1445{
1446 return pci_register_driver(&sdhci_driver);
1447}
1448
1449static void __exit sdhci_drv_exit(void)
1450{
1451 pci_unregister_driver(&sdhci_driver);
1452}
1453
1454module_init(sdhci_drv_init);
1455module_exit(sdhci_drv_exit);
1456
32710e8f 1457MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1458MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1459MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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