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0d1bb41a BD |
1 | /* linux/drivers/mmc/host/sdhci-s3c.c |
2 | * | |
3 | * Copyright 2008 Openmoko Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * SDHCI (HSMMC) support for Samsung SoC | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/platform_device.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
0d1bb41a BD |
19 | #include <linux/clk.h> |
20 | #include <linux/io.h> | |
21 | ||
22 | #include <linux/mmc/host.h> | |
23 | ||
24 | #include <plat/sdhci.h> | |
25 | #include <plat/regs-sdhci.h> | |
26 | ||
27 | #include "sdhci.h" | |
28 | ||
29 | #define MAX_BUS_CLK (4) | |
30 | ||
31 | /** | |
32 | * struct sdhci_s3c - S3C SDHCI instance | |
33 | * @host: The SDHCI host created | |
34 | * @pdev: The platform device we where created from. | |
35 | * @ioarea: The resource created when we claimed the IO area. | |
36 | * @pdata: The platform data for this controller. | |
37 | * @cur_clk: The index of the current bus clock. | |
38 | * @clk_io: The clock for the internal bus interface. | |
39 | * @clk_bus: The clocks that are available for the SD/MMC bus clock. | |
40 | */ | |
41 | struct sdhci_s3c { | |
42 | struct sdhci_host *host; | |
43 | struct platform_device *pdev; | |
44 | struct resource *ioarea; | |
45 | struct s3c_sdhci_platdata *pdata; | |
46 | unsigned int cur_clk; | |
47 | ||
48 | struct clk *clk_io; | |
49 | struct clk *clk_bus[MAX_BUS_CLK]; | |
50 | }; | |
51 | ||
52 | static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) | |
53 | { | |
54 | return sdhci_priv(host); | |
55 | } | |
56 | ||
57 | /** | |
58 | * get_curclk - convert ctrl2 register to clock source number | |
59 | * @ctrl2: Control2 register value. | |
60 | */ | |
61 | static u32 get_curclk(u32 ctrl2) | |
62 | { | |
63 | ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
64 | ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; | |
65 | ||
66 | return ctrl2; | |
67 | } | |
68 | ||
69 | static void sdhci_s3c_check_sclk(struct sdhci_host *host) | |
70 | { | |
71 | struct sdhci_s3c *ourhost = to_s3c(host); | |
72 | u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
73 | ||
74 | if (get_curclk(tmp) != ourhost->cur_clk) { | |
75 | dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n"); | |
76 | ||
77 | tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
78 | tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; | |
79 | writel(tmp, host->ioaddr + 0x80); | |
80 | } | |
81 | } | |
82 | ||
83 | /** | |
84 | * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. | |
85 | * @host: The SDHCI host instance. | |
86 | * | |
87 | * Callback to return the maximum clock rate acheivable by the controller. | |
88 | */ | |
89 | static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) | |
90 | { | |
91 | struct sdhci_s3c *ourhost = to_s3c(host); | |
92 | struct clk *busclk; | |
93 | unsigned int rate, max; | |
94 | int clk; | |
95 | ||
96 | /* note, a reset will reset the clock source */ | |
97 | ||
98 | sdhci_s3c_check_sclk(host); | |
99 | ||
100 | for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) { | |
101 | busclk = ourhost->clk_bus[clk]; | |
102 | if (!busclk) | |
103 | continue; | |
104 | ||
105 | rate = clk_get_rate(busclk); | |
106 | if (rate > max) | |
107 | max = rate; | |
108 | } | |
109 | ||
110 | return max; | |
111 | } | |
112 | ||
0d1bb41a BD |
113 | /** |
114 | * sdhci_s3c_consider_clock - consider one the bus clocks for current setting | |
115 | * @ourhost: Our SDHCI instance. | |
116 | * @src: The source clock index. | |
117 | * @wanted: The clock frequency wanted. | |
118 | */ | |
119 | static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, | |
120 | unsigned int src, | |
121 | unsigned int wanted) | |
122 | { | |
123 | unsigned long rate; | |
124 | struct clk *clksrc = ourhost->clk_bus[src]; | |
125 | int div; | |
126 | ||
127 | if (!clksrc) | |
128 | return UINT_MAX; | |
129 | ||
130 | rate = clk_get_rate(clksrc); | |
131 | ||
132 | for (div = 1; div < 256; div *= 2) { | |
133 | if ((rate / div) <= wanted) | |
134 | break; | |
135 | } | |
136 | ||
137 | dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", | |
138 | src, rate, wanted, rate / div); | |
139 | ||
140 | return (wanted - (rate / div)); | |
141 | } | |
142 | ||
143 | /** | |
144 | * sdhci_s3c_set_clock - callback on clock change | |
145 | * @host: The SDHCI host being changed | |
146 | * @clock: The clock rate being requested. | |
147 | * | |
148 | * When the card's clock is going to be changed, look at the new frequency | |
149 | * and find the best clock source to go with it. | |
150 | */ | |
151 | static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) | |
152 | { | |
153 | struct sdhci_s3c *ourhost = to_s3c(host); | |
154 | unsigned int best = UINT_MAX; | |
155 | unsigned int delta; | |
156 | int best_src = 0; | |
157 | int src; | |
158 | u32 ctrl; | |
159 | ||
160 | /* don't bother if the clock is going off. */ | |
161 | if (clock == 0) | |
162 | return; | |
163 | ||
164 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
165 | delta = sdhci_s3c_consider_clock(ourhost, src, clock); | |
166 | if (delta < best) { | |
167 | best = delta; | |
168 | best_src = src; | |
169 | } | |
170 | } | |
171 | ||
172 | dev_dbg(&ourhost->pdev->dev, | |
173 | "selected source %d, clock %d, delta %d\n", | |
174 | best_src, clock, best); | |
175 | ||
176 | /* select the new clock source */ | |
177 | ||
178 | if (ourhost->cur_clk != best_src) { | |
179 | struct clk *clk = ourhost->clk_bus[best_src]; | |
180 | ||
181 | /* turn clock off to card before changing clock source */ | |
182 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
183 | ||
184 | ourhost->cur_clk = best_src; | |
185 | host->max_clk = clk_get_rate(clk); | |
0d1bb41a BD |
186 | |
187 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
188 | ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
189 | ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; | |
190 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
191 | } | |
192 | ||
193 | /* reconfigure the hardware for new clock rate */ | |
194 | ||
195 | { | |
196 | struct mmc_ios ios; | |
197 | ||
198 | ios.clock = clock; | |
199 | ||
200 | if (ourhost->pdata->cfg_card) | |
201 | (ourhost->pdata->cfg_card)(ourhost->pdev, host->ioaddr, | |
202 | &ios, NULL); | |
203 | } | |
204 | } | |
205 | ||
206 | static struct sdhci_ops sdhci_s3c_ops = { | |
207 | .get_max_clock = sdhci_s3c_get_max_clk, | |
0d1bb41a BD |
208 | .set_clock = sdhci_s3c_set_clock, |
209 | }; | |
210 | ||
211 | static int __devinit sdhci_s3c_probe(struct platform_device *pdev) | |
212 | { | |
213 | struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data; | |
214 | struct device *dev = &pdev->dev; | |
215 | struct sdhci_host *host; | |
216 | struct sdhci_s3c *sc; | |
217 | struct resource *res; | |
218 | int ret, irq, ptr, clks; | |
219 | ||
220 | if (!pdata) { | |
221 | dev_err(dev, "no device data specified\n"); | |
222 | return -ENOENT; | |
223 | } | |
224 | ||
225 | irq = platform_get_irq(pdev, 0); | |
226 | if (irq < 0) { | |
227 | dev_err(dev, "no irq specified\n"); | |
228 | return irq; | |
229 | } | |
230 | ||
231 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
232 | if (!res) { | |
233 | dev_err(dev, "no memory specified\n"); | |
234 | return -ENOENT; | |
235 | } | |
236 | ||
237 | host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); | |
238 | if (IS_ERR(host)) { | |
239 | dev_err(dev, "sdhci_alloc_host() failed\n"); | |
240 | return PTR_ERR(host); | |
241 | } | |
242 | ||
243 | sc = sdhci_priv(host); | |
244 | ||
245 | sc->host = host; | |
246 | sc->pdev = pdev; | |
247 | sc->pdata = pdata; | |
248 | ||
249 | platform_set_drvdata(pdev, host); | |
250 | ||
251 | sc->clk_io = clk_get(dev, "hsmmc"); | |
252 | if (IS_ERR(sc->clk_io)) { | |
253 | dev_err(dev, "failed to get io clock\n"); | |
254 | ret = PTR_ERR(sc->clk_io); | |
255 | goto err_io_clk; | |
256 | } | |
257 | ||
258 | /* enable the local io clock and keep it running for the moment. */ | |
259 | clk_enable(sc->clk_io); | |
260 | ||
261 | for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { | |
262 | struct clk *clk; | |
263 | char *name = pdata->clocks[ptr]; | |
264 | ||
265 | if (name == NULL) | |
266 | continue; | |
267 | ||
268 | clk = clk_get(dev, name); | |
269 | if (IS_ERR(clk)) { | |
270 | dev_err(dev, "failed to get clock %s\n", name); | |
271 | continue; | |
272 | } | |
273 | ||
274 | clks++; | |
275 | sc->clk_bus[ptr] = clk; | |
276 | clk_enable(clk); | |
277 | ||
278 | dev_info(dev, "clock source %d: %s (%ld Hz)\n", | |
279 | ptr, name, clk_get_rate(clk)); | |
280 | } | |
281 | ||
282 | if (clks == 0) { | |
283 | dev_err(dev, "failed to find any bus clocks\n"); | |
284 | ret = -ENOENT; | |
285 | goto err_no_busclks; | |
286 | } | |
287 | ||
288 | sc->ioarea = request_mem_region(res->start, resource_size(res), | |
289 | mmc_hostname(host->mmc)); | |
290 | if (!sc->ioarea) { | |
291 | dev_err(dev, "failed to reserve register area\n"); | |
292 | ret = -ENXIO; | |
293 | goto err_req_regs; | |
294 | } | |
295 | ||
296 | host->ioaddr = ioremap_nocache(res->start, resource_size(res)); | |
297 | if (!host->ioaddr) { | |
298 | dev_err(dev, "failed to map registers\n"); | |
299 | ret = -ENXIO; | |
300 | goto err_req_regs; | |
301 | } | |
302 | ||
303 | /* Ensure we have minimal gpio selected CMD/CLK/Detect */ | |
304 | if (pdata->cfg_gpio) | |
305 | pdata->cfg_gpio(pdev, pdata->max_width); | |
306 | ||
307 | host->hw_name = "samsung-hsmmc"; | |
308 | host->ops = &sdhci_s3c_ops; | |
309 | host->quirks = 0; | |
310 | host->irq = irq; | |
311 | ||
312 | /* Setup quirks for the controller */ | |
b2e75eff | 313 | host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; |
0d1bb41a BD |
314 | |
315 | #ifndef CONFIG_MMC_SDHCI_S3C_DMA | |
316 | ||
317 | /* we currently see overruns on errors, so disable the SDMA | |
318 | * support as well. */ | |
319 | host->quirks |= SDHCI_QUIRK_BROKEN_DMA; | |
320 | ||
321 | #endif /* CONFIG_MMC_SDHCI_S3C_DMA */ | |
322 | ||
323 | /* It seems we do not get an DATA transfer complete on non-busy | |
324 | * transfers, not sure if this is a problem with this specific | |
325 | * SDHCI block, or a missing configuration that needs to be set. */ | |
326 | host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; | |
327 | ||
328 | host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | | |
329 | SDHCI_QUIRK_32BIT_DMA_SIZE); | |
330 | ||
3fe42e07 HL |
331 | /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ |
332 | host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; | |
333 | ||
0d1bb41a BD |
334 | ret = sdhci_add_host(host); |
335 | if (ret) { | |
336 | dev_err(dev, "sdhci_add_host() failed\n"); | |
337 | goto err_add_host; | |
338 | } | |
339 | ||
340 | return 0; | |
341 | ||
342 | err_add_host: | |
343 | release_resource(sc->ioarea); | |
344 | kfree(sc->ioarea); | |
345 | ||
346 | err_req_regs: | |
347 | for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) { | |
348 | clk_disable(sc->clk_bus[ptr]); | |
349 | clk_put(sc->clk_bus[ptr]); | |
350 | } | |
351 | ||
352 | err_no_busclks: | |
353 | clk_disable(sc->clk_io); | |
354 | clk_put(sc->clk_io); | |
355 | ||
356 | err_io_clk: | |
357 | sdhci_free_host(host); | |
358 | ||
359 | return ret; | |
360 | } | |
361 | ||
362 | static int __devexit sdhci_s3c_remove(struct platform_device *pdev) | |
363 | { | |
9d51a6b2 MS |
364 | struct sdhci_host *host = platform_get_drvdata(pdev); |
365 | struct sdhci_s3c *sc = sdhci_priv(host); | |
366 | int ptr; | |
367 | ||
368 | sdhci_remove_host(host, 1); | |
369 | ||
370 | for (ptr = 0; ptr < 3; ptr++) { | |
371 | clk_disable(sc->clk_bus[ptr]); | |
372 | clk_put(sc->clk_bus[ptr]); | |
373 | } | |
374 | clk_disable(sc->clk_io); | |
375 | clk_put(sc->clk_io); | |
376 | ||
377 | iounmap(host->ioaddr); | |
378 | release_resource(sc->ioarea); | |
379 | kfree(sc->ioarea); | |
380 | ||
381 | sdhci_free_host(host); | |
382 | platform_set_drvdata(pdev, NULL); | |
383 | ||
0d1bb41a BD |
384 | return 0; |
385 | } | |
386 | ||
387 | #ifdef CONFIG_PM | |
388 | ||
389 | static int sdhci_s3c_suspend(struct platform_device *dev, pm_message_t pm) | |
390 | { | |
391 | struct sdhci_host *host = platform_get_drvdata(dev); | |
392 | ||
393 | sdhci_suspend_host(host, pm); | |
394 | return 0; | |
395 | } | |
396 | ||
397 | static int sdhci_s3c_resume(struct platform_device *dev) | |
398 | { | |
399 | struct sdhci_host *host = platform_get_drvdata(dev); | |
400 | ||
401 | sdhci_resume_host(host); | |
402 | return 0; | |
403 | } | |
404 | ||
405 | #else | |
406 | #define sdhci_s3c_suspend NULL | |
407 | #define sdhci_s3c_resume NULL | |
408 | #endif | |
409 | ||
410 | static struct platform_driver sdhci_s3c_driver = { | |
411 | .probe = sdhci_s3c_probe, | |
412 | .remove = __devexit_p(sdhci_s3c_remove), | |
413 | .suspend = sdhci_s3c_suspend, | |
414 | .resume = sdhci_s3c_resume, | |
415 | .driver = { | |
416 | .owner = THIS_MODULE, | |
417 | .name = "s3c-sdhci", | |
418 | }, | |
419 | }; | |
420 | ||
421 | static int __init sdhci_s3c_init(void) | |
422 | { | |
423 | return platform_driver_register(&sdhci_s3c_driver); | |
424 | } | |
425 | ||
426 | static void __exit sdhci_s3c_exit(void) | |
427 | { | |
428 | platform_driver_unregister(&sdhci_s3c_driver); | |
429 | } | |
430 | ||
431 | module_init(sdhci_s3c_init); | |
432 | module_exit(sdhci_s3c_exit); | |
433 | ||
434 | MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); | |
435 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
436 | MODULE_LICENSE("GPL v2"); | |
437 | MODULE_ALIAS("platform:s3c-sdhci"); |