[deliverable/linux.git] / drivers / mmc / host / sdhci-st.c

/*
 * Support for SDHCI on STMicroelectronics SoCs
 *
 * Copyright (C) 2014 STMicroelectronics Ltd
 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 * Contributors: Peter Griffin <peter.griffin@linaro.org>
 *
 * Based on sdhci-cns3xxx.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/mmc/host.h>
#include <linux/reset.h>
#include "sdhci-pltfm.h"

struct st_mmc_platform_data {
	struct  reset_control *rstc;
	void __iomem *top_ioaddr;
};

/* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */

#define ST_MMC_CCONFIG_REG_1		0x400
#define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT	BIT(24)
#define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ	BIT(12)
#define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT	BIT(8)
#define ST_MMC_CCONFIG_ASYNC_WAKEUP	BIT(0)
#define ST_MMC_CCONFIG_1_DEFAULT	\
				((ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT) | \
				 (ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ) | \
				 (ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT))

#define ST_MMC_CCONFIG_REG_2		0x404
#define ST_MMC_CCONFIG_HIGH_SPEED	BIT(28)
#define ST_MMC_CCONFIG_ADMA2		BIT(24)
#define ST_MMC_CCONFIG_8BIT		BIT(20)
#define ST_MMC_CCONFIG_MAX_BLK_LEN	16
#define  MAX_BLK_LEN_1024		1
#define  MAX_BLK_LEN_2048		2
#define BASE_CLK_FREQ_200		0xc8
#define BASE_CLK_FREQ_100		0x64
#define BASE_CLK_FREQ_50		0x32
#define ST_MMC_CCONFIG_2_DEFAULT \
	(ST_MMC_CCONFIG_HIGH_SPEED | ST_MMC_CCONFIG_ADMA2 | \
	 ST_MMC_CCONFIG_8BIT | \
	 (MAX_BLK_LEN_1024 << ST_MMC_CCONFIG_MAX_BLK_LEN))

#define ST_MMC_CCONFIG_REG_3			0x408
#define ST_MMC_CCONFIG_EMMC_SLOT_TYPE		BIT(28)
#define ST_MMC_CCONFIG_64BIT			BIT(24)
#define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	BIT(20)
#define ST_MMC_CCONFIG_1P8_VOLT			BIT(16)
#define ST_MMC_CCONFIG_3P0_VOLT			BIT(12)
#define ST_MMC_CCONFIG_3P3_VOLT			BIT(8)
#define ST_MMC_CCONFIG_SUSP_RES_SUPPORT		BIT(4)
#define ST_MMC_CCONFIG_SDMA			BIT(0)
#define ST_MMC_CCONFIG_3_DEFAULT	\
			 (ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	| \
			  ST_MMC_CCONFIG_3P3_VOLT		| \
			  ST_MMC_CCONFIG_SUSP_RES_SUPPORT	| \
			  ST_MMC_CCONFIG_SDMA)

#define ST_MMC_CCONFIG_REG_4	0x40c
#define ST_MMC_CCONFIG_D_DRIVER	BIT(20)
#define ST_MMC_CCONFIG_C_DRIVER	BIT(16)
#define ST_MMC_CCONFIG_A_DRIVER	BIT(12)
#define ST_MMC_CCONFIG_DDR50	BIT(8)
#define ST_MMC_CCONFIG_SDR104	BIT(4)
#define ST_MMC_CCONFIG_SDR50	BIT(0)
#define ST_MMC_CCONFIG_4_DEFAULT	0

#define ST_MMC_CCONFIG_REG_5		0x410
#define ST_MMC_CCONFIG_TUNING_FOR_SDR50	BIT(8)
#define RETUNING_TIMER_CNT_MAX		0xf
#define ST_MMC_CCONFIG_5_DEFAULT	0

/* I/O configuration for Arasan IP */
#define ST_MMC_GP_OUTPUT	0x450
#define ST_MMC_GP_OUTPUT_CD	BIT(12)

#define ST_MMC_STATUS_R		0x460

#define ST_TOP_MMC_DLY_FIX_OFF(x)	(x - 0x8)

/* TOP config registers to manage static and dynamic delay */
#define ST_TOP_MMC_TX_CLK_DLY			ST_TOP_MMC_DLY_FIX_OFF(0x8)
#define ST_TOP_MMC_RX_CLK_DLY			ST_TOP_MMC_DLY_FIX_OFF(0xc)
/* MMC delay control register */
#define ST_TOP_MMC_DLY_CTRL			ST_TOP_MMC_DLY_FIX_OFF(0x18)
#define ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_CMD	BIT(0)
#define ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_PH_SEL	BIT(1)
#define ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE	BIT(8)
#define ST_TOP_MMC_DLY_CTRL_RX_DLL_ENABLE	BIT(9)
#define ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY	BIT(10)
#define ST_TOP_MMC_START_DLL_LOCK		BIT(11)

/* register to provide the phase-shift value for DLL */
#define ST_TOP_MMC_TX_DLL_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x1c)
#define ST_TOP_MMC_RX_DLL_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x20)
#define ST_TOP_MMC_RX_CMD_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x24)

/* phase shift delay on the tx clk 2.188ns */
#define ST_TOP_MMC_TX_DLL_STEP_DLY_VALID	0x6

#define ST_TOP_MMC_DLY_MAX			0xf

#define ST_TOP_MMC_DYN_DLY_CONF	\
		(ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE | \
		 ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY | \
		 ST_TOP_MMC_START_DLL_LOCK)

/*
 * For clock speeds greater than 90MHz, we need to check that the
 * DLL procedure has finished before switching to ultra-speed modes.
 */
#define	CLK_TO_CHECK_DLL_LOCK	90000000

static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
{
	if (!ioaddr)
		return;

	writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
	writel_relaxed(ST_TOP_MMC_DLY_MAX,
			ioaddr + ST_TOP_MMC_TX_CLK_DLY);
}

/**
 * st_mmcss_cconfig: configure the Arasan HC inside the flashSS.
 * @np: dt device node.
 * @host: sdhci host
 * Description: this function is to configure the Arasan host controller.
 * On some ST SoCs, i.e. STiH407 family, the MMC devices inside a dedicated
 * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
 * or eMMC4.3.  This has to be done before registering the sdhci host.
 */
static void st_mmcss_cconfig(struct device_node *np, struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct mmc_host *mhost = host->mmc;
	u32 cconf2, cconf3, cconf4, cconf5;

	if (!of_device_is_compatible(np, "st,sdhci-stih407"))
		return;

	cconf2 = ST_MMC_CCONFIG_2_DEFAULT;
	cconf3 = ST_MMC_CCONFIG_3_DEFAULT;
	cconf4 = ST_MMC_CCONFIG_4_DEFAULT;
	cconf5 = ST_MMC_CCONFIG_5_DEFAULT;

	writel_relaxed(ST_MMC_CCONFIG_1_DEFAULT,
			host->ioaddr + ST_MMC_CCONFIG_REG_1);

	/* Set clock frequency, default to 50MHz if max-frequency is not
	 * provided */

	switch (mhost->f_max) {
	case 200000000:
		clk_set_rate(pltfm_host->clk, mhost->f_max);
		cconf2 |= BASE_CLK_FREQ_200;
		break;
	case 100000000:
		clk_set_rate(pltfm_host->clk, mhost->f_max);
		cconf2 |= BASE_CLK_FREQ_100;
		break;
	default:
		clk_set_rate(pltfm_host->clk, 50000000);
		cconf2 |= BASE_CLK_FREQ_50;
	}

	writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2);

	if (mhost->caps & MMC_CAP_NONREMOVABLE)
		cconf3 |= ST_MMC_CCONFIG_EMMC_SLOT_TYPE;
	else
		/* CARD _D ET_CTRL */
		writel_relaxed(ST_MMC_GP_OUTPUT_CD,
				host->ioaddr + ST_MMC_GP_OUTPUT);

	if (mhost->caps & MMC_CAP_UHS_SDR50) {
		/* use 1.8V */
		cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
		cconf4 |= ST_MMC_CCONFIG_SDR50;
		/* Use tuning */
		cconf5 |= ST_MMC_CCONFIG_TUNING_FOR_SDR50;
		/* Max timeout for retuning */
		cconf5 |= RETUNING_TIMER_CNT_MAX;
	}

	if (mhost->caps & MMC_CAP_UHS_SDR104) {
		/*
		 * SDR104 implies the HC can support HS200 mode, so
		 * it's mandatory to use 1.8V
		 */
		cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
		cconf4 |= ST_MMC_CCONFIG_SDR104;
		/* Max timeout for retuning */
		cconf5 |= RETUNING_TIMER_CNT_MAX;
	}

	if (mhost->caps & MMC_CAP_UHS_DDR50)
		cconf4 |= ST_MMC_CCONFIG_DDR50;

	writel_relaxed(cconf3, host->ioaddr + ST_MMC_CCONFIG_REG_3);
	writel_relaxed(cconf4, host->ioaddr + ST_MMC_CCONFIG_REG_4);
	writel_relaxed(cconf5, host->ioaddr + ST_MMC_CCONFIG_REG_5);
}

static inline void st_mmcss_set_dll(void __iomem *ioaddr)
{
	if (!ioaddr)
		return;

	writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF,	ioaddr + ST_TOP_MMC_DLY_CTRL);
	writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID,
			ioaddr + ST_TOP_MMC_TX_DLL_STEP_DLY);
}

static int st_mmcss_lock_dll(void __iomem *ioaddr)
{
	unsigned long curr, value;
	unsigned long finish = jiffies + HZ;

	/* Checks if the DLL procedure is finished */
	do {
		curr = jiffies;
		value = readl(ioaddr + ST_MMC_STATUS_R);
		if (value & 0x1)
			return 0;

		cpu_relax();
	} while (!time_after_eq(curr, finish));

	return -EBUSY;
}

static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
{
	int ret = 0;
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct st_mmc_platform_data *pdata = pltfm_host->priv;

	if (host->clock > CLK_TO_CHECK_DLL_LOCK) {
		st_mmcss_set_dll(pdata->top_ioaddr);
		ret = st_mmcss_lock_dll(host->ioaddr);
	}

	return ret;
}

static void sdhci_st_set_uhs_signaling(struct sdhci_host *host,
					unsigned int uhs)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct st_mmc_platform_data *pdata = pltfm_host->priv;
	u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	int ret = 0;

	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	switch (uhs) {
	/*
	 * Set V18_EN -- UHS modes do not work without this.
	 * does not change signaling voltage
	 */

	case MMC_TIMING_UHS_SDR12:
		st_mmcss_set_static_delay(pdata->top_ioaddr);
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_SDR25:
		st_mmcss_set_static_delay(pdata->top_ioaddr);
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_SDR50:
		st_mmcss_set_static_delay(pdata->top_ioaddr);
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
		ret = sdhci_st_set_dll_for_clock(host);
		break;
	case MMC_TIMING_UHS_SDR104:
	case MMC_TIMING_MMC_HS200:
		st_mmcss_set_static_delay(pdata->top_ioaddr);
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
		ret =  sdhci_st_set_dll_for_clock(host);
		break;
	case MMC_TIMING_UHS_DDR50:
	case MMC_TIMING_MMC_DDR52:
		st_mmcss_set_static_delay(pdata->top_ioaddr);
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
		break;
	}

	if (ret)
		dev_warn(mmc_dev(host->mmc), "Error setting dll for clock "
						"(uhs %d)\n", uhs);

	dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);

	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
}

static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
{
	u32 ret;

	switch (reg) {
	case SDHCI_CAPABILITIES:
		ret = readl_relaxed(host->ioaddr + reg);
		/* Support 3.3V and 1.8V */
		ret &= ~SDHCI_CAN_VDD_300;
		break;
	default:
		ret = readl_relaxed(host->ioaddr + reg);
	}
	return ret;
}

static const struct sdhci_ops sdhci_st_ops = {
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
	.set_clock = sdhci_set_clock,
	.set_bus_width = sdhci_set_bus_width,
	.read_l = sdhci_st_readl,
	.reset = sdhci_reset,
	.set_uhs_signaling = sdhci_st_set_uhs_signaling,
};

static const struct sdhci_pltfm_data sdhci_st_pdata = {
	.ops = &sdhci_st_ops,
	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
		SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
		SDHCI_QUIRK_NO_HISPD_BIT,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
		SDHCI_QUIRK2_STOP_WITH_TC,
};


static int sdhci_st_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct sdhci_host *host;
	struct st_mmc_platform_data *pdata;
	struct sdhci_pltfm_host *pltfm_host;
	struct clk *clk;
	int ret = 0;
	u16 host_version;
	struct resource *res;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	clk =  devm_clk_get(&pdev->dev, "mmc");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Peripheral clk not found\n");
		return PTR_ERR(clk);
	}

	pdata->rstc = devm_reset_control_get(&pdev->dev, NULL);
	if (IS_ERR(pdata->rstc))
		pdata->rstc = NULL;
	else
		reset_control_deassert(pdata->rstc);

	host = sdhci_pltfm_init(pdev, &sdhci_st_pdata, 0);
	if (IS_ERR(host)) {
		dev_err(&pdev->dev, "Failed sdhci_pltfm_init\n");
		ret = PTR_ERR(host);
		goto err_pltfm_init;
	}

	ret = mmc_of_parse(host->mmc);
	if (ret) {
		dev_err(&pdev->dev, "Failed mmc_of_parse\n");
		goto err_of;
	}

	clk_prepare_enable(clk);

	/* Configure the FlashSS Top registers for setting eMMC TX/RX delay */
	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
					   "top-mmc-delay");
	pdata->top_ioaddr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(pdata->top_ioaddr)) {
		dev_warn(&pdev->dev, "FlashSS Top Dly registers not available");
		pdata->top_ioaddr = NULL;
	}

	pltfm_host = sdhci_priv(host);
	pltfm_host->priv = pdata;
	pltfm_host->clk = clk;

	/* Configure the Arasan HC inside the flashSS */
	st_mmcss_cconfig(np, host);

	ret = sdhci_add_host(host);
	if (ret) {
		dev_err(&pdev->dev, "Failed sdhci_add_host\n");
		goto err_out;
	}

	platform_set_drvdata(pdev, host);

	host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));

	dev_info(&pdev->dev, "SDHCI ST Initialised: Host Version: 0x%x Vendor Version 0x%x\n",
		((host_version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT),
		((host_version & SDHCI_VENDOR_VER_MASK) >>
		SDHCI_VENDOR_VER_SHIFT));

	return 0;

err_out:
	clk_disable_unprepare(clk);
err_of:
	sdhci_pltfm_free(pdev);
err_pltfm_init:
	if (pdata->rstc)
		reset_control_assert(pdata->rstc);

	return ret;
}

static int sdhci_st_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct st_mmc_platform_data *pdata = pltfm_host->priv;
	int ret;

	ret = sdhci_pltfm_unregister(pdev);

	if (pdata->rstc)
		reset_control_assert(pdata->rstc);

	return ret;
}

#ifdef CONFIG_PM_SLEEP
static int sdhci_st_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct st_mmc_platform_data *pdata = pltfm_host->priv;
	int ret = sdhci_suspend_host(host);

	if (ret)
		goto out;

	if (pdata->rstc)
		reset_control_assert(pdata->rstc);

	clk_disable_unprepare(pltfm_host->clk);
out:
	return ret;
}

static int sdhci_st_resume(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct st_mmc_platform_data *pdata = pltfm_host->priv;
	struct device_node *np = dev->of_node;

	clk_prepare_enable(pltfm_host->clk);

	if (pdata->rstc)
		reset_control_deassert(pdata->rstc);

	st_mmcss_cconfig(np, host);

	return sdhci_resume_host(host);
}
#endif

static SIMPLE_DEV_PM_OPS(sdhci_st_pmops, sdhci_st_suspend, sdhci_st_resume);

static const struct of_device_id st_sdhci_match[] = {
	{ .compatible = "st,sdhci" },
	{},
};

MODULE_DEVICE_TABLE(of, st_sdhci_match);

static struct platform_driver sdhci_st_driver = {
	.probe = sdhci_st_probe,
	.remove = sdhci_st_remove,
	.driver = {
		   .name = "sdhci-st",
		   .pm = &sdhci_st_pmops,
		   .of_match_table = of_match_ptr(st_sdhci_match),
		  },
};

module_platform_driver(sdhci_st_driver);

MODULE_DESCRIPTION("SDHCI driver for STMicroelectronics SoCs");
MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:sdhci-st");
Commit	Line	Data
f52d9c4f PG	1	/*
	2	* Support for SDHCI on STMicroelectronics SoCs
	3	*
	4	* Copyright (C) 2014 STMicroelectronics Ltd
	5	* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	6	* Contributors: Peter Griffin <peter.griffin@linaro.org>
	7	*
	8	* Based on sdhci-cns3xxx.c
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	*/
	20
	21	#include <linux/io.h>
	22	#include <linux/of.h>
	23	#include <linux/module.h>
	24	#include <linux/err.h>
	25	#include <linux/mmc/host.h>
406c2431	26	#include <linux/reset.h>
f52d9c4f PG	27	#include "sdhci-pltfm.h"
f52d9c4f PG	28
406c2431 PG	29	struct st_mmc_platform_data {
	30	struct reset_control *rstc;
	31	void __iomem *top_ioaddr;
	32	};
	33
8bef7178 PG	34	/* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
	35
	36	#define ST_MMC_CCONFIG_REG_1 0x400
	37	#define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT BIT(24)
	38	#define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ BIT(12)
	39	#define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT BIT(8)
	40	#define ST_MMC_CCONFIG_ASYNC_WAKEUP BIT(0)
	41	#define ST_MMC_CCONFIG_1_DEFAULT \
	42	((ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT) \| \
	43	(ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ) \| \
	44	(ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT))
	45
	46	#define ST_MMC_CCONFIG_REG_2 0x404
	47	#define ST_MMC_CCONFIG_HIGH_SPEED BIT(28)
	48	#define ST_MMC_CCONFIG_ADMA2 BIT(24)
	49	#define ST_MMC_CCONFIG_8BIT BIT(20)
	50	#define ST_MMC_CCONFIG_MAX_BLK_LEN 16
	51	#define MAX_BLK_LEN_1024 1
	52	#define MAX_BLK_LEN_2048 2
	53	#define BASE_CLK_FREQ_200 0xc8
	54	#define BASE_CLK_FREQ_100 0x64
	55	#define BASE_CLK_FREQ_50 0x32
	56	#define ST_MMC_CCONFIG_2_DEFAULT \
	57	(ST_MMC_CCONFIG_HIGH_SPEED \| ST_MMC_CCONFIG_ADMA2 \| \
	58	ST_MMC_CCONFIG_8BIT \| \
	59	(MAX_BLK_LEN_1024 << ST_MMC_CCONFIG_MAX_BLK_LEN))
	60
	61	#define ST_MMC_CCONFIG_REG_3 0x408
	62	#define ST_MMC_CCONFIG_EMMC_SLOT_TYPE BIT(28)
	63	#define ST_MMC_CCONFIG_64BIT BIT(24)
	64	#define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT BIT(20)
	65	#define ST_MMC_CCONFIG_1P8_VOLT BIT(16)
	66	#define ST_MMC_CCONFIG_3P0_VOLT BIT(12)
	67	#define ST_MMC_CCONFIG_3P3_VOLT BIT(8)
	68	#define ST_MMC_CCONFIG_SUSP_RES_SUPPORT BIT(4)
	69	#define ST_MMC_CCONFIG_SDMA BIT(0)
	70	#define ST_MMC_CCONFIG_3_DEFAULT \
	71	(ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT \| \
	72	ST_MMC_CCONFIG_3P3_VOLT \| \
	73	ST_MMC_CCONFIG_SUSP_RES_SUPPORT \| \
	74	ST_MMC_CCONFIG_SDMA)
	75
	76	#define ST_MMC_CCONFIG_REG_4 0x40c
	77	#define ST_MMC_CCONFIG_D_DRIVER BIT(20)
	78	#define ST_MMC_CCONFIG_C_DRIVER BIT(16)
	79	#define ST_MMC_CCONFIG_A_DRIVER BIT(12)
	80	#define ST_MMC_CCONFIG_DDR50 BIT(8)
	81	#define ST_MMC_CCONFIG_SDR104 BIT(4)
	82	#define ST_MMC_CCONFIG_SDR50 BIT(0)
	83	#define ST_MMC_CCONFIG_4_DEFAULT 0
	84
	85	#define ST_MMC_CCONFIG_REG_5 0x410
	86	#define ST_MMC_CCONFIG_TUNING_FOR_SDR50 BIT(8)
	87	#define RETUNING_TIMER_CNT_MAX 0xf
	88	#define ST_MMC_CCONFIG_5_DEFAULT 0
	89
	90	/* I/O configuration for Arasan IP */
	91	#define ST_MMC_GP_OUTPUT 0x450
	92	#define ST_MMC_GP_OUTPUT_CD BIT(12)
	93
	94	#define ST_MMC_STATUS_R 0x460
	95
	96	#define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
	97
98	/* TOP config registers to manage static and dynamic delay */
99	#define ST_TOP_MMC_TX_CLK_DLY ST_TOP_MMC_DLY_FIX_OFF(0x8)
100	#define ST_TOP_MMC_RX_CLK_DLY ST_TOP_MMC_DLY_FIX_OFF(0xc)
101	/* MMC delay control register */
102	#define ST_TOP_MMC_DLY_CTRL ST_TOP_MMC_DLY_FIX_OFF(0x18)
103	#define ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_CMD BIT(0)
104	#define ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_PH_SEL BIT(1)
105	#define ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE BIT(8)
106	#define ST_TOP_MMC_DLY_CTRL_RX_DLL_ENABLE BIT(9)
107	#define ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY BIT(10)
108	#define ST_TOP_MMC_START_DLL_LOCK BIT(11)
109
110	/* register to provide the phase-shift value for DLL */
111	#define ST_TOP_MMC_TX_DLL_STEP_DLY ST_TOP_MMC_DLY_FIX_OFF(0x1c)
112	#define ST_TOP_MMC_RX_DLL_STEP_DLY ST_TOP_MMC_DLY_FIX_OFF(0x20)
113	#define ST_TOP_MMC_RX_CMD_STEP_DLY ST_TOP_MMC_DLY_FIX_OFF(0x24)
114
115	/* phase shift delay on the tx clk 2.188ns */
116	#define ST_TOP_MMC_TX_DLL_STEP_DLY_VALID 0x6
117
118	#define ST_TOP_MMC_DLY_MAX 0xf
119
120	#define ST_TOP_MMC_DYN_DLY_CONF \
121	(ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE \| \
122	ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY \| \
123	ST_TOP_MMC_START_DLL_LOCK)
124
bfa44804 PG	125	/*
	126	* For clock speeds greater than 90MHz, we need to check that the
	127	* DLL procedure has finished before switching to ultra-speed modes.
	128	*/
	129	#define CLK_TO_CHECK_DLL_LOCK 90000000
	130
	131	static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
	132	{
	133	if (!ioaddr)
	134	return;
	135
	136	writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
	137	writel_relaxed(ST_TOP_MMC_DLY_MAX,
	138	ioaddr + ST_TOP_MMC_TX_CLK_DLY);
	139	}
	140
2053812f PG	141	/**
	142	* st_mmcss_cconfig: configure the Arasan HC inside the flashSS.
	143	* @np: dt device node.
	144	* @host: sdhci host
	145	* Description: this function is to configure the Arasan host controller.
	146	* On some ST SoCs, i.e. STiH407 family, the MMC devices inside a dedicated
	147	* flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
	148	* or eMMC4.3. This has to be done before registering the sdhci host.
	149	*/
	150	static void st_mmcss_cconfig(struct device_node np, struct sdhci_host host)
	151	{
	152	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	153	struct mmc_host *mhost = host->mmc;
	154	u32 cconf2, cconf3, cconf4, cconf5;
	155
	156	if (!of_device_is_compatible(np, "st,sdhci-stih407"))
	157	return;
	158
	159	cconf2 = ST_MMC_CCONFIG_2_DEFAULT;
	160	cconf3 = ST_MMC_CCONFIG_3_DEFAULT;
	161	cconf4 = ST_MMC_CCONFIG_4_DEFAULT;
	162	cconf5 = ST_MMC_CCONFIG_5_DEFAULT;
	163
	164	writel_relaxed(ST_MMC_CCONFIG_1_DEFAULT,
	165	host->ioaddr + ST_MMC_CCONFIG_REG_1);
	166
	167	/* Set clock frequency, default to 50MHz if max-frequency is not
	168	* provided */
	169
	170	switch (mhost->f_max) {
	171	case 200000000:
	172	clk_set_rate(pltfm_host->clk, mhost->f_max);
	173	cconf2 \|= BASE_CLK_FREQ_200;
	174	break;
	175	case 100000000:
	176	clk_set_rate(pltfm_host->clk, mhost->f_max);
	177	cconf2 \|= BASE_CLK_FREQ_100;
	178	break;
	179	default:
	180	clk_set_rate(pltfm_host->clk, 50000000);
	181	cconf2 \|= BASE_CLK_FREQ_50;
	182	}
	183
	184	writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2);
	185
	186	if (mhost->caps & MMC_CAP_NONREMOVABLE)
	187	cconf3 \|= ST_MMC_CCONFIG_EMMC_SLOT_TYPE;
	188	else
	189	/* CARD _D ET_CTRL */
	190	writel_relaxed(ST_MMC_GP_OUTPUT_CD,
	191	host->ioaddr + ST_MMC_GP_OUTPUT);
	192
	193	if (mhost->caps & MMC_CAP_UHS_SDR50) {
	194	/* use 1.8V */
	195	cconf3 \|= ST_MMC_CCONFIG_1P8_VOLT;
	196	cconf4 \|= ST_MMC_CCONFIG_SDR50;
	197	/* Use tuning */
	198	cconf5 \|= ST_MMC_CCONFIG_TUNING_FOR_SDR50;
	199	/* Max timeout for retuning */
	200	cconf5 \|= RETUNING_TIMER_CNT_MAX;
	201	}
	202
	203	if (mhost->caps & MMC_CAP_UHS_SDR104) {
	204	/*
205	* SDR104 implies the HC can support HS200 mode, so
206	* it's mandatory to use 1.8V
207	*/
208	cconf3 \|= ST_MMC_CCONFIG_1P8_VOLT;
209	cconf4 \|= ST_MMC_CCONFIG_SDR104;
210	/* Max timeout for retuning */
211	cconf5 \|= RETUNING_TIMER_CNT_MAX;
212	}
213
214	if (mhost->caps & MMC_CAP_UHS_DDR50)
215	cconf4 \|= ST_MMC_CCONFIG_DDR50;
216
217	writel_relaxed(cconf3, host->ioaddr + ST_MMC_CCONFIG_REG_3);
218	writel_relaxed(cconf4, host->ioaddr + ST_MMC_CCONFIG_REG_4);
219	writel_relaxed(cconf5, host->ioaddr + ST_MMC_CCONFIG_REG_5);
220	}
221
bfa44804 PG	222	static inline void st_mmcss_set_dll(void __iomem *ioaddr)
	223	{
	224	if (!ioaddr)
	225	return;
	226
	227	writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF, ioaddr + ST_TOP_MMC_DLY_CTRL);
	228	writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID,
	229	ioaddr + ST_TOP_MMC_TX_DLL_STEP_DLY);
	230	}
	231
	232	static int st_mmcss_lock_dll(void __iomem *ioaddr)
	233	{
	234	unsigned long curr, value;
	235	unsigned long finish = jiffies + HZ;
	236
	237	/* Checks if the DLL procedure is finished */
	238	do {
	239	curr = jiffies;
	240	value = readl(ioaddr + ST_MMC_STATUS_R);
	241	if (value & 0x1)
	242	return 0;
	243
	244	cpu_relax();
	245	} while (!time_after_eq(curr, finish));
	246
	247	return -EBUSY;
	248	}
	249
	250	static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
	251	{
	252	int ret = 0;
	253	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	254	struct st_mmc_platform_data *pdata = pltfm_host->priv;
	255
	256	if (host->clock > CLK_TO_CHECK_DLL_LOCK) {
	257	st_mmcss_set_dll(pdata->top_ioaddr);
	258	ret = st_mmcss_lock_dll(host->ioaddr);
	259	}
	260
	261	return ret;
	262	}
	263
cf48d32e PG	264	static void sdhci_st_set_uhs_signaling(struct sdhci_host *host,
	265	unsigned int uhs)
	266	{
	267	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	268	struct st_mmc_platform_data *pdata = pltfm_host->priv;
	269	u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	270	int ret = 0;
	271
	272	/* Select Bus Speed Mode for host */
	273	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	274	switch (uhs) {
	275	/*
	276	* Set V18_EN -- UHS modes do not work without this.
	277	* does not change signaling voltage
	278	*/
	279
	280	case MMC_TIMING_UHS_SDR12:
	281	st_mmcss_set_static_delay(pdata->top_ioaddr);
	282	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12 \| SDHCI_CTRL_VDD_180;
	283	break;
	284	case MMC_TIMING_UHS_SDR25:
	285	st_mmcss_set_static_delay(pdata->top_ioaddr);
	286	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25 \| SDHCI_CTRL_VDD_180;
	287	break;
	288	case MMC_TIMING_UHS_SDR50:
	289	st_mmcss_set_static_delay(pdata->top_ioaddr);
	290	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50 \| SDHCI_CTRL_VDD_180;
	291	ret = sdhci_st_set_dll_for_clock(host);
	292	break;
	293	case MMC_TIMING_UHS_SDR104:
	294	case MMC_TIMING_MMC_HS200:
	295	st_mmcss_set_static_delay(pdata->top_ioaddr);
	296	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
	297	ret = sdhci_st_set_dll_for_clock(host);
	298	break;
	299	case MMC_TIMING_UHS_DDR50:
	300	case MMC_TIMING_MMC_DDR52:
	301	st_mmcss_set_static_delay(pdata->top_ioaddr);
	302	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
	303	break;
	304	}
	305
	306	if (ret)
	307	dev_warn(mmc_dev(host->mmc), "Error setting dll for clock "
	308	"(uhs %d)\n", uhs);
	309
	310	dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);
	311
	312	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	313	}
bfa44804	314
f52d9c4f PG	315	static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
	316	{
	317	u32 ret;
	318
	319	switch (reg) {
	320	case SDHCI_CAPABILITIES:
	321	ret = readl_relaxed(host->ioaddr + reg);
	322	/* Support 3.3V and 1.8V */
	323	ret &= ~SDHCI_CAN_VDD_300;
	324	break;
	325	default:
	326	ret = readl_relaxed(host->ioaddr + reg);
	327	}
	328	return ret;
	329	}
	330
	331	static const struct sdhci_ops sdhci_st_ops = {
	332	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
	333	.set_clock = sdhci_set_clock,
	334	.set_bus_width = sdhci_set_bus_width,
	335	.read_l = sdhci_st_readl,
	336	.reset = sdhci_reset,
cf48d32e	337	.set_uhs_signaling = sdhci_st_set_uhs_signaling,
f52d9c4f PG	338	};
	339
	340	static const struct sdhci_pltfm_data sdhci_st_pdata = {
	341	.ops = &sdhci_st_ops,
	342	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC \|
4e187d31 PG	343	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN \|
	344	SDHCI_QUIRK_NO_HISPD_BIT,
	345	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN \|
	346	SDHCI_QUIRK2_STOP_WITH_TC,
f52d9c4f PG	347	};
	348
	349
	350	static int sdhci_st_probe(struct platform_device *pdev)
	351	{
2053812f	352	struct device_node *np = pdev->dev.of_node;
f52d9c4f	353	struct sdhci_host *host;
406c2431	354	struct st_mmc_platform_data *pdata;
f52d9c4f PG	355	struct sdhci_pltfm_host *pltfm_host;
	356	struct clk *clk;
	357	int ret = 0;
	358	u16 host_version;
406c2431 PG	359	struct resource *res;
	360
	361	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	362	if (!pdata)
	363	return -ENOMEM;
f52d9c4f PG	364
	365	clk = devm_clk_get(&pdev->dev, "mmc");
	366	if (IS_ERR(clk)) {
	367	dev_err(&pdev->dev, "Peripheral clk not found\n");
	368	return PTR_ERR(clk);
	369	}
	370
406c2431 PG	371	pdata->rstc = devm_reset_control_get(&pdev->dev, NULL);
	372	if (IS_ERR(pdata->rstc))
	373	pdata->rstc = NULL;
	374	else
	375	reset_control_deassert(pdata->rstc);
	376
f52d9c4f PG	377	host = sdhci_pltfm_init(pdev, &sdhci_st_pdata, 0);
	378	if (IS_ERR(host)) {
	379	dev_err(&pdev->dev, "Failed sdhci_pltfm_init\n");
406c2431 PG	380	ret = PTR_ERR(host);
406c2431 PG	381	goto err_pltfm_init;
f52d9c4f PG	382	}
	383
	384	ret = mmc_of_parse(host->mmc);
f52d9c4f PG	385	if (ret) {
f52d9c4f PG	386	dev_err(&pdev->dev, "Failed mmc_of_parse\n");
fc702cb3	387	goto err_of;
f52d9c4f PG	388	}
	389
	390	clk_prepare_enable(clk);
	391
406c2431 PG	392	/* Configure the FlashSS Top registers for setting eMMC TX/RX delay */
	393	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	394	"top-mmc-delay");
	395	pdata->top_ioaddr = devm_ioremap_resource(&pdev->dev, res);
	396	if (IS_ERR(pdata->top_ioaddr)) {
	397	dev_warn(&pdev->dev, "FlashSS Top Dly registers not available");
	398	pdata->top_ioaddr = NULL;
	399	}
	400
f52d9c4f	401	pltfm_host = sdhci_priv(host);
406c2431	402	pltfm_host->priv = pdata;
f52d9c4f PG	403	pltfm_host->clk = clk;
f52d9c4f PG	404
2053812f PG	405	/* Configure the Arasan HC inside the flashSS */
	406	st_mmcss_cconfig(np, host);
	407
f52d9c4f PG	408	ret = sdhci_add_host(host);
	409	if (ret) {
	410	dev_err(&pdev->dev, "Failed sdhci_add_host\n");
	411	goto err_out;
	412	}
	413
	414	platform_set_drvdata(pdev, host);
	415
	416	host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
	417
	418	dev_info(&pdev->dev, "SDHCI ST Initialised: Host Version: 0x%x Vendor Version 0x%x\n",
	419	((host_version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT),
	420	((host_version & SDHCI_VENDOR_VER_MASK) >>
	421	SDHCI_VENDOR_VER_SHIFT));
	422
	423	return 0;
	424
	425	err_out:
	426	clk_disable_unprepare(clk);
fc702cb3	427	err_of:
f52d9c4f	428	sdhci_pltfm_free(pdev);
406c2431 PG	429	err_pltfm_init:
	430	if (pdata->rstc)
	431	reset_control_assert(pdata->rstc);
	432
	433	return ret;
	434	}
	435
	436	static int sdhci_st_remove(struct platform_device *pdev)
	437	{
	438	struct sdhci_host *host = platform_get_drvdata(pdev);
	439	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	440	struct st_mmc_platform_data *pdata = pltfm_host->priv;
	441	int ret;
	442
	443	ret = sdhci_pltfm_unregister(pdev);
	444
	445	if (pdata->rstc)
	446	reset_control_assert(pdata->rstc);
f52d9c4f PG	447
	448	return ret;
	449	}
	450
f52d9c4f PG	451	#ifdef CONFIG_PM_SLEEP
	452	static int sdhci_st_suspend(struct device *dev)
	453	{
	454	struct sdhci_host *host = dev_get_drvdata(dev);
	455	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
406c2431	456	struct st_mmc_platform_data *pdata = pltfm_host->priv;
f52d9c4f PG	457	int ret = sdhci_suspend_host(host);
	458
	459	if (ret)
	460	goto out;
	461
406c2431 PG	462	if (pdata->rstc)
	463	reset_control_assert(pdata->rstc);
	464
f52d9c4f PG	465	clk_disable_unprepare(pltfm_host->clk);
	466	out:
	467	return ret;
	468	}
	469
	470	static int sdhci_st_resume(struct device *dev)
	471	{
	472	struct sdhci_host *host = dev_get_drvdata(dev);
	473	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
406c2431	474	struct st_mmc_platform_data *pdata = pltfm_host->priv;
2053812f	475	struct device_node *np = dev->of_node;
f52d9c4f PG	476
	477	clk_prepare_enable(pltfm_host->clk);
	478
406c2431 PG	479	if (pdata->rstc)
	480	reset_control_deassert(pdata->rstc);
	481
2053812f PG	482	st_mmcss_cconfig(np, host);
2053812f PG	483
f52d9c4f PG	484	return sdhci_resume_host(host);
	485	}
	486	#endif
	487
	488	static SIMPLE_DEV_PM_OPS(sdhci_st_pmops, sdhci_st_suspend, sdhci_st_resume);
	489
	490	static const struct of_device_id st_sdhci_match[] = {
	491	{ .compatible = "st,sdhci" },
	492	{},
	493	};
	494
	495	MODULE_DEVICE_TABLE(of, st_sdhci_match);
	496
	497	static struct platform_driver sdhci_st_driver = {
	498	.probe = sdhci_st_probe,
406c2431	499	.remove = sdhci_st_remove,
f52d9c4f PG	500	.driver = {
	501	.name = "sdhci-st",
	502	.pm = &sdhci_st_pmops,
	503	.of_match_table = of_match_ptr(st_sdhci_match),
	504	},
	505	};
	506
	507	module_platform_driver(sdhci_st_driver);
	508
	509	MODULE_DESCRIPTION("SDHCI driver for STMicroelectronics SoCs");
	510	MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
	511	MODULE_LICENSE("GPL v2");
e6ac184b	512	MODULE_ALIAS("platform:sdhci-st");