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03d2bfc8 OJ |
1 | /* |
2 | * Copyright (C) 2010 Google, Inc. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/err.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/io.h> | |
275173b2 | 20 | #include <linux/of_gpio.h> |
03d2bfc8 OJ |
21 | #include <linux/gpio.h> |
22 | #include <linux/mmc/card.h> | |
23 | #include <linux/mmc/host.h> | |
24 | ||
25 | #include <mach/gpio.h> | |
26 | #include <mach/sdhci.h> | |
27 | ||
03d2bfc8 OJ |
28 | #include "sdhci-pltfm.h" |
29 | ||
30 | static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg) | |
31 | { | |
32 | u32 val; | |
33 | ||
34 | if (unlikely(reg == SDHCI_PRESENT_STATE)) { | |
35 | /* Use wp_gpio here instead? */ | |
36 | val = readl(host->ioaddr + reg); | |
37 | return val | SDHCI_WRITE_PROTECT; | |
38 | } | |
39 | ||
40 | return readl(host->ioaddr + reg); | |
41 | } | |
42 | ||
43 | static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) | |
44 | { | |
45 | if (unlikely(reg == SDHCI_HOST_VERSION)) { | |
46 | /* Erratum: Version register is invalid in HW. */ | |
47 | return SDHCI_SPEC_200; | |
48 | } | |
49 | ||
50 | return readw(host->ioaddr + reg); | |
51 | } | |
52 | ||
53 | static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) | |
54 | { | |
55 | /* Seems like we're getting spurious timeout and crc errors, so | |
56 | * disable signalling of them. In case of real errors software | |
57 | * timers should take care of eventually detecting them. | |
58 | */ | |
59 | if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) | |
60 | val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); | |
61 | ||
62 | writel(val, host->ioaddr + reg); | |
63 | ||
64 | if (unlikely(reg == SDHCI_INT_ENABLE)) { | |
65 | /* Erratum: Must enable block gap interrupt detection */ | |
66 | u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); | |
67 | if (val & SDHCI_INT_CARD_INT) | |
68 | gap_ctrl |= 0x8; | |
69 | else | |
70 | gap_ctrl &= ~0x8; | |
71 | writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); | |
72 | } | |
73 | } | |
74 | ||
75 | static unsigned int tegra_sdhci_get_ro(struct sdhci_host *sdhci) | |
76 | { | |
275173b2 GL |
77 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci); |
78 | struct tegra_sdhci_platform_data *plat = pltfm_host->priv; | |
03d2bfc8 OJ |
79 | |
80 | if (!gpio_is_valid(plat->wp_gpio)) | |
81 | return -1; | |
82 | ||
83 | return gpio_get_value(plat->wp_gpio); | |
84 | } | |
85 | ||
86 | static irqreturn_t carddetect_irq(int irq, void *data) | |
87 | { | |
88 | struct sdhci_host *sdhost = (struct sdhci_host *)data; | |
89 | ||
90 | tasklet_schedule(&sdhost->card_tasklet); | |
91 | return IRQ_HANDLED; | |
92 | }; | |
93 | ||
94 | static int tegra_sdhci_8bit(struct sdhci_host *host, int bus_width) | |
95 | { | |
275173b2 GL |
96 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
97 | struct tegra_sdhci_platform_data *plat = pltfm_host->priv; | |
03d2bfc8 OJ |
98 | u32 ctrl; |
99 | ||
03d2bfc8 OJ |
100 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
101 | if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) { | |
102 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
103 | ctrl |= SDHCI_CTRL_8BITBUS; | |
104 | } else { | |
105 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
106 | if (bus_width == MMC_BUS_WIDTH_4) | |
107 | ctrl |= SDHCI_CTRL_4BITBUS; | |
108 | else | |
109 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
110 | } | |
111 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
112 | return 0; | |
113 | } | |
114 | ||
85d6509d SG |
115 | static struct sdhci_ops tegra_sdhci_ops = { |
116 | .get_ro = tegra_sdhci_get_ro, | |
117 | .read_l = tegra_sdhci_readl, | |
118 | .read_w = tegra_sdhci_readw, | |
119 | .write_l = tegra_sdhci_writel, | |
120 | .platform_8bit_width = tegra_sdhci_8bit, | |
121 | }; | |
122 | ||
123 | static struct sdhci_pltfm_data sdhci_tegra_pdata = { | |
124 | .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | | |
125 | SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
126 | SDHCI_QUIRK_NO_HISPD_BIT | | |
127 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, | |
128 | .ops = &tegra_sdhci_ops, | |
129 | }; | |
03d2bfc8 | 130 | |
275173b2 GL |
131 | static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = { |
132 | { .compatible = "nvidia,tegra20-sdhci", }, | |
133 | {} | |
134 | }; | |
135 | MODULE_DEVICE_TABLE(of, sdhci_dt_ids); | |
136 | ||
137 | static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata( | |
138 | struct platform_device *pdev) | |
139 | { | |
140 | struct tegra_sdhci_platform_data *plat; | |
141 | struct device_node *np = pdev->dev.of_node; | |
142 | ||
143 | if (!np) | |
144 | return NULL; | |
145 | ||
146 | plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); | |
147 | if (!plat) { | |
148 | dev_err(&pdev->dev, "Can't allocate platform data\n"); | |
149 | return NULL; | |
150 | } | |
151 | ||
152 | plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); | |
153 | plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); | |
154 | plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0); | |
155 | ||
156 | return plat; | |
157 | } | |
158 | ||
85d6509d | 159 | static int __devinit sdhci_tegra_probe(struct platform_device *pdev) |
03d2bfc8 | 160 | { |
85d6509d | 161 | struct sdhci_pltfm_host *pltfm_host; |
03d2bfc8 | 162 | struct tegra_sdhci_platform_data *plat; |
85d6509d | 163 | struct sdhci_host *host; |
03d2bfc8 OJ |
164 | struct clk *clk; |
165 | int rc; | |
166 | ||
85d6509d SG |
167 | host = sdhci_pltfm_init(pdev, &sdhci_tegra_pdata); |
168 | if (IS_ERR(host)) | |
169 | return PTR_ERR(host); | |
170 | ||
171 | pltfm_host = sdhci_priv(host); | |
172 | ||
03d2bfc8 | 173 | plat = pdev->dev.platform_data; |
85d6509d | 174 | |
275173b2 GL |
175 | if (plat == NULL) |
176 | plat = sdhci_tegra_dt_parse_pdata(pdev); | |
177 | ||
03d2bfc8 OJ |
178 | if (plat == NULL) { |
179 | dev_err(mmc_dev(host->mmc), "missing platform data\n"); | |
85d6509d SG |
180 | rc = -ENXIO; |
181 | goto err_no_plat; | |
03d2bfc8 OJ |
182 | } |
183 | ||
275173b2 GL |
184 | pltfm_host->priv = plat; |
185 | ||
03d2bfc8 OJ |
186 | if (gpio_is_valid(plat->power_gpio)) { |
187 | rc = gpio_request(plat->power_gpio, "sdhci_power"); | |
188 | if (rc) { | |
189 | dev_err(mmc_dev(host->mmc), | |
190 | "failed to allocate power gpio\n"); | |
85d6509d | 191 | goto err_power_req; |
03d2bfc8 OJ |
192 | } |
193 | tegra_gpio_enable(plat->power_gpio); | |
194 | gpio_direction_output(plat->power_gpio, 1); | |
195 | } | |
196 | ||
197 | if (gpio_is_valid(plat->cd_gpio)) { | |
198 | rc = gpio_request(plat->cd_gpio, "sdhci_cd"); | |
199 | if (rc) { | |
200 | dev_err(mmc_dev(host->mmc), | |
201 | "failed to allocate cd gpio\n"); | |
85d6509d | 202 | goto err_cd_req; |
03d2bfc8 OJ |
203 | } |
204 | tegra_gpio_enable(plat->cd_gpio); | |
205 | gpio_direction_input(plat->cd_gpio); | |
206 | ||
207 | rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq, | |
208 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | |
209 | mmc_hostname(host->mmc), host); | |
210 | ||
211 | if (rc) { | |
212 | dev_err(mmc_dev(host->mmc), "request irq error\n"); | |
85d6509d | 213 | goto err_cd_irq_req; |
03d2bfc8 OJ |
214 | } |
215 | ||
216 | } | |
217 | ||
218 | if (gpio_is_valid(plat->wp_gpio)) { | |
219 | rc = gpio_request(plat->wp_gpio, "sdhci_wp"); | |
220 | if (rc) { | |
221 | dev_err(mmc_dev(host->mmc), | |
222 | "failed to allocate wp gpio\n"); | |
85d6509d | 223 | goto err_wp_req; |
03d2bfc8 OJ |
224 | } |
225 | tegra_gpio_enable(plat->wp_gpio); | |
226 | gpio_direction_input(plat->wp_gpio); | |
227 | } | |
228 | ||
229 | clk = clk_get(mmc_dev(host->mmc), NULL); | |
230 | if (IS_ERR(clk)) { | |
231 | dev_err(mmc_dev(host->mmc), "clk err\n"); | |
232 | rc = PTR_ERR(clk); | |
85d6509d | 233 | goto err_clk_get; |
03d2bfc8 OJ |
234 | } |
235 | clk_enable(clk); | |
236 | pltfm_host->clk = clk; | |
237 | ||
c7f409e3 VR |
238 | host->mmc->pm_caps = plat->pm_flags; |
239 | ||
03d2bfc8 OJ |
240 | if (plat->is_8bit) |
241 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
242 | ||
85d6509d SG |
243 | rc = sdhci_add_host(host); |
244 | if (rc) | |
245 | goto err_add_host; | |
246 | ||
03d2bfc8 OJ |
247 | return 0; |
248 | ||
85d6509d SG |
249 | err_add_host: |
250 | clk_disable(pltfm_host->clk); | |
251 | clk_put(pltfm_host->clk); | |
252 | err_clk_get: | |
03d2bfc8 OJ |
253 | if (gpio_is_valid(plat->wp_gpio)) { |
254 | tegra_gpio_disable(plat->wp_gpio); | |
255 | gpio_free(plat->wp_gpio); | |
256 | } | |
85d6509d | 257 | err_wp_req: |
8154b575 WS |
258 | if (gpio_is_valid(plat->cd_gpio)) |
259 | free_irq(gpio_to_irq(plat->cd_gpio), host); | |
85d6509d | 260 | err_cd_irq_req: |
03d2bfc8 OJ |
261 | if (gpio_is_valid(plat->cd_gpio)) { |
262 | tegra_gpio_disable(plat->cd_gpio); | |
263 | gpio_free(plat->cd_gpio); | |
264 | } | |
85d6509d | 265 | err_cd_req: |
03d2bfc8 OJ |
266 | if (gpio_is_valid(plat->power_gpio)) { |
267 | tegra_gpio_disable(plat->power_gpio); | |
268 | gpio_free(plat->power_gpio); | |
269 | } | |
85d6509d SG |
270 | err_power_req: |
271 | err_no_plat: | |
272 | sdhci_pltfm_free(pdev); | |
03d2bfc8 OJ |
273 | return rc; |
274 | } | |
275 | ||
85d6509d | 276 | static int __devexit sdhci_tegra_remove(struct platform_device *pdev) |
03d2bfc8 | 277 | { |
85d6509d | 278 | struct sdhci_host *host = platform_get_drvdata(pdev); |
03d2bfc8 | 279 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
275173b2 | 280 | struct tegra_sdhci_platform_data *plat = pltfm_host->priv; |
85d6509d SG |
281 | int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
282 | ||
283 | sdhci_remove_host(host, dead); | |
03d2bfc8 | 284 | |
03d2bfc8 OJ |
285 | if (gpio_is_valid(plat->wp_gpio)) { |
286 | tegra_gpio_disable(plat->wp_gpio); | |
287 | gpio_free(plat->wp_gpio); | |
288 | } | |
289 | ||
290 | if (gpio_is_valid(plat->cd_gpio)) { | |
8154b575 | 291 | free_irq(gpio_to_irq(plat->cd_gpio), host); |
03d2bfc8 OJ |
292 | tegra_gpio_disable(plat->cd_gpio); |
293 | gpio_free(plat->cd_gpio); | |
294 | } | |
295 | ||
296 | if (gpio_is_valid(plat->power_gpio)) { | |
297 | tegra_gpio_disable(plat->power_gpio); | |
298 | gpio_free(plat->power_gpio); | |
299 | } | |
300 | ||
301 | clk_disable(pltfm_host->clk); | |
302 | clk_put(pltfm_host->clk); | |
85d6509d SG |
303 | |
304 | sdhci_pltfm_free(pdev); | |
305 | ||
306 | return 0; | |
03d2bfc8 OJ |
307 | } |
308 | ||
85d6509d SG |
309 | static struct platform_driver sdhci_tegra_driver = { |
310 | .driver = { | |
311 | .name = "sdhci-tegra", | |
312 | .owner = THIS_MODULE, | |
275173b2 | 313 | .of_match_table = sdhci_tegra_dt_match, |
85d6509d SG |
314 | }, |
315 | .probe = sdhci_tegra_probe, | |
316 | .remove = __devexit_p(sdhci_tegra_remove), | |
317 | #ifdef CONFIG_PM | |
318 | .suspend = sdhci_pltfm_suspend, | |
319 | .resume = sdhci_pltfm_resume, | |
320 | #endif | |
03d2bfc8 OJ |
321 | }; |
322 | ||
85d6509d SG |
323 | static int __init sdhci_tegra_init(void) |
324 | { | |
325 | return platform_driver_register(&sdhci_tegra_driver); | |
326 | } | |
327 | module_init(sdhci_tegra_init); | |
328 | ||
329 | static void __exit sdhci_tegra_exit(void) | |
330 | { | |
331 | platform_driver_unregister(&sdhci_tegra_driver); | |
332 | } | |
333 | module_exit(sdhci_tegra_exit); | |
334 | ||
335 | MODULE_DESCRIPTION("SDHCI driver for Tegra"); | |
336 | MODULE_AUTHOR(" Google, Inc."); | |
337 | MODULE_LICENSE("GPL v2"); |