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mmc: sdhci-spear: Remove exported header
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 55static void sdhci_tuning_timer(unsigned long data);
52983382 56static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
348487cb
HC		 57static int sdhci_pre_dma_transfer(struct sdhci_host *host,
58 struct mmc_data *data,
59 struct sdhci_host_next *next);
d129bceb 60
162d6f98 61#ifdef CONFIG_PM
66fd8ad5
AH		 62static int sdhci_runtime_pm_get(struct sdhci_host *host);
63static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 64static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
65static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 66#else
67static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
68{
69 return 0;
70}
71static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
72{
73 return 0;
74}
f0710a55
AH		 75static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
76{
77}
78static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
79{
80}
66fd8ad5
AH		 81#endif
82
d129bceb
PO		 83static void sdhci_dumpregs(struct sdhci_host *host)
84{
a3c76eb9 85 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 86 mmc_hostname(host->mmc));
d129bceb 87
a3c76eb9 88 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readl(host, SDHCI_DMA_ADDRESS),
90 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readw(host, SDHCI_BLOCK_SIZE),
93 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readl(host, SDHCI_ARGUMENT),
96 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readl(host, SDHCI_PRESENT_STATE),
99 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 100 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readb(host, SDHCI_POWER_CONTROL),
102 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 104 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
105 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 107 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
108 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 109 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 110 sdhci_readl(host, SDHCI_INT_ENABLE),
111 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 112 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 113 sdhci_readw(host, SDHCI_ACMD12_ERR),
114 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 115 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 116 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 117 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 118 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 119 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 120 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 121 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 122 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 123
e57a5f61
AH		 124 if (host->flags & SDHCI_USE_ADMA) {
125 if (host->flags & SDHCI_USE_64_BIT_DMA)
126 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
127 readl(host->ioaddr + SDHCI_ADMA_ERROR),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 else
131 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
132 readl(host->ioaddr + SDHCI_ADMA_ERROR),
133 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
134 }
be3f4ae0 135
a3c76eb9 136 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 137}
138
139/*****************************************************************************\
140 * *
141 * Low level functions *
142 * *
143\*****************************************************************************/
144
7260cf5e
AV		 145static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
146{
5b4f1f6c 147 u32 present;
7260cf5e 148
c79396c1 149 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 150 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 151 return;
152
5b4f1f6c
RK		 153 if (enable) {
154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT;
d25928d1 156
5b4f1f6c
RK		 157 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
158 SDHCI_INT_CARD_INSERT;
159 } else {
160 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
161 }
b537f94c
RK		 162
163 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
164 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 165}
166
167static void sdhci_enable_card_detection(struct sdhci_host *host)
168{
169 sdhci_set_card_detection(host, true);
170}
171
172static void sdhci_disable_card_detection(struct sdhci_host *host)
173{
174 sdhci_set_card_detection(host, false);
175}
176
03231f9b 177void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 178{
e16514d8 179 unsigned long timeout;
393c1a34 180
4e4141a5 181 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 182
f0710a55 183 if (mask & SDHCI_RESET_ALL) {
d129bceb 184 host->clock = 0;
f0710a55
AH		 185 /* Reset-all turns off SD Bus Power */
186 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
187 sdhci_runtime_pm_bus_off(host);
188 }
d129bceb 189
e16514d8
PO		 190 /* Wait max 100 ms */
191 timeout = 100;
192
193 /* hw clears the bit when it's done */
4e4141a5 194 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 195 if (timeout == 0) {
a3c76eb9 196 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 197 mmc_hostname(host->mmc), (int)mask);
198 sdhci_dumpregs(host);
199 return;
200 }
201 timeout--;
202 mdelay(1);
d129bceb 203 }
03231f9b
RK		 204}
205EXPORT_SYMBOL_GPL(sdhci_reset);
206
207static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
208{
209 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
210 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
211 SDHCI_CARD_PRESENT))
212 return;
213 }
063a9dbb 214
03231f9b 215 host->ops->reset(host, mask);
393c1a34 216
da91a8f9
RK		 217 if (mask & SDHCI_RESET_ALL) {
218 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
219 if (host->ops->enable_dma)
220 host->ops->enable_dma(host);
221 }
222
223 /* Resetting the controller clears many */
224 host->preset_enabled = false;
3abc1e80 225 }
d129bceb
PO		 226}
227
2f4cbb3d
NP		 228static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
229
230static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 231{
2f4cbb3d 232 if (soft)
03231f9b 233 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 234 else
03231f9b 235 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 236
b537f94c
RK		 237 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
238 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
239 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
240 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
241 SDHCI_INT_RESPONSE;
242
243 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
244 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 245
246 if (soft) {
247 /* force clock reconfiguration */
248 host->clock = 0;
249 sdhci_set_ios(host->mmc, &host->mmc->ios);
250 }
7260cf5e 251}
d129bceb 252
7260cf5e
AV		 253static void sdhci_reinit(struct sdhci_host *host)
254{
2f4cbb3d 255 sdhci_init(host, 0);
b67c6b41
AL		 256 /*
257 * Retuning stuffs are affected by different cards inserted and only
258 * applicable to UHS-I cards. So reset these fields to their initial
259 * value when card is removed.
260 */
973905fe
AL		 261 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
262 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
263
b67c6b41
AL		 264 del_timer_sync(&host->tuning_timer);
265 host->flags &= ~SDHCI_NEEDS_RETUNING;
b67c6b41 266 }
7260cf5e 267 sdhci_enable_card_detection(host);
d129bceb
PO		 268}
269
270static void sdhci_activate_led(struct sdhci_host *host)
271{
272 u8 ctrl;
273
4e4141a5 274 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 275 ctrl |= SDHCI_CTRL_LED;
4e4141a5 276 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 277}
278
279static void sdhci_deactivate_led(struct sdhci_host *host)
280{
281 u8 ctrl;
282
4e4141a5 283 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 284 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 285 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 286}
287
f9134319 288#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 289static void sdhci_led_control(struct led_classdev *led,
290 enum led_brightness brightness)
291{
292 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
293 unsigned long flags;
294
295 spin_lock_irqsave(&host->lock, flags);
296
66fd8ad5
AH		 297 if (host->runtime_suspended)
298 goto out;
299
2f730fec
PO		 300 if (brightness == LED_OFF)
301 sdhci_deactivate_led(host);
302 else
303 sdhci_activate_led(host);
66fd8ad5 304out:
2f730fec
PO		 305 spin_unlock_irqrestore(&host->lock, flags);
306}
307#endif
308
d129bceb
PO		 309/*****************************************************************************\
310 * *
311 * Core functions *
312 * *
313\*****************************************************************************/
314
a406f5a3 315static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 316{
7659150c
PO		 317 unsigned long flags;
318 size_t blksize, len, chunk;
7244b85b 319 u32 uninitialized_var(scratch);
7659150c 320 u8 *buf;
d129bceb 321
a406f5a3 322 DBG("PIO reading\n");
d129bceb 323
a406f5a3 324 blksize = host->data->blksz;
7659150c 325 chunk = 0;
d129bceb 326
7659150c 327 local_irq_save(flags);
d129bceb 328
a406f5a3 329 while (blksize) {
7659150c
PO		 330 if (!sg_miter_next(&host->sg_miter))
331 BUG();
d129bceb 332
7659150c 333 len = min(host->sg_miter.length, blksize);
d129bceb 334
7659150c
PO		 335 blksize -= len;
336 host->sg_miter.consumed = len;
14d836e7 337
7659150c 338 buf = host->sg_miter.addr;
d129bceb 339
7659150c
PO		 340 while (len) {
341 if (chunk == 0) {
4e4141a5 342 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 343 chunk = 4;
a406f5a3 344 }
7659150c
PO		 345
346 *buf = scratch & 0xFF;
347
348 buf++;
349 scratch >>= 8;
350 chunk--;
351 len--;
d129bceb 352 }
a406f5a3 353 }
7659150c
PO		 354
355 sg_miter_stop(&host->sg_miter);
356
357 local_irq_restore(flags);
a406f5a3 358}
d129bceb 359
a406f5a3
PO		 360static void sdhci_write_block_pio(struct sdhci_host *host)
361{
7659150c
PO		 362 unsigned long flags;
363 size_t blksize, len, chunk;
364 u32 scratch;
365 u8 *buf;
d129bceb 366
a406f5a3
PO		 367 DBG("PIO writing\n");
368
369 blksize = host->data->blksz;
7659150c
PO		 370 chunk = 0;
371 scratch = 0;
d129bceb 372
7659150c 373 local_irq_save(flags);
d129bceb 374
a406f5a3 375 while (blksize) {
7659150c
PO		 376 if (!sg_miter_next(&host->sg_miter))
377 BUG();
a406f5a3 378
7659150c
PO		 379 len = min(host->sg_miter.length, blksize);
380
381 blksize -= len;
382 host->sg_miter.consumed = len;
383
384 buf = host->sg_miter.addr;
d129bceb 385
7659150c
PO		 386 while (len) {
387 scratch |= (u32)*buf << (chunk * 8);
388
389 buf++;
390 chunk++;
391 len--;
392
393 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 394 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 395 chunk = 0;
396 scratch = 0;
d129bceb 397 }
d129bceb
PO		 398 }
399 }
7659150c
PO		 400
401 sg_miter_stop(&host->sg_miter);
402
403 local_irq_restore(flags);
a406f5a3
PO		 404}
405
406static void sdhci_transfer_pio(struct sdhci_host *host)
407{
408 u32 mask;
409
410 BUG_ON(!host->data);
411
7659150c 412 if (host->blocks == 0)
a406f5a3
PO		 413 return;
414
415 if (host->data->flags & MMC_DATA_READ)
416 mask = SDHCI_DATA_AVAILABLE;
417 else
418 mask = SDHCI_SPACE_AVAILABLE;
419
4a3cba32
PO		 420 /*
421 * Some controllers (JMicron JMB38x) mess up the buffer bits
422 * for transfers < 4 bytes. As long as it is just one block,
423 * we can ignore the bits.
424 */
425 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
426 (host->data->blocks == 1))
427 mask = ~0;
428
4e4141a5 429 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 430 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
431 udelay(100);
432
a406f5a3
PO		 433 if (host->data->flags & MMC_DATA_READ)
434 sdhci_read_block_pio(host);
435 else
436 sdhci_write_block_pio(host);
d129bceb 437
7659150c
PO		 438 host->blocks--;
439 if (host->blocks == 0)
a406f5a3 440 break;
a406f5a3 441 }
d129bceb 442
a406f5a3 443 DBG("PIO transfer complete.\n");
d129bceb
PO		 444}
445
2134a922
PO		 446static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
447{
448 local_irq_save(*flags);
482fce99 449 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 450}
451
452static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
453{
482fce99 454 kunmap_atomic(buffer);
2134a922
PO		 455 local_irq_restore(*flags);
456}
457
e57a5f61
AH		 458static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
459 dma_addr_t addr, int len, unsigned cmd)
118cd17d 460{
e57a5f61 461 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 462
e57a5f61 463 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 464 dma_desc->cmd = cpu_to_le16(cmd);
465 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 466 dma_desc->addr_lo = cpu_to_le32((u32)addr);
467
468 if (host->flags & SDHCI_USE_64_BIT_DMA)
469 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 470}
471
b5ffa674
AH		 472static void sdhci_adma_mark_end(void *desc)
473{
e57a5f61 474 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 475
e57a5f61 476 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 477 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 478}
479
8f1934ce 480static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 481 struct mmc_data *data)
482{
483 int direction;
484
1c3d5f6d
AH		 485 void *desc;
486 void *align;
2134a922
PO		 487 dma_addr_t addr;
488 dma_addr_t align_addr;
489 int len, offset;
490
491 struct scatterlist *sg;
492 int i;
493 char *buffer;
494 unsigned long flags;
495
496 /*
497 * The spec does not specify endianness of descriptor table.
498 * We currently guess that it is LE.
499 */
500
501 if (data->flags & MMC_DATA_READ)
502 direction = DMA_FROM_DEVICE;
503 else
504 direction = DMA_TO_DEVICE;
505
2134a922 506 host->align_addr = dma_map_single(mmc_dev(host->mmc),
76fe379a 507 host->align_buffer, host->align_buffer_sz, direction);
8d8bb39b 508 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 509 goto fail;
76fe379a 510 BUG_ON(host->align_addr & host->align_mask);
2134a922 511
348487cb
HC		 512 host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
513 if (host->sg_count < 0)
8f1934ce 514 goto unmap_align;
2134a922 515
4efaa6fb 516 desc = host->adma_table;
2134a922
PO		 517 align = host->align_buffer;
518
519 align_addr = host->align_addr;
520
521 for_each_sg(data->sg, sg, host->sg_count, i) {
522 addr = sg_dma_address(sg);
523 len = sg_dma_len(sg);
524
525 /*
526 * The SDHCI specification states that ADMA
527 * addresses must be 32-bit aligned. If they
528 * aren't, then we use a bounce buffer for
529 * the (up to three) bytes that screw up the
530 * alignment.
531 */
76fe379a
AH		 532 offset = (host->align_sz - (addr & host->align_mask)) &
533 host->align_mask;
2134a922
PO		 534 if (offset) {
535 if (data->flags & MMC_DATA_WRITE) {
536 buffer = sdhci_kmap_atomic(sg, &flags);
537 memcpy(align, buffer, offset);
538 sdhci_kunmap_atomic(buffer, &flags);
539 }
540
118cd17d 541 /* tran, valid */
e57a5f61 542 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 543 ADMA2_TRAN_VALID);
2134a922
PO		 544
545 BUG_ON(offset > 65536);
546
76fe379a
AH		 547 align += host->align_sz;
548 align_addr += host->align_sz;
2134a922 549
76fe379a 550 desc += host->desc_sz;
2134a922
PO		 551
552 addr += offset;
553 len -= offset;
554 }
555
2134a922
PO		 556 BUG_ON(len > 65536);
557
118cd17d 558 /* tran, valid */
e57a5f61 559 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
76fe379a 560 desc += host->desc_sz;
2134a922
PO		 561
562 /*
563 * If this triggers then we have a calculation bug
564 * somewhere. :/
565 */
76fe379a 566 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 567 }
568
70764a90
TA		 569 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
570 /*
571 * Mark the last descriptor as the terminating descriptor
572 */
4efaa6fb 573 if (desc != host->adma_table) {
76fe379a 574 desc -= host->desc_sz;
b5ffa674 575 sdhci_adma_mark_end(desc);
70764a90
TA		 576 }
577 } else {
578 /*
579 * Add a terminating entry.
580 */
2134a922 581
70764a90 582 /* nop, end, valid */
e57a5f61 583 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 584 }
2134a922
PO		 585
586 /*
587 * Resync align buffer as we might have changed it.
588 */
589 if (data->flags & MMC_DATA_WRITE) {
590 dma_sync_single_for_device(mmc_dev(host->mmc),
76fe379a 591 host->align_addr, host->align_buffer_sz, direction);
2134a922
PO		 592 }
593
8f1934ce
PO		 594 return 0;
595
8f1934ce
PO		 596unmap_align:
597 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 598 host->align_buffer_sz, direction);
8f1934ce
PO		 599fail:
600 return -EINVAL;
2134a922
PO		 601}
602
603static void sdhci_adma_table_post(struct sdhci_host *host,
604 struct mmc_data *data)
605{
606 int direction;
607
608 struct scatterlist *sg;
609 int i, size;
1c3d5f6d 610 void *align;
2134a922
PO		 611 char *buffer;
612 unsigned long flags;
de0b65a7 613 bool has_unaligned;
2134a922
PO		 614
615 if (data->flags & MMC_DATA_READ)
616 direction = DMA_FROM_DEVICE;
617 else
618 direction = DMA_TO_DEVICE;
619
2134a922 620 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 621 host->align_buffer_sz, direction);
2134a922 622
de0b65a7
RK		 623 /* Do a quick scan of the SG list for any unaligned mappings */
624 has_unaligned = false;
625 for_each_sg(data->sg, sg, host->sg_count, i)
76fe379a 626 if (sg_dma_address(sg) & host->align_mask) {
de0b65a7
RK		 627 has_unaligned = true;
628 break;
629 }
630
631 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 632 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
633 data->sg_len, direction);
634
635 align = host->align_buffer;
636
637 for_each_sg(data->sg, sg, host->sg_count, i) {
76fe379a
AH		 638 if (sg_dma_address(sg) & host->align_mask) {
639 size = host->align_sz -
640 (sg_dma_address(sg) & host->align_mask);
2134a922
PO		 641
642 buffer = sdhci_kmap_atomic(sg, &flags);
643 memcpy(buffer, align, size);
644 sdhci_kunmap_atomic(buffer, &flags);
645
76fe379a 646 align += host->align_sz;
2134a922
PO		 647 }
648 }
649 }
650
348487cb
HC		 651 if (!data->host_cookie)
652 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
653 data->sg_len, direction);
2134a922
PO		 654}
655
a3c7778f 656static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 657{
1c8cde92 658 u8 count;
a3c7778f 659 struct mmc_data *data = cmd->data;
1c8cde92 660 unsigned target_timeout, current_timeout;
d129bceb 661
ee53ab5d
PO		 662 /*
663 * If the host controller provides us with an incorrect timeout
664 * value, just skip the check and use 0xE. The hardware may take
665 * longer to time out, but that's much better than having a too-short
666 * timeout value.
667 */
11a2f1b7 668 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 669 return 0xE;
e538fbe8 670
a3c7778f 671 /* Unspecified timeout, assume max */
1d4d7744 672 if (!data && !cmd->busy_timeout)
a3c7778f 673 return 0xE;
d129bceb 674
a3c7778f
AW		 675 /* timeout in us */
676 if (!data)
1d4d7744 677 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 678 else {
679 target_timeout = data->timeout_ns / 1000;
680 if (host->clock)
681 target_timeout += data->timeout_clks / host->clock;
682 }
81b39802 683
1c8cde92
PO		 684 /*
685 * Figure out needed cycles.
686 * We do this in steps in order to fit inside a 32 bit int.
687 * The first step is the minimum timeout, which will have a
688 * minimum resolution of 6 bits:
689 * (1) 2^13*1000 > 2^22,
690 * (2) host->timeout_clk < 2^16
691 * =>
692 * (1) / (2) > 2^6
693 */
694 count = 0;
695 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
696 while (current_timeout < target_timeout) {
697 count++;
698 current_timeout <<= 1;
699 if (count >= 0xF)
700 break;
701 }
702
703 if (count >= 0xF) {
09eeff52
CB		 704 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
705 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 706 count = 0xE;
707 }
708
ee53ab5d
PO		 709 return count;
710}
711
6aa943ab
AV		 712static void sdhci_set_transfer_irqs(struct sdhci_host *host)
713{
714 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
715 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
716
717 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 718 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 719 else
b537f94c
RK		 720 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
721
722 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
723 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 724}
725
b45e668a 726static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 727{
728 u8 count;
b45e668a
AD		 729
730 if (host->ops->set_timeout) {
731 host->ops->set_timeout(host, cmd);
732 } else {
733 count = sdhci_calc_timeout(host, cmd);
734 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
735 }
736}
737
738static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
739{
2134a922 740 u8 ctrl;
a3c7778f 741 struct mmc_data *data = cmd->data;
8f1934ce 742 int ret;
ee53ab5d
PO		 743
744 WARN_ON(host->data);
745
b45e668a
AD		 746 if (data || (cmd->flags & MMC_RSP_BUSY))
747 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 748
749 if (!data)
ee53ab5d
PO		 750 return;
751
752 /* Sanity checks */
753 BUG_ON(data->blksz * data->blocks > 524288);
754 BUG_ON(data->blksz > host->mmc->max_blk_size);
755 BUG_ON(data->blocks > 65535);
756
757 host->data = data;
758 host->data_early = 0;
f6a03cbf 759 host->data->bytes_xfered = 0;
ee53ab5d 760
a13abc7b 761 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 762 host->flags |= SDHCI_REQ_USE_DMA;
763
2134a922
PO		 764 /*
765 * FIXME: This doesn't account for merging when mapping the
766 * scatterlist.
767 */
768 if (host->flags & SDHCI_REQ_USE_DMA) {
769 int broken, i;
770 struct scatterlist *sg;
771
772 broken = 0;
773 if (host->flags & SDHCI_USE_ADMA) {
774 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
775 broken = 1;
776 } else {
777 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
778 broken = 1;
779 }
780
781 if (unlikely(broken)) {
782 for_each_sg(data->sg, sg, data->sg_len, i) {
783 if (sg->length & 0x3) {
784 DBG("Reverting to PIO because of "
785 "transfer size (%d)\n",
786 sg->length);
787 host->flags &= ~SDHCI_REQ_USE_DMA;
788 break;
789 }
790 }
791 }
c9fddbc4
PO		 792 }
793
794 /*
795 * The assumption here being that alignment is the same after
796 * translation to device address space.
797 */
2134a922
PO		 798 if (host->flags & SDHCI_REQ_USE_DMA) {
799 int broken, i;
800 struct scatterlist *sg;
801
802 broken = 0;
803 if (host->flags & SDHCI_USE_ADMA) {
804 /*
805 * As we use 3 byte chunks to work around
806 * alignment problems, we need to check this
807 * quirk.
808 */
809 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
810 broken = 1;
811 } else {
812 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
813 broken = 1;
814 }
815
816 if (unlikely(broken)) {
817 for_each_sg(data->sg, sg, data->sg_len, i) {
818 if (sg->offset & 0x3) {
819 DBG("Reverting to PIO because of "
820 "bad alignment\n");
821 host->flags &= ~SDHCI_REQ_USE_DMA;
822 break;
823 }
824 }
825 }
826 }
827
8f1934ce
PO		 828 if (host->flags & SDHCI_REQ_USE_DMA) {
829 if (host->flags & SDHCI_USE_ADMA) {
830 ret = sdhci_adma_table_pre(host, data);
831 if (ret) {
832 /*
833 * This only happens when someone fed
834 * us an invalid request.
835 */
836 WARN_ON(1);
ebd6d357 837 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 838 } else {
4e4141a5
AV		 839 sdhci_writel(host, host->adma_addr,
840 SDHCI_ADMA_ADDRESS);
e57a5f61
AH		 841 if (host->flags & SDHCI_USE_64_BIT_DMA)
842 sdhci_writel(host,
843 (u64)host->adma_addr >> 32,
844 SDHCI_ADMA_ADDRESS_HI);
8f1934ce
PO		 845 }
846 } else {
c8b3e02e 847 int sg_cnt;
8f1934ce 848
348487cb 849 sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
c8b3e02e 850 if (sg_cnt == 0) {
8f1934ce
PO		 851 /*
852 * This only happens when someone fed
853 * us an invalid request.
854 */
855 WARN_ON(1);
ebd6d357 856 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 857 } else {
719a61b4 858 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 859 sdhci_writel(host, sg_dma_address(data->sg),
860 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 861 }
862 }
863 }
864
2134a922
PO		 865 /*
866 * Always adjust the DMA selection as some controllers
867 * (e.g. JMicron) can't do PIO properly when the selection
868 * is ADMA.
869 */
870 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 871 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 872 ctrl &= ~SDHCI_CTRL_DMA_MASK;
873 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 874 (host->flags & SDHCI_USE_ADMA)) {
875 if (host->flags & SDHCI_USE_64_BIT_DMA)
876 ctrl |= SDHCI_CTRL_ADMA64;
877 else
878 ctrl |= SDHCI_CTRL_ADMA32;
879 } else {
2134a922 880 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 881 }
4e4141a5 882 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 883 }
884
8f1934ce 885 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 886 int flags;
887
888 flags = SG_MITER_ATOMIC;
889 if (host->data->flags & MMC_DATA_READ)
890 flags |= SG_MITER_TO_SG;
891 else
892 flags |= SG_MITER_FROM_SG;
893 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 894 host->blocks = data->blocks;
d129bceb 895 }
c7fa9963 896
6aa943ab
AV		 897 sdhci_set_transfer_irqs(host);
898
f6a03cbf
MV		 899 /* Set the DMA boundary value and block size */
900 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
901 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 902 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 903}
904
905static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 906 struct mmc_command *cmd)
c7fa9963 907{
d3fc5d71 908 u16 mode = 0;
e89d456f 909 struct mmc_data *data = cmd->data;
c7fa9963 910
2b558c13 911 if (data == NULL) {
9b8ffea6
VW		 912 if (host->quirks2 &
913 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
914 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
915 } else {
2b558c13 916 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 917 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
918 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 919 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 920 }
c7fa9963 921 return;
2b558c13 922 }
c7fa9963 923
e538fbe8
PO		 924 WARN_ON(!host->data);
925
d3fc5d71
VY		 926 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
927 mode = SDHCI_TRNS_BLK_CNT_EN;
928
e89d456f 929 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 930 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 931 /*
932 * If we are sending CMD23, CMD12 never gets sent
933 * on successful completion (so no Auto-CMD12).
934 */
85cc1c33
CD		 935 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
936 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 937 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 938 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
939 mode |= SDHCI_TRNS_AUTO_CMD23;
940 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
941 }
c4512f79 942 }
8edf6371 943
c7fa9963
PO		 944 if (data->flags & MMC_DATA_READ)
945 mode |= SDHCI_TRNS_READ;
c9fddbc4 946 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 947 mode |= SDHCI_TRNS_DMA;
948
4e4141a5 949 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 950}
951
952static void sdhci_finish_data(struct sdhci_host *host)
953{
954 struct mmc_data *data;
d129bceb
PO		 955
956 BUG_ON(!host->data);
957
958 data = host->data;
959 host->data = NULL;
960
c9fddbc4 961 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 962 if (host->flags & SDHCI_USE_ADMA)
963 sdhci_adma_table_post(host, data);
964 else {
348487cb
HC		 965 if (!data->host_cookie)
966 dma_unmap_sg(mmc_dev(host->mmc),
967 data->sg, data->sg_len,
968 (data->flags & MMC_DATA_READ) ?
2134a922
PO		 969 DMA_FROM_DEVICE : DMA_TO_DEVICE);
970 }
d129bceb
PO		 971 }
972
973 /*
c9b74c5b
PO		 974 * The specification states that the block count register must
975 * be updated, but it does not specify at what point in the
976 * data flow. That makes the register entirely useless to read
977 * back so we have to assume that nothing made it to the card
978 * in the event of an error.
d129bceb 979 */
c9b74c5b
PO		 980 if (data->error)
981 data->bytes_xfered = 0;
d129bceb 982 else
c9b74c5b 983 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 984
e89d456f
AW		 985 /*
986 * Need to send CMD12 if -
987 * a) open-ended multiblock transfer (no CMD23)
988 * b) error in multiblock transfer
989 */
990 if (data->stop &&
991 (data->error ||
992 !host->mrq->sbc)) {
993
d129bceb
PO		 994 /*
995 * The controller needs a reset of internal state machines
996 * upon error conditions.
997 */
17b0429d 998 if (data->error) {
03231f9b
RK		 999 sdhci_do_reset(host, SDHCI_RESET_CMD);
1000 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 1001 }
1002
1003 sdhci_send_command(host, data->stop);
1004 } else
1005 tasklet_schedule(&host->finish_tasklet);
1006}
1007
c0e55129 1008void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1009{
1010 int flags;
fd2208d7 1011 u32 mask;
7cb2c76f 1012 unsigned long timeout;
d129bceb
PO		 1013
1014 WARN_ON(host->cmd);
1015
d129bceb 1016 /* Wait max 10 ms */
7cb2c76f 1017 timeout = 10;
fd2208d7
PO		 1018
1019 mask = SDHCI_CMD_INHIBIT;
1020 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1021 mask |= SDHCI_DATA_INHIBIT;
1022
1023 /* We shouldn't wait for data inihibit for stop commands, even
1024 though they might use busy signaling */
1025 if (host->mrq->data && (cmd == host->mrq->data->stop))
1026 mask &= ~SDHCI_DATA_INHIBIT;
1027
4e4141a5 1028 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1029 if (timeout == 0) {
a3c76eb9 1030 pr_err("%s: Controller never released "
acf1da45 1031 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1032 sdhci_dumpregs(host);
17b0429d 1033 cmd->error = -EIO;
d129bceb
PO		 1034 tasklet_schedule(&host->finish_tasklet);
1035 return;
1036 }
7cb2c76f
PO		 1037 timeout--;
1038 mdelay(1);
1039 }
d129bceb 1040
3e1a6892 1041 timeout = jiffies;
1d4d7744
UH		 1042 if (!cmd->data && cmd->busy_timeout > 9000)
1043 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1044 else
1045 timeout += 10 * HZ;
1046 mod_timer(&host->timer, timeout);
d129bceb
PO		 1047
1048 host->cmd = cmd;
e99783a4 1049 host->busy_handle = 0;
d129bceb 1050
a3c7778f 1051 sdhci_prepare_data(host, cmd);
d129bceb 1052
4e4141a5 1053 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1054
e89d456f 1055 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1056
d129bceb 1057 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1058 pr_err("%s: Unsupported response type!\n",
d129bceb 1059 mmc_hostname(host->mmc));
17b0429d 1060 cmd->error = -EINVAL;
d129bceb
PO		 1061 tasklet_schedule(&host->finish_tasklet);
1062 return;
1063 }
1064
1065 if (!(cmd->flags & MMC_RSP_PRESENT))
1066 flags = SDHCI_CMD_RESP_NONE;
1067 else if (cmd->flags & MMC_RSP_136)
1068 flags = SDHCI_CMD_RESP_LONG;
1069 else if (cmd->flags & MMC_RSP_BUSY)
1070 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1071 else
1072 flags = SDHCI_CMD_RESP_SHORT;
1073
1074 if (cmd->flags & MMC_RSP_CRC)
1075 flags |= SDHCI_CMD_CRC;
1076 if (cmd->flags & MMC_RSP_OPCODE)
1077 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1078
1079 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1080 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1081 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1082 flags |= SDHCI_CMD_DATA;
1083
4e4141a5 1084 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1085}
c0e55129 1086EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1087
1088static void sdhci_finish_command(struct sdhci_host *host)
1089{
1090 int i;
1091
1092 BUG_ON(host->cmd == NULL);
1093
1094 if (host->cmd->flags & MMC_RSP_PRESENT) {
1095 if (host->cmd->flags & MMC_RSP_136) {
1096 /* CRC is stripped so we need to do some shifting. */
1097 for (i = 0;i < 4;i++) {
4e4141a5 1098 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1099 SDHCI_RESPONSE + (3-i)*4) << 8;
1100 if (i != 3)
1101 host->cmd->resp[i] |=
4e4141a5 1102 sdhci_readb(host,
d129bceb
PO		 1103 SDHCI_RESPONSE + (3-i)*4-1);
1104 }
1105 } else {
4e4141a5 1106 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1107 }
1108 }
1109
17b0429d 1110 host->cmd->error = 0;
d129bceb 1111
e89d456f
AW		 1112 /* Finished CMD23, now send actual command. */
1113 if (host->cmd == host->mrq->sbc) {
1114 host->cmd = NULL;
1115 sdhci_send_command(host, host->mrq->cmd);
1116 } else {
e538fbe8 1117
e89d456f
AW		 1118 /* Processed actual command. */
1119 if (host->data && host->data_early)
1120 sdhci_finish_data(host);
d129bceb 1121
e89d456f
AW		 1122 if (!host->cmd->data)
1123 tasklet_schedule(&host->finish_tasklet);
1124
1125 host->cmd = NULL;
1126 }
d129bceb
PO		 1127}
1128
52983382
KL		 1129static u16 sdhci_get_preset_value(struct sdhci_host *host)
1130{
d975f121 1131 u16 preset = 0;
52983382 1132
d975f121
RK		 1133 switch (host->timing) {
1134 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1135 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1136 break;
d975f121 1137 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1138 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1139 break;
d975f121 1140 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1141 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1142 break;
d975f121
RK		 1143 case MMC_TIMING_UHS_SDR104:
1144 case MMC_TIMING_MMC_HS200:
52983382
KL		 1145 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1146 break;
d975f121 1147 case MMC_TIMING_UHS_DDR50:
52983382
KL		 1148 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1149 break;
e9fb05d5
AH		 1150 case MMC_TIMING_MMC_HS400:
1151 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1152 break;
52983382
KL		 1153 default:
1154 pr_warn("%s: Invalid UHS-I mode selected\n",
1155 mmc_hostname(host->mmc));
1156 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1157 break;
1158 }
1159 return preset;
1160}
1161
1771059c 1162void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1163{
c3ed3877 1164 int div = 0; /* Initialized for compiler warning */
df16219f 1165 int real_div = div, clk_mul = 1;
c3ed3877 1166 u16 clk = 0;
7cb2c76f 1167 unsigned long timeout;
d129bceb 1168
1650d0c7
RK		 1169 host->mmc->actual_clock = 0;
1170
4e4141a5 1171 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1172
1173 if (clock == 0)
373073ef 1174 return;
d129bceb 1175
85105c53 1176 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1177 if (host->preset_enabled) {
52983382
KL		 1178 u16 pre_val;
1179
1180 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1181 pre_val = sdhci_get_preset_value(host);
1182 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1183 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1184 if (host->clk_mul &&
1185 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1186 clk = SDHCI_PROG_CLOCK_MODE;
1187 real_div = div + 1;
1188 clk_mul = host->clk_mul;
1189 } else {
1190 real_div = max_t(int, 1, div << 1);
1191 }
1192 goto clock_set;
1193 }
1194
c3ed3877
AN		 1195 /*
1196 * Check if the Host Controller supports Programmable Clock
1197 * Mode.
1198 */
1199 if (host->clk_mul) {
52983382
KL		 1200 for (div = 1; div <= 1024; div++) {
1201 if ((host->max_clk * host->clk_mul / div)
1202 <= clock)
1203 break;
1204 }
c3ed3877 1205 /*
52983382
KL		 1206 * Set Programmable Clock Mode in the Clock
1207 * Control register.
c3ed3877 1208 */
52983382
KL		 1209 clk = SDHCI_PROG_CLOCK_MODE;
1210 real_div = div;
1211 clk_mul = host->clk_mul;
1212 div--;
c3ed3877
AN		 1213 } else {
1214 /* Version 3.00 divisors must be a multiple of 2. */
1215 if (host->max_clk <= clock)
1216 div = 1;
1217 else {
1218 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1219 div += 2) {
1220 if ((host->max_clk / div) <= clock)
1221 break;
1222 }
85105c53 1223 }
df16219f 1224 real_div = div;
c3ed3877 1225 div >>= 1;
85105c53
ZG		 1226 }
1227 } else {
1228 /* Version 2.00 divisors must be a power of 2. */
0397526d 1229 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1230 if ((host->max_clk / div) <= clock)
1231 break;
1232 }
df16219f 1233 real_div = div;
c3ed3877 1234 div >>= 1;
d129bceb 1235 }
d129bceb 1236
52983382 1237clock_set:
03d6f5ff 1238 if (real_div)
df16219f 1239 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1240 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1241 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1242 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1243 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1244 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1245
27f6cb16
CB		 1246 /* Wait max 20 ms */
1247 timeout = 20;
4e4141a5 1248 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1249 & SDHCI_CLOCK_INT_STABLE)) {
1250 if (timeout == 0) {
a3c76eb9 1251 pr_err("%s: Internal clock never "
acf1da45 1252 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1253 sdhci_dumpregs(host);
1254 return;
1255 }
7cb2c76f
PO		 1256 timeout--;
1257 mdelay(1);
1258 }
d129bceb
PO		 1259
1260 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1261 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1262}
1771059c 1263EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1264
24fbb3ca
RK		 1265static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1266 unsigned short vdd)
146ad66e 1267{
3a48edc4 1268 struct mmc_host *mmc = host->mmc;
8364248a 1269 u8 pwr = 0;
146ad66e 1270
52221610
TK		 1271 if (!IS_ERR(mmc->supply.vmmc)) {
1272 spin_unlock_irq(&host->lock);
4e743f1f 1273 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
52221610 1274 spin_lock_irq(&host->lock);
3cbc6123
TK		 1275
1276 if (mode != MMC_POWER_OFF)
1277 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1278 else
1279 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1280
52221610
TK		 1281 return;
1282 }
1283
24fbb3ca
RK		 1284 if (mode != MMC_POWER_OFF) {
1285 switch (1 << vdd) {
ae628903
PO		 1286 case MMC_VDD_165_195:
1287 pwr = SDHCI_POWER_180;
1288 break;
1289 case MMC_VDD_29_30:
1290 case MMC_VDD_30_31:
1291 pwr = SDHCI_POWER_300;
1292 break;
1293 case MMC_VDD_32_33:
1294 case MMC_VDD_33_34:
1295 pwr = SDHCI_POWER_330;
1296 break;
1297 default:
1298 BUG();
1299 }
1300 }
1301
1302 if (host->pwr == pwr)
e921a8b6 1303 return;
146ad66e 1304
ae628903
PO		 1305 host->pwr = pwr;
1306
1307 if (pwr == 0) {
4e4141a5 1308 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1309 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1310 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1311 vdd = 0;
e921a8b6
RK		 1312 } else {
1313 /*
1314 * Spec says that we should clear the power reg before setting
1315 * a new value. Some controllers don't seem to like this though.
1316 */
1317 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1318 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1319
e921a8b6
RK		 1320 /*
1321 * At least the Marvell CaFe chip gets confused if we set the
1322 * voltage and set turn on power at the same time, so set the
1323 * voltage first.
1324 */
1325 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1326 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1327
e921a8b6 1328 pwr |= SDHCI_POWER_ON;
146ad66e 1329
e921a8b6 1330 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1331
e921a8b6
RK		 1332 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1333 sdhci_runtime_pm_bus_on(host);
f0710a55 1334
e921a8b6
RK		 1335 /*
1336 * Some controllers need an extra 10ms delay of 10ms before
1337 * they can apply clock after applying power
1338 */
1339 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1340 mdelay(10);
1341 }
146ad66e
PO		 1342}
1343
d129bceb
PO		 1344/*****************************************************************************\
1345 * *
1346 * MMC callbacks *
1347 * *
1348\*****************************************************************************/
1349
1350static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1351{
1352 struct sdhci_host *host;
505a8680 1353 int present;
d129bceb 1354 unsigned long flags;
473b095a 1355 u32 tuning_opcode;
d129bceb
PO		 1356
1357 host = mmc_priv(mmc);
1358
66fd8ad5
AH		 1359 sdhci_runtime_pm_get(host);
1360
2836766a
KK		 1361 present = mmc_gpio_get_cd(host->mmc);
1362
d129bceb
PO		 1363 spin_lock_irqsave(&host->lock, flags);
1364
1365 WARN_ON(host->mrq != NULL);
1366
f9134319 1367#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1368 sdhci_activate_led(host);
2f730fec 1369#endif
e89d456f
AW		 1370
1371 /*
1372 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1373 * requests if Auto-CMD12 is enabled.
1374 */
1375 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1376 if (mrq->stop) {
1377 mrq->data->stop = NULL;
1378 mrq->stop = NULL;
1379 }
1380 }
d129bceb
PO		 1381
1382 host->mrq = mrq;
1383
505a8680
SG		 1384 /*
1385 * Firstly check card presence from cd-gpio. The return could
1386 * be one of the following possibilities:
1387 * negative: cd-gpio is not available
1388 * zero: cd-gpio is used, and card is removed
1389 * one: cd-gpio is used, and card is present
1390 */
505a8680
SG		 1391 if (present < 0) {
1392 /* If polling, assume that the card is always present. */
1393 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1394 present = 1;
1395 else
1396 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1397 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1398 }
1399
68d1fb7e 1400 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1401 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1402 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1403 } else {
1404 u32 present_state;
1405
1406 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1407 /*
1408 * Check if the re-tuning timer has already expired and there
7756a96d
YS		 1409 * is no on-going data transfer and DAT0 is not busy. If so,
1410 * we need to execute tuning procedure before sending command.
cf2b5eea
AN		 1411 */
1412 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
7756a96d
YS		 1413 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1414 (present_state & SDHCI_DATA_0_LVL_MASK)) {
14efd957
CB		 1415 if (mmc->card) {
1416 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1417 tuning_opcode =
1418 mmc->card->type == MMC_TYPE_MMC ?
1419 MMC_SEND_TUNING_BLOCK_HS200 :
1420 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1421
1422 /* Here we need to set the host->mrq to NULL,
1423 * in case the pending finish_tasklet
1424 * finishes it incorrectly.
1425 */
1426 host->mrq = NULL;
1427
14efd957
CB		 1428 spin_unlock_irqrestore(&host->lock, flags);
1429 sdhci_execute_tuning(mmc, tuning_opcode);
1430 spin_lock_irqsave(&host->lock, flags);
1431
1432 /* Restore original mmc_request structure */
1433 host->mrq = mrq;
1434 }
cf2b5eea
AN		 1435 }
1436
8edf6371 1437 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1438 sdhci_send_command(host, mrq->sbc);
1439 else
1440 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1441 }
d129bceb 1442
5f25a66f 1443 mmiowb();
d129bceb
PO		 1444 spin_unlock_irqrestore(&host->lock, flags);
1445}
1446
2317f56c
RK		 1447void sdhci_set_bus_width(struct sdhci_host *host, int width)
1448{
1449 u8 ctrl;
1450
1451 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1452 if (width == MMC_BUS_WIDTH_8) {
1453 ctrl &= ~SDHCI_CTRL_4BITBUS;
1454 if (host->version >= SDHCI_SPEC_300)
1455 ctrl |= SDHCI_CTRL_8BITBUS;
1456 } else {
1457 if (host->version >= SDHCI_SPEC_300)
1458 ctrl &= ~SDHCI_CTRL_8BITBUS;
1459 if (width == MMC_BUS_WIDTH_4)
1460 ctrl |= SDHCI_CTRL_4BITBUS;
1461 else
1462 ctrl &= ~SDHCI_CTRL_4BITBUS;
1463 }
1464 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1465}
1466EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1467
96d7b78c
RK		 1468void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1469{
1470 u16 ctrl_2;
1471
1472 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1473 /* Select Bus Speed Mode for host */
1474 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1475 if ((timing == MMC_TIMING_MMC_HS200) ||
1476 (timing == MMC_TIMING_UHS_SDR104))
1477 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1478 else if (timing == MMC_TIMING_UHS_SDR12)
1479 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1480 else if (timing == MMC_TIMING_UHS_SDR25)
1481 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1482 else if (timing == MMC_TIMING_UHS_SDR50)
1483 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1484 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1485 (timing == MMC_TIMING_MMC_DDR52))
1486 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1487 else if (timing == MMC_TIMING_MMC_HS400)
1488 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1489 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1490}
1491EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1492
66fd8ad5 1493static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1494{
d129bceb
PO		 1495 unsigned long flags;
1496 u8 ctrl;
3a48edc4 1497 struct mmc_host *mmc = host->mmc;
d129bceb 1498
d129bceb
PO		 1499 spin_lock_irqsave(&host->lock, flags);
1500
ceb6143b
AH		 1501 if (host->flags & SDHCI_DEVICE_DEAD) {
1502 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1503 if (!IS_ERR(mmc->supply.vmmc) &&
1504 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1505 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1506 return;
1507 }
1e72859e 1508
d129bceb
PO		 1509 /*
1510 * Reset the chip on each power off.
1511 * Should clear out any weird states.
1512 */
1513 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1514 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1515 sdhci_reinit(host);
d129bceb
PO		 1516 }
1517
52983382 1518 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1519 (ios->power_mode == MMC_POWER_UP) &&
1520 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1521 sdhci_enable_preset_value(host, false);
1522
373073ef 1523 if (!ios->clock || ios->clock != host->clock) {
1771059c 1524 host->ops->set_clock(host, ios->clock);
373073ef 1525 host->clock = ios->clock;
03d6f5ff
AD		 1526
1527 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1528 host->clock) {
1529 host->timeout_clk = host->mmc->actual_clock ?
1530 host->mmc->actual_clock / 1000 :
1531 host->clock / 1000;
1532 host->mmc->max_busy_timeout =
1533 host->ops->get_max_timeout_count ?
1534 host->ops->get_max_timeout_count(host) :
1535 1 << 27;
1536 host->mmc->max_busy_timeout /= host->timeout_clk;
1537 }
373073ef 1538 }
d129bceb 1539
24fbb3ca 1540 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1541
643a81ff
PR		 1542 if (host->ops->platform_send_init_74_clocks)
1543 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1544
2317f56c 1545 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1546
15ec4461 1547 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1548
3ab9c8da
PR		 1549 if ((ios->timing == MMC_TIMING_SD_HS ||
1550 ios->timing == MMC_TIMING_MMC_HS)
1551 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1552 ctrl |= SDHCI_CTRL_HISPD;
1553 else
1554 ctrl &= ~SDHCI_CTRL_HISPD;
1555
d6d50a15 1556 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1557 u16 clk, ctrl_2;
49c468fc
AN		 1558
1559 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1560 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1561 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1562 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1563 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1564 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1565 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1566 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1567 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1568
da91a8f9 1569 if (!host->preset_enabled) {
758535c4 1570 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1571 /*
1572 * We only need to set Driver Strength if the
1573 * preset value enable is not set.
1574 */
da91a8f9 1575 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1576 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1577 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1578 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1579 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1580 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1581
1582 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1583 } else {
1584 /*
1585 * According to SDHC Spec v3.00, if the Preset Value
1586 * Enable in the Host Control 2 register is set, we
1587 * need to reset SD Clock Enable before changing High
1588 * Speed Enable to avoid generating clock gliches.
1589 */
758535c4
AN		 1590
1591 /* Reset SD Clock Enable */
1592 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1593 clk &= ~SDHCI_CLOCK_CARD_EN;
1594 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1595
1596 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1597
1598 /* Re-enable SD Clock */
1771059c 1599 host->ops->set_clock(host, host->clock);
d6d50a15 1600 }
49c468fc 1601
49c468fc
AN		 1602 /* Reset SD Clock Enable */
1603 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1604 clk &= ~SDHCI_CLOCK_CARD_EN;
1605 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1606
96d7b78c 1607 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1608 host->timing = ios->timing;
49c468fc 1609
52983382
KL		 1610 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1611 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1612 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1613 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1614 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1615 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1616 u16 preset;
1617
1618 sdhci_enable_preset_value(host, true);
1619 preset = sdhci_get_preset_value(host);
1620 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1621 >> SDHCI_PRESET_DRV_SHIFT;
1622 }
1623
49c468fc 1624 /* Re-enable SD Clock */
1771059c 1625 host->ops->set_clock(host, host->clock);
758535c4
AN		 1626 } else
1627 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1628
b8352260
LD		 1629 /*
1630 * Some (ENE) controllers go apeshit on some ios operation,
1631 * signalling timeout and CRC errors even on CMD0. Resetting
1632 * it on each ios seems to solve the problem.
1633 */
c63705e1 1634 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1635 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1636
5f25a66f 1637 mmiowb();
d129bceb
PO		 1638 spin_unlock_irqrestore(&host->lock, flags);
1639}
1640
66fd8ad5
AH		 1641static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1642{
1643 struct sdhci_host *host = mmc_priv(mmc);
1644
1645 sdhci_runtime_pm_get(host);
1646 sdhci_do_set_ios(host, ios);
1647 sdhci_runtime_pm_put(host);
1648}
1649
94144a46
KL		 1650static int sdhci_do_get_cd(struct sdhci_host *host)
1651{
1652 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1653
1654 if (host->flags & SDHCI_DEVICE_DEAD)
1655 return 0;
1656
1657 /* If polling/nonremovable, assume that the card is always present. */
1658 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1659 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1660 return 1;
1661
1662 /* Try slot gpio detect */
1663 if (!IS_ERR_VALUE(gpio_cd))
1664 return !!gpio_cd;
1665
1666 /* Host native card detect */
1667 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1668}
1669
1670static int sdhci_get_cd(struct mmc_host *mmc)
1671{
1672 struct sdhci_host *host = mmc_priv(mmc);
1673 int ret;
1674
1675 sdhci_runtime_pm_get(host);
1676 ret = sdhci_do_get_cd(host);
1677 sdhci_runtime_pm_put(host);
1678 return ret;
1679}
1680
66fd8ad5 1681static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1682{
d129bceb 1683 unsigned long flags;
2dfb579c 1684 int is_readonly;
d129bceb 1685
d129bceb
PO		 1686 spin_lock_irqsave(&host->lock, flags);
1687
1e72859e 1688 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1689 is_readonly = 0;
1690 else if (host->ops->get_ro)
1691 is_readonly = host->ops->get_ro(host);
1e72859e 1692 else
2dfb579c
WS		 1693 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1694 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1695
1696 spin_unlock_irqrestore(&host->lock, flags);
1697
2dfb579c
WS		 1698 /* This quirk needs to be replaced by a callback-function later */
1699 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1700 !is_readonly : is_readonly;
d129bceb
PO		 1701}
1702
82b0e23a
TI		 1703#define SAMPLE_COUNT 5
1704
66fd8ad5 1705static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1706{
82b0e23a
TI		 1707 int i, ro_count;
1708
82b0e23a 1709 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1710 return sdhci_check_ro(host);
82b0e23a
TI		 1711
1712 ro_count = 0;
1713 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1714 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1715 if (++ro_count > SAMPLE_COUNT / 2)
1716 return 1;
1717 }
1718 msleep(30);
1719 }
1720 return 0;
1721}
1722
20758b66
AH		 1723static void sdhci_hw_reset(struct mmc_host *mmc)
1724{
1725 struct sdhci_host *host = mmc_priv(mmc);
1726
1727 if (host->ops && host->ops->hw_reset)
1728 host->ops->hw_reset(host);
1729}
1730
66fd8ad5 1731static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1732{
66fd8ad5
AH		 1733 struct sdhci_host *host = mmc_priv(mmc);
1734 int ret;
f75979b7 1735
66fd8ad5
AH		 1736 sdhci_runtime_pm_get(host);
1737 ret = sdhci_do_get_ro(host);
1738 sdhci_runtime_pm_put(host);
1739 return ret;
1740}
f75979b7 1741
66fd8ad5
AH		 1742static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1743{
be138554 1744 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1745 if (enable)
b537f94c 1746 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1747 else
b537f94c
RK		 1748 host->ier &= ~SDHCI_INT_CARD_INT;
1749
1750 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1751 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1752 mmiowb();
1753 }
66fd8ad5
AH		 1754}
1755
1756static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1757{
1758 struct sdhci_host *host = mmc_priv(mmc);
1759 unsigned long flags;
f75979b7 1760
ef104333
RK		 1761 sdhci_runtime_pm_get(host);
1762
66fd8ad5 1763 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1764 if (enable)
1765 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1766 else
1767 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1768
66fd8ad5 1769 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1770 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1771
1772 sdhci_runtime_pm_put(host);
f75979b7
PO		 1773}
1774
20b92a30 1775static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1776 struct mmc_ios *ios)
f2119df6 1777{
3a48edc4 1778 struct mmc_host *mmc = host->mmc;
20b92a30 1779 u16 ctrl;
6231f3de 1780 int ret;
f2119df6 1781
20b92a30
KL		 1782 /*
1783 * Signal Voltage Switching is only applicable for Host Controllers
1784 * v3.00 and above.
1785 */
1786 if (host->version < SDHCI_SPEC_300)
1787 return 0;
6231f3de 1788
f2119df6 1789 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1790
21f5998f 1791 switch (ios->signal_voltage) {
20b92a30
KL		 1792 case MMC_SIGNAL_VOLTAGE_330:
1793 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1794 ctrl &= ~SDHCI_CTRL_VDD_180;
1795 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1796
3a48edc4
TK		 1797 if (!IS_ERR(mmc->supply.vqmmc)) {
1798 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1799 3600000);
20b92a30 1800 if (ret) {
6606110d
JP		 1801 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1802 mmc_hostname(mmc));
20b92a30
KL		 1803 return -EIO;
1804 }
1805 }
1806 /* Wait for 5ms */
1807 usleep_range(5000, 5500);
f2119df6 1808
20b92a30
KL		 1809 /* 3.3V regulator output should be stable within 5 ms */
1810 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1811 if (!(ctrl & SDHCI_CTRL_VDD_180))
1812 return 0;
6231f3de 1813
6606110d
JP		 1814 pr_warn("%s: 3.3V regulator output did not became stable\n",
1815 mmc_hostname(mmc));
20b92a30
KL		 1816
1817 return -EAGAIN;
1818 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1819 if (!IS_ERR(mmc->supply.vqmmc)) {
1820 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1821 1700000, 1950000);
1822 if (ret) {
6606110d
JP		 1823 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1824 mmc_hostname(mmc));
20b92a30
KL		 1825 return -EIO;
1826 }
1827 }
6231f3de 1828
6231f3de
PR		 1829 /*
1830 * Enable 1.8V Signal Enable in the Host Control2
1831 * register
1832 */
20b92a30
KL		 1833 ctrl |= SDHCI_CTRL_VDD_180;
1834 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1835
9d967a61
VY		 1836 /* Some controller need to do more when switching */
1837 if (host->ops->voltage_switch)
1838 host->ops->voltage_switch(host);
1839
20b92a30
KL		 1840 /* 1.8V regulator output should be stable within 5 ms */
1841 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1842 if (ctrl & SDHCI_CTRL_VDD_180)
1843 return 0;
f2119df6 1844
6606110d
JP		 1845 pr_warn("%s: 1.8V regulator output did not became stable\n",
1846 mmc_hostname(mmc));
f2119df6 1847
20b92a30
KL		 1848 return -EAGAIN;
1849 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1850 if (!IS_ERR(mmc->supply.vqmmc)) {
1851 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1852 1300000);
20b92a30 1853 if (ret) {
6606110d
JP		 1854 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1855 mmc_hostname(mmc));
20b92a30 1856 return -EIO;
f2119df6
AN		 1857 }
1858 }
6231f3de 1859 return 0;
20b92a30 1860 default:
f2119df6
AN		 1861 /* No signal voltage switch required */
1862 return 0;
20b92a30 1863 }
f2119df6
AN		 1864}
1865
66fd8ad5 1866static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1867 struct mmc_ios *ios)
66fd8ad5
AH		 1868{
1869 struct sdhci_host *host = mmc_priv(mmc);
1870 int err;
1871
1872 if (host->version < SDHCI_SPEC_300)
1873 return 0;
1874 sdhci_runtime_pm_get(host);
21f5998f 1875 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1876 sdhci_runtime_pm_put(host);
1877 return err;
1878}
1879
20b92a30
KL		 1880static int sdhci_card_busy(struct mmc_host *mmc)
1881{
1882 struct sdhci_host *host = mmc_priv(mmc);
1883 u32 present_state;
1884
1885 sdhci_runtime_pm_get(host);
1886 /* Check whether DAT[3:0] is 0000 */
1887 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1888 sdhci_runtime_pm_put(host);
1889
1890 return !(present_state & SDHCI_DATA_LVL_MASK);
1891}
1892
b5540ce1
AH		 1893static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1894{
1895 struct sdhci_host *host = mmc_priv(mmc);
1896 unsigned long flags;
1897
1898 spin_lock_irqsave(&host->lock, flags);
1899 host->flags |= SDHCI_HS400_TUNING;
1900 spin_unlock_irqrestore(&host->lock, flags);
1901
1902 return 0;
1903}
1904
069c9f14 1905static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1906{
4b6f37d3 1907 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1908 u16 ctrl;
b513ea25 1909 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1910 int err = 0;
2b35bd83 1911 unsigned long flags;
38e40bf5 1912 unsigned int tuning_count = 0;
b5540ce1 1913 bool hs400_tuning;
b513ea25 1914
66fd8ad5 1915 sdhci_runtime_pm_get(host);
2b35bd83 1916 spin_lock_irqsave(&host->lock, flags);
b513ea25 1917
b5540ce1
AH		 1918 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1919 host->flags &= ~SDHCI_HS400_TUNING;
1920
38e40bf5
AH		 1921 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1922 tuning_count = host->tuning_count;
1923
b513ea25 1924 /*
069c9f14
G		 1925 * The Host Controller needs tuning only in case of SDR104 mode
1926 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1927 * Capabilities register.
069c9f14
G		 1928 * If the Host Controller supports the HS200 mode then the
1929 * tuning function has to be executed.
b513ea25 1930 */
4b6f37d3 1931 switch (host->timing) {
b5540ce1 1932 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1933 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1934 err = -EINVAL;
1935 goto out_unlock;
1936
4b6f37d3 1937 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1938 /*
1939 * Periodic re-tuning for HS400 is not expected to be needed, so
1940 * disable it here.
1941 */
1942 if (hs400_tuning)
1943 tuning_count = 0;
1944 break;
1945
4b6f37d3
RK		 1946 case MMC_TIMING_UHS_SDR104:
1947 break;
1948
1949 case MMC_TIMING_UHS_SDR50:
1950 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1951 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1952 break;
1953 /* FALLTHROUGH */
1954
1955 default:
d519c863 1956 goto out_unlock;
b513ea25
AN		 1957 }
1958
45251812 1959 if (host->ops->platform_execute_tuning) {
2b35bd83 1960 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1961 err = host->ops->platform_execute_tuning(host, opcode);
1962 sdhci_runtime_pm_put(host);
1963 return err;
1964 }
1965
4b6f37d3
RK		 1966 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1967 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1968 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1969 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1970 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1971
1972 /*
1973 * As per the Host Controller spec v3.00, tuning command
1974 * generates Buffer Read Ready interrupt, so enable that.
1975 *
1976 * Note: The spec clearly says that when tuning sequence
1977 * is being performed, the controller does not generate
1978 * interrupts other than Buffer Read Ready interrupt. But
1979 * to make sure we don't hit a controller bug, we _only_
1980 * enable Buffer Read Ready interrupt here.
1981 */
b537f94c
RK		 1982 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1983 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1984
1985 /*
1986 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1987 * of loops reaches 40 times or a timeout of 150ms occurs.
1988 */
b513ea25
AN		 1989 do {
1990 struct mmc_command cmd = {0};
66fd8ad5 1991 struct mmc_request mrq = {NULL};
b513ea25 1992
069c9f14 1993 cmd.opcode = opcode;
b513ea25
AN		 1994 cmd.arg = 0;
1995 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1996 cmd.retries = 0;
1997 cmd.data = NULL;
1998 cmd.error = 0;
1999
7ce45e95
AC		 2000 if (tuning_loop_counter-- == 0)
2001 break;
2002
b513ea25
AN		 2003 mrq.cmd = &cmd;
2004 host->mrq = &mrq;
2005
2006 /*
2007 * In response to CMD19, the card sends 64 bytes of tuning
2008 * block to the Host Controller. So we set the block size
2009 * to 64 here.
2010 */
069c9f14
G		 2011 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2012 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2013 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2014 SDHCI_BLOCK_SIZE);
2015 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2016 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2017 SDHCI_BLOCK_SIZE);
2018 } else {
2019 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2020 SDHCI_BLOCK_SIZE);
2021 }
b513ea25
AN		 2022
2023 /*
2024 * The tuning block is sent by the card to the host controller.
2025 * So we set the TRNS_READ bit in the Transfer Mode register.
2026 * This also takes care of setting DMA Enable and Multi Block
2027 * Select in the same register to 0.
2028 */
2029 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2030
2031 sdhci_send_command(host, &cmd);
2032
2033 host->cmd = NULL;
2034 host->mrq = NULL;
2035
2b35bd83 2036 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2037 /* Wait for Buffer Read Ready interrupt */
2038 wait_event_interruptible_timeout(host->buf_ready_int,
2039 (host->tuning_done == 1),
2040 msecs_to_jiffies(50));
2b35bd83 2041 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 2042
2043 if (!host->tuning_done) {
a3c76eb9 2044 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 2045 "Buffer Read Ready interrupt during tuning "
2046 "procedure, falling back to fixed sampling "
2047 "clock\n");
2048 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2049 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2050 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2051 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2052
2053 err = -EIO;
2054 goto out;
2055 }
2056
2057 host->tuning_done = 0;
2058
2059 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2060
2061 /* eMMC spec does not require a delay between tuning cycles */
2062 if (opcode == MMC_SEND_TUNING_BLOCK)
2063 mdelay(1);
b513ea25
AN		 2064 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2065
2066 /*
2067 * The Host Driver has exhausted the maximum number of loops allowed,
2068 * so use fixed sampling frequency.
2069 */
7ce45e95 2070 if (tuning_loop_counter < 0) {
b513ea25
AN		 2071 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2072 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2073 }
2074 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2075 pr_info(DRIVER_NAME ": Tuning procedure"
2076 " failed, falling back to fixed sampling"
2077 " clock\n");
114f2bf6 2078 err = -EIO;
b513ea25
AN		 2079 }
2080
2081out:
38e40bf5
AH		 2082 host->flags &= ~SDHCI_NEEDS_RETUNING;
2083
2084 if (tuning_count) {
973905fe 2085 host->flags |= SDHCI_USING_RETUNING_TIMER;
38e40bf5 2086 mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ);
cf2b5eea
AN		 2087 }
2088
2089 /*
2090 * In case tuning fails, host controllers which support re-tuning can
2091 * try tuning again at a later time, when the re-tuning timer expires.
2092 * So for these controllers, we return 0. Since there might be other
2093 * controllers who do not have this capability, we return error for
973905fe
AL		 2094 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2095 * a retuning timer to do the retuning for the card.
cf2b5eea 2096 */
973905fe 2097 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2098 err = 0;
2099
b537f94c
RK		 2100 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2101 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2102out_unlock:
2b35bd83 2103 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2104 sdhci_runtime_pm_put(host);
b513ea25
AN		 2105
2106 return err;
2107}
2108
52983382
KL		 2109
2110static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2111{
4d55c5a1
AN		 2112 /* Host Controller v3.00 defines preset value registers */
2113 if (host->version < SDHCI_SPEC_300)
2114 return;
2115
4d55c5a1
AN		 2116 /*
2117 * We only enable or disable Preset Value if they are not already
2118 * enabled or disabled respectively. Otherwise, we bail out.
2119 */
da91a8f9
RK		 2120 if (host->preset_enabled != enable) {
2121 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2122
2123 if (enable)
2124 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2125 else
2126 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2127
4d55c5a1 2128 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2129
2130 if (enable)
2131 host->flags |= SDHCI_PV_ENABLED;
2132 else
2133 host->flags &= ~SDHCI_PV_ENABLED;
2134
2135 host->preset_enabled = enable;
4d55c5a1 2136 }
66fd8ad5
AH		 2137}
2138
348487cb
HC		 2139static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2140 int err)
2141{
2142 struct sdhci_host *host = mmc_priv(mmc);
2143 struct mmc_data *data = mrq->data;
2144
2145 if (host->flags & SDHCI_REQ_USE_DMA) {
2146 if (data->host_cookie)
2147 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2148 data->flags & MMC_DATA_WRITE ?
2149 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2150 mrq->data->host_cookie = 0;
2151 }
2152}
2153
2154static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2155 struct mmc_data *data,
2156 struct sdhci_host_next *next)
2157{
2158 int sg_count;
2159
2160 if (!next && data->host_cookie &&
2161 data->host_cookie != host->next_data.cookie) {
2162 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2163 __func__, data->host_cookie, host->next_data.cookie);
2164 data->host_cookie = 0;
2165 }
2166
2167 /* Check if next job is already prepared */
2168 if (next ||
2169 (!next && data->host_cookie != host->next_data.cookie)) {
2170 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2171 data->sg_len,
2172 data->flags & MMC_DATA_WRITE ?
2173 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2174
2175 } else {
2176 sg_count = host->next_data.sg_count;
2177 host->next_data.sg_count = 0;
2178 }
2179
2180
2181 if (sg_count == 0)
2182 return -EINVAL;
2183
2184 if (next) {
2185 next->sg_count = sg_count;
2186 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2187 } else
2188 host->sg_count = sg_count;
2189
2190 return sg_count;
2191}
2192
2193static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2194 bool is_first_req)
2195{
2196 struct sdhci_host *host = mmc_priv(mmc);
2197
2198 if (mrq->data->host_cookie) {
2199 mrq->data->host_cookie = 0;
2200 return;
2201 }
2202
2203 if (host->flags & SDHCI_REQ_USE_DMA)
2204 if (sdhci_pre_dma_transfer(host,
2205 mrq->data,
2206 &host->next_data) < 0)
2207 mrq->data->host_cookie = 0;
2208}
2209
71e69211 2210static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2211{
71e69211 2212 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2213 unsigned long flags;
2836766a 2214 int present;
d129bceb 2215
722e1280
CD		 2216 /* First check if client has provided their own card event */
2217 if (host->ops->card_event)
2218 host->ops->card_event(host);
2219
2836766a
KK		 2220 present = sdhci_do_get_cd(host);
2221
d129bceb
PO		 2222 spin_lock_irqsave(&host->lock, flags);
2223
66fd8ad5 2224 /* Check host->mrq first in case we are runtime suspended */
2836766a 2225 if (host->mrq && !present) {
a3c76eb9 2226 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2227 mmc_hostname(host->mmc));
a3c76eb9 2228 pr_err("%s: Resetting controller.\n",
66fd8ad5 2229 mmc_hostname(host->mmc));
d129bceb 2230
03231f9b
RK		 2231 sdhci_do_reset(host, SDHCI_RESET_CMD);
2232 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2233
66fd8ad5
AH		 2234 host->mrq->cmd->error = -ENOMEDIUM;
2235 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2236 }
2237
2238 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2239}
2240
2241static const struct mmc_host_ops sdhci_ops = {
2242 .request = sdhci_request,
348487cb
HC		 2243 .post_req = sdhci_post_req,
2244 .pre_req = sdhci_pre_req,
71e69211 2245 .set_ios = sdhci_set_ios,
94144a46 2246 .get_cd = sdhci_get_cd,
71e69211
GL		 2247 .get_ro = sdhci_get_ro,
2248 .hw_reset = sdhci_hw_reset,
2249 .enable_sdio_irq = sdhci_enable_sdio_irq,
2250 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2251 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2252 .execute_tuning = sdhci_execute_tuning,
71e69211 2253 .card_event = sdhci_card_event,
20b92a30 2254 .card_busy = sdhci_card_busy,
71e69211
GL		 2255};
2256
2257/*****************************************************************************\
2258 * *
2259 * Tasklets *
2260 * *
2261\*****************************************************************************/
2262
d129bceb
PO		 2263static void sdhci_tasklet_finish(unsigned long param)
2264{
2265 struct sdhci_host *host;
2266 unsigned long flags;
2267 struct mmc_request *mrq;
2268
2269 host = (struct sdhci_host*)param;
2270
66fd8ad5
AH		 2271 spin_lock_irqsave(&host->lock, flags);
2272
0c9c99a7
CB		 2273 /*
2274 * If this tasklet gets rescheduled while running, it will
2275 * be run again afterwards but without any active request.
2276 */
66fd8ad5
AH		 2277 if (!host->mrq) {
2278 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2279 return;
66fd8ad5 2280 }
d129bceb
PO		 2281
2282 del_timer(&host->timer);
2283
2284 mrq = host->mrq;
2285
d129bceb
PO		 2286 /*
2287 * The controller needs a reset of internal state machines
2288 * upon error conditions.
2289 */
1e72859e 2290 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2291 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2292 (mrq->sbc && mrq->sbc->error) ||
2293 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2294 (mrq->data->stop && mrq->data->stop->error))) ||
2295 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2296
2297 /* Some controllers need this kick or reset won't work here */
8213af3b 2298 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2299 /* This is to force an update */
1771059c 2300 host->ops->set_clock(host, host->clock);
645289dc
PO		 2301
2302 /* Spec says we should do both at the same time, but Ricoh
2303 controllers do not like that. */
03231f9b
RK		 2304 sdhci_do_reset(host, SDHCI_RESET_CMD);
2305 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2306 }
2307
2308 host->mrq = NULL;
2309 host->cmd = NULL;
2310 host->data = NULL;
2311
f9134319 2312#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2313 sdhci_deactivate_led(host);
2f730fec 2314#endif
d129bceb 2315
5f25a66f 2316 mmiowb();
d129bceb
PO		 2317 spin_unlock_irqrestore(&host->lock, flags);
2318
2319 mmc_request_done(host->mmc, mrq);
66fd8ad5 2320 sdhci_runtime_pm_put(host);
d129bceb
PO		 2321}
2322
2323static void sdhci_timeout_timer(unsigned long data)
2324{
2325 struct sdhci_host *host;
2326 unsigned long flags;
2327
2328 host = (struct sdhci_host*)data;
2329
2330 spin_lock_irqsave(&host->lock, flags);
2331
2332 if (host->mrq) {
a3c76eb9 2333 pr_err("%s: Timeout waiting for hardware "
acf1da45 2334 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2335 sdhci_dumpregs(host);
2336
2337 if (host->data) {
17b0429d 2338 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2339 sdhci_finish_data(host);
2340 } else {
2341 if (host->cmd)
17b0429d 2342 host->cmd->error = -ETIMEDOUT;
d129bceb 2343 else
17b0429d 2344 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2345
2346 tasklet_schedule(&host->finish_tasklet);
2347 }
2348 }
2349
5f25a66f 2350 mmiowb();
d129bceb
PO		 2351 spin_unlock_irqrestore(&host->lock, flags);
2352}
2353
cf2b5eea
AN		 2354static void sdhci_tuning_timer(unsigned long data)
2355{
2356 struct sdhci_host *host;
2357 unsigned long flags;
2358
2359 host = (struct sdhci_host *)data;
2360
2361 spin_lock_irqsave(&host->lock, flags);
2362
2363 host->flags |= SDHCI_NEEDS_RETUNING;
2364
2365 spin_unlock_irqrestore(&host->lock, flags);
2366}
2367
d129bceb
PO		 2368/*****************************************************************************\
2369 * *
2370 * Interrupt handling *
2371 * *
2372\*****************************************************************************/
2373
61541397 2374static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2375{
2376 BUG_ON(intmask == 0);
2377
2378 if (!host->cmd) {
a3c76eb9 2379 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2380 "though no command operation was in progress.\n",
2381 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2382 sdhci_dumpregs(host);
2383 return;
2384 }
2385
43b58b36 2386 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2387 host->cmd->error = -ETIMEDOUT;
2388 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2389 SDHCI_INT_INDEX))
2390 host->cmd->error = -EILSEQ;
43b58b36 2391
e809517f 2392 if (host->cmd->error) {
d129bceb 2393 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2394 return;
2395 }
2396
2397 /*
2398 * The host can send and interrupt when the busy state has
2399 * ended, allowing us to wait without wasting CPU cycles.
2400 * Unfortunately this is overloaded on the "data complete"
2401 * interrupt, so we need to take some care when handling
2402 * it.
2403 *
2404 * Note: The 1.0 specification is a bit ambiguous about this
2405 * feature so there might be some problems with older
2406 * controllers.
2407 */
2408 if (host->cmd->flags & MMC_RSP_BUSY) {
2409 if (host->cmd->data)
2410 DBG("Cannot wait for busy signal when also "
2411 "doing a data transfer");
e99783a4
CM		 2412 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2413 && !host->busy_handle) {
2414 /* Mark that command complete before busy is ended */
2415 host->busy_handle = 1;
e809517f 2416 return;
e99783a4 2417 }
f945405c
BD		 2418
2419 /* The controller does not support the end-of-busy IRQ,
2420 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2421 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2422 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2423 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2424 }
2425
2426 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2427 sdhci_finish_command(host);
d129bceb
PO		 2428}
2429
0957c333 2430#ifdef CONFIG_MMC_DEBUG
08621b18 2431static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2432{
2433 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2434 void *desc = host->adma_table;
6882a8c0
BD		 2435
2436 sdhci_dumpregs(host);
2437
2438 while (true) {
e57a5f61
AH		 2439 struct sdhci_adma2_64_desc *dma_desc = desc;
2440
2441 if (host->flags & SDHCI_USE_64_BIT_DMA)
2442 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2443 name, desc, le32_to_cpu(dma_desc->addr_hi),
2444 le32_to_cpu(dma_desc->addr_lo),
2445 le16_to_cpu(dma_desc->len),
2446 le16_to_cpu(dma_desc->cmd));
2447 else
2448 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2449 name, desc, le32_to_cpu(dma_desc->addr_lo),
2450 le16_to_cpu(dma_desc->len),
2451 le16_to_cpu(dma_desc->cmd));
6882a8c0 2452
76fe379a 2453 desc += host->desc_sz;
6882a8c0 2454
0545230f 2455 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2456 break;
2457 }
2458}
2459#else
08621b18 2460static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2461#endif
2462
d129bceb
PO		 2463static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2464{
069c9f14 2465 u32 command;
d129bceb
PO		 2466 BUG_ON(intmask == 0);
2467
b513ea25
AN		 2468 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2469 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2470 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2471 if (command == MMC_SEND_TUNING_BLOCK ||
2472 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2473 host->tuning_done = 1;
2474 wake_up(&host->buf_ready_int);
2475 return;
2476 }
2477 }
2478
d129bceb
PO		 2479 if (!host->data) {
2480 /*
e809517f
PO		 2481 * The "data complete" interrupt is also used to
2482 * indicate that a busy state has ended. See comment
2483 * above in sdhci_cmd_irq().
d129bceb 2484 */
e809517f 2485 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2486 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2487 host->cmd->error = -ETIMEDOUT;
2488 tasklet_schedule(&host->finish_tasklet);
2489 return;
2490 }
e809517f 2491 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2492 /*
2493 * Some cards handle busy-end interrupt
2494 * before the command completed, so make
2495 * sure we do things in the proper order.
2496 */
2497 if (host->busy_handle)
2498 sdhci_finish_command(host);
2499 else
2500 host->busy_handle = 1;
e809517f
PO		 2501 return;
2502 }
2503 }
d129bceb 2504
a3c76eb9 2505 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2506 "though no data operation was in progress.\n",
2507 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2508 sdhci_dumpregs(host);
2509
2510 return;
2511 }
2512
2513 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2514 host->data->error = -ETIMEDOUT;
22113efd
AL		 2515 else if (intmask & SDHCI_INT_DATA_END_BIT)
2516 host->data->error = -EILSEQ;
2517 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2518 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2519 != MMC_BUS_TEST_R)
17b0429d 2520 host->data->error = -EILSEQ;
6882a8c0 2521 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2522 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2523 sdhci_adma_show_error(host);
2134a922 2524 host->data->error = -EIO;
a4071fbb
HZ		 2525 if (host->ops->adma_workaround)
2526 host->ops->adma_workaround(host, intmask);
6882a8c0 2527 }
d129bceb 2528
17b0429d 2529 if (host->data->error)
d129bceb
PO		 2530 sdhci_finish_data(host);
2531 else {
a406f5a3 2532 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2533 sdhci_transfer_pio(host);
2534
6ba736a1
PO		 2535 /*
2536 * We currently don't do anything fancy with DMA
2537 * boundaries, but as we can't disable the feature
2538 * we need to at least restart the transfer.
f6a03cbf
MV		 2539 *
2540 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2541 * should return a valid address to continue from, but as
2542 * some controllers are faulty, don't trust them.
6ba736a1 2543 */
f6a03cbf
MV		 2544 if (intmask & SDHCI_INT_DMA_END) {
2545 u32 dmastart, dmanow;
2546 dmastart = sg_dma_address(host->data->sg);
2547 dmanow = dmastart + host->data->bytes_xfered;
2548 /*
2549 * Force update to the next DMA block boundary.
2550 */
2551 dmanow = (dmanow &
2552 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2553 SDHCI_DEFAULT_BOUNDARY_SIZE;
2554 host->data->bytes_xfered = dmanow - dmastart;
2555 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2556 " next 0x%08x\n",
2557 mmc_hostname(host->mmc), dmastart,
2558 host->data->bytes_xfered, dmanow);
2559 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2560 }
6ba736a1 2561
e538fbe8
PO		 2562 if (intmask & SDHCI_INT_DATA_END) {
2563 if (host->cmd) {
2564 /*
2565 * Data managed to finish before the
2566 * command completed. Make sure we do
2567 * things in the proper order.
2568 */
2569 host->data_early = 1;
2570 } else {
2571 sdhci_finish_data(host);
2572 }
2573 }
d129bceb
PO		 2574 }
2575}
2576
7d12e780 2577static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2578{
781e989c 2579 irqreturn_t result = IRQ_NONE;
66fd8ad5 2580 struct sdhci_host *host = dev_id;
41005003 2581 u32 intmask, mask, unexpected = 0;
781e989c 2582 int max_loops = 16;
d129bceb
PO		 2583
2584 spin_lock(&host->lock);
2585
be138554 2586 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2587 spin_unlock(&host->lock);
655bca76 2588 return IRQ_NONE;
66fd8ad5
AH		 2589 }
2590
4e4141a5 2591 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2592 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2593 result = IRQ_NONE;
2594 goto out;
2595 }
2596
41005003
RK		 2597 do {
2598 /* Clear selected interrupts. */
2599 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2600 SDHCI_INT_BUS_POWER);
2601 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2602
41005003
RK		 2603 DBG("*** %s got interrupt: 0x%08x\n",
2604 mmc_hostname(host->mmc), intmask);
d129bceb 2605
41005003
RK		 2606 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2607 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2608 SDHCI_CARD_PRESENT;
d129bceb 2609
41005003
RK		 2610 /*
2611 * There is a observation on i.mx esdhc. INSERT
2612 * bit will be immediately set again when it gets
2613 * cleared, if a card is inserted. We have to mask
2614 * the irq to prevent interrupt storm which will
2615 * freeze the system. And the REMOVE gets the
2616 * same situation.
2617 *
2618 * More testing are needed here to ensure it works
2619 * for other platforms though.
2620 */
b537f94c
RK		 2621 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2622 SDHCI_INT_CARD_REMOVE);
2623 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2624 SDHCI_INT_CARD_INSERT;
2625 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2626 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2627
2628 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2629 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2630
2631 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2632 SDHCI_INT_CARD_REMOVE);
2633 result = IRQ_WAKE_THREAD;
41005003 2634 }
d129bceb 2635
41005003 2636 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2637 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2638 &intmask);
964f9ce2 2639
41005003
RK		 2640 if (intmask & SDHCI_INT_DATA_MASK)
2641 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2642
41005003
RK		 2643 if (intmask & SDHCI_INT_BUS_POWER)
2644 pr_err("%s: Card is consuming too much power!\n",
2645 mmc_hostname(host->mmc));
3192a28f 2646
781e989c
RK		 2647 if (intmask & SDHCI_INT_CARD_INT) {
2648 sdhci_enable_sdio_irq_nolock(host, false);
2649 host->thread_isr |= SDHCI_INT_CARD_INT;
2650 result = IRQ_WAKE_THREAD;
2651 }
f75979b7 2652
41005003
RK		 2653 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2654 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2655 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2656 SDHCI_INT_CARD_INT);
f75979b7 2657
41005003
RK		 2658 if (intmask) {
2659 unexpected |= intmask;
2660 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2661 }
d129bceb 2662
781e989c
RK		 2663 if (result == IRQ_NONE)
2664 result = IRQ_HANDLED;
d129bceb 2665
41005003 2666 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2667 } while (intmask && --max_loops);
d129bceb
PO		 2668out:
2669 spin_unlock(&host->lock);
2670
6379b237
AS		 2671 if (unexpected) {
2672 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2673 mmc_hostname(host->mmc), unexpected);
2674 sdhci_dumpregs(host);
2675 }
f75979b7 2676
d129bceb
PO		 2677 return result;
2678}
2679
781e989c
RK		 2680static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2681{
2682 struct sdhci_host *host = dev_id;
2683 unsigned long flags;
2684 u32 isr;
2685
2686 spin_lock_irqsave(&host->lock, flags);
2687 isr = host->thread_isr;
2688 host->thread_isr = 0;
2689 spin_unlock_irqrestore(&host->lock, flags);
2690
3560db8e
RK		 2691 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2692 sdhci_card_event(host->mmc);
2693 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2694 }
2695
781e989c
RK		 2696 if (isr & SDHCI_INT_CARD_INT) {
2697 sdio_run_irqs(host->mmc);
2698
2699 spin_lock_irqsave(&host->lock, flags);
2700 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2701 sdhci_enable_sdio_irq_nolock(host, true);
2702 spin_unlock_irqrestore(&host->lock, flags);
2703 }
2704
2705 return isr ? IRQ_HANDLED : IRQ_NONE;
2706}
2707
d129bceb
PO		 2708/*****************************************************************************\
2709 * *
2710 * Suspend/resume *
2711 * *
2712\*****************************************************************************/
2713
2714#ifdef CONFIG_PM
ad080d79
KL		 2715void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2716{
2717 u8 val;
2718 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2719 | SDHCI_WAKE_ON_INT;
2720
2721 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2722 val |= mask ;
2723 /* Avoid fake wake up */
2724 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2725 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2726 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2727}
2728EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2729
0b10f478 2730static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2731{
2732 u8 val;
2733 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2734 | SDHCI_WAKE_ON_INT;
2735
2736 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2737 val &= ~mask;
2738 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2739}
d129bceb 2740
29495aa0 2741int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2742{
7260cf5e
AV		 2743 sdhci_disable_card_detection(host);
2744
cf2b5eea 2745 /* Disable tuning since we are suspending */
973905fe 2746 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2747 del_timer_sync(&host->tuning_timer);
cf2b5eea 2748 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2749 }
2750
ad080d79 2751 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2752 host->ier = 0;
2753 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2754 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2755 free_irq(host->irq, host);
2756 } else {
2757 sdhci_enable_irq_wakeups(host);
2758 enable_irq_wake(host->irq);
2759 }
4ee14ec6 2760 return 0;
d129bceb
PO		 2761}
2762
b8c86fc5 2763EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2764
b8c86fc5
PO		 2765int sdhci_resume_host(struct sdhci_host *host)
2766{
4ee14ec6 2767 int ret = 0;
d129bceb 2768
a13abc7b 2769 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2770 if (host->ops->enable_dma)
2771 host->ops->enable_dma(host);
2772 }
d129bceb 2773
ad080d79 2774 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2775 ret = request_threaded_irq(host->irq, sdhci_irq,
2776 sdhci_thread_irq, IRQF_SHARED,
2777 mmc_hostname(host->mmc), host);
ad080d79
KL		 2778 if (ret)
2779 return ret;
2780 } else {
2781 sdhci_disable_irq_wakeups(host);
2782 disable_irq_wake(host->irq);
2783 }
d129bceb 2784
6308d290
AH		 2785 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2786 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2787 /* Card keeps power but host controller does not */
2788 sdhci_init(host, 0);
2789 host->pwr = 0;
2790 host->clock = 0;
2791 sdhci_do_set_ios(host, &host->mmc->ios);
2792 } else {
2793 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2794 mmiowb();
2795 }
b8c86fc5 2796
7260cf5e
AV		 2797 sdhci_enable_card_detection(host);
2798
cf2b5eea 2799 /* Set the re-tuning expiration flag */
973905fe 2800 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2801 host->flags |= SDHCI_NEEDS_RETUNING;
2802
2f4cbb3d 2803 return ret;
d129bceb
PO		 2804}
2805
b8c86fc5 2806EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2807
2808static int sdhci_runtime_pm_get(struct sdhci_host *host)
2809{
2810 return pm_runtime_get_sync(host->mmc->parent);
2811}
2812
2813static int sdhci_runtime_pm_put(struct sdhci_host *host)
2814{
2815 pm_runtime_mark_last_busy(host->mmc->parent);
2816 return pm_runtime_put_autosuspend(host->mmc->parent);
2817}
2818
f0710a55
AH		 2819static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2820{
2821 if (host->runtime_suspended || host->bus_on)
2822 return;
2823 host->bus_on = true;
2824 pm_runtime_get_noresume(host->mmc->parent);
2825}
2826
2827static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2828{
2829 if (host->runtime_suspended || !host->bus_on)
2830 return;
2831 host->bus_on = false;
2832 pm_runtime_put_noidle(host->mmc->parent);
2833}
2834
66fd8ad5
AH		 2835int sdhci_runtime_suspend_host(struct sdhci_host *host)
2836{
2837 unsigned long flags;
66fd8ad5
AH		 2838
2839 /* Disable tuning since we are suspending */
973905fe 2840 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2841 del_timer_sync(&host->tuning_timer);
2842 host->flags &= ~SDHCI_NEEDS_RETUNING;
2843 }
2844
2845 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2846 host->ier &= SDHCI_INT_CARD_INT;
2847 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2848 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2849 spin_unlock_irqrestore(&host->lock, flags);
2850
781e989c 2851 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2852
2853 spin_lock_irqsave(&host->lock, flags);
2854 host->runtime_suspended = true;
2855 spin_unlock_irqrestore(&host->lock, flags);
2856
8a125bad 2857 return 0;
66fd8ad5
AH		 2858}
2859EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2860
2861int sdhci_runtime_resume_host(struct sdhci_host *host)
2862{
2863 unsigned long flags;
8a125bad 2864 int host_flags = host->flags;
66fd8ad5
AH		 2865
2866 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2867 if (host->ops->enable_dma)
2868 host->ops->enable_dma(host);
2869 }
2870
2871 sdhci_init(host, 0);
2872
2873 /* Force clock and power re-program */
2874 host->pwr = 0;
2875 host->clock = 0;
3396e736 2876 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2877 sdhci_do_set_ios(host, &host->mmc->ios);
2878
52983382
KL		 2879 if ((host_flags & SDHCI_PV_ENABLED) &&
2880 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2881 spin_lock_irqsave(&host->lock, flags);
2882 sdhci_enable_preset_value(host, true);
2883 spin_unlock_irqrestore(&host->lock, flags);
2884 }
66fd8ad5
AH		 2885
2886 /* Set the re-tuning expiration flag */
973905fe 2887 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2888 host->flags |= SDHCI_NEEDS_RETUNING;
2889
2890 spin_lock_irqsave(&host->lock, flags);
2891
2892 host->runtime_suspended = false;
2893
2894 /* Enable SDIO IRQ */
ef104333 2895 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2896 sdhci_enable_sdio_irq_nolock(host, true);
2897
2898 /* Enable Card Detection */
2899 sdhci_enable_card_detection(host);
2900
2901 spin_unlock_irqrestore(&host->lock, flags);
2902
8a125bad 2903 return 0;
66fd8ad5
AH		 2904}
2905EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2906
162d6f98 2907#endif /* CONFIG_PM */
66fd8ad5 2908
d129bceb
PO		 2909/*****************************************************************************\
2910 * *
b8c86fc5 2911 * Device allocation/registration *
d129bceb
PO		 2912 * *
2913\*****************************************************************************/
2914
b8c86fc5
PO		 2915struct sdhci_host *sdhci_alloc_host(struct device *dev,
2916 size_t priv_size)
d129bceb 2917{
d129bceb
PO		 2918 struct mmc_host *mmc;
2919 struct sdhci_host *host;
2920
b8c86fc5 2921 WARN_ON(dev == NULL);
d129bceb 2922
b8c86fc5 2923 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2924 if (!mmc)
b8c86fc5 2925 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2926
2927 host = mmc_priv(mmc);
2928 host->mmc = mmc;
2929
b8c86fc5
PO		 2930 return host;
2931}
8a4da143 2932
b8c86fc5 2933EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2934
b8c86fc5
PO		 2935int sdhci_add_host(struct sdhci_host *host)
2936{
2937 struct mmc_host *mmc;
bd6a8c30 2938 u32 caps[2] = {0, 0};
f2119df6
AN		 2939 u32 max_current_caps;
2940 unsigned int ocr_avail;
f5fa92e5 2941 unsigned int override_timeout_clk;
b8c86fc5 2942 int ret;
d129bceb 2943
b8c86fc5
PO		 2944 WARN_ON(host == NULL);
2945 if (host == NULL)
2946 return -EINVAL;
d129bceb 2947
b8c86fc5 2948 mmc = host->mmc;
d129bceb 2949
b8c86fc5
PO		 2950 if (debug_quirks)
2951 host->quirks = debug_quirks;
66fd8ad5
AH		 2952 if (debug_quirks2)
2953 host->quirks2 = debug_quirks2;
d129bceb 2954
f5fa92e5
AH		 2955 override_timeout_clk = host->timeout_clk;
2956
03231f9b 2957 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2958
4e4141a5 2959 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2960 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2961 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2962 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2963 pr_err("%s: Unknown controller version (%d). "
b69c9058 2964 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2965 host->version);
4a965505
PO		 2966 }
2967
f2119df6 2968 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2969 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2970
bd6a8c30
PR		 2971 if (host->version >= SDHCI_SPEC_300)
2972 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2973 host->caps1 :
2974 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2975
b8c86fc5 2976 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2977 host->flags |= SDHCI_USE_SDMA;
f2119df6 2978 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2979 DBG("Controller doesn't have SDMA capability\n");
67435274 2980 else
a13abc7b 2981 host->flags |= SDHCI_USE_SDMA;
d129bceb 2982
b8c86fc5 2983 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2984 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2985 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2986 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2987 }
2988
f2119df6
AN		 2989 if ((host->version >= SDHCI_SPEC_200) &&
2990 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2991 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2992
2993 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2994 (host->flags & SDHCI_USE_ADMA)) {
2995 DBG("Disabling ADMA as it is marked broken\n");
2996 host->flags &= ~SDHCI_USE_ADMA;
2997 }
2998
e57a5f61
AH		 2999 /*
3000 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3001 * and *must* do 64-bit DMA. A driver has the opportunity to change
3002 * that during the first call to ->enable_dma(). Similarly
3003 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3004 * implement.
3005 */
3006 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
3007 host->flags |= SDHCI_USE_64_BIT_DMA;
3008
a13abc7b 3009 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 3010 if (host->ops->enable_dma) {
3011 if (host->ops->enable_dma(host)) {
6606110d 3012 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 3013 mmc_hostname(mmc));
a13abc7b
RR		 3014 host->flags &=
3015 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 3016 }
d129bceb
PO		 3017 }
3018 }
3019
e57a5f61
AH		 3020 /* SDMA does not support 64-bit DMA */
3021 if (host->flags & SDHCI_USE_64_BIT_DMA)
3022 host->flags &= ~SDHCI_USE_SDMA;
3023
2134a922
PO		 3024 if (host->flags & SDHCI_USE_ADMA) {
3025 /*
76fe379a
AH		 3026 * The DMA descriptor table size is calculated as the maximum
3027 * number of segments times 2, to allow for an alignment
3028 * descriptor for each segment, plus 1 for a nop end descriptor,
3029 * all multipled by the descriptor size.
2134a922 3030 */
e57a5f61
AH		 3031 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3032 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3033 SDHCI_ADMA2_64_DESC_SZ;
3034 host->align_buffer_sz = SDHCI_MAX_SEGS *
3035 SDHCI_ADMA2_64_ALIGN;
3036 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3037 host->align_sz = SDHCI_ADMA2_64_ALIGN;
3038 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
3039 } else {
3040 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3041 SDHCI_ADMA2_32_DESC_SZ;
3042 host->align_buffer_sz = SDHCI_MAX_SEGS *
3043 SDHCI_ADMA2_32_ALIGN;
3044 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3045 host->align_sz = SDHCI_ADMA2_32_ALIGN;
3046 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
3047 }
4efaa6fb 3048 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
76fe379a 3049 host->adma_table_sz,
4efaa6fb
AH		 3050 &host->adma_addr,
3051 GFP_KERNEL);
76fe379a 3052 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
4efaa6fb 3053 if (!host->adma_table || !host->align_buffer) {
76fe379a 3054 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3055 host->adma_table, host->adma_addr);
2134a922 3056 kfree(host->align_buffer);
6606110d 3057 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 3058 mmc_hostname(mmc));
3059 host->flags &= ~SDHCI_USE_ADMA;
4efaa6fb 3060 host->adma_table = NULL;
d1e49f77 3061 host->align_buffer = NULL;
76fe379a 3062 } else if (host->adma_addr & host->align_mask) {
6606110d
JP		 3063 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3064 mmc_hostname(mmc));
d1e49f77 3065 host->flags &= ~SDHCI_USE_ADMA;
76fe379a 3066 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3067 host->adma_table, host->adma_addr);
d1e49f77 3068 kfree(host->align_buffer);
4efaa6fb 3069 host->adma_table = NULL;
d1e49f77 3070 host->align_buffer = NULL;
2134a922
PO		 3071 }
3072 }
3073
7659150c
PO		 3074 /*
3075 * If we use DMA, then it's up to the caller to set the DMA
3076 * mask, but PIO does not need the hw shim so we set a new
3077 * mask here in that case.
3078 */
a13abc7b 3079 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3080 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3081 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3082 }
d129bceb 3083
c4687d5f 3084 if (host->version >= SDHCI_SPEC_300)
f2119df6 3085 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3086 >> SDHCI_CLOCK_BASE_SHIFT;
3087 else
f2119df6 3088 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3089 >> SDHCI_CLOCK_BASE_SHIFT;
3090
4240ff0a 3091 host->max_clk *= 1000000;
f27f47ef
AV		 3092 if (host->max_clk == 0 || host->quirks &
3093 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3094 if (!host->ops->get_max_clock) {
a3c76eb9 3095 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 3096 "frequency.\n", mmc_hostname(mmc));
3097 return -ENODEV;
3098 }
3099 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3100 }
d129bceb 3101
348487cb 3102 host->next_data.cookie = 1;
c3ed3877
AN		 3103 /*
3104 * In case of Host Controller v3.00, find out whether clock
3105 * multiplier is supported.
3106 */
3107 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3108 SDHCI_CLOCK_MUL_SHIFT;
3109
3110 /*
3111 * In case the value in Clock Multiplier is 0, then programmable
3112 * clock mode is not supported, otherwise the actual clock
3113 * multiplier is one more than the value of Clock Multiplier
3114 * in the Capabilities Register.
3115 */
3116 if (host->clk_mul)
3117 host->clk_mul += 1;
3118
d129bceb
PO		 3119 /*
3120 * Set host parameters.
3121 */
3122 mmc->ops = &sdhci_ops;
c3ed3877 3123 mmc->f_max = host->max_clk;
ce5f036b 3124 if (host->ops->get_min_clock)
a9e58f25 3125 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3126 else if (host->version >= SDHCI_SPEC_300) {
3127 if (host->clk_mul) {
3128 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3129 mmc->f_max = host->max_clk * host->clk_mul;
3130 } else
3131 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3132 } else
0397526d 3133 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3134
28aab053
AD		 3135 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3136 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3137 SDHCI_TIMEOUT_CLK_SHIFT;
3138 if (host->timeout_clk == 0) {
3139 if (host->ops->get_timeout_clock) {
3140 host->timeout_clk =
3141 host->ops->get_timeout_clock(host);
3142 } else {
3143 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3144 mmc_hostname(mmc));
3145 return -ENODEV;
3146 }
272308ca 3147 }
272308ca 3148
28aab053
AD		 3149 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3150 host->timeout_clk *= 1000;
272308ca 3151
28aab053 3152 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3153 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3154 mmc->max_busy_timeout /= host->timeout_clk;
3155 }
58d1246d 3156
f5fa92e5
AH		 3157 if (override_timeout_clk)
3158 host->timeout_clk = override_timeout_clk;
3159
e89d456f 3160 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3161 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3162
3163 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3164 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3165
8edf6371 3166 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3167 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3168 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3169 !(host->flags & SDHCI_USE_SDMA)) &&
3170 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3171 host->flags |= SDHCI_AUTO_CMD23;
3172 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3173 } else {
3174 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3175 }
3176
15ec4461
PR		 3177 /*
3178 * A controller may support 8-bit width, but the board itself
3179 * might not have the pins brought out. Boards that support
3180 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3181 * their platform code before calling sdhci_add_host(), and we
3182 * won't assume 8-bit width for hosts without that CAP.
3183 */
5fe23c7f 3184 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3185 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3186
63ef5d8c
JH		 3187 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3188 mmc->caps &= ~MMC_CAP_CMD23;
3189
f2119df6 3190 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3191 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3192
176d1ed4 3193 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4e743f1f 3194 !(mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 3195 mmc->caps |= MMC_CAP_NEEDS_POLL;
3196
3a48edc4
TK		 3197 /* If there are external regulators, get them */
3198 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3199 return -EPROBE_DEFER;
3200
6231f3de 3201 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3202 if (!IS_ERR(mmc->supply.vqmmc)) {
3203 ret = regulator_enable(mmc->supply.vqmmc);
3204 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3205 1950000))
8363c374
KL		 3206 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3207 SDHCI_SUPPORT_SDR50 |
3208 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3209 if (ret) {
3210 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3211 mmc_hostname(mmc), ret);
4bb74313 3212 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3213 }
8363c374 3214 }
6231f3de 3215
6a66180a
DD		 3216 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3217 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3218 SDHCI_SUPPORT_DDR50);
3219
4188bba0
AC		 3220 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3221 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3222 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3223 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3224
3225 /* SDR104 supports also implies SDR50 support */
156e14b1 3226 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3227 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3228 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3229 * field can be promoted to support HS200.
3230 */
549c0b18 3231 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3232 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3233 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3234 mmc->caps |= MMC_CAP_UHS_SDR50;
3235
e9fb05d5
AH		 3236 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3237 (caps[1] & SDHCI_SUPPORT_HS400))
3238 mmc->caps2 |= MMC_CAP2_HS400;
3239
549c0b18
AH		 3240 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3241 (IS_ERR(mmc->supply.vqmmc) ||
3242 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3243 1300000)))
3244 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3245
9107ebbf
MC		 3246 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3247 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3248 mmc->caps |= MMC_CAP_UHS_DDR50;
3249
069c9f14 3250 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3251 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3252 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3253
156e14b1 3254 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3255 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3256 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3257
d6d50a15
AN		 3258 /* Driver Type(s) (A, C, D) supported by the host */
3259 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3260 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3261 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3262 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3263 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3264 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3265
cf2b5eea
AN		 3266 /* Initial value for re-tuning timer count */
3267 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3268 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3269
3270 /*
3271 * In case Re-tuning Timer is not disabled, the actual value of
3272 * re-tuning timer will be 2 ^ (n - 1).
3273 */
3274 if (host->tuning_count)
3275 host->tuning_count = 1 << (host->tuning_count - 1);
3276
3277 /* Re-tuning mode supported by the Host Controller */
3278 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3279 SDHCI_RETUNING_MODE_SHIFT;
3280
8f230f45 3281 ocr_avail = 0;
bad37e1a 3282
f2119df6
AN		 3283 /*
3284 * According to SD Host Controller spec v3.00, if the Host System
3285 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3286 * the value is meaningful only if Voltage Support in the Capabilities
3287 * register is set. The actual current value is 4 times the register
3288 * value.
3289 */
3290 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3291 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3292 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3293 if (curr > 0) {
3294
3295 /* convert to SDHCI_MAX_CURRENT format */
3296 curr = curr/1000; /* convert to mA */
3297 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3298
3299 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3300 max_current_caps =
3301 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3302 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3303 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3304 }
3305 }
f2119df6
AN		 3306
3307 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3308 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3309
55c4665e 3310 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3311 SDHCI_MAX_CURRENT_330_MASK) >>
3312 SDHCI_MAX_CURRENT_330_SHIFT) *
3313 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3314 }
3315 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3316 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3317
55c4665e 3318 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3319 SDHCI_MAX_CURRENT_300_MASK) >>
3320 SDHCI_MAX_CURRENT_300_SHIFT) *
3321 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3322 }
3323 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3324 ocr_avail |= MMC_VDD_165_195;
3325
55c4665e 3326 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3327 SDHCI_MAX_CURRENT_180_MASK) >>
3328 SDHCI_MAX_CURRENT_180_SHIFT) *
3329 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3330 }
3331
52221610 3332 /* If OCR set by external regulators, use it instead */
3a48edc4 3333 if (mmc->ocr_avail)
52221610 3334 ocr_avail = mmc->ocr_avail;
3a48edc4 3335
c0b887b6 3336 if (host->ocr_mask)
3a48edc4 3337 ocr_avail &= host->ocr_mask;
c0b887b6 3338
8f230f45
TI		 3339 mmc->ocr_avail = ocr_avail;
3340 mmc->ocr_avail_sdio = ocr_avail;
3341 if (host->ocr_avail_sdio)
3342 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3343 mmc->ocr_avail_sd = ocr_avail;
3344 if (host->ocr_avail_sd)
3345 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3346 else /* normal SD controllers don't support 1.8V */
3347 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3348 mmc->ocr_avail_mmc = ocr_avail;
3349 if (host->ocr_avail_mmc)
3350 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3351
3352 if (mmc->ocr_avail == 0) {
a3c76eb9 3353 pr_err("%s: Hardware doesn't report any "
b69c9058 3354 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3355 return -ENODEV;
146ad66e
PO		 3356 }
3357
d129bceb
PO		 3358 spin_lock_init(&host->lock);
3359
3360 /*
2134a922
PO		 3361 * Maximum number of segments. Depends on if the hardware
3362 * can do scatter/gather or not.
d129bceb 3363 */
2134a922 3364 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3365 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3366 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3367 mmc->max_segs = 1;
2134a922 3368 else /* PIO */
4fb213f8 3369 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3370
3371 /*
ac00531d
AH		 3372 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3373 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3374 * is less anyway.
d129bceb 3375 */
55db890a 3376 mmc->max_req_size = 524288;
d129bceb
PO		 3377
3378 /*
3379 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3380 * of bytes. When doing hardware scatter/gather, each entry cannot
3381 * be larger than 64 KiB though.
d129bceb 3382 */
30652aa3
OJ		 3383 if (host->flags & SDHCI_USE_ADMA) {
3384 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3385 mmc->max_seg_size = 65535;
3386 else
3387 mmc->max_seg_size = 65536;
3388 } else {
2134a922 3389 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3390 }
d129bceb 3391
fe4a3c7a
PO		 3392 /*
3393 * Maximum block size. This varies from controller to controller and
3394 * is specified in the capabilities register.
3395 */
0633f654
AV		 3396 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3397 mmc->max_blk_size = 2;
3398 } else {
f2119df6 3399 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3400 SDHCI_MAX_BLOCK_SHIFT;
3401 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3402 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3403 mmc_hostname(mmc));
0633f654
AV		 3404 mmc->max_blk_size = 0;
3405 }
3406 }
3407
3408 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3409
55db890a
PO		 3410 /*
3411 * Maximum block count.
3412 */
1388eefd 3413 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3414
d129bceb
PO		 3415 /*
3416 * Init tasklets.
3417 */
d129bceb
PO		 3418 tasklet_init(&host->finish_tasklet,
3419 sdhci_tasklet_finish, (unsigned long)host);
3420
e4cad1b5 3421 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3422
250fb7b4 3423 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3424
250fb7b4 3425 if (host->version >= SDHCI_SPEC_300) {
cf2b5eea
AN		 3426 /* Initialize re-tuning timer */
3427 init_timer(&host->tuning_timer);
3428 host->tuning_timer.data = (unsigned long)host;
3429 host->tuning_timer.function = sdhci_tuning_timer;
3430 }
3431
2af502ca
SG		 3432 sdhci_init(host, 0);
3433
781e989c
RK		 3434 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3435 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3436 if (ret) {
3437 pr_err("%s: Failed to request IRQ %d: %d\n",
3438 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3439 goto untasklet;
0fc81ee3 3440 }
d129bceb 3441
d129bceb
PO		 3442#ifdef CONFIG_MMC_DEBUG
3443 sdhci_dumpregs(host);
3444#endif
3445
f9134319 3446#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3447 snprintf(host->led_name, sizeof(host->led_name),
3448 "%s::", mmc_hostname(mmc));
3449 host->led.name = host->led_name;
2f730fec
PO		 3450 host->led.brightness = LED_OFF;
3451 host->led.default_trigger = mmc_hostname(mmc);
3452 host->led.brightness_set = sdhci_led_control;
3453
b8c86fc5 3454 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3455 if (ret) {
3456 pr_err("%s: Failed to register LED device: %d\n",
3457 mmc_hostname(mmc), ret);
2f730fec 3458 goto reset;
0fc81ee3 3459 }
2f730fec
PO		 3460#endif
3461
5f25a66f
PO		 3462 mmiowb();
3463
d129bceb
PO		 3464 mmc_add_host(mmc);
3465
a3c76eb9 3466 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3467 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3468 (host->flags & SDHCI_USE_ADMA) ?
3469 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3470 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3471
7260cf5e
AV		 3472 sdhci_enable_card_detection(host);
3473
d129bceb
PO		 3474 return 0;
3475
f9134319 3476#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3477reset:
03231f9b 3478 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3479 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3480 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3481 free_irq(host->irq, host);
3482#endif
8ef1a143 3483untasklet:
d129bceb 3484 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3485
3486 return ret;
3487}
3488
b8c86fc5 3489EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3490
1e72859e 3491void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3492{
3a48edc4 3493 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3494 unsigned long flags;
3495
3496 if (dead) {
3497 spin_lock_irqsave(&host->lock, flags);
3498
3499 host->flags |= SDHCI_DEVICE_DEAD;
3500
3501 if (host->mrq) {
a3c76eb9 3502 pr_err("%s: Controller removed during "
4e743f1f 3503 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3504
3505 host->mrq->cmd->error = -ENOMEDIUM;
3506 tasklet_schedule(&host->finish_tasklet);
3507 }
3508
3509 spin_unlock_irqrestore(&host->lock, flags);
3510 }
3511
7260cf5e
AV		 3512 sdhci_disable_card_detection(host);
3513
4e743f1f 3514 mmc_remove_host(mmc);
d129bceb 3515
f9134319 3516#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3517 led_classdev_unregister(&host->led);
3518#endif
3519
1e72859e 3520 if (!dead)
03231f9b 3521 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3522
b537f94c
RK		 3523 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3524 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3525 free_irq(host->irq, host);
3526
3527 del_timer_sync(&host->timer);
3528
d129bceb 3529 tasklet_kill(&host->finish_tasklet);
2134a922 3530
3a48edc4
TK		 3531 if (!IS_ERR(mmc->supply.vqmmc))
3532 regulator_disable(mmc->supply.vqmmc);
6231f3de 3533
4efaa6fb 3534 if (host->adma_table)
76fe379a 3535 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3536 host->adma_table, host->adma_addr);
2134a922
PO		 3537 kfree(host->align_buffer);
3538
4efaa6fb 3539 host->adma_table = NULL;
2134a922 3540 host->align_buffer = NULL;
d129bceb
PO		 3541}
3542
b8c86fc5 3543EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3544
b8c86fc5 3545void sdhci_free_host(struct sdhci_host *host)
d129bceb 3546{
b8c86fc5 3547 mmc_free_host(host->mmc);
d129bceb
PO		 3548}
3549
b8c86fc5 3550EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3551
3552/*****************************************************************************\
3553 * *
3554 * Driver init/exit *
3555 * *
3556\*****************************************************************************/
3557
3558static int __init sdhci_drv_init(void)
3559{
a3c76eb9 3560 pr_info(DRIVER_NAME
52fbf9c9 3561 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3562 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3563
b8c86fc5 3564 return 0;
d129bceb
PO		 3565}
3566
3567static void __exit sdhci_drv_exit(void)
3568{
d129bceb
PO		 3569}
3570
3571module_init(sdhci_drv_init);
3572module_exit(sdhci_drv_exit);
3573
df673b22 3574module_param(debug_quirks, uint, 0444);
66fd8ad5 3575module_param(debug_quirks2, uint, 0444);
67435274 3576
32710e8f 3577MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3578MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3579MODULE_LICENSE("GPL");
67435274 3580
df673b22 3581MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3582MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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