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mmc: Aggressive clock gating framework
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
9bea3c85 22#include <linux/regulator/consumer.h>
d129bceb 23
2f730fec
PO		 24#include <linux/leds.h>
25
d129bceb 26#include <linux/mmc/host.h>
d129bceb 27
d129bceb
PO		 28#include "sdhci.h"
29
30#define DRIVER_NAME "sdhci"
d129bceb 31
d129bceb 32#define DBG(f, x...) \
c6563178 33 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 34
f9134319
PO		 35#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
36 defined(CONFIG_MMC_SDHCI_MODULE))
37#define SDHCI_USE_LEDS_CLASS
38#endif
39
df673b22 40static unsigned int debug_quirks = 0;
67435274 41
d129bceb
PO		 42static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
43static void sdhci_finish_data(struct sdhci_host *);
44
45static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
46static void sdhci_finish_command(struct sdhci_host *);
47
48static void sdhci_dumpregs(struct sdhci_host *host)
49{
412ab659
PR		 50 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
51 mmc_hostname(host->mmc));
d129bceb
PO		 52
53 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 54 sdhci_readl(host, SDHCI_DMA_ADDRESS),
55 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 56 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 57 sdhci_readw(host, SDHCI_BLOCK_SIZE),
58 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 59 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 60 sdhci_readl(host, SDHCI_ARGUMENT),
61 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 62 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 63 sdhci_readl(host, SDHCI_PRESENT_STATE),
64 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 65 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 66 sdhci_readb(host, SDHCI_POWER_CONTROL),
67 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 68 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 69 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
70 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 71 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 72 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
73 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 74 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 75 sdhci_readl(host, SDHCI_INT_ENABLE),
76 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 77 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readw(host, SDHCI_ACMD12_ERR),
79 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
d129bceb 80 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
4e4141a5
AV		 81 sdhci_readl(host, SDHCI_CAPABILITIES),
82 sdhci_readl(host, SDHCI_MAX_CURRENT));
d129bceb 83
be3f4ae0
BD		 84 if (host->flags & SDHCI_USE_ADMA)
85 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
86 readl(host->ioaddr + SDHCI_ADMA_ERROR),
87 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
88
d129bceb
PO		 89 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
90}
91
92/*****************************************************************************\
93 * *
94 * Low level functions *
95 * *
96\*****************************************************************************/
97
7260cf5e
AV		 98static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
99{
100 u32 ier;
101
102 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
103 ier &= ~clear;
104 ier |= set;
105 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
106 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
107}
108
109static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
110{
111 sdhci_clear_set_irqs(host, 0, irqs);
112}
113
114static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
115{
116 sdhci_clear_set_irqs(host, irqs, 0);
117}
118
119static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
120{
121 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
122
68d1fb7e
AV		 123 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
124 return;
125
7260cf5e
AV		 126 if (enable)
127 sdhci_unmask_irqs(host, irqs);
128 else
129 sdhci_mask_irqs(host, irqs);
130}
131
132static void sdhci_enable_card_detection(struct sdhci_host *host)
133{
134 sdhci_set_card_detection(host, true);
135}
136
137static void sdhci_disable_card_detection(struct sdhci_host *host)
138{
139 sdhci_set_card_detection(host, false);
140}
141
d129bceb
PO		 142static void sdhci_reset(struct sdhci_host *host, u8 mask)
143{
e16514d8 144 unsigned long timeout;
063a9dbb 145 u32 uninitialized_var(ier);
e16514d8 146
b8c86fc5 147 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 148 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 149 SDHCI_CARD_PRESENT))
150 return;
151 }
152
063a9dbb
AV		 153 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
154 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
155
4e4141a5 156 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 157
e16514d8 158 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 159 host->clock = 0;
160
e16514d8
PO		 161 /* Wait max 100 ms */
162 timeout = 100;
163
164 /* hw clears the bit when it's done */
4e4141a5 165 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 166 if (timeout == 0) {
acf1da45 167 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 168 mmc_hostname(host->mmc), (int)mask);
169 sdhci_dumpregs(host);
170 return;
171 }
172 timeout--;
173 mdelay(1);
d129bceb 174 }
063a9dbb
AV		 175
176 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
177 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 178}
179
2f4cbb3d
NP		 180static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
181
182static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 183{
2f4cbb3d
NP		 184 if (soft)
185 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
186 else
187 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 188
7260cf5e
AV		 189 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
190 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 191 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
192 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 193 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 194
195 if (soft) {
196 /* force clock reconfiguration */
197 host->clock = 0;
198 sdhci_set_ios(host->mmc, &host->mmc->ios);
199 }
7260cf5e 200}
d129bceb 201
7260cf5e
AV		 202static void sdhci_reinit(struct sdhci_host *host)
203{
2f4cbb3d 204 sdhci_init(host, 0);
7260cf5e 205 sdhci_enable_card_detection(host);
d129bceb
PO		 206}
207
208static void sdhci_activate_led(struct sdhci_host *host)
209{
210 u8 ctrl;
211
4e4141a5 212 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 213 ctrl |= SDHCI_CTRL_LED;
4e4141a5 214 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 215}
216
217static void sdhci_deactivate_led(struct sdhci_host *host)
218{
219 u8 ctrl;
220
4e4141a5 221 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 222 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 223 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 224}
225
f9134319 226#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 227static void sdhci_led_control(struct led_classdev *led,
228 enum led_brightness brightness)
229{
230 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
231 unsigned long flags;
232
233 spin_lock_irqsave(&host->lock, flags);
234
235 if (brightness == LED_OFF)
236 sdhci_deactivate_led(host);
237 else
238 sdhci_activate_led(host);
239
240 spin_unlock_irqrestore(&host->lock, flags);
241}
242#endif
243
d129bceb
PO		 244/*****************************************************************************\
245 * *
246 * Core functions *
247 * *
248\*****************************************************************************/
249
a406f5a3 250static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 251{
7659150c
PO		 252 unsigned long flags;
253 size_t blksize, len, chunk;
7244b85b 254 u32 uninitialized_var(scratch);
7659150c 255 u8 *buf;
d129bceb 256
a406f5a3 257 DBG("PIO reading\n");
d129bceb 258
a406f5a3 259 blksize = host->data->blksz;
7659150c 260 chunk = 0;
d129bceb 261
7659150c 262 local_irq_save(flags);
d129bceb 263
a406f5a3 264 while (blksize) {
7659150c
PO		 265 if (!sg_miter_next(&host->sg_miter))
266 BUG();
d129bceb 267
7659150c 268 len = min(host->sg_miter.length, blksize);
d129bceb 269
7659150c
PO		 270 blksize -= len;
271 host->sg_miter.consumed = len;
14d836e7 272
7659150c 273 buf = host->sg_miter.addr;
d129bceb 274
7659150c
PO		 275 while (len) {
276 if (chunk == 0) {
4e4141a5 277 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 278 chunk = 4;
a406f5a3 279 }
7659150c
PO		 280
281 *buf = scratch & 0xFF;
282
283 buf++;
284 scratch >>= 8;
285 chunk--;
286 len--;
d129bceb 287 }
a406f5a3 288 }
7659150c
PO		 289
290 sg_miter_stop(&host->sg_miter);
291
292 local_irq_restore(flags);
a406f5a3 293}
d129bceb 294
a406f5a3
PO		 295static void sdhci_write_block_pio(struct sdhci_host *host)
296{
7659150c
PO		 297 unsigned long flags;
298 size_t blksize, len, chunk;
299 u32 scratch;
300 u8 *buf;
d129bceb 301
a406f5a3
PO		 302 DBG("PIO writing\n");
303
304 blksize = host->data->blksz;
7659150c
PO		 305 chunk = 0;
306 scratch = 0;
d129bceb 307
7659150c 308 local_irq_save(flags);
d129bceb 309
a406f5a3 310 while (blksize) {
7659150c
PO		 311 if (!sg_miter_next(&host->sg_miter))
312 BUG();
a406f5a3 313
7659150c
PO		 314 len = min(host->sg_miter.length, blksize);
315
316 blksize -= len;
317 host->sg_miter.consumed = len;
318
319 buf = host->sg_miter.addr;
d129bceb 320
7659150c
PO		 321 while (len) {
322 scratch |= (u32)*buf << (chunk * 8);
323
324 buf++;
325 chunk++;
326 len--;
327
328 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 329 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 330 chunk = 0;
331 scratch = 0;
d129bceb 332 }
d129bceb
PO		 333 }
334 }
7659150c
PO		 335
336 sg_miter_stop(&host->sg_miter);
337
338 local_irq_restore(flags);
a406f5a3
PO		 339}
340
341static void sdhci_transfer_pio(struct sdhci_host *host)
342{
343 u32 mask;
344
345 BUG_ON(!host->data);
346
7659150c 347 if (host->blocks == 0)
a406f5a3
PO		 348 return;
349
350 if (host->data->flags & MMC_DATA_READ)
351 mask = SDHCI_DATA_AVAILABLE;
352 else
353 mask = SDHCI_SPACE_AVAILABLE;
354
4a3cba32
PO		 355 /*
356 * Some controllers (JMicron JMB38x) mess up the buffer bits
357 * for transfers < 4 bytes. As long as it is just one block,
358 * we can ignore the bits.
359 */
360 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
361 (host->data->blocks == 1))
362 mask = ~0;
363
4e4141a5 364 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 365 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
366 udelay(100);
367
a406f5a3
PO		 368 if (host->data->flags & MMC_DATA_READ)
369 sdhci_read_block_pio(host);
370 else
371 sdhci_write_block_pio(host);
d129bceb 372
7659150c
PO		 373 host->blocks--;
374 if (host->blocks == 0)
a406f5a3 375 break;
a406f5a3 376 }
d129bceb 377
a406f5a3 378 DBG("PIO transfer complete.\n");
d129bceb
PO		 379}
380
2134a922
PO		 381static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
382{
383 local_irq_save(*flags);
384 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
385}
386
387static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
388{
389 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
390 local_irq_restore(*flags);
391}
392
118cd17d
BD		 393static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
394{
9e506f35
BD		 395 __le32 *dataddr = (__le32 __force *)(desc + 4);
396 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 397
9e506f35
BD		 398 /* SDHCI specification says ADMA descriptors should be 4 byte
399 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 400
9e506f35
BD		 401 cmdlen[0] = cpu_to_le16(cmd);
402 cmdlen[1] = cpu_to_le16(len);
403
404 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 405}
406
8f1934ce 407static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 408 struct mmc_data *data)
409{
410 int direction;
411
412 u8 *desc;
413 u8 *align;
414 dma_addr_t addr;
415 dma_addr_t align_addr;
416 int len, offset;
417
418 struct scatterlist *sg;
419 int i;
420 char *buffer;
421 unsigned long flags;
422
423 /*
424 * The spec does not specify endianness of descriptor table.
425 * We currently guess that it is LE.
426 */
427
428 if (data->flags & MMC_DATA_READ)
429 direction = DMA_FROM_DEVICE;
430 else
431 direction = DMA_TO_DEVICE;
432
433 /*
434 * The ADMA descriptor table is mapped further down as we
435 * need to fill it with data first.
436 */
437
438 host->align_addr = dma_map_single(mmc_dev(host->mmc),
439 host->align_buffer, 128 * 4, direction);
8d8bb39b 440 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 441 goto fail;
2134a922
PO		 442 BUG_ON(host->align_addr & 0x3);
443
444 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
445 data->sg, data->sg_len, direction);
8f1934ce
PO		 446 if (host->sg_count == 0)
447 goto unmap_align;
2134a922
PO		 448
449 desc = host->adma_desc;
450 align = host->align_buffer;
451
452 align_addr = host->align_addr;
453
454 for_each_sg(data->sg, sg, host->sg_count, i) {
455 addr = sg_dma_address(sg);
456 len = sg_dma_len(sg);
457
458 /*
459 * The SDHCI specification states that ADMA
460 * addresses must be 32-bit aligned. If they
461 * aren't, then we use a bounce buffer for
462 * the (up to three) bytes that screw up the
463 * alignment.
464 */
465 offset = (4 - (addr & 0x3)) & 0x3;
466 if (offset) {
467 if (data->flags & MMC_DATA_WRITE) {
468 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 469 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 470 memcpy(align, buffer, offset);
471 sdhci_kunmap_atomic(buffer, &flags);
472 }
473
118cd17d
BD		 474 /* tran, valid */
475 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 476
477 BUG_ON(offset > 65536);
478
2134a922
PO		 479 align += 4;
480 align_addr += 4;
481
482 desc += 8;
483
484 addr += offset;
485 len -= offset;
486 }
487
2134a922
PO		 488 BUG_ON(len > 65536);
489
118cd17d
BD		 490 /* tran, valid */
491 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 492 desc += 8;
493
494 /*
495 * If this triggers then we have a calculation bug
496 * somewhere. :/
497 */
498 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
499 }
500
70764a90
TA		 501 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
502 /*
503 * Mark the last descriptor as the terminating descriptor
504 */
505 if (desc != host->adma_desc) {
506 desc -= 8;
507 desc[0] |= 0x2; /* end */
508 }
509 } else {
510 /*
511 * Add a terminating entry.
512 */
2134a922 513
70764a90
TA		 514 /* nop, end, valid */
515 sdhci_set_adma_desc(desc, 0, 0, 0x3);
516 }
2134a922
PO		 517
518 /*
519 * Resync align buffer as we might have changed it.
520 */
521 if (data->flags & MMC_DATA_WRITE) {
522 dma_sync_single_for_device(mmc_dev(host->mmc),
523 host->align_addr, 128 * 4, direction);
524 }
525
526 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
527 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 528 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 529 goto unmap_entries;
2134a922 530 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 531
532 return 0;
533
534unmap_entries:
535 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
536 data->sg_len, direction);
537unmap_align:
538 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
539 128 * 4, direction);
540fail:
541 return -EINVAL;
2134a922
PO		 542}
543
544static void sdhci_adma_table_post(struct sdhci_host *host,
545 struct mmc_data *data)
546{
547 int direction;
548
549 struct scatterlist *sg;
550 int i, size;
551 u8 *align;
552 char *buffer;
553 unsigned long flags;
554
555 if (data->flags & MMC_DATA_READ)
556 direction = DMA_FROM_DEVICE;
557 else
558 direction = DMA_TO_DEVICE;
559
560 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
561 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
562
563 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
564 128 * 4, direction);
565
566 if (data->flags & MMC_DATA_READ) {
567 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
568 data->sg_len, direction);
569
570 align = host->align_buffer;
571
572 for_each_sg(data->sg, sg, host->sg_count, i) {
573 if (sg_dma_address(sg) & 0x3) {
574 size = 4 - (sg_dma_address(sg) & 0x3);
575
576 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 577 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 578 memcpy(buffer, align, size);
579 sdhci_kunmap_atomic(buffer, &flags);
580
581 align += 4;
582 }
583 }
584 }
585
586 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
587 data->sg_len, direction);
588}
589
ee53ab5d 590static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
d129bceb 591{
1c8cde92
PO		 592 u8 count;
593 unsigned target_timeout, current_timeout;
d129bceb 594
ee53ab5d
PO		 595 /*
596 * If the host controller provides us with an incorrect timeout
597 * value, just skip the check and use 0xE. The hardware may take
598 * longer to time out, but that's much better than having a too-short
599 * timeout value.
600 */
11a2f1b7 601 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 602 return 0xE;
e538fbe8 603
1c8cde92
PO		 604 /* timeout in us */
605 target_timeout = data->timeout_ns / 1000 +
606 data->timeout_clks / host->clock;
d129bceb 607
81b39802
AV		 608 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
609 host->timeout_clk = host->clock / 1000;
610
1c8cde92
PO		 611 /*
612 * Figure out needed cycles.
613 * We do this in steps in order to fit inside a 32 bit int.
614 * The first step is the minimum timeout, which will have a
615 * minimum resolution of 6 bits:
616 * (1) 2^13*1000 > 2^22,
617 * (2) host->timeout_clk < 2^16
618 * =>
619 * (1) / (2) > 2^6
620 */
621 count = 0;
622 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
623 while (current_timeout < target_timeout) {
624 count++;
625 current_timeout <<= 1;
626 if (count >= 0xF)
627 break;
628 }
629
630 if (count >= 0xF) {
631 printk(KERN_WARNING "%s: Too large timeout requested!\n",
632 mmc_hostname(host->mmc));
633 count = 0xE;
634 }
635
ee53ab5d
PO		 636 return count;
637}
638
6aa943ab
AV		 639static void sdhci_set_transfer_irqs(struct sdhci_host *host)
640{
641 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
642 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
643
644 if (host->flags & SDHCI_REQ_USE_DMA)
645 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
646 else
647 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
648}
649
ee53ab5d
PO		 650static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
651{
652 u8 count;
2134a922 653 u8 ctrl;
8f1934ce 654 int ret;
ee53ab5d
PO		 655
656 WARN_ON(host->data);
657
658 if (data == NULL)
659 return;
660
661 /* Sanity checks */
662 BUG_ON(data->blksz * data->blocks > 524288);
663 BUG_ON(data->blksz > host->mmc->max_blk_size);
664 BUG_ON(data->blocks > 65535);
665
666 host->data = data;
667 host->data_early = 0;
668
669 count = sdhci_calc_timeout(host, data);
4e4141a5 670 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
d129bceb 671
a13abc7b 672 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 673 host->flags |= SDHCI_REQ_USE_DMA;
674
2134a922
PO		 675 /*
676 * FIXME: This doesn't account for merging when mapping the
677 * scatterlist.
678 */
679 if (host->flags & SDHCI_REQ_USE_DMA) {
680 int broken, i;
681 struct scatterlist *sg;
682
683 broken = 0;
684 if (host->flags & SDHCI_USE_ADMA) {
685 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
686 broken = 1;
687 } else {
688 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
689 broken = 1;
690 }
691
692 if (unlikely(broken)) {
693 for_each_sg(data->sg, sg, data->sg_len, i) {
694 if (sg->length & 0x3) {
695 DBG("Reverting to PIO because of "
696 "transfer size (%d)\n",
697 sg->length);
698 host->flags &= ~SDHCI_REQ_USE_DMA;
699 break;
700 }
701 }
702 }
c9fddbc4
PO		 703 }
704
705 /*
706 * The assumption here being that alignment is the same after
707 * translation to device address space.
708 */
2134a922
PO		 709 if (host->flags & SDHCI_REQ_USE_DMA) {
710 int broken, i;
711 struct scatterlist *sg;
712
713 broken = 0;
714 if (host->flags & SDHCI_USE_ADMA) {
715 /*
716 * As we use 3 byte chunks to work around
717 * alignment problems, we need to check this
718 * quirk.
719 */
720 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
721 broken = 1;
722 } else {
723 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
724 broken = 1;
725 }
726
727 if (unlikely(broken)) {
728 for_each_sg(data->sg, sg, data->sg_len, i) {
729 if (sg->offset & 0x3) {
730 DBG("Reverting to PIO because of "
731 "bad alignment\n");
732 host->flags &= ~SDHCI_REQ_USE_DMA;
733 break;
734 }
735 }
736 }
737 }
738
8f1934ce
PO		 739 if (host->flags & SDHCI_REQ_USE_DMA) {
740 if (host->flags & SDHCI_USE_ADMA) {
741 ret = sdhci_adma_table_pre(host, data);
742 if (ret) {
743 /*
744 * This only happens when someone fed
745 * us an invalid request.
746 */
747 WARN_ON(1);
ebd6d357 748 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 749 } else {
4e4141a5
AV		 750 sdhci_writel(host, host->adma_addr,
751 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 752 }
753 } else {
c8b3e02e 754 int sg_cnt;
8f1934ce 755
c8b3e02e 756 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 757 data->sg, data->sg_len,
758 (data->flags & MMC_DATA_READ) ?
759 DMA_FROM_DEVICE :
760 DMA_TO_DEVICE);
c8b3e02e 761 if (sg_cnt == 0) {
8f1934ce
PO		 762 /*
763 * This only happens when someone fed
764 * us an invalid request.
765 */
766 WARN_ON(1);
ebd6d357 767 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 768 } else {
719a61b4 769 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 770 sdhci_writel(host, sg_dma_address(data->sg),
771 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 772 }
773 }
774 }
775
2134a922
PO		 776 /*
777 * Always adjust the DMA selection as some controllers
778 * (e.g. JMicron) can't do PIO properly when the selection
779 * is ADMA.
780 */
781 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 782 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 783 ctrl &= ~SDHCI_CTRL_DMA_MASK;
784 if ((host->flags & SDHCI_REQ_USE_DMA) &&
785 (host->flags & SDHCI_USE_ADMA))
786 ctrl |= SDHCI_CTRL_ADMA32;
787 else
788 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 789 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 790 }
791
8f1934ce 792 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 793 int flags;
794
795 flags = SG_MITER_ATOMIC;
796 if (host->data->flags & MMC_DATA_READ)
797 flags |= SG_MITER_TO_SG;
798 else
799 flags |= SG_MITER_FROM_SG;
800 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 801 host->blocks = data->blocks;
d129bceb 802 }
c7fa9963 803
6aa943ab
AV		 804 sdhci_set_transfer_irqs(host);
805
bab76961 806 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
4e4141a5
AV		 807 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
808 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 809}
810
811static void sdhci_set_transfer_mode(struct sdhci_host *host,
812 struct mmc_data *data)
813{
814 u16 mode;
815
c7fa9963
PO		 816 if (data == NULL)
817 return;
818
e538fbe8
PO		 819 WARN_ON(!host->data);
820
c7fa9963 821 mode = SDHCI_TRNS_BLK_CNT_EN;
c4512f79
JH		 822 if (data->blocks > 1) {
823 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
824 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
825 else
826 mode |= SDHCI_TRNS_MULTI;
827 }
c7fa9963
PO		 828 if (data->flags & MMC_DATA_READ)
829 mode |= SDHCI_TRNS_READ;
c9fddbc4 830 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 831 mode |= SDHCI_TRNS_DMA;
832
4e4141a5 833 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 834}
835
836static void sdhci_finish_data(struct sdhci_host *host)
837{
838 struct mmc_data *data;
d129bceb
PO		 839
840 BUG_ON(!host->data);
841
842 data = host->data;
843 host->data = NULL;
844
c9fddbc4 845 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 846 if (host->flags & SDHCI_USE_ADMA)
847 sdhci_adma_table_post(host, data);
848 else {
849 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
850 data->sg_len, (data->flags & MMC_DATA_READ) ?
851 DMA_FROM_DEVICE : DMA_TO_DEVICE);
852 }
d129bceb
PO		 853 }
854
855 /*
c9b74c5b
PO		 856 * The specification states that the block count register must
857 * be updated, but it does not specify at what point in the
858 * data flow. That makes the register entirely useless to read
859 * back so we have to assume that nothing made it to the card
860 * in the event of an error.
d129bceb 861 */
c9b74c5b
PO		 862 if (data->error)
863 data->bytes_xfered = 0;
d129bceb 864 else
c9b74c5b 865 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 866
d129bceb
PO		 867 if (data->stop) {
868 /*
869 * The controller needs a reset of internal state machines
870 * upon error conditions.
871 */
17b0429d 872 if (data->error) {
d129bceb
PO		 873 sdhci_reset(host, SDHCI_RESET_CMD);
874 sdhci_reset(host, SDHCI_RESET_DATA);
875 }
876
877 sdhci_send_command(host, data->stop);
878 } else
879 tasklet_schedule(&host->finish_tasklet);
880}
881
882static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
883{
884 int flags;
fd2208d7 885 u32 mask;
7cb2c76f 886 unsigned long timeout;
d129bceb
PO		 887
888 WARN_ON(host->cmd);
889
d129bceb 890 /* Wait max 10 ms */
7cb2c76f 891 timeout = 10;
fd2208d7
PO		 892
893 mask = SDHCI_CMD_INHIBIT;
894 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
895 mask |= SDHCI_DATA_INHIBIT;
896
897 /* We shouldn't wait for data inihibit for stop commands, even
898 though they might use busy signaling */
899 if (host->mrq->data && (cmd == host->mrq->data->stop))
900 mask &= ~SDHCI_DATA_INHIBIT;
901
4e4141a5 902 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 903 if (timeout == 0) {
d129bceb 904 printk(KERN_ERR "%s: Controller never released "
acf1da45 905 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 906 sdhci_dumpregs(host);
17b0429d 907 cmd->error = -EIO;
d129bceb
PO		 908 tasklet_schedule(&host->finish_tasklet);
909 return;
910 }
7cb2c76f
PO		 911 timeout--;
912 mdelay(1);
913 }
d129bceb
PO		 914
915 mod_timer(&host->timer, jiffies + 10 * HZ);
916
917 host->cmd = cmd;
918
919 sdhci_prepare_data(host, cmd->data);
920
4e4141a5 921 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 922
c7fa9963
PO		 923 sdhci_set_transfer_mode(host, cmd->data);
924
d129bceb 925 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 926 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 927 mmc_hostname(host->mmc));
17b0429d 928 cmd->error = -EINVAL;
d129bceb
PO		 929 tasklet_schedule(&host->finish_tasklet);
930 return;
931 }
932
933 if (!(cmd->flags & MMC_RSP_PRESENT))
934 flags = SDHCI_CMD_RESP_NONE;
935 else if (cmd->flags & MMC_RSP_136)
936 flags = SDHCI_CMD_RESP_LONG;
937 else if (cmd->flags & MMC_RSP_BUSY)
938 flags = SDHCI_CMD_RESP_SHORT_BUSY;
939 else
940 flags = SDHCI_CMD_RESP_SHORT;
941
942 if (cmd->flags & MMC_RSP_CRC)
943 flags |= SDHCI_CMD_CRC;
944 if (cmd->flags & MMC_RSP_OPCODE)
945 flags |= SDHCI_CMD_INDEX;
946 if (cmd->data)
947 flags |= SDHCI_CMD_DATA;
948
4e4141a5 949 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 950}
951
952static void sdhci_finish_command(struct sdhci_host *host)
953{
954 int i;
955
956 BUG_ON(host->cmd == NULL);
957
958 if (host->cmd->flags & MMC_RSP_PRESENT) {
959 if (host->cmd->flags & MMC_RSP_136) {
960 /* CRC is stripped so we need to do some shifting. */
961 for (i = 0;i < 4;i++) {
4e4141a5 962 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 963 SDHCI_RESPONSE + (3-i)*4) << 8;
964 if (i != 3)
965 host->cmd->resp[i] |=
4e4141a5 966 sdhci_readb(host,
d129bceb
PO		 967 SDHCI_RESPONSE + (3-i)*4-1);
968 }
969 } else {
4e4141a5 970 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 971 }
972 }
973
17b0429d 974 host->cmd->error = 0;
d129bceb 975
e538fbe8
PO		 976 if (host->data && host->data_early)
977 sdhci_finish_data(host);
978
979 if (!host->cmd->data)
d129bceb
PO		 980 tasklet_schedule(&host->finish_tasklet);
981
982 host->cmd = NULL;
983}
984
985static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
986{
987 int div;
988 u16 clk;
7cb2c76f 989 unsigned long timeout;
d129bceb
PO		 990
991 if (clock == host->clock)
992 return;
993
8114634c
AV		 994 if (host->ops->set_clock) {
995 host->ops->set_clock(host, clock);
996 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
997 return;
998 }
999
4e4141a5 1000 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1001
1002 if (clock == 0)
1003 goto out;
1004
85105c53
ZG		 1005 if (host->version >= SDHCI_SPEC_300) {
1006 /* Version 3.00 divisors must be a multiple of 2. */
1007 if (host->max_clk <= clock)
1008 div = 1;
1009 else {
0397526d 1010 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
85105c53
ZG		 1011 if ((host->max_clk / div) <= clock)
1012 break;
1013 }
1014 }
1015 } else {
1016 /* Version 2.00 divisors must be a power of 2. */
0397526d 1017 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1018 if ((host->max_clk / div) <= clock)
1019 break;
1020 }
d129bceb
PO		 1021 }
1022 div >>= 1;
1023
85105c53
ZG		 1024 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1025 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1026 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1027 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1028 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1029
27f6cb16
CB		 1030 /* Wait max 20 ms */
1031 timeout = 20;
4e4141a5 1032 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1033 & SDHCI_CLOCK_INT_STABLE)) {
1034 if (timeout == 0) {
acf1da45
PO		 1035 printk(KERN_ERR "%s: Internal clock never "
1036 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1037 sdhci_dumpregs(host);
1038 return;
1039 }
7cb2c76f
PO		 1040 timeout--;
1041 mdelay(1);
1042 }
d129bceb
PO		 1043
1044 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1045 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1046
1047out:
1048 host->clock = clock;
1049}
1050
146ad66e
PO		 1051static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1052{
8364248a 1053 u8 pwr = 0;
146ad66e 1054
8364248a 1055 if (power != (unsigned short)-1) {
ae628903
PO		 1056 switch (1 << power) {
1057 case MMC_VDD_165_195:
1058 pwr = SDHCI_POWER_180;
1059 break;
1060 case MMC_VDD_29_30:
1061 case MMC_VDD_30_31:
1062 pwr = SDHCI_POWER_300;
1063 break;
1064 case MMC_VDD_32_33:
1065 case MMC_VDD_33_34:
1066 pwr = SDHCI_POWER_330;
1067 break;
1068 default:
1069 BUG();
1070 }
1071 }
1072
1073 if (host->pwr == pwr)
146ad66e
PO		 1074 return;
1075
ae628903
PO		 1076 host->pwr = pwr;
1077
1078 if (pwr == 0) {
4e4141a5 1079 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1080 return;
9e9dc5f2
DS		 1081 }
1082
1083 /*
1084 * Spec says that we should clear the power reg before setting
1085 * a new value. Some controllers don't seem to like this though.
1086 */
b8c86fc5 1087 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1088 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1089
e08c1694 1090 /*
c71f6512 1091 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1092 * and set turn on power at the same time, so set the voltage first.
1093 */
11a2f1b7 1094 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1095 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1096
ae628903 1097 pwr |= SDHCI_POWER_ON;
146ad66e 1098
ae628903 1099 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1100
1101 /*
1102 * Some controllers need an extra 10ms delay of 10ms before they
1103 * can apply clock after applying power
1104 */
11a2f1b7 1105 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1106 mdelay(10);
146ad66e
PO		 1107}
1108
d129bceb
PO		 1109/*****************************************************************************\
1110 * *
1111 * MMC callbacks *
1112 * *
1113\*****************************************************************************/
1114
1115static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1116{
1117 struct sdhci_host *host;
68d1fb7e 1118 bool present;
d129bceb
PO		 1119 unsigned long flags;
1120
1121 host = mmc_priv(mmc);
1122
1123 spin_lock_irqsave(&host->lock, flags);
1124
1125 WARN_ON(host->mrq != NULL);
1126
f9134319 1127#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1128 sdhci_activate_led(host);
2f730fec 1129#endif
c4512f79
JH		 1130 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1131 if (mrq->stop) {
1132 mrq->data->stop = NULL;
1133 mrq->stop = NULL;
1134 }
1135 }
d129bceb
PO		 1136
1137 host->mrq = mrq;
1138
68d1fb7e
AV		 1139 /* If polling, assume that the card is always present. */
1140 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1141 present = true;
1142 else
1143 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1144 SDHCI_CARD_PRESENT;
1145
1146 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1147 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1148 tasklet_schedule(&host->finish_tasklet);
1149 } else
1150 sdhci_send_command(host, mrq->cmd);
1151
5f25a66f 1152 mmiowb();
d129bceb
PO		 1153 spin_unlock_irqrestore(&host->lock, flags);
1154}
1155
1156static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1157{
1158 struct sdhci_host *host;
1159 unsigned long flags;
1160 u8 ctrl;
1161
1162 host = mmc_priv(mmc);
1163
1164 spin_lock_irqsave(&host->lock, flags);
1165
1e72859e
PO		 1166 if (host->flags & SDHCI_DEVICE_DEAD)
1167 goto out;
1168
d129bceb
PO		 1169 /*
1170 * Reset the chip on each power off.
1171 * Should clear out any weird states.
1172 */
1173 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1174 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1175 sdhci_reinit(host);
d129bceb
PO		 1176 }
1177
1178 sdhci_set_clock(host, ios->clock);
1179
1180 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1181 sdhci_set_power(host, -1);
d129bceb 1182 else
146ad66e 1183 sdhci_set_power(host, ios->vdd);
d129bceb 1184
643a81ff
PR		 1185 if (host->ops->platform_send_init_74_clocks)
1186 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1187
15ec4461
PR		 1188 /*
1189 * If your platform has 8-bit width support but is not a v3 controller,
1190 * or if it requires special setup code, you should implement that in
1191 * platform_8bit_width().
1192 */
1193 if (host->ops->platform_8bit_width)
1194 host->ops->platform_8bit_width(host, ios->bus_width);
1195 else {
1196 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1197 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1198 ctrl &= ~SDHCI_CTRL_4BITBUS;
1199 if (host->version >= SDHCI_SPEC_300)
1200 ctrl |= SDHCI_CTRL_8BITBUS;
1201 } else {
1202 if (host->version >= SDHCI_SPEC_300)
1203 ctrl &= ~SDHCI_CTRL_8BITBUS;
1204 if (ios->bus_width == MMC_BUS_WIDTH_4)
1205 ctrl |= SDHCI_CTRL_4BITBUS;
1206 else
1207 ctrl &= ~SDHCI_CTRL_4BITBUS;
1208 }
1209 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1210 }
ae6d6c92 1211
15ec4461 1212 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1213
3ab9c8da
PR		 1214 if ((ios->timing == MMC_TIMING_SD_HS ||
1215 ios->timing == MMC_TIMING_MMC_HS)
1216 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1217 ctrl |= SDHCI_CTRL_HISPD;
1218 else
1219 ctrl &= ~SDHCI_CTRL_HISPD;
1220
4e4141a5 1221 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb 1222
b8352260
LD		 1223 /*
1224 * Some (ENE) controllers go apeshit on some ios operation,
1225 * signalling timeout and CRC errors even on CMD0. Resetting
1226 * it on each ios seems to solve the problem.
1227 */
b8c86fc5 1228 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1229 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1230
1e72859e 1231out:
5f25a66f 1232 mmiowb();
d129bceb
PO		 1233 spin_unlock_irqrestore(&host->lock, flags);
1234}
1235
1236static int sdhci_get_ro(struct mmc_host *mmc)
1237{
1238 struct sdhci_host *host;
1239 unsigned long flags;
2dfb579c 1240 int is_readonly;
d129bceb
PO		 1241
1242 host = mmc_priv(mmc);
1243
1244 spin_lock_irqsave(&host->lock, flags);
1245
1e72859e 1246 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1247 is_readonly = 0;
1248 else if (host->ops->get_ro)
1249 is_readonly = host->ops->get_ro(host);
1e72859e 1250 else
2dfb579c
WS		 1251 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1252 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1253
1254 spin_unlock_irqrestore(&host->lock, flags);
1255
2dfb579c
WS		 1256 /* This quirk needs to be replaced by a callback-function later */
1257 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1258 !is_readonly : is_readonly;
d129bceb
PO		 1259}
1260
f75979b7
PO		 1261static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1262{
1263 struct sdhci_host *host;
1264 unsigned long flags;
f75979b7
PO		 1265
1266 host = mmc_priv(mmc);
1267
1268 spin_lock_irqsave(&host->lock, flags);
1269
1e72859e
PO		 1270 if (host->flags & SDHCI_DEVICE_DEAD)
1271 goto out;
1272
f75979b7 1273 if (enable)
7260cf5e
AV		 1274 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1275 else
1276 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1277out:
f75979b7
PO		 1278 mmiowb();
1279
1280 spin_unlock_irqrestore(&host->lock, flags);
1281}
1282
ab7aefd0 1283static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1284 .request = sdhci_request,
1285 .set_ios = sdhci_set_ios,
1286 .get_ro = sdhci_get_ro,
f75979b7 1287 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 1288};
1289
1290/*****************************************************************************\
1291 * *
1292 * Tasklets *
1293 * *
1294\*****************************************************************************/
1295
1296static void sdhci_tasklet_card(unsigned long param)
1297{
1298 struct sdhci_host *host;
1299 unsigned long flags;
1300
1301 host = (struct sdhci_host*)param;
1302
1303 spin_lock_irqsave(&host->lock, flags);
1304
4e4141a5 1305 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1306 if (host->mrq) {
1307 printk(KERN_ERR "%s: Card removed during transfer!\n",
1308 mmc_hostname(host->mmc));
1309 printk(KERN_ERR "%s: Resetting controller.\n",
1310 mmc_hostname(host->mmc));
1311
1312 sdhci_reset(host, SDHCI_RESET_CMD);
1313 sdhci_reset(host, SDHCI_RESET_DATA);
1314
17b0429d 1315 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1316 tasklet_schedule(&host->finish_tasklet);
1317 }
1318 }
1319
1320 spin_unlock_irqrestore(&host->lock, flags);
1321
04cf585d 1322 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1323}
1324
1325static void sdhci_tasklet_finish(unsigned long param)
1326{
1327 struct sdhci_host *host;
1328 unsigned long flags;
1329 struct mmc_request *mrq;
1330
1331 host = (struct sdhci_host*)param;
1332
1333 spin_lock_irqsave(&host->lock, flags);
1334
1335 del_timer(&host->timer);
1336
1337 mrq = host->mrq;
1338
d129bceb
PO		 1339 /*
1340 * The controller needs a reset of internal state machines
1341 * upon error conditions.
1342 */
1e72859e
PO		 1343 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1344 (mrq->cmd->error ||
1345 (mrq->data && (mrq->data->error ||
1346 (mrq->data->stop && mrq->data->stop->error))) ||
1347 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1348
1349 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1350 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1351 unsigned int clock;
1352
1353 /* This is to force an update */
1354 clock = host->clock;
1355 host->clock = 0;
1356 sdhci_set_clock(host, clock);
1357 }
1358
1359 /* Spec says we should do both at the same time, but Ricoh
1360 controllers do not like that. */
d129bceb
PO		 1361 sdhci_reset(host, SDHCI_RESET_CMD);
1362 sdhci_reset(host, SDHCI_RESET_DATA);
1363 }
1364
1365 host->mrq = NULL;
1366 host->cmd = NULL;
1367 host->data = NULL;
1368
f9134319 1369#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1370 sdhci_deactivate_led(host);
2f730fec 1371#endif
d129bceb 1372
5f25a66f 1373 mmiowb();
d129bceb
PO		 1374 spin_unlock_irqrestore(&host->lock, flags);
1375
1376 mmc_request_done(host->mmc, mrq);
1377}
1378
1379static void sdhci_timeout_timer(unsigned long data)
1380{
1381 struct sdhci_host *host;
1382 unsigned long flags;
1383
1384 host = (struct sdhci_host*)data;
1385
1386 spin_lock_irqsave(&host->lock, flags);
1387
1388 if (host->mrq) {
acf1da45
PO		 1389 printk(KERN_ERR "%s: Timeout waiting for hardware "
1390 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1391 sdhci_dumpregs(host);
1392
1393 if (host->data) {
17b0429d 1394 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1395 sdhci_finish_data(host);
1396 } else {
1397 if (host->cmd)
17b0429d 1398 host->cmd->error = -ETIMEDOUT;
d129bceb 1399 else
17b0429d 1400 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1401
1402 tasklet_schedule(&host->finish_tasklet);
1403 }
1404 }
1405
5f25a66f 1406 mmiowb();
d129bceb
PO		 1407 spin_unlock_irqrestore(&host->lock, flags);
1408}
1409
1410/*****************************************************************************\
1411 * *
1412 * Interrupt handling *
1413 * *
1414\*****************************************************************************/
1415
1416static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1417{
1418 BUG_ON(intmask == 0);
1419
1420 if (!host->cmd) {
b67ac3f3
PO		 1421 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1422 "though no command operation was in progress.\n",
1423 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1424 sdhci_dumpregs(host);
1425 return;
1426 }
1427
43b58b36 1428 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1429 host->cmd->error = -ETIMEDOUT;
1430 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1431 SDHCI_INT_INDEX))
1432 host->cmd->error = -EILSEQ;
43b58b36 1433
e809517f 1434 if (host->cmd->error) {
d129bceb 1435 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1436 return;
1437 }
1438
1439 /*
1440 * The host can send and interrupt when the busy state has
1441 * ended, allowing us to wait without wasting CPU cycles.
1442 * Unfortunately this is overloaded on the "data complete"
1443 * interrupt, so we need to take some care when handling
1444 * it.
1445 *
1446 * Note: The 1.0 specification is a bit ambiguous about this
1447 * feature so there might be some problems with older
1448 * controllers.
1449 */
1450 if (host->cmd->flags & MMC_RSP_BUSY) {
1451 if (host->cmd->data)
1452 DBG("Cannot wait for busy signal when also "
1453 "doing a data transfer");
f945405c 1454 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1455 return;
f945405c
BD		 1456
1457 /* The controller does not support the end-of-busy IRQ,
1458 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 1459 }
1460
1461 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 1462 sdhci_finish_command(host);
d129bceb
PO		 1463}
1464
0957c333 1465#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 1466static void sdhci_show_adma_error(struct sdhci_host *host)
1467{
1468 const char *name = mmc_hostname(host->mmc);
1469 u8 *desc = host->adma_desc;
1470 __le32 *dma;
1471 __le16 *len;
1472 u8 attr;
1473
1474 sdhci_dumpregs(host);
1475
1476 while (true) {
1477 dma = (__le32 *)(desc + 4);
1478 len = (__le16 *)(desc + 2);
1479 attr = *desc;
1480
1481 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1482 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1483
1484 desc += 8;
1485
1486 if (attr & 2)
1487 break;
1488 }
1489}
1490#else
1491static void sdhci_show_adma_error(struct sdhci_host *host) { }
1492#endif
1493
d129bceb
PO		 1494static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1495{
1496 BUG_ON(intmask == 0);
1497
1498 if (!host->data) {
1499 /*
e809517f
PO		 1500 * The "data complete" interrupt is also used to
1501 * indicate that a busy state has ended. See comment
1502 * above in sdhci_cmd_irq().
d129bceb 1503 */
e809517f
PO		 1504 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1505 if (intmask & SDHCI_INT_DATA_END) {
1506 sdhci_finish_command(host);
1507 return;
1508 }
1509 }
d129bceb 1510
b67ac3f3
PO		 1511 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1512 "though no data operation was in progress.\n",
1513 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1514 sdhci_dumpregs(host);
1515
1516 return;
1517 }
1518
1519 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d
PO		 1520 host->data->error = -ETIMEDOUT;
1521 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1522 host->data->error = -EILSEQ;
6882a8c0
BD		 1523 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1524 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1525 sdhci_show_adma_error(host);
2134a922 1526 host->data->error = -EIO;
6882a8c0 1527 }
d129bceb 1528
17b0429d 1529 if (host->data->error)
d129bceb
PO		 1530 sdhci_finish_data(host);
1531 else {
a406f5a3 1532 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1533 sdhci_transfer_pio(host);
1534
6ba736a1
PO		 1535 /*
1536 * We currently don't do anything fancy with DMA
1537 * boundaries, but as we can't disable the feature
1538 * we need to at least restart the transfer.
1539 */
1540 if (intmask & SDHCI_INT_DMA_END)
4e4141a5
AV		 1541 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1542 SDHCI_DMA_ADDRESS);
6ba736a1 1543
e538fbe8
PO		 1544 if (intmask & SDHCI_INT_DATA_END) {
1545 if (host->cmd) {
1546 /*
1547 * Data managed to finish before the
1548 * command completed. Make sure we do
1549 * things in the proper order.
1550 */
1551 host->data_early = 1;
1552 } else {
1553 sdhci_finish_data(host);
1554 }
1555 }
d129bceb
PO		 1556 }
1557}
1558
7d12e780 1559static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1560{
1561 irqreturn_t result;
1562 struct sdhci_host* host = dev_id;
1563 u32 intmask;
f75979b7 1564 int cardint = 0;
d129bceb
PO		 1565
1566 spin_lock(&host->lock);
1567
4e4141a5 1568 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 1569
62df67a5 1570 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1571 result = IRQ_NONE;
1572 goto out;
1573 }
1574
b69c9058
PO		 1575 DBG("*** %s got interrupt: 0x%08x\n",
1576 mmc_hostname(host->mmc), intmask);
d129bceb 1577
3192a28f 1578 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
4e4141a5
AV		 1579 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1580 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
d129bceb 1581 tasklet_schedule(&host->card_tasklet);
3192a28f 1582 }
d129bceb 1583
3192a28f 1584 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1585
3192a28f 1586 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 1587 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1588 SDHCI_INT_STATUS);
3192a28f 1589 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1590 }
1591
1592 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 1593 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1594 SDHCI_INT_STATUS);
3192a28f 1595 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1596 }
1597
1598 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1599
964f9ce2
PO		 1600 intmask &= ~SDHCI_INT_ERROR;
1601
d129bceb 1602 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1603 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1604 mmc_hostname(host->mmc));
4e4141a5 1605 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 1606 }
1607
9d26a5d3 1608 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1609
f75979b7
PO		 1610 if (intmask & SDHCI_INT_CARD_INT)
1611 cardint = 1;
1612
1613 intmask &= ~SDHCI_INT_CARD_INT;
1614
3192a28f 1615 if (intmask) {
acf1da45 1616 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1617 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1618 sdhci_dumpregs(host);
1619
4e4141a5 1620 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 1621 }
d129bceb
PO		 1622
1623 result = IRQ_HANDLED;
1624
5f25a66f 1625 mmiowb();
d129bceb
PO		 1626out:
1627 spin_unlock(&host->lock);
1628
f75979b7
PO		 1629 /*
1630 * We have to delay this as it calls back into the driver.
1631 */
1632 if (cardint)
1633 mmc_signal_sdio_irq(host->mmc);
1634
d129bceb
PO		 1635 return result;
1636}
1637
1638/*****************************************************************************\
1639 * *
1640 * Suspend/resume *
1641 * *
1642\*****************************************************************************/
1643
1644#ifdef CONFIG_PM
1645
b8c86fc5 1646int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 1647{
b8c86fc5 1648 int ret;
a715dfc7 1649
7260cf5e
AV		 1650 sdhci_disable_card_detection(host);
1651
1a13f8fa 1652 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 1653 if (ret)
1654 return ret;
a715dfc7 1655
b8c86fc5 1656 free_irq(host->irq, host);
d129bceb 1657
9bea3c85
MS		 1658 if (host->vmmc)
1659 ret = regulator_disable(host->vmmc);
1660
1661 return ret;
d129bceb
PO		 1662}
1663
b8c86fc5 1664EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 1665
b8c86fc5
PO		 1666int sdhci_resume_host(struct sdhci_host *host)
1667{
1668 int ret;
d129bceb 1669
9bea3c85
MS		 1670 if (host->vmmc) {
1671 int ret = regulator_enable(host->vmmc);
1672 if (ret)
1673 return ret;
1674 }
1675
1676
a13abc7b 1677 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 1678 if (host->ops->enable_dma)
1679 host->ops->enable_dma(host);
1680 }
d129bceb 1681
b8c86fc5
PO		 1682 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1683 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 1684 if (ret)
1685 return ret;
d129bceb 1686
2f4cbb3d 1687 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 1688 mmiowb();
1689
1690 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 1691 sdhci_enable_card_detection(host);
1692
2f4cbb3d 1693 return ret;
d129bceb
PO		 1694}
1695
b8c86fc5 1696EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 1697
5f619704
DD		 1698void sdhci_enable_irq_wakeups(struct sdhci_host *host)
1699{
1700 u8 val;
1701 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
1702 val |= SDHCI_WAKE_ON_INT;
1703 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
1704}
1705
1706EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
1707
d129bceb
PO		 1708#endif /* CONFIG_PM */
1709
1710/*****************************************************************************\
1711 * *
b8c86fc5 1712 * Device allocation/registration *
d129bceb
PO		 1713 * *
1714\*****************************************************************************/
1715
b8c86fc5
PO		 1716struct sdhci_host *sdhci_alloc_host(struct device *dev,
1717 size_t priv_size)
d129bceb 1718{
d129bceb
PO		 1719 struct mmc_host *mmc;
1720 struct sdhci_host *host;
1721
b8c86fc5 1722 WARN_ON(dev == NULL);
d129bceb 1723
b8c86fc5 1724 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 1725 if (!mmc)
b8c86fc5 1726 return ERR_PTR(-ENOMEM);
d129bceb
PO		 1727
1728 host = mmc_priv(mmc);
1729 host->mmc = mmc;
1730
b8c86fc5
PO		 1731 return host;
1732}
8a4da143 1733
b8c86fc5 1734EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 1735
b8c86fc5
PO		 1736int sdhci_add_host(struct sdhci_host *host)
1737{
1738 struct mmc_host *mmc;
1739 unsigned int caps;
b8c86fc5 1740 int ret;
d129bceb 1741
b8c86fc5
PO		 1742 WARN_ON(host == NULL);
1743 if (host == NULL)
1744 return -EINVAL;
d129bceb 1745
b8c86fc5 1746 mmc = host->mmc;
d129bceb 1747
b8c86fc5
PO		 1748 if (debug_quirks)
1749 host->quirks = debug_quirks;
d129bceb 1750
d96649ed
PO		 1751 sdhci_reset(host, SDHCI_RESET_ALL);
1752
4e4141a5 1753 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 1754 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1755 >> SDHCI_SPEC_VER_SHIFT;
85105c53 1756 if (host->version > SDHCI_SPEC_300) {
4a965505 1757 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 1758 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 1759 host->version);
4a965505
PO		 1760 }
1761
ccc92c23
ML		 1762 caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1763 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 1764
b8c86fc5 1765 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b
RR		 1766 host->flags |= SDHCI_USE_SDMA;
1767 else if (!(caps & SDHCI_CAN_DO_SDMA))
1768 DBG("Controller doesn't have SDMA capability\n");
67435274 1769 else
a13abc7b 1770 host->flags |= SDHCI_USE_SDMA;
d129bceb 1771
b8c86fc5 1772 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 1773 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 1774 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 1775 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 1776 }
1777
a13abc7b
RR		 1778 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1779 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 1780
1781 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1782 (host->flags & SDHCI_USE_ADMA)) {
1783 DBG("Disabling ADMA as it is marked broken\n");
1784 host->flags &= ~SDHCI_USE_ADMA;
1785 }
1786
a13abc7b 1787 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 1788 if (host->ops->enable_dma) {
1789 if (host->ops->enable_dma(host)) {
1790 printk(KERN_WARNING "%s: No suitable DMA "
1791 "available. Falling back to PIO.\n",
1792 mmc_hostname(mmc));
a13abc7b
RR		 1793 host->flags &=
1794 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 1795 }
d129bceb
PO		 1796 }
1797 }
1798
2134a922
PO		 1799 if (host->flags & SDHCI_USE_ADMA) {
1800 /*
1801 * We need to allocate descriptors for all sg entries
1802 * (128) and potentially one alignment transfer for
1803 * each of those entries.
1804 */
1805 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1806 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1807 if (!host->adma_desc || !host->align_buffer) {
1808 kfree(host->adma_desc);
1809 kfree(host->align_buffer);
1810 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1811 "buffers. Falling back to standard DMA.\n",
1812 mmc_hostname(mmc));
1813 host->flags &= ~SDHCI_USE_ADMA;
1814 }
1815 }
1816
7659150c
PO		 1817 /*
1818 * If we use DMA, then it's up to the caller to set the DMA
1819 * mask, but PIO does not need the hw shim so we set a new
1820 * mask here in that case.
1821 */
a13abc7b 1822 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 1823 host->dma_mask = DMA_BIT_MASK(64);
1824 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1825 }
d129bceb 1826
c4687d5f
ZG		 1827 if (host->version >= SDHCI_SPEC_300)
1828 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK)
1829 >> SDHCI_CLOCK_BASE_SHIFT;
1830 else
1831 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK)
1832 >> SDHCI_CLOCK_BASE_SHIFT;
1833
4240ff0a 1834 host->max_clk *= 1000000;
f27f47ef
AV		 1835 if (host->max_clk == 0 || host->quirks &
1836 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a
BD		 1837 if (!host->ops->get_max_clock) {
1838 printk(KERN_ERR
1839 "%s: Hardware doesn't specify base clock "
1840 "frequency.\n", mmc_hostname(mmc));
1841 return -ENODEV;
1842 }
1843 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 1844 }
d129bceb 1845
1c8cde92
PO		 1846 host->timeout_clk =
1847 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1848 if (host->timeout_clk == 0) {
81b39802
AV		 1849 if (host->ops->get_timeout_clock) {
1850 host->timeout_clk = host->ops->get_timeout_clock(host);
1851 } else if (!(host->quirks &
1852 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4240ff0a
BD		 1853 printk(KERN_ERR
1854 "%s: Hardware doesn't specify timeout clock "
1855 "frequency.\n", mmc_hostname(mmc));
1856 return -ENODEV;
1857 }
1c8cde92
PO		 1858 }
1859 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1860 host->timeout_clk *= 1000;
d129bceb
PO		 1861
1862 /*
1863 * Set host parameters.
1864 */
1865 mmc->ops = &sdhci_ops;
ce5f036b 1866 if (host->ops->get_min_clock)
a9e58f25 1867 mmc->f_min = host->ops->get_min_clock(host);
0397526d
ZG		 1868 else if (host->version >= SDHCI_SPEC_300)
1869 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
a9e58f25 1870 else
0397526d 1871 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 1872
d129bceb 1873 mmc->f_max = host->max_clk;
c1f5977c 1874 mmc->caps |= MMC_CAP_SDIO_IRQ;
5fe23c7f 1875
15ec4461
PR		 1876 /*
1877 * A controller may support 8-bit width, but the board itself
1878 * might not have the pins brought out. Boards that support
1879 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
1880 * their platform code before calling sdhci_add_host(), and we
1881 * won't assume 8-bit width for hosts without that CAP.
1882 */
5fe23c7f 1883 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 1884 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 1885
86a6a874 1886 if (caps & SDHCI_CAN_DO_HISPD)
a29e7e18 1887 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 1888
176d1ed4
JC		 1889 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
1890 mmc_card_is_removable(mmc))
68d1fb7e
AV		 1891 mmc->caps |= MMC_CAP_NEEDS_POLL;
1892
146ad66e
PO		 1893 mmc->ocr_avail = 0;
1894 if (caps & SDHCI_CAN_VDD_330)
1895 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1896 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1897 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1898 if (caps & SDHCI_CAN_VDD_180)
55556da0 1899 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1900
1901 if (mmc->ocr_avail == 0) {
1902 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 1903 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 1904 return -ENODEV;
146ad66e
PO		 1905 }
1906
d129bceb
PO		 1907 spin_lock_init(&host->lock);
1908
1909 /*
2134a922
PO		 1910 * Maximum number of segments. Depends on if the hardware
1911 * can do scatter/gather or not.
d129bceb 1912 */
2134a922 1913 if (host->flags & SDHCI_USE_ADMA)
a36274e0 1914 mmc->max_segs = 128;
a13abc7b 1915 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 1916 mmc->max_segs = 1;
2134a922 1917 else /* PIO */
a36274e0 1918 mmc->max_segs = 128;
d129bceb
PO		 1919
1920 /*
bab76961 1921 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1922 * size (512KiB).
d129bceb 1923 */
55db890a 1924 mmc->max_req_size = 524288;
d129bceb
PO		 1925
1926 /*
1927 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 1928 * of bytes. When doing hardware scatter/gather, each entry cannot
1929 * be larger than 64 KiB though.
d129bceb 1930 */
2134a922
PO		 1931 if (host->flags & SDHCI_USE_ADMA)
1932 mmc->max_seg_size = 65536;
1933 else
1934 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1935
fe4a3c7a
PO		 1936 /*
1937 * Maximum block size. This varies from controller to controller and
1938 * is specified in the capabilities register.
1939 */
0633f654
AV		 1940 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1941 mmc->max_blk_size = 2;
1942 } else {
1943 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1944 SDHCI_MAX_BLOCK_SHIFT;
1945 if (mmc->max_blk_size >= 3) {
1946 printk(KERN_WARNING "%s: Invalid maximum block size, "
1947 "assuming 512 bytes\n", mmc_hostname(mmc));
1948 mmc->max_blk_size = 0;
1949 }
1950 }
1951
1952 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1953
55db890a
PO		 1954 /*
1955 * Maximum block count.
1956 */
1388eefd 1957 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 1958
d129bceb
PO		 1959 /*
1960 * Init tasklets.
1961 */
1962 tasklet_init(&host->card_tasklet,
1963 sdhci_tasklet_card, (unsigned long)host);
1964 tasklet_init(&host->finish_tasklet,
1965 sdhci_tasklet_finish, (unsigned long)host);
1966
e4cad1b5 1967 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1968
dace1453 1969 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 1970 mmc_hostname(mmc), host);
d129bceb 1971 if (ret)
8ef1a143 1972 goto untasklet;
d129bceb 1973
9bea3c85
MS		 1974 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1975 if (IS_ERR(host->vmmc)) {
1976 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1977 host->vmmc = NULL;
1978 } else {
1979 regulator_enable(host->vmmc);
1980 }
1981
2f4cbb3d 1982 sdhci_init(host, 0);
d129bceb
PO		 1983
1984#ifdef CONFIG_MMC_DEBUG
1985 sdhci_dumpregs(host);
1986#endif
1987
f9134319 1988#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 1989 snprintf(host->led_name, sizeof(host->led_name),
1990 "%s::", mmc_hostname(mmc));
1991 host->led.name = host->led_name;
2f730fec
PO		 1992 host->led.brightness = LED_OFF;
1993 host->led.default_trigger = mmc_hostname(mmc);
1994 host->led.brightness_set = sdhci_led_control;
1995
b8c86fc5 1996 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 1997 if (ret)
1998 goto reset;
1999#endif
2000
5f25a66f
PO		 2001 mmiowb();
2002
d129bceb
PO		 2003 mmc_add_host(mmc);
2004
a13abc7b 2005 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2006 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2007 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2008 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2009
7260cf5e
AV		 2010 sdhci_enable_card_detection(host);
2011
d129bceb
PO		 2012 return 0;
2013
f9134319 2014#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2015reset:
2016 sdhci_reset(host, SDHCI_RESET_ALL);
2017 free_irq(host->irq, host);
2018#endif
8ef1a143 2019untasklet:
d129bceb
PO		 2020 tasklet_kill(&host->card_tasklet);
2021 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2022
2023 return ret;
2024}
2025
b8c86fc5 2026EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2027
1e72859e 2028void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2029{
1e72859e
PO		 2030 unsigned long flags;
2031
2032 if (dead) {
2033 spin_lock_irqsave(&host->lock, flags);
2034
2035 host->flags |= SDHCI_DEVICE_DEAD;
2036
2037 if (host->mrq) {
2038 printk(KERN_ERR "%s: Controller removed during "
2039 " transfer!\n", mmc_hostname(host->mmc));
2040
2041 host->mrq->cmd->error = -ENOMEDIUM;
2042 tasklet_schedule(&host->finish_tasklet);
2043 }
2044
2045 spin_unlock_irqrestore(&host->lock, flags);
2046 }
2047
7260cf5e
AV		 2048 sdhci_disable_card_detection(host);
2049
b8c86fc5 2050 mmc_remove_host(host->mmc);
d129bceb 2051
f9134319 2052#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2053 led_classdev_unregister(&host->led);
2054#endif
2055
1e72859e
PO		 2056 if (!dead)
2057 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 2058
2059 free_irq(host->irq, host);
2060
2061 del_timer_sync(&host->timer);
2062
2063 tasklet_kill(&host->card_tasklet);
2064 tasklet_kill(&host->finish_tasklet);
2134a922 2065
9bea3c85
MS		 2066 if (host->vmmc) {
2067 regulator_disable(host->vmmc);
2068 regulator_put(host->vmmc);
2069 }
2070
2134a922
PO		 2071 kfree(host->adma_desc);
2072 kfree(host->align_buffer);
2073
2074 host->adma_desc = NULL;
2075 host->align_buffer = NULL;
d129bceb
PO		 2076}
2077
b8c86fc5 2078EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 2079
b8c86fc5 2080void sdhci_free_host(struct sdhci_host *host)
d129bceb 2081{
b8c86fc5 2082 mmc_free_host(host->mmc);
d129bceb
PO		 2083}
2084
b8c86fc5 2085EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 2086
2087/*****************************************************************************\
2088 * *
2089 * Driver init/exit *
2090 * *
2091\*****************************************************************************/
2092
2093static int __init sdhci_drv_init(void)
2094{
2095 printk(KERN_INFO DRIVER_NAME
52fbf9c9 2096 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 2097 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2098
b8c86fc5 2099 return 0;
d129bceb
PO		 2100}
2101
2102static void __exit sdhci_drv_exit(void)
2103{
d129bceb
PO		 2104}
2105
2106module_init(sdhci_drv_init);
2107module_exit(sdhci_drv_exit);
2108
df673b22 2109module_param(debug_quirks, uint, 0444);
67435274 2110
32710e8f 2111MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 2112MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 2113MODULE_LICENSE("GPL");
67435274 2114
df673b22 2115MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux kernel - Deliverables
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