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mmc: sdhci: move FSL ESDHC reset handling quirk into esdhc code
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
d129bceb 52static void sdhci_finish_command(struct sdhci_host *);
069c9f14 53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 54static void sdhci_tuning_timer(unsigned long data);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 56
66fd8ad5
AH		 57#ifdef CONFIG_PM_RUNTIME
58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 60static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 62#else
63static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
64{
65 return 0;
66}
67static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
68{
69 return 0;
70}
f0710a55
AH		 71static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
72{
73}
74static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
75{
76}
66fd8ad5
AH		 77#endif
78
d129bceb
PO		 79static void sdhci_dumpregs(struct sdhci_host *host)
80{
a3c76eb9 81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 82 mmc_hostname(host->mmc));
d129bceb 83
a3c76eb9 84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 112 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 115 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 116 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 119
be3f4ae0 120 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 121 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 122 readl(host->ioaddr + SDHCI_ADMA_ERROR),
123 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
124
a3c76eb9 125 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 126}
127
128/*****************************************************************************\
129 * *
130 * Low level functions *
131 * *
132\*****************************************************************************/
133
7260cf5e
AV		 134static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
135{
5b4f1f6c 136 u32 present;
7260cf5e 137
c79396c1 138 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 139 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 140 return;
141
5b4f1f6c
RK		 142 if (enable) {
143 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
144 SDHCI_CARD_PRESENT;
d25928d1 145
5b4f1f6c
RK		 146 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
147 SDHCI_INT_CARD_INSERT;
148 } else {
149 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
150 }
b537f94c
RK		 151
152 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
153 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 154}
155
156static void sdhci_enable_card_detection(struct sdhci_host *host)
157{
158 sdhci_set_card_detection(host, true);
159}
160
161static void sdhci_disable_card_detection(struct sdhci_host *host)
162{
163 sdhci_set_card_detection(host, false);
164}
165
03231f9b 166void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 167{
e16514d8 168 unsigned long timeout;
393c1a34 169
4e4141a5 170 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 171
f0710a55 172 if (mask & SDHCI_RESET_ALL) {
d129bceb 173 host->clock = 0;
f0710a55
AH		 174 /* Reset-all turns off SD Bus Power */
175 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
176 sdhci_runtime_pm_bus_off(host);
177 }
d129bceb 178
e16514d8
PO		 179 /* Wait max 100 ms */
180 timeout = 100;
181
182 /* hw clears the bit when it's done */
4e4141a5 183 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 184 if (timeout == 0) {
a3c76eb9 185 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 186 mmc_hostname(host->mmc), (int)mask);
187 sdhci_dumpregs(host);
188 return;
189 }
190 timeout--;
191 mdelay(1);
d129bceb 192 }
03231f9b
RK		 193}
194EXPORT_SYMBOL_GPL(sdhci_reset);
195
196static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
197{
198 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
199 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
200 SDHCI_CARD_PRESENT))
201 return;
202 }
063a9dbb 203
03231f9b 204 host->ops->reset(host, mask);
393c1a34 205
3abc1e80
SX		 206 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
207 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
208 host->ops->enable_dma(host);
209 }
d129bceb
PO		 210}
211
2f4cbb3d
NP		 212static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
213
214static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 215{
2f4cbb3d 216 if (soft)
03231f9b 217 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 218 else
03231f9b 219 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 220
b537f94c
RK		 221 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
222 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
223 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
224 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
225 SDHCI_INT_RESPONSE;
226
227 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
228 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 229
230 if (soft) {
231 /* force clock reconfiguration */
232 host->clock = 0;
233 sdhci_set_ios(host->mmc, &host->mmc->ios);
234 }
7260cf5e 235}
d129bceb 236
7260cf5e
AV		 237static void sdhci_reinit(struct sdhci_host *host)
238{
2f4cbb3d 239 sdhci_init(host, 0);
b67c6b41
AL		 240 /*
241 * Retuning stuffs are affected by different cards inserted and only
242 * applicable to UHS-I cards. So reset these fields to their initial
243 * value when card is removed.
244 */
973905fe
AL		 245 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
246 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
247
b67c6b41
AL		 248 del_timer_sync(&host->tuning_timer);
249 host->flags &= ~SDHCI_NEEDS_RETUNING;
250 host->mmc->max_blk_count =
251 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
252 }
7260cf5e 253 sdhci_enable_card_detection(host);
d129bceb
PO		 254}
255
256static void sdhci_activate_led(struct sdhci_host *host)
257{
258 u8 ctrl;
259
4e4141a5 260 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 261 ctrl |= SDHCI_CTRL_LED;
4e4141a5 262 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 263}
264
265static void sdhci_deactivate_led(struct sdhci_host *host)
266{
267 u8 ctrl;
268
4e4141a5 269 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 270 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 271 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 272}
273
f9134319 274#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 275static void sdhci_led_control(struct led_classdev *led,
276 enum led_brightness brightness)
277{
278 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
279 unsigned long flags;
280
281 spin_lock_irqsave(&host->lock, flags);
282
66fd8ad5
AH		 283 if (host->runtime_suspended)
284 goto out;
285
2f730fec
PO		 286 if (brightness == LED_OFF)
287 sdhci_deactivate_led(host);
288 else
289 sdhci_activate_led(host);
66fd8ad5 290out:
2f730fec
PO		 291 spin_unlock_irqrestore(&host->lock, flags);
292}
293#endif
294
d129bceb
PO		 295/*****************************************************************************\
296 * *
297 * Core functions *
298 * *
299\*****************************************************************************/
300
a406f5a3 301static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 302{
7659150c
PO		 303 unsigned long flags;
304 size_t blksize, len, chunk;
7244b85b 305 u32 uninitialized_var(scratch);
7659150c 306 u8 *buf;
d129bceb 307
a406f5a3 308 DBG("PIO reading\n");
d129bceb 309
a406f5a3 310 blksize = host->data->blksz;
7659150c 311 chunk = 0;
d129bceb 312
7659150c 313 local_irq_save(flags);
d129bceb 314
a406f5a3 315 while (blksize) {
7659150c
PO		 316 if (!sg_miter_next(&host->sg_miter))
317 BUG();
d129bceb 318
7659150c 319 len = min(host->sg_miter.length, blksize);
d129bceb 320
7659150c
PO		 321 blksize -= len;
322 host->sg_miter.consumed = len;
14d836e7 323
7659150c 324 buf = host->sg_miter.addr;
d129bceb 325
7659150c
PO		 326 while (len) {
327 if (chunk == 0) {
4e4141a5 328 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 329 chunk = 4;
a406f5a3 330 }
7659150c
PO		 331
332 *buf = scratch & 0xFF;
333
334 buf++;
335 scratch >>= 8;
336 chunk--;
337 len--;
d129bceb 338 }
a406f5a3 339 }
7659150c
PO		 340
341 sg_miter_stop(&host->sg_miter);
342
343 local_irq_restore(flags);
a406f5a3 344}
d129bceb 345
a406f5a3
PO		 346static void sdhci_write_block_pio(struct sdhci_host *host)
347{
7659150c
PO		 348 unsigned long flags;
349 size_t blksize, len, chunk;
350 u32 scratch;
351 u8 *buf;
d129bceb 352
a406f5a3
PO		 353 DBG("PIO writing\n");
354
355 blksize = host->data->blksz;
7659150c
PO		 356 chunk = 0;
357 scratch = 0;
d129bceb 358
7659150c 359 local_irq_save(flags);
d129bceb 360
a406f5a3 361 while (blksize) {
7659150c
PO		 362 if (!sg_miter_next(&host->sg_miter))
363 BUG();
a406f5a3 364
7659150c
PO		 365 len = min(host->sg_miter.length, blksize);
366
367 blksize -= len;
368 host->sg_miter.consumed = len;
369
370 buf = host->sg_miter.addr;
d129bceb 371
7659150c
PO		 372 while (len) {
373 scratch |= (u32)*buf << (chunk * 8);
374
375 buf++;
376 chunk++;
377 len--;
378
379 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 380 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 381 chunk = 0;
382 scratch = 0;
d129bceb 383 }
d129bceb
PO		 384 }
385 }
7659150c
PO		 386
387 sg_miter_stop(&host->sg_miter);
388
389 local_irq_restore(flags);
a406f5a3
PO		 390}
391
392static void sdhci_transfer_pio(struct sdhci_host *host)
393{
394 u32 mask;
395
396 BUG_ON(!host->data);
397
7659150c 398 if (host->blocks == 0)
a406f5a3
PO		 399 return;
400
401 if (host->data->flags & MMC_DATA_READ)
402 mask = SDHCI_DATA_AVAILABLE;
403 else
404 mask = SDHCI_SPACE_AVAILABLE;
405
4a3cba32
PO		 406 /*
407 * Some controllers (JMicron JMB38x) mess up the buffer bits
408 * for transfers < 4 bytes. As long as it is just one block,
409 * we can ignore the bits.
410 */
411 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
412 (host->data->blocks == 1))
413 mask = ~0;
414
4e4141a5 415 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 416 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
417 udelay(100);
418
a406f5a3
PO		 419 if (host->data->flags & MMC_DATA_READ)
420 sdhci_read_block_pio(host);
421 else
422 sdhci_write_block_pio(host);
d129bceb 423
7659150c
PO		 424 host->blocks--;
425 if (host->blocks == 0)
a406f5a3 426 break;
a406f5a3 427 }
d129bceb 428
a406f5a3 429 DBG("PIO transfer complete.\n");
d129bceb
PO		 430}
431
2134a922
PO		 432static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
433{
434 local_irq_save(*flags);
482fce99 435 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 436}
437
438static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
439{
482fce99 440 kunmap_atomic(buffer);
2134a922
PO		 441 local_irq_restore(*flags);
442}
443
118cd17d
BD		 444static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
445{
9e506f35
BD		 446 __le32 *dataddr = (__le32 __force *)(desc + 4);
447 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 448
9e506f35
BD		 449 /* SDHCI specification says ADMA descriptors should be 4 byte
450 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 451
9e506f35
BD		 452 cmdlen[0] = cpu_to_le16(cmd);
453 cmdlen[1] = cpu_to_le16(len);
454
455 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 456}
457
8f1934ce 458static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 459 struct mmc_data *data)
460{
461 int direction;
462
463 u8 *desc;
464 u8 *align;
465 dma_addr_t addr;
466 dma_addr_t align_addr;
467 int len, offset;
468
469 struct scatterlist *sg;
470 int i;
471 char *buffer;
472 unsigned long flags;
473
474 /*
475 * The spec does not specify endianness of descriptor table.
476 * We currently guess that it is LE.
477 */
478
479 if (data->flags & MMC_DATA_READ)
480 direction = DMA_FROM_DEVICE;
481 else
482 direction = DMA_TO_DEVICE;
483
484 /*
485 * The ADMA descriptor table is mapped further down as we
486 * need to fill it with data first.
487 */
488
489 host->align_addr = dma_map_single(mmc_dev(host->mmc),
490 host->align_buffer, 128 * 4, direction);
8d8bb39b 491 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 492 goto fail;
2134a922
PO		 493 BUG_ON(host->align_addr & 0x3);
494
495 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
496 data->sg, data->sg_len, direction);
8f1934ce
PO		 497 if (host->sg_count == 0)
498 goto unmap_align;
2134a922
PO		 499
500 desc = host->adma_desc;
501 align = host->align_buffer;
502
503 align_addr = host->align_addr;
504
505 for_each_sg(data->sg, sg, host->sg_count, i) {
506 addr = sg_dma_address(sg);
507 len = sg_dma_len(sg);
508
509 /*
510 * The SDHCI specification states that ADMA
511 * addresses must be 32-bit aligned. If they
512 * aren't, then we use a bounce buffer for
513 * the (up to three) bytes that screw up the
514 * alignment.
515 */
516 offset = (4 - (addr & 0x3)) & 0x3;
517 if (offset) {
518 if (data->flags & MMC_DATA_WRITE) {
519 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 520 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 521 memcpy(align, buffer, offset);
522 sdhci_kunmap_atomic(buffer, &flags);
523 }
524
118cd17d
BD		 525 /* tran, valid */
526 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 527
528 BUG_ON(offset > 65536);
529
2134a922
PO		 530 align += 4;
531 align_addr += 4;
532
533 desc += 8;
534
535 addr += offset;
536 len -= offset;
537 }
538
2134a922
PO		 539 BUG_ON(len > 65536);
540
118cd17d
BD		 541 /* tran, valid */
542 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 543 desc += 8;
544
545 /*
546 * If this triggers then we have a calculation bug
547 * somewhere. :/
548 */
549 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
550 }
551
70764a90
TA		 552 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
553 /*
554 * Mark the last descriptor as the terminating descriptor
555 */
556 if (desc != host->adma_desc) {
557 desc -= 8;
558 desc[0] |= 0x2; /* end */
559 }
560 } else {
561 /*
562 * Add a terminating entry.
563 */
2134a922 564
70764a90
TA		 565 /* nop, end, valid */
566 sdhci_set_adma_desc(desc, 0, 0, 0x3);
567 }
2134a922
PO		 568
569 /*
570 * Resync align buffer as we might have changed it.
571 */
572 if (data->flags & MMC_DATA_WRITE) {
573 dma_sync_single_for_device(mmc_dev(host->mmc),
574 host->align_addr, 128 * 4, direction);
575 }
576
577 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
578 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 579 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 580 goto unmap_entries;
2134a922 581 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 582
583 return 0;
584
585unmap_entries:
586 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
587 data->sg_len, direction);
588unmap_align:
589 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
590 128 * 4, direction);
591fail:
592 return -EINVAL;
2134a922
PO		 593}
594
595static void sdhci_adma_table_post(struct sdhci_host *host,
596 struct mmc_data *data)
597{
598 int direction;
599
600 struct scatterlist *sg;
601 int i, size;
602 u8 *align;
603 char *buffer;
604 unsigned long flags;
605
606 if (data->flags & MMC_DATA_READ)
607 direction = DMA_FROM_DEVICE;
608 else
609 direction = DMA_TO_DEVICE;
610
611 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
612 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
613
614 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
615 128 * 4, direction);
616
617 if (data->flags & MMC_DATA_READ) {
618 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
619 data->sg_len, direction);
620
621 align = host->align_buffer;
622
623 for_each_sg(data->sg, sg, host->sg_count, i) {
624 if (sg_dma_address(sg) & 0x3) {
625 size = 4 - (sg_dma_address(sg) & 0x3);
626
627 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 628 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 629 memcpy(buffer, align, size);
630 sdhci_kunmap_atomic(buffer, &flags);
631
632 align += 4;
633 }
634 }
635 }
636
637 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
638 data->sg_len, direction);
639}
640
a3c7778f 641static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 642{
1c8cde92 643 u8 count;
a3c7778f 644 struct mmc_data *data = cmd->data;
1c8cde92 645 unsigned target_timeout, current_timeout;
d129bceb 646
ee53ab5d
PO		 647 /*
648 * If the host controller provides us with an incorrect timeout
649 * value, just skip the check and use 0xE. The hardware may take
650 * longer to time out, but that's much better than having a too-short
651 * timeout value.
652 */
11a2f1b7 653 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 654 return 0xE;
e538fbe8 655
a3c7778f 656 /* Unspecified timeout, assume max */
1d4d7744 657 if (!data && !cmd->busy_timeout)
a3c7778f 658 return 0xE;
d129bceb 659
a3c7778f
AW		 660 /* timeout in us */
661 if (!data)
1d4d7744 662 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 663 else {
664 target_timeout = data->timeout_ns / 1000;
665 if (host->clock)
666 target_timeout += data->timeout_clks / host->clock;
667 }
81b39802 668
1c8cde92
PO		 669 /*
670 * Figure out needed cycles.
671 * We do this in steps in order to fit inside a 32 bit int.
672 * The first step is the minimum timeout, which will have a
673 * minimum resolution of 6 bits:
674 * (1) 2^13*1000 > 2^22,
675 * (2) host->timeout_clk < 2^16
676 * =>
677 * (1) / (2) > 2^6
678 */
679 count = 0;
680 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
681 while (current_timeout < target_timeout) {
682 count++;
683 current_timeout <<= 1;
684 if (count >= 0xF)
685 break;
686 }
687
688 if (count >= 0xF) {
09eeff52
CB		 689 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
690 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 691 count = 0xE;
692 }
693
ee53ab5d
PO		 694 return count;
695}
696
6aa943ab
AV		 697static void sdhci_set_transfer_irqs(struct sdhci_host *host)
698{
699 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
700 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
701
702 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 703 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 704 else
b537f94c
RK		 705 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
706
707 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
708 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 709}
710
a3c7778f 711static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 712{
713 u8 count;
2134a922 714 u8 ctrl;
a3c7778f 715 struct mmc_data *data = cmd->data;
8f1934ce 716 int ret;
ee53ab5d
PO		 717
718 WARN_ON(host->data);
719
a3c7778f
AW		 720 if (data || (cmd->flags & MMC_RSP_BUSY)) {
721 count = sdhci_calc_timeout(host, cmd);
722 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
723 }
724
725 if (!data)
ee53ab5d
PO		 726 return;
727
728 /* Sanity checks */
729 BUG_ON(data->blksz * data->blocks > 524288);
730 BUG_ON(data->blksz > host->mmc->max_blk_size);
731 BUG_ON(data->blocks > 65535);
732
733 host->data = data;
734 host->data_early = 0;
f6a03cbf 735 host->data->bytes_xfered = 0;
ee53ab5d 736
a13abc7b 737 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 738 host->flags |= SDHCI_REQ_USE_DMA;
739
2134a922
PO		 740 /*
741 * FIXME: This doesn't account for merging when mapping the
742 * scatterlist.
743 */
744 if (host->flags & SDHCI_REQ_USE_DMA) {
745 int broken, i;
746 struct scatterlist *sg;
747
748 broken = 0;
749 if (host->flags & SDHCI_USE_ADMA) {
750 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
751 broken = 1;
752 } else {
753 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
754 broken = 1;
755 }
756
757 if (unlikely(broken)) {
758 for_each_sg(data->sg, sg, data->sg_len, i) {
759 if (sg->length & 0x3) {
760 DBG("Reverting to PIO because of "
761 "transfer size (%d)\n",
762 sg->length);
763 host->flags &= ~SDHCI_REQ_USE_DMA;
764 break;
765 }
766 }
767 }
c9fddbc4
PO		 768 }
769
770 /*
771 * The assumption here being that alignment is the same after
772 * translation to device address space.
773 */
2134a922
PO		 774 if (host->flags & SDHCI_REQ_USE_DMA) {
775 int broken, i;
776 struct scatterlist *sg;
777
778 broken = 0;
779 if (host->flags & SDHCI_USE_ADMA) {
780 /*
781 * As we use 3 byte chunks to work around
782 * alignment problems, we need to check this
783 * quirk.
784 */
785 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
786 broken = 1;
787 } else {
788 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
789 broken = 1;
790 }
791
792 if (unlikely(broken)) {
793 for_each_sg(data->sg, sg, data->sg_len, i) {
794 if (sg->offset & 0x3) {
795 DBG("Reverting to PIO because of "
796 "bad alignment\n");
797 host->flags &= ~SDHCI_REQ_USE_DMA;
798 break;
799 }
800 }
801 }
802 }
803
8f1934ce
PO		 804 if (host->flags & SDHCI_REQ_USE_DMA) {
805 if (host->flags & SDHCI_USE_ADMA) {
806 ret = sdhci_adma_table_pre(host, data);
807 if (ret) {
808 /*
809 * This only happens when someone fed
810 * us an invalid request.
811 */
812 WARN_ON(1);
ebd6d357 813 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 814 } else {
4e4141a5
AV		 815 sdhci_writel(host, host->adma_addr,
816 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 817 }
818 } else {
c8b3e02e 819 int sg_cnt;
8f1934ce 820
c8b3e02e 821 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 822 data->sg, data->sg_len,
823 (data->flags & MMC_DATA_READ) ?
824 DMA_FROM_DEVICE :
825 DMA_TO_DEVICE);
c8b3e02e 826 if (sg_cnt == 0) {
8f1934ce
PO		 827 /*
828 * This only happens when someone fed
829 * us an invalid request.
830 */
831 WARN_ON(1);
ebd6d357 832 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 833 } else {
719a61b4 834 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 835 sdhci_writel(host, sg_dma_address(data->sg),
836 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 837 }
838 }
839 }
840
2134a922
PO		 841 /*
842 * Always adjust the DMA selection as some controllers
843 * (e.g. JMicron) can't do PIO properly when the selection
844 * is ADMA.
845 */
846 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 847 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 848 ctrl &= ~SDHCI_CTRL_DMA_MASK;
849 if ((host->flags & SDHCI_REQ_USE_DMA) &&
850 (host->flags & SDHCI_USE_ADMA))
851 ctrl |= SDHCI_CTRL_ADMA32;
852 else
853 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 854 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 855 }
856
8f1934ce 857 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 858 int flags;
859
860 flags = SG_MITER_ATOMIC;
861 if (host->data->flags & MMC_DATA_READ)
862 flags |= SG_MITER_TO_SG;
863 else
864 flags |= SG_MITER_FROM_SG;
865 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 866 host->blocks = data->blocks;
d129bceb 867 }
c7fa9963 868
6aa943ab
AV		 869 sdhci_set_transfer_irqs(host);
870
f6a03cbf
MV		 871 /* Set the DMA boundary value and block size */
872 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
873 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 874 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 875}
876
877static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 878 struct mmc_command *cmd)
c7fa9963
PO		 879{
880 u16 mode;
e89d456f 881 struct mmc_data *data = cmd->data;
c7fa9963 882
2b558c13
DA		 883 if (data == NULL) {
884 /* clear Auto CMD settings for no data CMDs */
885 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
886 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
887 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
c7fa9963 888 return;
2b558c13 889 }
c7fa9963 890
e538fbe8
PO		 891 WARN_ON(!host->data);
892
c7fa9963 893 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 894 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
895 mode |= SDHCI_TRNS_MULTI;
896 /*
897 * If we are sending CMD23, CMD12 never gets sent
898 * on successful completion (so no Auto-CMD12).
899 */
900 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
901 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 902 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
903 mode |= SDHCI_TRNS_AUTO_CMD23;
904 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
905 }
c4512f79 906 }
8edf6371 907
c7fa9963
PO		 908 if (data->flags & MMC_DATA_READ)
909 mode |= SDHCI_TRNS_READ;
c9fddbc4 910 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 911 mode |= SDHCI_TRNS_DMA;
912
4e4141a5 913 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 914}
915
916static void sdhci_finish_data(struct sdhci_host *host)
917{
918 struct mmc_data *data;
d129bceb
PO		 919
920 BUG_ON(!host->data);
921
922 data = host->data;
923 host->data = NULL;
924
c9fddbc4 925 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 926 if (host->flags & SDHCI_USE_ADMA)
927 sdhci_adma_table_post(host, data);
928 else {
929 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
930 data->sg_len, (data->flags & MMC_DATA_READ) ?
931 DMA_FROM_DEVICE : DMA_TO_DEVICE);
932 }
d129bceb
PO		 933 }
934
935 /*
c9b74c5b
PO		 936 * The specification states that the block count register must
937 * be updated, but it does not specify at what point in the
938 * data flow. That makes the register entirely useless to read
939 * back so we have to assume that nothing made it to the card
940 * in the event of an error.
d129bceb 941 */
c9b74c5b
PO		 942 if (data->error)
943 data->bytes_xfered = 0;
d129bceb 944 else
c9b74c5b 945 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 946
e89d456f
AW		 947 /*
948 * Need to send CMD12 if -
949 * a) open-ended multiblock transfer (no CMD23)
950 * b) error in multiblock transfer
951 */
952 if (data->stop &&
953 (data->error ||
954 !host->mrq->sbc)) {
955
d129bceb
PO		 956 /*
957 * The controller needs a reset of internal state machines
958 * upon error conditions.
959 */
17b0429d 960 if (data->error) {
03231f9b
RK		 961 sdhci_do_reset(host, SDHCI_RESET_CMD);
962 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 963 }
964
965 sdhci_send_command(host, data->stop);
966 } else
967 tasklet_schedule(&host->finish_tasklet);
968}
969
c0e55129 970void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 971{
972 int flags;
fd2208d7 973 u32 mask;
7cb2c76f 974 unsigned long timeout;
d129bceb
PO		 975
976 WARN_ON(host->cmd);
977
d129bceb 978 /* Wait max 10 ms */
7cb2c76f 979 timeout = 10;
fd2208d7
PO		 980
981 mask = SDHCI_CMD_INHIBIT;
982 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
983 mask |= SDHCI_DATA_INHIBIT;
984
985 /* We shouldn't wait for data inihibit for stop commands, even
986 though they might use busy signaling */
987 if (host->mrq->data && (cmd == host->mrq->data->stop))
988 mask &= ~SDHCI_DATA_INHIBIT;
989
4e4141a5 990 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 991 if (timeout == 0) {
a3c76eb9 992 pr_err("%s: Controller never released "
acf1da45 993 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 994 sdhci_dumpregs(host);
17b0429d 995 cmd->error = -EIO;
d129bceb
PO		 996 tasklet_schedule(&host->finish_tasklet);
997 return;
998 }
7cb2c76f
PO		 999 timeout--;
1000 mdelay(1);
1001 }
d129bceb 1002
3e1a6892 1003 timeout = jiffies;
1d4d7744
UH		 1004 if (!cmd->data && cmd->busy_timeout > 9000)
1005 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1006 else
1007 timeout += 10 * HZ;
1008 mod_timer(&host->timer, timeout);
d129bceb
PO		 1009
1010 host->cmd = cmd;
1011
a3c7778f 1012 sdhci_prepare_data(host, cmd);
d129bceb 1013
4e4141a5 1014 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1015
e89d456f 1016 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1017
d129bceb 1018 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1019 pr_err("%s: Unsupported response type!\n",
d129bceb 1020 mmc_hostname(host->mmc));
17b0429d 1021 cmd->error = -EINVAL;
d129bceb
PO		 1022 tasklet_schedule(&host->finish_tasklet);
1023 return;
1024 }
1025
1026 if (!(cmd->flags & MMC_RSP_PRESENT))
1027 flags = SDHCI_CMD_RESP_NONE;
1028 else if (cmd->flags & MMC_RSP_136)
1029 flags = SDHCI_CMD_RESP_LONG;
1030 else if (cmd->flags & MMC_RSP_BUSY)
1031 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1032 else
1033 flags = SDHCI_CMD_RESP_SHORT;
1034
1035 if (cmd->flags & MMC_RSP_CRC)
1036 flags |= SDHCI_CMD_CRC;
1037 if (cmd->flags & MMC_RSP_OPCODE)
1038 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1039
1040 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1041 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1042 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1043 flags |= SDHCI_CMD_DATA;
1044
4e4141a5 1045 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1046}
c0e55129 1047EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1048
1049static void sdhci_finish_command(struct sdhci_host *host)
1050{
1051 int i;
1052
1053 BUG_ON(host->cmd == NULL);
1054
1055 if (host->cmd->flags & MMC_RSP_PRESENT) {
1056 if (host->cmd->flags & MMC_RSP_136) {
1057 /* CRC is stripped so we need to do some shifting. */
1058 for (i = 0;i < 4;i++) {
4e4141a5 1059 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1060 SDHCI_RESPONSE + (3-i)*4) << 8;
1061 if (i != 3)
1062 host->cmd->resp[i] |=
4e4141a5 1063 sdhci_readb(host,
d129bceb
PO		 1064 SDHCI_RESPONSE + (3-i)*4-1);
1065 }
1066 } else {
4e4141a5 1067 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1068 }
1069 }
1070
17b0429d 1071 host->cmd->error = 0;
d129bceb 1072
e89d456f
AW		 1073 /* Finished CMD23, now send actual command. */
1074 if (host->cmd == host->mrq->sbc) {
1075 host->cmd = NULL;
1076 sdhci_send_command(host, host->mrq->cmd);
1077 } else {
e538fbe8 1078
e89d456f
AW		 1079 /* Processed actual command. */
1080 if (host->data && host->data_early)
1081 sdhci_finish_data(host);
d129bceb 1082
e89d456f
AW		 1083 if (!host->cmd->data)
1084 tasklet_schedule(&host->finish_tasklet);
1085
1086 host->cmd = NULL;
1087 }
d129bceb
PO		 1088}
1089
52983382
KL		 1090static u16 sdhci_get_preset_value(struct sdhci_host *host)
1091{
1092 u16 ctrl, preset = 0;
1093
1094 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1095
1096 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1097 case SDHCI_CTRL_UHS_SDR12:
1098 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1099 break;
1100 case SDHCI_CTRL_UHS_SDR25:
1101 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1102 break;
1103 case SDHCI_CTRL_UHS_SDR50:
1104 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1105 break;
1106 case SDHCI_CTRL_UHS_SDR104:
1107 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1108 break;
1109 case SDHCI_CTRL_UHS_DDR50:
1110 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1111 break;
1112 default:
1113 pr_warn("%s: Invalid UHS-I mode selected\n",
1114 mmc_hostname(host->mmc));
1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1116 break;
1117 }
1118 return preset;
1119}
1120
d129bceb
PO		 1121static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1122{
c3ed3877 1123 int div = 0; /* Initialized for compiler warning */
df16219f 1124 int real_div = div, clk_mul = 1;
c3ed3877 1125 u16 clk = 0;
7cb2c76f 1126 unsigned long timeout;
d129bceb 1127
30832ab5 1128 if (clock && clock == host->clock)
d129bceb
PO		 1129 return;
1130
df16219f
GC		 1131 host->mmc->actual_clock = 0;
1132
8114634c
AV		 1133 if (host->ops->set_clock) {
1134 host->ops->set_clock(host, clock);
1135 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1136 return;
1137 }
1138
4e4141a5 1139 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1140
1141 if (clock == 0)
1142 goto out;
1143
85105c53 1144 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1145 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1146 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1147 u16 pre_val;
1148
1149 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1150 pre_val = sdhci_get_preset_value(host);
1151 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1152 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1153 if (host->clk_mul &&
1154 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1155 clk = SDHCI_PROG_CLOCK_MODE;
1156 real_div = div + 1;
1157 clk_mul = host->clk_mul;
1158 } else {
1159 real_div = max_t(int, 1, div << 1);
1160 }
1161 goto clock_set;
1162 }
1163
c3ed3877
AN		 1164 /*
1165 * Check if the Host Controller supports Programmable Clock
1166 * Mode.
1167 */
1168 if (host->clk_mul) {
52983382
KL		 1169 for (div = 1; div <= 1024; div++) {
1170 if ((host->max_clk * host->clk_mul / div)
1171 <= clock)
1172 break;
1173 }
c3ed3877 1174 /*
52983382
KL		 1175 * Set Programmable Clock Mode in the Clock
1176 * Control register.
c3ed3877 1177 */
52983382
KL		 1178 clk = SDHCI_PROG_CLOCK_MODE;
1179 real_div = div;
1180 clk_mul = host->clk_mul;
1181 div--;
c3ed3877
AN		 1182 } else {
1183 /* Version 3.00 divisors must be a multiple of 2. */
1184 if (host->max_clk <= clock)
1185 div = 1;
1186 else {
1187 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1188 div += 2) {
1189 if ((host->max_clk / div) <= clock)
1190 break;
1191 }
85105c53 1192 }
df16219f 1193 real_div = div;
c3ed3877 1194 div >>= 1;
85105c53
ZG		 1195 }
1196 } else {
1197 /* Version 2.00 divisors must be a power of 2. */
0397526d 1198 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1199 if ((host->max_clk / div) <= clock)
1200 break;
1201 }
df16219f 1202 real_div = div;
c3ed3877 1203 div >>= 1;
d129bceb 1204 }
d129bceb 1205
52983382 1206clock_set:
df16219f
GC		 1207 if (real_div)
1208 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1209
c3ed3877 1210 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1211 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1212 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1213 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1214 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1215
27f6cb16
CB		 1216 /* Wait max 20 ms */
1217 timeout = 20;
4e4141a5 1218 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1219 & SDHCI_CLOCK_INT_STABLE)) {
1220 if (timeout == 0) {
a3c76eb9 1221 pr_err("%s: Internal clock never "
acf1da45 1222 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1223 sdhci_dumpregs(host);
1224 return;
1225 }
7cb2c76f
PO		 1226 timeout--;
1227 mdelay(1);
1228 }
d129bceb
PO		 1229
1230 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1231 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1232
1233out:
1234 host->clock = clock;
1235}
1236
8213af3b
AS		 1237static inline void sdhci_update_clock(struct sdhci_host *host)
1238{
1239 unsigned int clock;
1240
1241 clock = host->clock;
1242 host->clock = 0;
1243 sdhci_set_clock(host, clock);
1244}
1245
ceb6143b 1246static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1247{
8364248a 1248 u8 pwr = 0;
146ad66e 1249
8364248a 1250 if (power != (unsigned short)-1) {
ae628903
PO		 1251 switch (1 << power) {
1252 case MMC_VDD_165_195:
1253 pwr = SDHCI_POWER_180;
1254 break;
1255 case MMC_VDD_29_30:
1256 case MMC_VDD_30_31:
1257 pwr = SDHCI_POWER_300;
1258 break;
1259 case MMC_VDD_32_33:
1260 case MMC_VDD_33_34:
1261 pwr = SDHCI_POWER_330;
1262 break;
1263 default:
1264 BUG();
1265 }
1266 }
1267
1268 if (host->pwr == pwr)
ceb6143b 1269 return -1;
146ad66e 1270
ae628903
PO		 1271 host->pwr = pwr;
1272
1273 if (pwr == 0) {
4e4141a5 1274 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1275 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1276 sdhci_runtime_pm_bus_off(host);
ceb6143b 1277 return 0;
9e9dc5f2
DS		 1278 }
1279
1280 /*
1281 * Spec says that we should clear the power reg before setting
1282 * a new value. Some controllers don't seem to like this though.
1283 */
b8c86fc5 1284 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1285 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1286
e08c1694 1287 /*
c71f6512 1288 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1289 * and set turn on power at the same time, so set the voltage first.
1290 */
11a2f1b7 1291 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1292 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1293
ae628903 1294 pwr |= SDHCI_POWER_ON;
146ad66e 1295
ae628903 1296 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1297
f0710a55
AH		 1298 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1299 sdhci_runtime_pm_bus_on(host);
1300
557b0697
HW		 1301 /*
1302 * Some controllers need an extra 10ms delay of 10ms before they
1303 * can apply clock after applying power
1304 */
11a2f1b7 1305 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1306 mdelay(10);
ceb6143b
AH		 1307
1308 return power;
146ad66e
PO		 1309}
1310
d129bceb
PO		 1311/*****************************************************************************\
1312 * *
1313 * MMC callbacks *
1314 * *
1315\*****************************************************************************/
1316
1317static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1318{
1319 struct sdhci_host *host;
505a8680 1320 int present;
d129bceb 1321 unsigned long flags;
473b095a 1322 u32 tuning_opcode;
d129bceb
PO		 1323
1324 host = mmc_priv(mmc);
1325
66fd8ad5
AH		 1326 sdhci_runtime_pm_get(host);
1327
d129bceb
PO		 1328 spin_lock_irqsave(&host->lock, flags);
1329
1330 WARN_ON(host->mrq != NULL);
1331
f9134319 1332#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1333 sdhci_activate_led(host);
2f730fec 1334#endif
e89d456f
AW		 1335
1336 /*
1337 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1338 * requests if Auto-CMD12 is enabled.
1339 */
1340 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1341 if (mrq->stop) {
1342 mrq->data->stop = NULL;
1343 mrq->stop = NULL;
1344 }
1345 }
d129bceb
PO		 1346
1347 host->mrq = mrq;
1348
505a8680
SG		 1349 /*
1350 * Firstly check card presence from cd-gpio. The return could
1351 * be one of the following possibilities:
1352 * negative: cd-gpio is not available
1353 * zero: cd-gpio is used, and card is removed
1354 * one: cd-gpio is used, and card is present
1355 */
1356 present = mmc_gpio_get_cd(host->mmc);
1357 if (present < 0) {
1358 /* If polling, assume that the card is always present. */
1359 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1360 present = 1;
1361 else
1362 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1363 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1364 }
1365
68d1fb7e 1366 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1367 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1368 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1369 } else {
1370 u32 present_state;
1371
1372 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1373 /*
1374 * Check if the re-tuning timer has already expired and there
1375 * is no on-going data transfer. If so, we need to execute
1376 * tuning procedure before sending command.
1377 */
1378 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1379 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1380 if (mmc->card) {
1381 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1382 tuning_opcode =
1383 mmc->card->type == MMC_TYPE_MMC ?
1384 MMC_SEND_TUNING_BLOCK_HS200 :
1385 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1386
1387 /* Here we need to set the host->mrq to NULL,
1388 * in case the pending finish_tasklet
1389 * finishes it incorrectly.
1390 */
1391 host->mrq = NULL;
1392
14efd957
CB		 1393 spin_unlock_irqrestore(&host->lock, flags);
1394 sdhci_execute_tuning(mmc, tuning_opcode);
1395 spin_lock_irqsave(&host->lock, flags);
1396
1397 /* Restore original mmc_request structure */
1398 host->mrq = mrq;
1399 }
cf2b5eea
AN		 1400 }
1401
8edf6371 1402 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1403 sdhci_send_command(host, mrq->sbc);
1404 else
1405 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1406 }
d129bceb 1407
5f25a66f 1408 mmiowb();
d129bceb
PO		 1409 spin_unlock_irqrestore(&host->lock, flags);
1410}
1411
2317f56c
RK		 1412void sdhci_set_bus_width(struct sdhci_host *host, int width)
1413{
1414 u8 ctrl;
1415
1416 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1417 if (width == MMC_BUS_WIDTH_8) {
1418 ctrl &= ~SDHCI_CTRL_4BITBUS;
1419 if (host->version >= SDHCI_SPEC_300)
1420 ctrl |= SDHCI_CTRL_8BITBUS;
1421 } else {
1422 if (host->version >= SDHCI_SPEC_300)
1423 ctrl &= ~SDHCI_CTRL_8BITBUS;
1424 if (width == MMC_BUS_WIDTH_4)
1425 ctrl |= SDHCI_CTRL_4BITBUS;
1426 else
1427 ctrl &= ~SDHCI_CTRL_4BITBUS;
1428 }
1429 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1430}
1431EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1432
66fd8ad5 1433static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1434{
d129bceb 1435 unsigned long flags;
ceb6143b 1436 int vdd_bit = -1;
d129bceb
PO		 1437 u8 ctrl;
1438
d129bceb
PO		 1439 spin_lock_irqsave(&host->lock, flags);
1440
ceb6143b
AH		 1441 if (host->flags & SDHCI_DEVICE_DEAD) {
1442 spin_unlock_irqrestore(&host->lock, flags);
1443 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1444 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1445 return;
1446 }
1e72859e 1447
d129bceb
PO		 1448 /*
1449 * Reset the chip on each power off.
1450 * Should clear out any weird states.
1451 */
1452 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1453 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1454 sdhci_reinit(host);
d129bceb
PO		 1455 }
1456
52983382 1457 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1458 (ios->power_mode == MMC_POWER_UP) &&
1459 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1460 sdhci_enable_preset_value(host, false);
1461
d129bceb
PO		 1462 sdhci_set_clock(host, ios->clock);
1463
1464 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1465 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1466 else
ceb6143b
AH		 1467 vdd_bit = sdhci_set_power(host, ios->vdd);
1468
1469 if (host->vmmc && vdd_bit != -1) {
1470 spin_unlock_irqrestore(&host->lock, flags);
1471 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1472 spin_lock_irqsave(&host->lock, flags);
1473 }
d129bceb 1474
643a81ff
PR		 1475 if (host->ops->platform_send_init_74_clocks)
1476 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1477
2317f56c 1478 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1479
15ec4461 1480 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1481
3ab9c8da
PR		 1482 if ((ios->timing == MMC_TIMING_SD_HS ||
1483 ios->timing == MMC_TIMING_MMC_HS)
1484 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1485 ctrl |= SDHCI_CTRL_HISPD;
1486 else
1487 ctrl &= ~SDHCI_CTRL_HISPD;
1488
d6d50a15 1489 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1490 u16 clk, ctrl_2;
49c468fc
AN		 1491
1492 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1493 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1494 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1495 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1496 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1497 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1498 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1499 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1500
1501 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1502 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1503 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1504 /*
1505 * We only need to set Driver Strength if the
1506 * preset value enable is not set.
1507 */
1508 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1509 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1510 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1511 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1512 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1513
1514 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1515 } else {
1516 /*
1517 * According to SDHC Spec v3.00, if the Preset Value
1518 * Enable in the Host Control 2 register is set, we
1519 * need to reset SD Clock Enable before changing High
1520 * Speed Enable to avoid generating clock gliches.
1521 */
758535c4
AN		 1522
1523 /* Reset SD Clock Enable */
1524 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1525 clk &= ~SDHCI_CLOCK_CARD_EN;
1526 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1527
1528 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1529
1530 /* Re-enable SD Clock */
8213af3b 1531 sdhci_update_clock(host);
d6d50a15 1532 }
49c468fc 1533
49c468fc
AN		 1534
1535 /* Reset SD Clock Enable */
1536 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1537 clk &= ~SDHCI_CLOCK_CARD_EN;
1538 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1539
6322cdd0
PR		 1540 if (host->ops->set_uhs_signaling)
1541 host->ops->set_uhs_signaling(host, ios->timing);
1542 else {
1543 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1544 /* Select Bus Speed Mode for host */
1545 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
59911568
GC		 1546 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1547 (ios->timing == MMC_TIMING_UHS_SDR104))
1548 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
069c9f14 1549 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1550 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1551 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1552 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1553 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1554 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
bb8175a8
SJ		 1555 else if ((ios->timing == MMC_TIMING_UHS_DDR50) ||
1556 (ios->timing == MMC_TIMING_MMC_DDR52))
6322cdd0
PR		 1557 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1558 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1559 }
49c468fc 1560
52983382
KL		 1561 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1562 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1563 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1564 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1565 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1566 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1567 u16 preset;
1568
1569 sdhci_enable_preset_value(host, true);
1570 preset = sdhci_get_preset_value(host);
1571 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1572 >> SDHCI_PRESET_DRV_SHIFT;
1573 }
1574
49c468fc 1575 /* Re-enable SD Clock */
8213af3b 1576 sdhci_update_clock(host);
758535c4
AN		 1577 } else
1578 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1579
b8352260
LD		 1580 /*
1581 * Some (ENE) controllers go apeshit on some ios operation,
1582 * signalling timeout and CRC errors even on CMD0. Resetting
1583 * it on each ios seems to solve the problem.
1584 */
b8c86fc5 1585 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1586 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1587
5f25a66f 1588 mmiowb();
d129bceb
PO		 1589 spin_unlock_irqrestore(&host->lock, flags);
1590}
1591
66fd8ad5
AH		 1592static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1593{
1594 struct sdhci_host *host = mmc_priv(mmc);
1595
1596 sdhci_runtime_pm_get(host);
1597 sdhci_do_set_ios(host, ios);
1598 sdhci_runtime_pm_put(host);
1599}
1600
94144a46
KL		 1601static int sdhci_do_get_cd(struct sdhci_host *host)
1602{
1603 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1604
1605 if (host->flags & SDHCI_DEVICE_DEAD)
1606 return 0;
1607
1608 /* If polling/nonremovable, assume that the card is always present. */
1609 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1610 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1611 return 1;
1612
1613 /* Try slot gpio detect */
1614 if (!IS_ERR_VALUE(gpio_cd))
1615 return !!gpio_cd;
1616
1617 /* Host native card detect */
1618 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1619}
1620
1621static int sdhci_get_cd(struct mmc_host *mmc)
1622{
1623 struct sdhci_host *host = mmc_priv(mmc);
1624 int ret;
1625
1626 sdhci_runtime_pm_get(host);
1627 ret = sdhci_do_get_cd(host);
1628 sdhci_runtime_pm_put(host);
1629 return ret;
1630}
1631
66fd8ad5 1632static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1633{
d129bceb 1634 unsigned long flags;
2dfb579c 1635 int is_readonly;
d129bceb 1636
d129bceb
PO		 1637 spin_lock_irqsave(&host->lock, flags);
1638
1e72859e 1639 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1640 is_readonly = 0;
1641 else if (host->ops->get_ro)
1642 is_readonly = host->ops->get_ro(host);
1e72859e 1643 else
2dfb579c
WS		 1644 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1645 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1646
1647 spin_unlock_irqrestore(&host->lock, flags);
1648
2dfb579c
WS		 1649 /* This quirk needs to be replaced by a callback-function later */
1650 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1651 !is_readonly : is_readonly;
d129bceb
PO		 1652}
1653
82b0e23a
TI		 1654#define SAMPLE_COUNT 5
1655
66fd8ad5 1656static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1657{
82b0e23a
TI		 1658 int i, ro_count;
1659
82b0e23a 1660 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1661 return sdhci_check_ro(host);
82b0e23a
TI		 1662
1663 ro_count = 0;
1664 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1665 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1666 if (++ro_count > SAMPLE_COUNT / 2)
1667 return 1;
1668 }
1669 msleep(30);
1670 }
1671 return 0;
1672}
1673
20758b66
AH		 1674static void sdhci_hw_reset(struct mmc_host *mmc)
1675{
1676 struct sdhci_host *host = mmc_priv(mmc);
1677
1678 if (host->ops && host->ops->hw_reset)
1679 host->ops->hw_reset(host);
1680}
1681
66fd8ad5 1682static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1683{
66fd8ad5
AH		 1684 struct sdhci_host *host = mmc_priv(mmc);
1685 int ret;
f75979b7 1686
66fd8ad5
AH		 1687 sdhci_runtime_pm_get(host);
1688 ret = sdhci_do_get_ro(host);
1689 sdhci_runtime_pm_put(host);
1690 return ret;
1691}
f75979b7 1692
66fd8ad5
AH		 1693static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1694{
be138554 1695 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1696 if (enable)
b537f94c 1697 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1698 else
b537f94c
RK		 1699 host->ier &= ~SDHCI_INT_CARD_INT;
1700
1701 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1702 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1703 mmiowb();
1704 }
66fd8ad5
AH		 1705}
1706
1707static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1708{
1709 struct sdhci_host *host = mmc_priv(mmc);
1710 unsigned long flags;
f75979b7 1711
ef104333
RK		 1712 sdhci_runtime_pm_get(host);
1713
66fd8ad5 1714 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1715 if (enable)
1716 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1717 else
1718 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1719
66fd8ad5 1720 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1721 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1722
1723 sdhci_runtime_pm_put(host);
f75979b7
PO		 1724}
1725
20b92a30 1726static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1727 struct mmc_ios *ios)
f2119df6 1728{
20b92a30 1729 u16 ctrl;
6231f3de 1730 int ret;
f2119df6 1731
20b92a30
KL		 1732 /*
1733 * Signal Voltage Switching is only applicable for Host Controllers
1734 * v3.00 and above.
1735 */
1736 if (host->version < SDHCI_SPEC_300)
1737 return 0;
6231f3de 1738
f2119df6 1739 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1740
21f5998f 1741 switch (ios->signal_voltage) {
20b92a30
KL		 1742 case MMC_SIGNAL_VOLTAGE_330:
1743 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1744 ctrl &= ~SDHCI_CTRL_VDD_180;
1745 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1746
20b92a30
KL		 1747 if (host->vqmmc) {
1748 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1749 if (ret) {
1750 pr_warning("%s: Switching to 3.3V signalling voltage "
1751 " failed\n", mmc_hostname(host->mmc));
1752 return -EIO;
1753 }
1754 }
1755 /* Wait for 5ms */
1756 usleep_range(5000, 5500);
f2119df6 1757
20b92a30
KL		 1758 /* 3.3V regulator output should be stable within 5 ms */
1759 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1760 if (!(ctrl & SDHCI_CTRL_VDD_180))
1761 return 0;
6231f3de 1762
20b92a30
KL		 1763 pr_warning("%s: 3.3V regulator output did not became stable\n",
1764 mmc_hostname(host->mmc));
1765
1766 return -EAGAIN;
1767 case MMC_SIGNAL_VOLTAGE_180:
1768 if (host->vqmmc) {
1769 ret = regulator_set_voltage(host->vqmmc,
1770 1700000, 1950000);
1771 if (ret) {
1772 pr_warning("%s: Switching to 1.8V signalling voltage "
1773 " failed\n", mmc_hostname(host->mmc));
1774 return -EIO;
1775 }
1776 }
6231f3de 1777
6231f3de
PR		 1778 /*
1779 * Enable 1.8V Signal Enable in the Host Control2
1780 * register
1781 */
20b92a30
KL		 1782 ctrl |= SDHCI_CTRL_VDD_180;
1783 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1784
20b92a30
KL		 1785 /* Wait for 5ms */
1786 usleep_range(5000, 5500);
f2119df6 1787
20b92a30
KL		 1788 /* 1.8V regulator output should be stable within 5 ms */
1789 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1790 if (ctrl & SDHCI_CTRL_VDD_180)
1791 return 0;
f2119df6 1792
20b92a30
KL		 1793 pr_warning("%s: 1.8V regulator output did not became stable\n",
1794 mmc_hostname(host->mmc));
f2119df6 1795
20b92a30
KL		 1796 return -EAGAIN;
1797 case MMC_SIGNAL_VOLTAGE_120:
1798 if (host->vqmmc) {
1799 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1800 if (ret) {
1801 pr_warning("%s: Switching to 1.2V signalling voltage "
1802 " failed\n", mmc_hostname(host->mmc));
1803 return -EIO;
f2119df6
AN		 1804 }
1805 }
6231f3de 1806 return 0;
20b92a30 1807 default:
f2119df6
AN		 1808 /* No signal voltage switch required */
1809 return 0;
20b92a30 1810 }
f2119df6
AN		 1811}
1812
66fd8ad5 1813static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1814 struct mmc_ios *ios)
66fd8ad5
AH		 1815{
1816 struct sdhci_host *host = mmc_priv(mmc);
1817 int err;
1818
1819 if (host->version < SDHCI_SPEC_300)
1820 return 0;
1821 sdhci_runtime_pm_get(host);
21f5998f 1822 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1823 sdhci_runtime_pm_put(host);
1824 return err;
1825}
1826
20b92a30
KL		 1827static int sdhci_card_busy(struct mmc_host *mmc)
1828{
1829 struct sdhci_host *host = mmc_priv(mmc);
1830 u32 present_state;
1831
1832 sdhci_runtime_pm_get(host);
1833 /* Check whether DAT[3:0] is 0000 */
1834 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1835 sdhci_runtime_pm_put(host);
1836
1837 return !(present_state & SDHCI_DATA_LVL_MASK);
1838}
1839
069c9f14 1840static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1841{
1842 struct sdhci_host *host;
1843 u16 ctrl;
b513ea25
AN		 1844 int tuning_loop_counter = MAX_TUNING_LOOP;
1845 unsigned long timeout;
1846 int err = 0;
069c9f14 1847 bool requires_tuning_nonuhs = false;
2b35bd83 1848 unsigned long flags;
b513ea25
AN		 1849
1850 host = mmc_priv(mmc);
1851
66fd8ad5 1852 sdhci_runtime_pm_get(host);
2b35bd83 1853 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1854
1855 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1856
1857 /*
069c9f14
G		 1858 * The Host Controller needs tuning only in case of SDR104 mode
1859 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1860 * Capabilities register.
069c9f14
G		 1861 * If the Host Controller supports the HS200 mode then the
1862 * tuning function has to be executed.
b513ea25 1863 */
069c9f14
G		 1864 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1865 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
156e14b1 1866 host->flags & SDHCI_SDR104_NEEDS_TUNING))
069c9f14
G		 1867 requires_tuning_nonuhs = true;
1868
b513ea25 1869 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1870 requires_tuning_nonuhs)
b513ea25
AN		 1871 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1872 else {
2b35bd83 1873 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1874 sdhci_runtime_pm_put(host);
b513ea25
AN		 1875 return 0;
1876 }
1877
45251812 1878 if (host->ops->platform_execute_tuning) {
2b35bd83 1879 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1880 err = host->ops->platform_execute_tuning(host, opcode);
1881 sdhci_runtime_pm_put(host);
1882 return err;
1883 }
1884
b513ea25
AN		 1885 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1886
1887 /*
1888 * As per the Host Controller spec v3.00, tuning command
1889 * generates Buffer Read Ready interrupt, so enable that.
1890 *
1891 * Note: The spec clearly says that when tuning sequence
1892 * is being performed, the controller does not generate
1893 * interrupts other than Buffer Read Ready interrupt. But
1894 * to make sure we don't hit a controller bug, we _only_
1895 * enable Buffer Read Ready interrupt here.
1896 */
b537f94c
RK		 1897 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1898 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1899
1900 /*
1901 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1902 * of loops reaches 40 times or a timeout of 150ms occurs.
1903 */
1904 timeout = 150;
1905 do {
1906 struct mmc_command cmd = {0};
66fd8ad5 1907 struct mmc_request mrq = {NULL};
b513ea25
AN		 1908
1909 if (!tuning_loop_counter && !timeout)
1910 break;
1911
069c9f14 1912 cmd.opcode = opcode;
b513ea25
AN		 1913 cmd.arg = 0;
1914 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1915 cmd.retries = 0;
1916 cmd.data = NULL;
1917 cmd.error = 0;
1918
1919 mrq.cmd = &cmd;
1920 host->mrq = &mrq;
1921
1922 /*
1923 * In response to CMD19, the card sends 64 bytes of tuning
1924 * block to the Host Controller. So we set the block size
1925 * to 64 here.
1926 */
069c9f14
G		 1927 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1928 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1929 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1930 SDHCI_BLOCK_SIZE);
1931 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1932 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1933 SDHCI_BLOCK_SIZE);
1934 } else {
1935 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1936 SDHCI_BLOCK_SIZE);
1937 }
b513ea25
AN		 1938
1939 /*
1940 * The tuning block is sent by the card to the host controller.
1941 * So we set the TRNS_READ bit in the Transfer Mode register.
1942 * This also takes care of setting DMA Enable and Multi Block
1943 * Select in the same register to 0.
1944 */
1945 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1946
1947 sdhci_send_command(host, &cmd);
1948
1949 host->cmd = NULL;
1950 host->mrq = NULL;
1951
2b35bd83 1952 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1953 /* Wait for Buffer Read Ready interrupt */
1954 wait_event_interruptible_timeout(host->buf_ready_int,
1955 (host->tuning_done == 1),
1956 msecs_to_jiffies(50));
2b35bd83 1957 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1958
1959 if (!host->tuning_done) {
a3c76eb9 1960 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1961 "Buffer Read Ready interrupt during tuning "
1962 "procedure, falling back to fixed sampling "
1963 "clock\n");
1964 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1965 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1966 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1967 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1968
1969 err = -EIO;
1970 goto out;
1971 }
1972
1973 host->tuning_done = 0;
1974
1975 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1976 tuning_loop_counter--;
1977 timeout--;
197160d5
NS		 1978
1979 /* eMMC spec does not require a delay between tuning cycles */
1980 if (opcode == MMC_SEND_TUNING_BLOCK)
1981 mdelay(1);
b513ea25
AN		 1982 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1983
1984 /*
1985 * The Host Driver has exhausted the maximum number of loops allowed,
1986 * so use fixed sampling frequency.
1987 */
1988 if (!tuning_loop_counter || !timeout) {
1989 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1990 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
114f2bf6 1991 err = -EIO;
b513ea25
AN		 1992 } else {
1993 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1994 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1995 " failed, falling back to fixed sampling"
1996 " clock\n");
1997 err = -EIO;
1998 }
1999 }
2000
2001out:
cf2b5eea
AN		 2002 /*
2003 * If this is the very first time we are here, we start the retuning
2004 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2005 * flag won't be set, we check this condition before actually starting
2006 * the timer.
2007 */
2008 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2009 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 2010 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 2011 mod_timer(&host->tuning_timer, jiffies +
2012 host->tuning_count * HZ);
2013 /* Tuning mode 1 limits the maximum data length to 4MB */
2014 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 2015 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 2016 host->flags &= ~SDHCI_NEEDS_RETUNING;
2017 /* Reload the new initial value for timer */
2bc02485
AS		 2018 mod_timer(&host->tuning_timer, jiffies +
2019 host->tuning_count * HZ);
cf2b5eea
AN		 2020 }
2021
2022 /*
2023 * In case tuning fails, host controllers which support re-tuning can
2024 * try tuning again at a later time, when the re-tuning timer expires.
2025 * So for these controllers, we return 0. Since there might be other
2026 * controllers who do not have this capability, we return error for
973905fe
AL		 2027 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2028 * a retuning timer to do the retuning for the card.
cf2b5eea 2029 */
973905fe 2030 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2031 err = 0;
2032
b537f94c
RK		 2033 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2034 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2b35bd83 2035 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2036 sdhci_runtime_pm_put(host);
b513ea25
AN		 2037
2038 return err;
2039}
2040
52983382
KL		 2041
2042static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2043{
4d55c5a1 2044 u16 ctrl;
4d55c5a1 2045
4d55c5a1
AN		 2046 /* Host Controller v3.00 defines preset value registers */
2047 if (host->version < SDHCI_SPEC_300)
2048 return;
2049
4d55c5a1
AN		 2050 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2051
2052 /*
2053 * We only enable or disable Preset Value if they are not already
2054 * enabled or disabled respectively. Otherwise, we bail out.
2055 */
2056 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2057 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2058 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2059 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2060 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2061 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2062 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2063 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2064 }
66fd8ad5
AH		 2065}
2066
71e69211 2067static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2068{
71e69211 2069 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2070 unsigned long flags;
2071
722e1280
CD		 2072 /* First check if client has provided their own card event */
2073 if (host->ops->card_event)
2074 host->ops->card_event(host);
2075
d129bceb
PO		 2076 spin_lock_irqsave(&host->lock, flags);
2077
66fd8ad5 2078 /* Check host->mrq first in case we are runtime suspended */
9668d765 2079 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2080 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2081 mmc_hostname(host->mmc));
a3c76eb9 2082 pr_err("%s: Resetting controller.\n",
66fd8ad5 2083 mmc_hostname(host->mmc));
d129bceb 2084
03231f9b
RK		 2085 sdhci_do_reset(host, SDHCI_RESET_CMD);
2086 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2087
66fd8ad5
AH		 2088 host->mrq->cmd->error = -ENOMEDIUM;
2089 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2090 }
2091
2092 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2093}
2094
2095static const struct mmc_host_ops sdhci_ops = {
2096 .request = sdhci_request,
2097 .set_ios = sdhci_set_ios,
94144a46 2098 .get_cd = sdhci_get_cd,
71e69211
GL		 2099 .get_ro = sdhci_get_ro,
2100 .hw_reset = sdhci_hw_reset,
2101 .enable_sdio_irq = sdhci_enable_sdio_irq,
2102 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2103 .execute_tuning = sdhci_execute_tuning,
71e69211 2104 .card_event = sdhci_card_event,
20b92a30 2105 .card_busy = sdhci_card_busy,
71e69211
GL		 2106};
2107
2108/*****************************************************************************\
2109 * *
2110 * Tasklets *
2111 * *
2112\*****************************************************************************/
2113
d129bceb
PO		 2114static void sdhci_tasklet_finish(unsigned long param)
2115{
2116 struct sdhci_host *host;
2117 unsigned long flags;
2118 struct mmc_request *mrq;
2119
2120 host = (struct sdhci_host*)param;
2121
66fd8ad5
AH		 2122 spin_lock_irqsave(&host->lock, flags);
2123
0c9c99a7
CB		 2124 /*
2125 * If this tasklet gets rescheduled while running, it will
2126 * be run again afterwards but without any active request.
2127 */
66fd8ad5
AH		 2128 if (!host->mrq) {
2129 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2130 return;
66fd8ad5 2131 }
d129bceb
PO		 2132
2133 del_timer(&host->timer);
2134
2135 mrq = host->mrq;
2136
d129bceb
PO		 2137 /*
2138 * The controller needs a reset of internal state machines
2139 * upon error conditions.
2140 */
1e72859e 2141 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2142 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2143 (mrq->data && (mrq->data->error ||
2144 (mrq->data->stop && mrq->data->stop->error))) ||
2145 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2146
2147 /* Some controllers need this kick or reset won't work here */
8213af3b 2148 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2149 /* This is to force an update */
8213af3b 2150 sdhci_update_clock(host);
645289dc
PO		 2151
2152 /* Spec says we should do both at the same time, but Ricoh
2153 controllers do not like that. */
03231f9b
RK		 2154 sdhci_do_reset(host, SDHCI_RESET_CMD);
2155 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2156 }
2157
2158 host->mrq = NULL;
2159 host->cmd = NULL;
2160 host->data = NULL;
2161
f9134319 2162#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2163 sdhci_deactivate_led(host);
2f730fec 2164#endif
d129bceb 2165
5f25a66f 2166 mmiowb();
d129bceb
PO		 2167 spin_unlock_irqrestore(&host->lock, flags);
2168
2169 mmc_request_done(host->mmc, mrq);
66fd8ad5 2170 sdhci_runtime_pm_put(host);
d129bceb
PO		 2171}
2172
2173static void sdhci_timeout_timer(unsigned long data)
2174{
2175 struct sdhci_host *host;
2176 unsigned long flags;
2177
2178 host = (struct sdhci_host*)data;
2179
2180 spin_lock_irqsave(&host->lock, flags);
2181
2182 if (host->mrq) {
a3c76eb9 2183 pr_err("%s: Timeout waiting for hardware "
acf1da45 2184 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2185 sdhci_dumpregs(host);
2186
2187 if (host->data) {
17b0429d 2188 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2189 sdhci_finish_data(host);
2190 } else {
2191 if (host->cmd)
17b0429d 2192 host->cmd->error = -ETIMEDOUT;
d129bceb 2193 else
17b0429d 2194 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2195
2196 tasklet_schedule(&host->finish_tasklet);
2197 }
2198 }
2199
5f25a66f 2200 mmiowb();
d129bceb
PO		 2201 spin_unlock_irqrestore(&host->lock, flags);
2202}
2203
cf2b5eea
AN		 2204static void sdhci_tuning_timer(unsigned long data)
2205{
2206 struct sdhci_host *host;
2207 unsigned long flags;
2208
2209 host = (struct sdhci_host *)data;
2210
2211 spin_lock_irqsave(&host->lock, flags);
2212
2213 host->flags |= SDHCI_NEEDS_RETUNING;
2214
2215 spin_unlock_irqrestore(&host->lock, flags);
2216}
2217
d129bceb
PO		 2218/*****************************************************************************\
2219 * *
2220 * Interrupt handling *
2221 * *
2222\*****************************************************************************/
2223
2224static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2225{
2226 BUG_ON(intmask == 0);
2227
2228 if (!host->cmd) {
a3c76eb9 2229 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2230 "though no command operation was in progress.\n",
2231 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2232 sdhci_dumpregs(host);
2233 return;
2234 }
2235
43b58b36 2236 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2237 host->cmd->error = -ETIMEDOUT;
2238 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2239 SDHCI_INT_INDEX))
2240 host->cmd->error = -EILSEQ;
43b58b36 2241
e809517f 2242 if (host->cmd->error) {
d129bceb 2243 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2244 return;
2245 }
2246
2247 /*
2248 * The host can send and interrupt when the busy state has
2249 * ended, allowing us to wait without wasting CPU cycles.
2250 * Unfortunately this is overloaded on the "data complete"
2251 * interrupt, so we need to take some care when handling
2252 * it.
2253 *
2254 * Note: The 1.0 specification is a bit ambiguous about this
2255 * feature so there might be some problems with older
2256 * controllers.
2257 */
2258 if (host->cmd->flags & MMC_RSP_BUSY) {
2259 if (host->cmd->data)
2260 DBG("Cannot wait for busy signal when also "
2261 "doing a data transfer");
f945405c 2262 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2263 return;
f945405c
BD		 2264
2265 /* The controller does not support the end-of-busy IRQ,
2266 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2267 }
2268
2269 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2270 sdhci_finish_command(host);
d129bceb
PO		 2271}
2272
0957c333 2273#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2274static void sdhci_show_adma_error(struct sdhci_host *host)
2275{
2276 const char *name = mmc_hostname(host->mmc);
2277 u8 *desc = host->adma_desc;
2278 __le32 *dma;
2279 __le16 *len;
2280 u8 attr;
2281
2282 sdhci_dumpregs(host);
2283
2284 while (true) {
2285 dma = (__le32 *)(desc + 4);
2286 len = (__le16 *)(desc + 2);
2287 attr = *desc;
2288
2289 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2290 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2291
2292 desc += 8;
2293
2294 if (attr & 2)
2295 break;
2296 }
2297}
2298#else
2299static void sdhci_show_adma_error(struct sdhci_host *host) { }
2300#endif
2301
d129bceb
PO		 2302static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2303{
069c9f14 2304 u32 command;
d129bceb
PO		 2305 BUG_ON(intmask == 0);
2306
b513ea25
AN		 2307 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2308 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2309 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2310 if (command == MMC_SEND_TUNING_BLOCK ||
2311 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2312 host->tuning_done = 1;
2313 wake_up(&host->buf_ready_int);
2314 return;
2315 }
2316 }
2317
d129bceb
PO		 2318 if (!host->data) {
2319 /*
e809517f
PO		 2320 * The "data complete" interrupt is also used to
2321 * indicate that a busy state has ended. See comment
2322 * above in sdhci_cmd_irq().
d129bceb 2323 */
e809517f
PO		 2324 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2325 if (intmask & SDHCI_INT_DATA_END) {
2326 sdhci_finish_command(host);
2327 return;
2328 }
2329 }
d129bceb 2330
a3c76eb9 2331 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2332 "though no data operation was in progress.\n",
2333 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2334 sdhci_dumpregs(host);
2335
2336 return;
2337 }
2338
2339 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2340 host->data->error = -ETIMEDOUT;
22113efd
AL		 2341 else if (intmask & SDHCI_INT_DATA_END_BIT)
2342 host->data->error = -EILSEQ;
2343 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2344 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2345 != MMC_BUS_TEST_R)
17b0429d 2346 host->data->error = -EILSEQ;
6882a8c0 2347 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2348 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2349 sdhci_show_adma_error(host);
2134a922 2350 host->data->error = -EIO;
a4071fbb
HZ		 2351 if (host->ops->adma_workaround)
2352 host->ops->adma_workaround(host, intmask);
6882a8c0 2353 }
d129bceb 2354
17b0429d 2355 if (host->data->error)
d129bceb
PO		 2356 sdhci_finish_data(host);
2357 else {
a406f5a3 2358 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2359 sdhci_transfer_pio(host);
2360
6ba736a1
PO		 2361 /*
2362 * We currently don't do anything fancy with DMA
2363 * boundaries, but as we can't disable the feature
2364 * we need to at least restart the transfer.
f6a03cbf
MV		 2365 *
2366 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2367 * should return a valid address to continue from, but as
2368 * some controllers are faulty, don't trust them.
6ba736a1 2369 */
f6a03cbf
MV		 2370 if (intmask & SDHCI_INT_DMA_END) {
2371 u32 dmastart, dmanow;
2372 dmastart = sg_dma_address(host->data->sg);
2373 dmanow = dmastart + host->data->bytes_xfered;
2374 /*
2375 * Force update to the next DMA block boundary.
2376 */
2377 dmanow = (dmanow &
2378 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2379 SDHCI_DEFAULT_BOUNDARY_SIZE;
2380 host->data->bytes_xfered = dmanow - dmastart;
2381 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2382 " next 0x%08x\n",
2383 mmc_hostname(host->mmc), dmastart,
2384 host->data->bytes_xfered, dmanow);
2385 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2386 }
6ba736a1 2387
e538fbe8
PO		 2388 if (intmask & SDHCI_INT_DATA_END) {
2389 if (host->cmd) {
2390 /*
2391 * Data managed to finish before the
2392 * command completed. Make sure we do
2393 * things in the proper order.
2394 */
2395 host->data_early = 1;
2396 } else {
2397 sdhci_finish_data(host);
2398 }
2399 }
d129bceb
PO		 2400 }
2401}
2402
7d12e780 2403static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2404{
781e989c 2405 irqreturn_t result = IRQ_NONE;
66fd8ad5 2406 struct sdhci_host *host = dev_id;
41005003 2407 u32 intmask, mask, unexpected = 0;
781e989c 2408 int max_loops = 16;
d129bceb
PO		 2409
2410 spin_lock(&host->lock);
2411
be138554 2412 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2413 spin_unlock(&host->lock);
655bca76 2414 return IRQ_NONE;
66fd8ad5
AH		 2415 }
2416
4e4141a5 2417 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2418 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2419 result = IRQ_NONE;
2420 goto out;
2421 }
2422
41005003
RK		 2423 do {
2424 /* Clear selected interrupts. */
2425 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2426 SDHCI_INT_BUS_POWER);
2427 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2428
41005003
RK		 2429 DBG("*** %s got interrupt: 0x%08x\n",
2430 mmc_hostname(host->mmc), intmask);
d129bceb 2431
41005003
RK		 2432 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2433 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2434 SDHCI_CARD_PRESENT;
d129bceb 2435
41005003
RK		 2436 /*
2437 * There is a observation on i.mx esdhc. INSERT
2438 * bit will be immediately set again when it gets
2439 * cleared, if a card is inserted. We have to mask
2440 * the irq to prevent interrupt storm which will
2441 * freeze the system. And the REMOVE gets the
2442 * same situation.
2443 *
2444 * More testing are needed here to ensure it works
2445 * for other platforms though.
2446 */
b537f94c
RK		 2447 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2448 SDHCI_INT_CARD_REMOVE);
2449 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2450 SDHCI_INT_CARD_INSERT;
2451 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2452 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2453
2454 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2455 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2456
2457 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2458 SDHCI_INT_CARD_REMOVE);
2459 result = IRQ_WAKE_THREAD;
41005003 2460 }
d129bceb 2461
41005003
RK		 2462 if (intmask & SDHCI_INT_CMD_MASK)
2463 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2464
41005003
RK		 2465 if (intmask & SDHCI_INT_DATA_MASK)
2466 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2467
41005003
RK		 2468 if (intmask & SDHCI_INT_BUS_POWER)
2469 pr_err("%s: Card is consuming too much power!\n",
2470 mmc_hostname(host->mmc));
3192a28f 2471
781e989c
RK		 2472 if (intmask & SDHCI_INT_CARD_INT) {
2473 sdhci_enable_sdio_irq_nolock(host, false);
2474 host->thread_isr |= SDHCI_INT_CARD_INT;
2475 result = IRQ_WAKE_THREAD;
2476 }
f75979b7 2477
41005003
RK		 2478 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2479 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2480 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2481 SDHCI_INT_CARD_INT);
f75979b7 2482
41005003
RK		 2483 if (intmask) {
2484 unexpected |= intmask;
2485 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2486 }
d129bceb 2487
781e989c
RK		 2488 if (result == IRQ_NONE)
2489 result = IRQ_HANDLED;
d129bceb 2490
41005003 2491 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2492 } while (intmask && --max_loops);
d129bceb
PO		 2493out:
2494 spin_unlock(&host->lock);
2495
6379b237
AS		 2496 if (unexpected) {
2497 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2498 mmc_hostname(host->mmc), unexpected);
2499 sdhci_dumpregs(host);
2500 }
f75979b7 2501
d129bceb
PO		 2502 return result;
2503}
2504
781e989c
RK		 2505static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2506{
2507 struct sdhci_host *host = dev_id;
2508 unsigned long flags;
2509 u32 isr;
2510
2511 spin_lock_irqsave(&host->lock, flags);
2512 isr = host->thread_isr;
2513 host->thread_isr = 0;
2514 spin_unlock_irqrestore(&host->lock, flags);
2515
3560db8e
RK		 2516 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2517 sdhci_card_event(host->mmc);
2518 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2519 }
2520
781e989c
RK		 2521 if (isr & SDHCI_INT_CARD_INT) {
2522 sdio_run_irqs(host->mmc);
2523
2524 spin_lock_irqsave(&host->lock, flags);
2525 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2526 sdhci_enable_sdio_irq_nolock(host, true);
2527 spin_unlock_irqrestore(&host->lock, flags);
2528 }
2529
2530 return isr ? IRQ_HANDLED : IRQ_NONE;
2531}
2532
d129bceb
PO		 2533/*****************************************************************************\
2534 * *
2535 * Suspend/resume *
2536 * *
2537\*****************************************************************************/
2538
2539#ifdef CONFIG_PM
ad080d79
KL		 2540void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2541{
2542 u8 val;
2543 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2544 | SDHCI_WAKE_ON_INT;
2545
2546 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2547 val |= mask ;
2548 /* Avoid fake wake up */
2549 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2550 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2551 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2552}
2553EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2554
2555void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2556{
2557 u8 val;
2558 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2559 | SDHCI_WAKE_ON_INT;
2560
2561 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2562 val &= ~mask;
2563 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2564}
2565EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2566
29495aa0 2567int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2568{
a1b13b4e
CB		 2569 if (host->ops->platform_suspend)
2570 host->ops->platform_suspend(host);
2571
7260cf5e
AV		 2572 sdhci_disable_card_detection(host);
2573
cf2b5eea 2574 /* Disable tuning since we are suspending */
973905fe 2575 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2576 del_timer_sync(&host->tuning_timer);
cf2b5eea 2577 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2578 }
2579
ad080d79 2580 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2581 host->ier = 0;
2582 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2583 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2584 free_irq(host->irq, host);
2585 } else {
2586 sdhci_enable_irq_wakeups(host);
2587 enable_irq_wake(host->irq);
2588 }
4ee14ec6 2589 return 0;
d129bceb
PO		 2590}
2591
b8c86fc5 2592EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2593
b8c86fc5
PO		 2594int sdhci_resume_host(struct sdhci_host *host)
2595{
4ee14ec6 2596 int ret = 0;
d129bceb 2597
a13abc7b 2598 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2599 if (host->ops->enable_dma)
2600 host->ops->enable_dma(host);
2601 }
d129bceb 2602
ad080d79 2603 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2604 ret = request_threaded_irq(host->irq, sdhci_irq,
2605 sdhci_thread_irq, IRQF_SHARED,
2606 mmc_hostname(host->mmc), host);
ad080d79
KL		 2607 if (ret)
2608 return ret;
2609 } else {
2610 sdhci_disable_irq_wakeups(host);
2611 disable_irq_wake(host->irq);
2612 }
d129bceb 2613
6308d290
AH		 2614 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2615 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2616 /* Card keeps power but host controller does not */
2617 sdhci_init(host, 0);
2618 host->pwr = 0;
2619 host->clock = 0;
2620 sdhci_do_set_ios(host, &host->mmc->ios);
2621 } else {
2622 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2623 mmiowb();
2624 }
b8c86fc5 2625
7260cf5e
AV		 2626 sdhci_enable_card_detection(host);
2627
a1b13b4e
CB		 2628 if (host->ops->platform_resume)
2629 host->ops->platform_resume(host);
2630
cf2b5eea 2631 /* Set the re-tuning expiration flag */
973905fe 2632 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2633 host->flags |= SDHCI_NEEDS_RETUNING;
2634
2f4cbb3d 2635 return ret;
d129bceb
PO		 2636}
2637
b8c86fc5 2638EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2639#endif /* CONFIG_PM */
2640
66fd8ad5
AH		 2641#ifdef CONFIG_PM_RUNTIME
2642
2643static int sdhci_runtime_pm_get(struct sdhci_host *host)
2644{
2645 return pm_runtime_get_sync(host->mmc->parent);
2646}
2647
2648static int sdhci_runtime_pm_put(struct sdhci_host *host)
2649{
2650 pm_runtime_mark_last_busy(host->mmc->parent);
2651 return pm_runtime_put_autosuspend(host->mmc->parent);
2652}
2653
f0710a55
AH		 2654static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2655{
2656 if (host->runtime_suspended || host->bus_on)
2657 return;
2658 host->bus_on = true;
2659 pm_runtime_get_noresume(host->mmc->parent);
2660}
2661
2662static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2663{
2664 if (host->runtime_suspended || !host->bus_on)
2665 return;
2666 host->bus_on = false;
2667 pm_runtime_put_noidle(host->mmc->parent);
2668}
2669
66fd8ad5
AH		 2670int sdhci_runtime_suspend_host(struct sdhci_host *host)
2671{
2672 unsigned long flags;
2673 int ret = 0;
2674
2675 /* Disable tuning since we are suspending */
973905fe 2676 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2677 del_timer_sync(&host->tuning_timer);
2678 host->flags &= ~SDHCI_NEEDS_RETUNING;
2679 }
2680
2681 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2682 host->ier &= SDHCI_INT_CARD_INT;
2683 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2684 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2685 spin_unlock_irqrestore(&host->lock, flags);
2686
781e989c 2687 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2688
2689 spin_lock_irqsave(&host->lock, flags);
2690 host->runtime_suspended = true;
2691 spin_unlock_irqrestore(&host->lock, flags);
2692
2693 return ret;
2694}
2695EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2696
2697int sdhci_runtime_resume_host(struct sdhci_host *host)
2698{
2699 unsigned long flags;
2700 int ret = 0, host_flags = host->flags;
2701
2702 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2703 if (host->ops->enable_dma)
2704 host->ops->enable_dma(host);
2705 }
2706
2707 sdhci_init(host, 0);
2708
2709 /* Force clock and power re-program */
2710 host->pwr = 0;
2711 host->clock = 0;
2712 sdhci_do_set_ios(host, &host->mmc->ios);
2713
2714 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2715 if ((host_flags & SDHCI_PV_ENABLED) &&
2716 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2717 spin_lock_irqsave(&host->lock, flags);
2718 sdhci_enable_preset_value(host, true);
2719 spin_unlock_irqrestore(&host->lock, flags);
2720 }
66fd8ad5
AH		 2721
2722 /* Set the re-tuning expiration flag */
973905fe 2723 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2724 host->flags |= SDHCI_NEEDS_RETUNING;
2725
2726 spin_lock_irqsave(&host->lock, flags);
2727
2728 host->runtime_suspended = false;
2729
2730 /* Enable SDIO IRQ */
ef104333 2731 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2732 sdhci_enable_sdio_irq_nolock(host, true);
2733
2734 /* Enable Card Detection */
2735 sdhci_enable_card_detection(host);
2736
2737 spin_unlock_irqrestore(&host->lock, flags);
2738
2739 return ret;
2740}
2741EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2742
2743#endif
2744
d129bceb
PO		 2745/*****************************************************************************\
2746 * *
b8c86fc5 2747 * Device allocation/registration *
d129bceb
PO		 2748 * *
2749\*****************************************************************************/
2750
b8c86fc5
PO		 2751struct sdhci_host *sdhci_alloc_host(struct device *dev,
2752 size_t priv_size)
d129bceb 2753{
d129bceb
PO		 2754 struct mmc_host *mmc;
2755 struct sdhci_host *host;
2756
b8c86fc5 2757 WARN_ON(dev == NULL);
d129bceb 2758
b8c86fc5 2759 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2760 if (!mmc)
b8c86fc5 2761 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2762
2763 host = mmc_priv(mmc);
2764 host->mmc = mmc;
2765
b8c86fc5
PO		 2766 return host;
2767}
8a4da143 2768
b8c86fc5 2769EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2770
b8c86fc5
PO		 2771int sdhci_add_host(struct sdhci_host *host)
2772{
2773 struct mmc_host *mmc;
bd6a8c30 2774 u32 caps[2] = {0, 0};
f2119df6
AN		 2775 u32 max_current_caps;
2776 unsigned int ocr_avail;
b8c86fc5 2777 int ret;
d129bceb 2778
b8c86fc5
PO		 2779 WARN_ON(host == NULL);
2780 if (host == NULL)
2781 return -EINVAL;
d129bceb 2782
b8c86fc5 2783 mmc = host->mmc;
d129bceb 2784
b8c86fc5
PO		 2785 if (debug_quirks)
2786 host->quirks = debug_quirks;
66fd8ad5
AH		 2787 if (debug_quirks2)
2788 host->quirks2 = debug_quirks2;
d129bceb 2789
03231f9b 2790 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2791
4e4141a5 2792 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2793 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2794 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2795 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2796 pr_err("%s: Unknown controller version (%d). "
b69c9058 2797 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2798 host->version);
4a965505
PO		 2799 }
2800
f2119df6 2801 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2802 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2803
bd6a8c30
PR		 2804 if (host->version >= SDHCI_SPEC_300)
2805 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2806 host->caps1 :
2807 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2808
b8c86fc5 2809 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2810 host->flags |= SDHCI_USE_SDMA;
f2119df6 2811 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2812 DBG("Controller doesn't have SDMA capability\n");
67435274 2813 else
a13abc7b 2814 host->flags |= SDHCI_USE_SDMA;
d129bceb 2815
b8c86fc5 2816 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2817 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2818 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2819 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2820 }
2821
f2119df6
AN		 2822 if ((host->version >= SDHCI_SPEC_200) &&
2823 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2824 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2825
2826 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2827 (host->flags & SDHCI_USE_ADMA)) {
2828 DBG("Disabling ADMA as it is marked broken\n");
2829 host->flags &= ~SDHCI_USE_ADMA;
2830 }
2831
a13abc7b 2832 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2833 if (host->ops->enable_dma) {
2834 if (host->ops->enable_dma(host)) {
a3c76eb9 2835 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2836 "available. Falling back to PIO.\n",
2837 mmc_hostname(mmc));
a13abc7b
RR		 2838 host->flags &=
2839 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2840 }
d129bceb
PO		 2841 }
2842 }
2843
2134a922
PO		 2844 if (host->flags & SDHCI_USE_ADMA) {
2845 /*
2846 * We need to allocate descriptors for all sg entries
2847 * (128) and potentially one alignment transfer for
2848 * each of those entries.
2849 */
2850 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2851 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2852 if (!host->adma_desc || !host->align_buffer) {
2853 kfree(host->adma_desc);
2854 kfree(host->align_buffer);
a3c76eb9 2855 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2856 "buffers. Falling back to standard DMA.\n",
2857 mmc_hostname(mmc));
2858 host->flags &= ~SDHCI_USE_ADMA;
2859 }
2860 }
2861
7659150c
PO		 2862 /*
2863 * If we use DMA, then it's up to the caller to set the DMA
2864 * mask, but PIO does not need the hw shim so we set a new
2865 * mask here in that case.
2866 */
a13abc7b 2867 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2868 host->dma_mask = DMA_BIT_MASK(64);
2869 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2870 }
d129bceb 2871
c4687d5f 2872 if (host->version >= SDHCI_SPEC_300)
f2119df6 2873 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2874 >> SDHCI_CLOCK_BASE_SHIFT;
2875 else
f2119df6 2876 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2877 >> SDHCI_CLOCK_BASE_SHIFT;
2878
4240ff0a 2879 host->max_clk *= 1000000;
f27f47ef
AV		 2880 if (host->max_clk == 0 || host->quirks &
2881 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2882 if (!host->ops->get_max_clock) {
a3c76eb9 2883 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2884 "frequency.\n", mmc_hostname(mmc));
2885 return -ENODEV;
2886 }
2887 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2888 }
d129bceb 2889
c3ed3877
AN		 2890 /*
2891 * In case of Host Controller v3.00, find out whether clock
2892 * multiplier is supported.
2893 */
2894 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2895 SDHCI_CLOCK_MUL_SHIFT;
2896
2897 /*
2898 * In case the value in Clock Multiplier is 0, then programmable
2899 * clock mode is not supported, otherwise the actual clock
2900 * multiplier is one more than the value of Clock Multiplier
2901 * in the Capabilities Register.
2902 */
2903 if (host->clk_mul)
2904 host->clk_mul += 1;
2905
d129bceb
PO		 2906 /*
2907 * Set host parameters.
2908 */
2909 mmc->ops = &sdhci_ops;
c3ed3877 2910 mmc->f_max = host->max_clk;
ce5f036b 2911 if (host->ops->get_min_clock)
a9e58f25 2912 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2913 else if (host->version >= SDHCI_SPEC_300) {
2914 if (host->clk_mul) {
2915 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2916 mmc->f_max = host->max_clk * host->clk_mul;
2917 } else
2918 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2919 } else
0397526d 2920 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2921
272308ca
AS		 2922 host->timeout_clk =
2923 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2924 if (host->timeout_clk == 0) {
2925 if (host->ops->get_timeout_clock) {
2926 host->timeout_clk = host->ops->get_timeout_clock(host);
2927 } else if (!(host->quirks &
2928 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2929 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2930 "frequency.\n", mmc_hostname(mmc));
2931 return -ENODEV;
2932 }
2933 }
2934 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2935 host->timeout_clk *= 1000;
2936
2937 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2938 host->timeout_clk = mmc->f_max / 1000;
272308ca 2939
68eb80e0 2940 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
58d1246d 2941
e89d456f 2942 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 2943 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 2944
2945 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2946 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2947
8edf6371 2948 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2949 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2950 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2951 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2952 host->flags |= SDHCI_AUTO_CMD23;
2953 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2954 } else {
2955 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2956 }
2957
15ec4461
PR		 2958 /*
2959 * A controller may support 8-bit width, but the board itself
2960 * might not have the pins brought out. Boards that support
2961 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2962 * their platform code before calling sdhci_add_host(), and we
2963 * won't assume 8-bit width for hosts without that CAP.
2964 */
5fe23c7f 2965 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2966 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2967
63ef5d8c
JH		 2968 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2969 mmc->caps &= ~MMC_CAP_CMD23;
2970
f2119df6 2971 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2972 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2973
176d1ed4 2974 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2975 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2976 mmc->caps |= MMC_CAP_NEEDS_POLL;
2977
6231f3de 2978 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
462849aa 2979 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2980 if (IS_ERR_OR_NULL(host->vqmmc)) {
2981 if (PTR_ERR(host->vqmmc) < 0) {
2982 pr_info("%s: no vqmmc regulator found\n",
2983 mmc_hostname(mmc));
2984 host->vqmmc = NULL;
2985 }
8363c374 2986 } else {
a3361aba 2987 ret = regulator_enable(host->vqmmc);
cec2e216
KL		 2988 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2989 1950000))
8363c374
KL		 2990 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2991 SDHCI_SUPPORT_SDR50 |
2992 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 2993 if (ret) {
2994 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2995 mmc_hostname(mmc), ret);
2996 host->vqmmc = NULL;
2997 }
8363c374 2998 }
6231f3de 2999
6a66180a
DD		 3000 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3001 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3002 SDHCI_SUPPORT_DDR50);
3003
4188bba0
AC		 3004 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3005 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3006 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3007 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3008
3009 /* SDR104 supports also implies SDR50 support */
156e14b1 3010 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3011 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3012 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3013 * field can be promoted to support HS200.
3014 */
13868bf2
DC		 3015 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3016 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3017 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3018 mmc->caps |= MMC_CAP_UHS_SDR50;
3019
9107ebbf
MC		 3020 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3021 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3022 mmc->caps |= MMC_CAP_UHS_DDR50;
3023
069c9f14 3024 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3025 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3026 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3027
156e14b1 3028 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3029 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3030 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3031
d6d50a15
AN		 3032 /* Driver Type(s) (A, C, D) supported by the host */
3033 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3034 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3035 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3036 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3037 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3038 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3039
cf2b5eea
AN		 3040 /* Initial value for re-tuning timer count */
3041 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3042 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3043
3044 /*
3045 * In case Re-tuning Timer is not disabled, the actual value of
3046 * re-tuning timer will be 2 ^ (n - 1).
3047 */
3048 if (host->tuning_count)
3049 host->tuning_count = 1 << (host->tuning_count - 1);
3050
3051 /* Re-tuning mode supported by the Host Controller */
3052 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3053 SDHCI_RETUNING_MODE_SHIFT;
3054
8f230f45 3055 ocr_avail = 0;
bad37e1a 3056
462849aa 3057 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
657d5982
KL		 3058 if (IS_ERR_OR_NULL(host->vmmc)) {
3059 if (PTR_ERR(host->vmmc) < 0) {
3060 pr_info("%s: no vmmc regulator found\n",
3061 mmc_hostname(mmc));
3062 host->vmmc = NULL;
3063 }
8363c374 3064 }
bad37e1a 3065
68737043 3066#ifdef CONFIG_REGULATOR
a4f8f257
MS		 3067 /*
3068 * Voltage range check makes sense only if regulator reports
3069 * any voltage value.
3070 */
3071 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 3072 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3073 3600000);
68737043
PR		 3074 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3075 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 3076 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3077 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 3078 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3079 1950000);
68737043
PR		 3080 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3081 caps[0] &= ~SDHCI_CAN_VDD_180;
3082 }
3083#endif /* CONFIG_REGULATOR */
3084
f2119df6
AN		 3085 /*
3086 * According to SD Host Controller spec v3.00, if the Host System
3087 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3088 * the value is meaningful only if Voltage Support in the Capabilities
3089 * register is set. The actual current value is 4 times the register
3090 * value.
3091 */
3092 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3093 if (!max_current_caps && host->vmmc) {
3094 u32 curr = regulator_get_current_limit(host->vmmc);
3095 if (curr > 0) {
3096
3097 /* convert to SDHCI_MAX_CURRENT format */
3098 curr = curr/1000; /* convert to mA */
3099 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3100
3101 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3102 max_current_caps =
3103 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3104 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3105 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3106 }
3107 }
f2119df6
AN		 3108
3109 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3110 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3111
55c4665e 3112 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3113 SDHCI_MAX_CURRENT_330_MASK) >>
3114 SDHCI_MAX_CURRENT_330_SHIFT) *
3115 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3116 }
3117 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3118 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3119
55c4665e 3120 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3121 SDHCI_MAX_CURRENT_300_MASK) >>
3122 SDHCI_MAX_CURRENT_300_SHIFT) *
3123 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3124 }
3125 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3126 ocr_avail |= MMC_VDD_165_195;
3127
55c4665e 3128 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3129 SDHCI_MAX_CURRENT_180_MASK) >>
3130 SDHCI_MAX_CURRENT_180_SHIFT) *
3131 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3132 }
3133
c0b887b6
HZ		 3134 if (host->ocr_mask)
3135 ocr_avail = host->ocr_mask;
3136
8f230f45
TI		 3137 mmc->ocr_avail = ocr_avail;
3138 mmc->ocr_avail_sdio = ocr_avail;
3139 if (host->ocr_avail_sdio)
3140 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3141 mmc->ocr_avail_sd = ocr_avail;
3142 if (host->ocr_avail_sd)
3143 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3144 else /* normal SD controllers don't support 1.8V */
3145 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3146 mmc->ocr_avail_mmc = ocr_avail;
3147 if (host->ocr_avail_mmc)
3148 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3149
3150 if (mmc->ocr_avail == 0) {
a3c76eb9 3151 pr_err("%s: Hardware doesn't report any "
b69c9058 3152 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3153 return -ENODEV;
146ad66e
PO		 3154 }
3155
d129bceb
PO		 3156 spin_lock_init(&host->lock);
3157
3158 /*
2134a922
PO		 3159 * Maximum number of segments. Depends on if the hardware
3160 * can do scatter/gather or not.
d129bceb 3161 */
2134a922 3162 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3163 mmc->max_segs = 128;
a13abc7b 3164 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3165 mmc->max_segs = 1;
2134a922 3166 else /* PIO */
a36274e0 3167 mmc->max_segs = 128;
d129bceb
PO		 3168
3169 /*
bab76961 3170 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3171 * size (512KiB).
d129bceb 3172 */
55db890a 3173 mmc->max_req_size = 524288;
d129bceb
PO		 3174
3175 /*
3176 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3177 * of bytes. When doing hardware scatter/gather, each entry cannot
3178 * be larger than 64 KiB though.
d129bceb 3179 */
30652aa3
OJ		 3180 if (host->flags & SDHCI_USE_ADMA) {
3181 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3182 mmc->max_seg_size = 65535;
3183 else
3184 mmc->max_seg_size = 65536;
3185 } else {
2134a922 3186 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3187 }
d129bceb 3188
fe4a3c7a
PO		 3189 /*
3190 * Maximum block size. This varies from controller to controller and
3191 * is specified in the capabilities register.
3192 */
0633f654
AV		 3193 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3194 mmc->max_blk_size = 2;
3195 } else {
f2119df6 3196 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3197 SDHCI_MAX_BLOCK_SHIFT;
3198 if (mmc->max_blk_size >= 3) {
a3c76eb9 3199 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3200 "assuming 512 bytes\n", mmc_hostname(mmc));
3201 mmc->max_blk_size = 0;
3202 }
3203 }
3204
3205 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3206
55db890a
PO		 3207 /*
3208 * Maximum block count.
3209 */
1388eefd 3210 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3211
d129bceb
PO		 3212 /*
3213 * Init tasklets.
3214 */
d129bceb
PO		 3215 tasklet_init(&host->finish_tasklet,
3216 sdhci_tasklet_finish, (unsigned long)host);
3217
e4cad1b5 3218 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3219
cf2b5eea 3220 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3221 init_waitqueue_head(&host->buf_ready_int);
3222
cf2b5eea
AN		 3223 /* Initialize re-tuning timer */
3224 init_timer(&host->tuning_timer);
3225 host->tuning_timer.data = (unsigned long)host;
3226 host->tuning_timer.function = sdhci_tuning_timer;
3227 }
3228
2af502ca
SG		 3229 sdhci_init(host, 0);
3230
781e989c
RK		 3231 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3232 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3233 if (ret) {
3234 pr_err("%s: Failed to request IRQ %d: %d\n",
3235 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3236 goto untasklet;
0fc81ee3 3237 }
d129bceb 3238
d129bceb
PO		 3239#ifdef CONFIG_MMC_DEBUG
3240 sdhci_dumpregs(host);
3241#endif
3242
f9134319 3243#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3244 snprintf(host->led_name, sizeof(host->led_name),
3245 "%s::", mmc_hostname(mmc));
3246 host->led.name = host->led_name;
2f730fec
PO		 3247 host->led.brightness = LED_OFF;
3248 host->led.default_trigger = mmc_hostname(mmc);
3249 host->led.brightness_set = sdhci_led_control;
3250
b8c86fc5 3251 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3252 if (ret) {
3253 pr_err("%s: Failed to register LED device: %d\n",
3254 mmc_hostname(mmc), ret);
2f730fec 3255 goto reset;
0fc81ee3 3256 }
2f730fec
PO		 3257#endif
3258
5f25a66f
PO		 3259 mmiowb();
3260
d129bceb
PO		 3261 mmc_add_host(mmc);
3262
a3c76eb9 3263 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3264 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3265 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3266 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3267
7260cf5e
AV		 3268 sdhci_enable_card_detection(host);
3269
d129bceb
PO		 3270 return 0;
3271
f9134319 3272#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3273reset:
03231f9b 3274 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3275 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3276 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3277 free_irq(host->irq, host);
3278#endif
8ef1a143 3279untasklet:
d129bceb 3280 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3281
3282 return ret;
3283}
3284
b8c86fc5 3285EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3286
1e72859e 3287void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3288{
1e72859e
PO		 3289 unsigned long flags;
3290
3291 if (dead) {
3292 spin_lock_irqsave(&host->lock, flags);
3293
3294 host->flags |= SDHCI_DEVICE_DEAD;
3295
3296 if (host->mrq) {
a3c76eb9 3297 pr_err("%s: Controller removed during "
1e72859e
PO		 3298 " transfer!\n", mmc_hostname(host->mmc));
3299
3300 host->mrq->cmd->error = -ENOMEDIUM;
3301 tasklet_schedule(&host->finish_tasklet);
3302 }
3303
3304 spin_unlock_irqrestore(&host->lock, flags);
3305 }
3306
7260cf5e
AV		 3307 sdhci_disable_card_detection(host);
3308
b8c86fc5 3309 mmc_remove_host(host->mmc);
d129bceb 3310
f9134319 3311#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3312 led_classdev_unregister(&host->led);
3313#endif
3314
1e72859e 3315 if (!dead)
03231f9b 3316 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3317
b537f94c
RK		 3318 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3319 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3320 free_irq(host->irq, host);
3321
3322 del_timer_sync(&host->timer);
3323
d129bceb 3324 tasklet_kill(&host->finish_tasklet);
2134a922 3325
77dcb3f4
PR		 3326 if (host->vmmc) {
3327 regulator_disable(host->vmmc);
9bea3c85 3328 regulator_put(host->vmmc);
77dcb3f4 3329 }
9bea3c85 3330
6231f3de
PR		 3331 if (host->vqmmc) {
3332 regulator_disable(host->vqmmc);
3333 regulator_put(host->vqmmc);
3334 }
3335
2134a922
PO		 3336 kfree(host->adma_desc);
3337 kfree(host->align_buffer);
3338
3339 host->adma_desc = NULL;
3340 host->align_buffer = NULL;
d129bceb
PO		 3341}
3342
b8c86fc5 3343EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3344
b8c86fc5 3345void sdhci_free_host(struct sdhci_host *host)
d129bceb 3346{
b8c86fc5 3347 mmc_free_host(host->mmc);
d129bceb
PO		 3348}
3349
b8c86fc5 3350EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3351
3352/*****************************************************************************\
3353 * *
3354 * Driver init/exit *
3355 * *
3356\*****************************************************************************/
3357
3358static int __init sdhci_drv_init(void)
3359{
a3c76eb9 3360 pr_info(DRIVER_NAME
52fbf9c9 3361 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3362 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3363
b8c86fc5 3364 return 0;
d129bceb
PO		 3365}
3366
3367static void __exit sdhci_drv_exit(void)
3368{
d129bceb
PO		 3369}
3370
3371module_init(sdhci_drv_init);
3372module_exit(sdhci_drv_exit);
3373
df673b22 3374module_param(debug_quirks, uint, 0444);
66fd8ad5 3375module_param(debug_quirks2, uint, 0444);
67435274 3376
32710e8f 3377MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3378MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3379MODULE_LICENSE("GPL");
67435274 3380
df673b22 3381MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3382MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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