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mmc: core: Fixup signal voltage switch
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
52static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 55static void sdhci_tuning_timer(unsigned long data);
d129bceb 56
66fd8ad5
AH		 57#ifdef CONFIG_PM_RUNTIME
58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
60#else
61static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
62{
63 return 0;
64}
65static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
66{
67 return 0;
68}
69#endif
70
d129bceb
PO		 71static void sdhci_dumpregs(struct sdhci_host *host)
72{
a3c76eb9 73 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 74 mmc_hostname(host->mmc));
d129bceb 75
a3c76eb9 76 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 77 sdhci_readl(host, SDHCI_DMA_ADDRESS),
78 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 79 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 80 sdhci_readw(host, SDHCI_BLOCK_SIZE),
81 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 82 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 83 sdhci_readl(host, SDHCI_ARGUMENT),
84 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 85 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 86 sdhci_readl(host, SDHCI_PRESENT_STATE),
87 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 88 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readb(host, SDHCI_POWER_CONTROL),
90 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
93 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
96 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readl(host, SDHCI_INT_ENABLE),
99 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 100 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readw(host, SDHCI_ACMD12_ERR),
102 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 104 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 105 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 107 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 108 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 109 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 110 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 111
be3f4ae0 112 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 113 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 114 readl(host->ioaddr + SDHCI_ADMA_ERROR),
115 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
116
a3c76eb9 117 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 118}
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
7260cf5e
AV		 126static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
127{
128 u32 ier;
129
130 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
131 ier &= ~clear;
132 ier |= set;
133 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
134 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
135}
136
137static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
138{
139 sdhci_clear_set_irqs(host, 0, irqs);
140}
141
142static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
143{
144 sdhci_clear_set_irqs(host, irqs, 0);
145}
146
147static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
148{
d25928d1 149 u32 present, irqs;
7260cf5e 150
c79396c1 151 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 152 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 153 return;
154
d25928d1
SG		 155 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
156 SDHCI_CARD_PRESENT;
157 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
158
7260cf5e
AV		 159 if (enable)
160 sdhci_unmask_irqs(host, irqs);
161 else
162 sdhci_mask_irqs(host, irqs);
163}
164
165static void sdhci_enable_card_detection(struct sdhci_host *host)
166{
167 sdhci_set_card_detection(host, true);
168}
169
170static void sdhci_disable_card_detection(struct sdhci_host *host)
171{
172 sdhci_set_card_detection(host, false);
173}
174
d129bceb
PO		 175static void sdhci_reset(struct sdhci_host *host, u8 mask)
176{
e16514d8 177 unsigned long timeout;
063a9dbb 178 u32 uninitialized_var(ier);
e16514d8 179
b8c86fc5 180 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 181 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 182 SDHCI_CARD_PRESENT))
183 return;
184 }
185
063a9dbb
AV		 186 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
187 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
188
393c1a34
PR		 189 if (host->ops->platform_reset_enter)
190 host->ops->platform_reset_enter(host, mask);
191
4e4141a5 192 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 193
e16514d8 194 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 195 host->clock = 0;
196
e16514d8
PO		 197 /* Wait max 100 ms */
198 timeout = 100;
199
200 /* hw clears the bit when it's done */
4e4141a5 201 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 202 if (timeout == 0) {
a3c76eb9 203 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 204 mmc_hostname(host->mmc), (int)mask);
205 sdhci_dumpregs(host);
206 return;
207 }
208 timeout--;
209 mdelay(1);
d129bceb 210 }
063a9dbb 211
393c1a34
PR		 212 if (host->ops->platform_reset_exit)
213 host->ops->platform_reset_exit(host, mask);
214
063a9dbb
AV		 215 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
216 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
3abc1e80
SX		 217
218 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
219 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
220 host->ops->enable_dma(host);
221 }
d129bceb
PO		 222}
223
2f4cbb3d
NP		 224static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 227{
2f4cbb3d
NP		 228 if (soft)
229 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
230 else
231 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 232
7260cf5e
AV		 233 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
234 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 235 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
236 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 237 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 238
239 if (soft) {
240 /* force clock reconfiguration */
241 host->clock = 0;
242 sdhci_set_ios(host->mmc, &host->mmc->ios);
243 }
7260cf5e 244}
d129bceb 245
7260cf5e
AV		 246static void sdhci_reinit(struct sdhci_host *host)
247{
2f4cbb3d 248 sdhci_init(host, 0);
b67c6b41
AL		 249 /*
250 * Retuning stuffs are affected by different cards inserted and only
251 * applicable to UHS-I cards. So reset these fields to their initial
252 * value when card is removed.
253 */
973905fe
AL		 254 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
255 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
256
b67c6b41
AL		 257 del_timer_sync(&host->tuning_timer);
258 host->flags &= ~SDHCI_NEEDS_RETUNING;
259 host->mmc->max_blk_count =
260 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
261 }
7260cf5e 262 sdhci_enable_card_detection(host);
d129bceb
PO		 263}
264
265static void sdhci_activate_led(struct sdhci_host *host)
266{
267 u8 ctrl;
268
4e4141a5 269 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 270 ctrl |= SDHCI_CTRL_LED;
4e4141a5 271 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 272}
273
274static void sdhci_deactivate_led(struct sdhci_host *host)
275{
276 u8 ctrl;
277
4e4141a5 278 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 279 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 280 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 281}
282
f9134319 283#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 284static void sdhci_led_control(struct led_classdev *led,
285 enum led_brightness brightness)
286{
287 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
288 unsigned long flags;
289
290 spin_lock_irqsave(&host->lock, flags);
291
66fd8ad5
AH		 292 if (host->runtime_suspended)
293 goto out;
294
2f730fec
PO		 295 if (brightness == LED_OFF)
296 sdhci_deactivate_led(host);
297 else
298 sdhci_activate_led(host);
66fd8ad5 299out:
2f730fec
PO		 300 spin_unlock_irqrestore(&host->lock, flags);
301}
302#endif
303
d129bceb
PO		 304/*****************************************************************************\
305 * *
306 * Core functions *
307 * *
308\*****************************************************************************/
309
a406f5a3 310static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 311{
7659150c
PO		 312 unsigned long flags;
313 size_t blksize, len, chunk;
7244b85b 314 u32 uninitialized_var(scratch);
7659150c 315 u8 *buf;
d129bceb 316
a406f5a3 317 DBG("PIO reading\n");
d129bceb 318
a406f5a3 319 blksize = host->data->blksz;
7659150c 320 chunk = 0;
d129bceb 321
7659150c 322 local_irq_save(flags);
d129bceb 323
a406f5a3 324 while (blksize) {
7659150c
PO		 325 if (!sg_miter_next(&host->sg_miter))
326 BUG();
d129bceb 327
7659150c 328 len = min(host->sg_miter.length, blksize);
d129bceb 329
7659150c
PO		 330 blksize -= len;
331 host->sg_miter.consumed = len;
14d836e7 332
7659150c 333 buf = host->sg_miter.addr;
d129bceb 334
7659150c
PO		 335 while (len) {
336 if (chunk == 0) {
4e4141a5 337 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 338 chunk = 4;
a406f5a3 339 }
7659150c
PO		 340
341 *buf = scratch & 0xFF;
342
343 buf++;
344 scratch >>= 8;
345 chunk--;
346 len--;
d129bceb 347 }
a406f5a3 348 }
7659150c
PO		 349
350 sg_miter_stop(&host->sg_miter);
351
352 local_irq_restore(flags);
a406f5a3 353}
d129bceb 354
a406f5a3
PO		 355static void sdhci_write_block_pio(struct sdhci_host *host)
356{
7659150c
PO		 357 unsigned long flags;
358 size_t blksize, len, chunk;
359 u32 scratch;
360 u8 *buf;
d129bceb 361
a406f5a3
PO		 362 DBG("PIO writing\n");
363
364 blksize = host->data->blksz;
7659150c
PO		 365 chunk = 0;
366 scratch = 0;
d129bceb 367
7659150c 368 local_irq_save(flags);
d129bceb 369
a406f5a3 370 while (blksize) {
7659150c
PO		 371 if (!sg_miter_next(&host->sg_miter))
372 BUG();
a406f5a3 373
7659150c
PO		 374 len = min(host->sg_miter.length, blksize);
375
376 blksize -= len;
377 host->sg_miter.consumed = len;
378
379 buf = host->sg_miter.addr;
d129bceb 380
7659150c
PO		 381 while (len) {
382 scratch |= (u32)*buf << (chunk * 8);
383
384 buf++;
385 chunk++;
386 len--;
387
388 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 389 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 390 chunk = 0;
391 scratch = 0;
d129bceb 392 }
d129bceb
PO		 393 }
394 }
7659150c
PO		 395
396 sg_miter_stop(&host->sg_miter);
397
398 local_irq_restore(flags);
a406f5a3
PO		 399}
400
401static void sdhci_transfer_pio(struct sdhci_host *host)
402{
403 u32 mask;
404
405 BUG_ON(!host->data);
406
7659150c 407 if (host->blocks == 0)
a406f5a3
PO		 408 return;
409
410 if (host->data->flags & MMC_DATA_READ)
411 mask = SDHCI_DATA_AVAILABLE;
412 else
413 mask = SDHCI_SPACE_AVAILABLE;
414
4a3cba32
PO		 415 /*
416 * Some controllers (JMicron JMB38x) mess up the buffer bits
417 * for transfers < 4 bytes. As long as it is just one block,
418 * we can ignore the bits.
419 */
420 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
421 (host->data->blocks == 1))
422 mask = ~0;
423
4e4141a5 424 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 425 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
426 udelay(100);
427
a406f5a3
PO		 428 if (host->data->flags & MMC_DATA_READ)
429 sdhci_read_block_pio(host);
430 else
431 sdhci_write_block_pio(host);
d129bceb 432
7659150c
PO		 433 host->blocks--;
434 if (host->blocks == 0)
a406f5a3 435 break;
a406f5a3 436 }
d129bceb 437
a406f5a3 438 DBG("PIO transfer complete.\n");
d129bceb
PO		 439}
440
2134a922
PO		 441static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
442{
443 local_irq_save(*flags);
482fce99 444 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 445}
446
447static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
448{
482fce99 449 kunmap_atomic(buffer);
2134a922
PO		 450 local_irq_restore(*flags);
451}
452
118cd17d
BD		 453static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
454{
9e506f35
BD		 455 __le32 *dataddr = (__le32 __force *)(desc + 4);
456 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 457
9e506f35
BD		 458 /* SDHCI specification says ADMA descriptors should be 4 byte
459 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 460
9e506f35
BD		 461 cmdlen[0] = cpu_to_le16(cmd);
462 cmdlen[1] = cpu_to_le16(len);
463
464 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 465}
466
8f1934ce 467static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 468 struct mmc_data *data)
469{
470 int direction;
471
472 u8 *desc;
473 u8 *align;
474 dma_addr_t addr;
475 dma_addr_t align_addr;
476 int len, offset;
477
478 struct scatterlist *sg;
479 int i;
480 char *buffer;
481 unsigned long flags;
482
483 /*
484 * The spec does not specify endianness of descriptor table.
485 * We currently guess that it is LE.
486 */
487
488 if (data->flags & MMC_DATA_READ)
489 direction = DMA_FROM_DEVICE;
490 else
491 direction = DMA_TO_DEVICE;
492
493 /*
494 * The ADMA descriptor table is mapped further down as we
495 * need to fill it with data first.
496 */
497
498 host->align_addr = dma_map_single(mmc_dev(host->mmc),
499 host->align_buffer, 128 * 4, direction);
8d8bb39b 500 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 501 goto fail;
2134a922
PO		 502 BUG_ON(host->align_addr & 0x3);
503
504 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
505 data->sg, data->sg_len, direction);
8f1934ce
PO		 506 if (host->sg_count == 0)
507 goto unmap_align;
2134a922
PO		 508
509 desc = host->adma_desc;
510 align = host->align_buffer;
511
512 align_addr = host->align_addr;
513
514 for_each_sg(data->sg, sg, host->sg_count, i) {
515 addr = sg_dma_address(sg);
516 len = sg_dma_len(sg);
517
518 /*
519 * The SDHCI specification states that ADMA
520 * addresses must be 32-bit aligned. If they
521 * aren't, then we use a bounce buffer for
522 * the (up to three) bytes that screw up the
523 * alignment.
524 */
525 offset = (4 - (addr & 0x3)) & 0x3;
526 if (offset) {
527 if (data->flags & MMC_DATA_WRITE) {
528 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 529 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 530 memcpy(align, buffer, offset);
531 sdhci_kunmap_atomic(buffer, &flags);
532 }
533
118cd17d
BD		 534 /* tran, valid */
535 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 536
537 BUG_ON(offset > 65536);
538
2134a922
PO		 539 align += 4;
540 align_addr += 4;
541
542 desc += 8;
543
544 addr += offset;
545 len -= offset;
546 }
547
2134a922
PO		 548 BUG_ON(len > 65536);
549
118cd17d
BD		 550 /* tran, valid */
551 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 552 desc += 8;
553
554 /*
555 * If this triggers then we have a calculation bug
556 * somewhere. :/
557 */
558 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
559 }
560
70764a90
TA		 561 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
562 /*
563 * Mark the last descriptor as the terminating descriptor
564 */
565 if (desc != host->adma_desc) {
566 desc -= 8;
567 desc[0] |= 0x2; /* end */
568 }
569 } else {
570 /*
571 * Add a terminating entry.
572 */
2134a922 573
70764a90
TA		 574 /* nop, end, valid */
575 sdhci_set_adma_desc(desc, 0, 0, 0x3);
576 }
2134a922
PO		 577
578 /*
579 * Resync align buffer as we might have changed it.
580 */
581 if (data->flags & MMC_DATA_WRITE) {
582 dma_sync_single_for_device(mmc_dev(host->mmc),
583 host->align_addr, 128 * 4, direction);
584 }
585
586 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
587 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 588 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 589 goto unmap_entries;
2134a922 590 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 591
592 return 0;
593
594unmap_entries:
595 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
596 data->sg_len, direction);
597unmap_align:
598 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
599 128 * 4, direction);
600fail:
601 return -EINVAL;
2134a922
PO		 602}
603
604static void sdhci_adma_table_post(struct sdhci_host *host,
605 struct mmc_data *data)
606{
607 int direction;
608
609 struct scatterlist *sg;
610 int i, size;
611 u8 *align;
612 char *buffer;
613 unsigned long flags;
614
615 if (data->flags & MMC_DATA_READ)
616 direction = DMA_FROM_DEVICE;
617 else
618 direction = DMA_TO_DEVICE;
619
620 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
621 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
622
623 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
624 128 * 4, direction);
625
626 if (data->flags & MMC_DATA_READ) {
627 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
628 data->sg_len, direction);
629
630 align = host->align_buffer;
631
632 for_each_sg(data->sg, sg, host->sg_count, i) {
633 if (sg_dma_address(sg) & 0x3) {
634 size = 4 - (sg_dma_address(sg) & 0x3);
635
636 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 637 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 638 memcpy(buffer, align, size);
639 sdhci_kunmap_atomic(buffer, &flags);
640
641 align += 4;
642 }
643 }
644 }
645
646 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
647 data->sg_len, direction);
648}
649
a3c7778f 650static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 651{
1c8cde92 652 u8 count;
a3c7778f 653 struct mmc_data *data = cmd->data;
1c8cde92 654 unsigned target_timeout, current_timeout;
d129bceb 655
ee53ab5d
PO		 656 /*
657 * If the host controller provides us with an incorrect timeout
658 * value, just skip the check and use 0xE. The hardware may take
659 * longer to time out, but that's much better than having a too-short
660 * timeout value.
661 */
11a2f1b7 662 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 663 return 0xE;
e538fbe8 664
a3c7778f
AW		 665 /* Unspecified timeout, assume max */
666 if (!data && !cmd->cmd_timeout_ms)
667 return 0xE;
d129bceb 668
a3c7778f
AW		 669 /* timeout in us */
670 if (!data)
671 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 672 else {
673 target_timeout = data->timeout_ns / 1000;
674 if (host->clock)
675 target_timeout += data->timeout_clks / host->clock;
676 }
81b39802 677
1c8cde92
PO		 678 /*
679 * Figure out needed cycles.
680 * We do this in steps in order to fit inside a 32 bit int.
681 * The first step is the minimum timeout, which will have a
682 * minimum resolution of 6 bits:
683 * (1) 2^13*1000 > 2^22,
684 * (2) host->timeout_clk < 2^16
685 * =>
686 * (1) / (2) > 2^6
687 */
688 count = 0;
689 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
690 while (current_timeout < target_timeout) {
691 count++;
692 current_timeout <<= 1;
693 if (count >= 0xF)
694 break;
695 }
696
697 if (count >= 0xF) {
09eeff52
CB		 698 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
699 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 700 count = 0xE;
701 }
702
ee53ab5d
PO		 703 return count;
704}
705
6aa943ab
AV		 706static void sdhci_set_transfer_irqs(struct sdhci_host *host)
707{
708 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
709 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
710
711 if (host->flags & SDHCI_REQ_USE_DMA)
712 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
713 else
714 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
715}
716
a3c7778f 717static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 718{
719 u8 count;
2134a922 720 u8 ctrl;
a3c7778f 721 struct mmc_data *data = cmd->data;
8f1934ce 722 int ret;
ee53ab5d
PO		 723
724 WARN_ON(host->data);
725
a3c7778f
AW		 726 if (data || (cmd->flags & MMC_RSP_BUSY)) {
727 count = sdhci_calc_timeout(host, cmd);
728 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
729 }
730
731 if (!data)
ee53ab5d
PO		 732 return;
733
734 /* Sanity checks */
735 BUG_ON(data->blksz * data->blocks > 524288);
736 BUG_ON(data->blksz > host->mmc->max_blk_size);
737 BUG_ON(data->blocks > 65535);
738
739 host->data = data;
740 host->data_early = 0;
f6a03cbf 741 host->data->bytes_xfered = 0;
ee53ab5d 742
a13abc7b 743 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 744 host->flags |= SDHCI_REQ_USE_DMA;
745
2134a922
PO		 746 /*
747 * FIXME: This doesn't account for merging when mapping the
748 * scatterlist.
749 */
750 if (host->flags & SDHCI_REQ_USE_DMA) {
751 int broken, i;
752 struct scatterlist *sg;
753
754 broken = 0;
755 if (host->flags & SDHCI_USE_ADMA) {
756 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
757 broken = 1;
758 } else {
759 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
760 broken = 1;
761 }
762
763 if (unlikely(broken)) {
764 for_each_sg(data->sg, sg, data->sg_len, i) {
765 if (sg->length & 0x3) {
766 DBG("Reverting to PIO because of "
767 "transfer size (%d)\n",
768 sg->length);
769 host->flags &= ~SDHCI_REQ_USE_DMA;
770 break;
771 }
772 }
773 }
c9fddbc4
PO		 774 }
775
776 /*
777 * The assumption here being that alignment is the same after
778 * translation to device address space.
779 */
2134a922
PO		 780 if (host->flags & SDHCI_REQ_USE_DMA) {
781 int broken, i;
782 struct scatterlist *sg;
783
784 broken = 0;
785 if (host->flags & SDHCI_USE_ADMA) {
786 /*
787 * As we use 3 byte chunks to work around
788 * alignment problems, we need to check this
789 * quirk.
790 */
791 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
792 broken = 1;
793 } else {
794 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
795 broken = 1;
796 }
797
798 if (unlikely(broken)) {
799 for_each_sg(data->sg, sg, data->sg_len, i) {
800 if (sg->offset & 0x3) {
801 DBG("Reverting to PIO because of "
802 "bad alignment\n");
803 host->flags &= ~SDHCI_REQ_USE_DMA;
804 break;
805 }
806 }
807 }
808 }
809
8f1934ce
PO		 810 if (host->flags & SDHCI_REQ_USE_DMA) {
811 if (host->flags & SDHCI_USE_ADMA) {
812 ret = sdhci_adma_table_pre(host, data);
813 if (ret) {
814 /*
815 * This only happens when someone fed
816 * us an invalid request.
817 */
818 WARN_ON(1);
ebd6d357 819 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 820 } else {
4e4141a5
AV		 821 sdhci_writel(host, host->adma_addr,
822 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 823 }
824 } else {
c8b3e02e 825 int sg_cnt;
8f1934ce 826
c8b3e02e 827 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 828 data->sg, data->sg_len,
829 (data->flags & MMC_DATA_READ) ?
830 DMA_FROM_DEVICE :
831 DMA_TO_DEVICE);
c8b3e02e 832 if (sg_cnt == 0) {
8f1934ce
PO		 833 /*
834 * This only happens when someone fed
835 * us an invalid request.
836 */
837 WARN_ON(1);
ebd6d357 838 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 839 } else {
719a61b4 840 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 841 sdhci_writel(host, sg_dma_address(data->sg),
842 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 843 }
844 }
845 }
846
2134a922
PO		 847 /*
848 * Always adjust the DMA selection as some controllers
849 * (e.g. JMicron) can't do PIO properly when the selection
850 * is ADMA.
851 */
852 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 853 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 854 ctrl &= ~SDHCI_CTRL_DMA_MASK;
855 if ((host->flags & SDHCI_REQ_USE_DMA) &&
856 (host->flags & SDHCI_USE_ADMA))
857 ctrl |= SDHCI_CTRL_ADMA32;
858 else
859 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 860 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 861 }
862
8f1934ce 863 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 864 int flags;
865
866 flags = SG_MITER_ATOMIC;
867 if (host->data->flags & MMC_DATA_READ)
868 flags |= SG_MITER_TO_SG;
869 else
870 flags |= SG_MITER_FROM_SG;
871 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 872 host->blocks = data->blocks;
d129bceb 873 }
c7fa9963 874
6aa943ab
AV		 875 sdhci_set_transfer_irqs(host);
876
f6a03cbf
MV		 877 /* Set the DMA boundary value and block size */
878 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
879 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 880 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 881}
882
883static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 884 struct mmc_command *cmd)
c7fa9963
PO		 885{
886 u16 mode;
e89d456f 887 struct mmc_data *data = cmd->data;
c7fa9963 888
c7fa9963
PO		 889 if (data == NULL)
890 return;
891
e538fbe8
PO		 892 WARN_ON(!host->data);
893
c7fa9963 894 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 895 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
896 mode |= SDHCI_TRNS_MULTI;
897 /*
898 * If we are sending CMD23, CMD12 never gets sent
899 * on successful completion (so no Auto-CMD12).
900 */
901 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
902 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 903 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
904 mode |= SDHCI_TRNS_AUTO_CMD23;
905 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
906 }
c4512f79 907 }
8edf6371 908
c7fa9963
PO		 909 if (data->flags & MMC_DATA_READ)
910 mode |= SDHCI_TRNS_READ;
c9fddbc4 911 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 912 mode |= SDHCI_TRNS_DMA;
913
4e4141a5 914 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 915}
916
917static void sdhci_finish_data(struct sdhci_host *host)
918{
919 struct mmc_data *data;
d129bceb
PO		 920
921 BUG_ON(!host->data);
922
923 data = host->data;
924 host->data = NULL;
925
c9fddbc4 926 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 927 if (host->flags & SDHCI_USE_ADMA)
928 sdhci_adma_table_post(host, data);
929 else {
930 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
931 data->sg_len, (data->flags & MMC_DATA_READ) ?
932 DMA_FROM_DEVICE : DMA_TO_DEVICE);
933 }
d129bceb
PO		 934 }
935
936 /*
c9b74c5b
PO		 937 * The specification states that the block count register must
938 * be updated, but it does not specify at what point in the
939 * data flow. That makes the register entirely useless to read
940 * back so we have to assume that nothing made it to the card
941 * in the event of an error.
d129bceb 942 */
c9b74c5b
PO		 943 if (data->error)
944 data->bytes_xfered = 0;
d129bceb 945 else
c9b74c5b 946 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 947
e89d456f
AW		 948 /*
949 * Need to send CMD12 if -
950 * a) open-ended multiblock transfer (no CMD23)
951 * b) error in multiblock transfer
952 */
953 if (data->stop &&
954 (data->error ||
955 !host->mrq->sbc)) {
956
d129bceb
PO		 957 /*
958 * The controller needs a reset of internal state machines
959 * upon error conditions.
960 */
17b0429d 961 if (data->error) {
d129bceb
PO		 962 sdhci_reset(host, SDHCI_RESET_CMD);
963 sdhci_reset(host, SDHCI_RESET_DATA);
964 }
965
966 sdhci_send_command(host, data->stop);
967 } else
968 tasklet_schedule(&host->finish_tasklet);
969}
970
971static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
972{
973 int flags;
fd2208d7 974 u32 mask;
7cb2c76f 975 unsigned long timeout;
d129bceb
PO		 976
977 WARN_ON(host->cmd);
978
d129bceb 979 /* Wait max 10 ms */
7cb2c76f 980 timeout = 10;
fd2208d7
PO		 981
982 mask = SDHCI_CMD_INHIBIT;
983 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
984 mask |= SDHCI_DATA_INHIBIT;
985
986 /* We shouldn't wait for data inihibit for stop commands, even
987 though they might use busy signaling */
988 if (host->mrq->data && (cmd == host->mrq->data->stop))
989 mask &= ~SDHCI_DATA_INHIBIT;
990
4e4141a5 991 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 992 if (timeout == 0) {
a3c76eb9 993 pr_err("%s: Controller never released "
acf1da45 994 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 995 sdhci_dumpregs(host);
17b0429d 996 cmd->error = -EIO;
d129bceb
PO		 997 tasklet_schedule(&host->finish_tasklet);
998 return;
999 }
7cb2c76f
PO		 1000 timeout--;
1001 mdelay(1);
1002 }
d129bceb
PO		 1003
1004 mod_timer(&host->timer, jiffies + 10 * HZ);
1005
1006 host->cmd = cmd;
1007
a3c7778f 1008 sdhci_prepare_data(host, cmd);
d129bceb 1009
4e4141a5 1010 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1011
e89d456f 1012 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1013
d129bceb 1014 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1015 pr_err("%s: Unsupported response type!\n",
d129bceb 1016 mmc_hostname(host->mmc));
17b0429d 1017 cmd->error = -EINVAL;
d129bceb
PO		 1018 tasklet_schedule(&host->finish_tasklet);
1019 return;
1020 }
1021
1022 if (!(cmd->flags & MMC_RSP_PRESENT))
1023 flags = SDHCI_CMD_RESP_NONE;
1024 else if (cmd->flags & MMC_RSP_136)
1025 flags = SDHCI_CMD_RESP_LONG;
1026 else if (cmd->flags & MMC_RSP_BUSY)
1027 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1028 else
1029 flags = SDHCI_CMD_RESP_SHORT;
1030
1031 if (cmd->flags & MMC_RSP_CRC)
1032 flags |= SDHCI_CMD_CRC;
1033 if (cmd->flags & MMC_RSP_OPCODE)
1034 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1035
1036 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1037 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1038 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1039 flags |= SDHCI_CMD_DATA;
1040
4e4141a5 1041 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1042}
1043
1044static void sdhci_finish_command(struct sdhci_host *host)
1045{
1046 int i;
1047
1048 BUG_ON(host->cmd == NULL);
1049
1050 if (host->cmd->flags & MMC_RSP_PRESENT) {
1051 if (host->cmd->flags & MMC_RSP_136) {
1052 /* CRC is stripped so we need to do some shifting. */
1053 for (i = 0;i < 4;i++) {
4e4141a5 1054 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1055 SDHCI_RESPONSE + (3-i)*4) << 8;
1056 if (i != 3)
1057 host->cmd->resp[i] |=
4e4141a5 1058 sdhci_readb(host,
d129bceb
PO		 1059 SDHCI_RESPONSE + (3-i)*4-1);
1060 }
1061 } else {
4e4141a5 1062 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1063 }
1064 }
1065
17b0429d 1066 host->cmd->error = 0;
d129bceb 1067
e89d456f
AW		 1068 /* Finished CMD23, now send actual command. */
1069 if (host->cmd == host->mrq->sbc) {
1070 host->cmd = NULL;
1071 sdhci_send_command(host, host->mrq->cmd);
1072 } else {
e538fbe8 1073
e89d456f
AW		 1074 /* Processed actual command. */
1075 if (host->data && host->data_early)
1076 sdhci_finish_data(host);
d129bceb 1077
e89d456f
AW		 1078 if (!host->cmd->data)
1079 tasklet_schedule(&host->finish_tasklet);
1080
1081 host->cmd = NULL;
1082 }
d129bceb
PO		 1083}
1084
1085static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1086{
c3ed3877 1087 int div = 0; /* Initialized for compiler warning */
df16219f 1088 int real_div = div, clk_mul = 1;
c3ed3877 1089 u16 clk = 0;
7cb2c76f 1090 unsigned long timeout;
d129bceb 1091
30832ab5 1092 if (clock && clock == host->clock)
d129bceb
PO		 1093 return;
1094
df16219f
GC		 1095 host->mmc->actual_clock = 0;
1096
8114634c
AV		 1097 if (host->ops->set_clock) {
1098 host->ops->set_clock(host, clock);
1099 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1100 return;
1101 }
1102
4e4141a5 1103 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1104
1105 if (clock == 0)
1106 goto out;
1107
85105c53 1108 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1109 /*
1110 * Check if the Host Controller supports Programmable Clock
1111 * Mode.
1112 */
1113 if (host->clk_mul) {
1114 u16 ctrl;
1115
1116 /*
1117 * We need to figure out whether the Host Driver needs
1118 * to select Programmable Clock Mode, or the value can
1119 * be set automatically by the Host Controller based on
1120 * the Preset Value registers.
1121 */
1122 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1123 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1124 for (div = 1; div <= 1024; div++) {
1125 if (((host->max_clk * host->clk_mul) /
1126 div) <= clock)
1127 break;
1128 }
1129 /*
1130 * Set Programmable Clock Mode in the Clock
1131 * Control register.
1132 */
1133 clk = SDHCI_PROG_CLOCK_MODE;
df16219f
GC		 1134 real_div = div;
1135 clk_mul = host->clk_mul;
c3ed3877
AN		 1136 div--;
1137 }
1138 } else {
1139 /* Version 3.00 divisors must be a multiple of 2. */
1140 if (host->max_clk <= clock)
1141 div = 1;
1142 else {
1143 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1144 div += 2) {
1145 if ((host->max_clk / div) <= clock)
1146 break;
1147 }
85105c53 1148 }
df16219f 1149 real_div = div;
c3ed3877 1150 div >>= 1;
85105c53
ZG		 1151 }
1152 } else {
1153 /* Version 2.00 divisors must be a power of 2. */
0397526d 1154 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1155 if ((host->max_clk / div) <= clock)
1156 break;
1157 }
df16219f 1158 real_div = div;
c3ed3877 1159 div >>= 1;
d129bceb 1160 }
d129bceb 1161
df16219f
GC		 1162 if (real_div)
1163 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1164
c3ed3877 1165 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1166 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1167 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1168 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1169 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1170
27f6cb16
CB		 1171 /* Wait max 20 ms */
1172 timeout = 20;
4e4141a5 1173 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1174 & SDHCI_CLOCK_INT_STABLE)) {
1175 if (timeout == 0) {
a3c76eb9 1176 pr_err("%s: Internal clock never "
acf1da45 1177 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1178 sdhci_dumpregs(host);
1179 return;
1180 }
7cb2c76f
PO		 1181 timeout--;
1182 mdelay(1);
1183 }
d129bceb
PO		 1184
1185 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1186 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1187
1188out:
1189 host->clock = clock;
1190}
1191
8213af3b
AS		 1192static inline void sdhci_update_clock(struct sdhci_host *host)
1193{
1194 unsigned int clock;
1195
1196 clock = host->clock;
1197 host->clock = 0;
1198 sdhci_set_clock(host, clock);
1199}
1200
ceb6143b 1201static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1202{
8364248a 1203 u8 pwr = 0;
146ad66e 1204
8364248a 1205 if (power != (unsigned short)-1) {
ae628903
PO		 1206 switch (1 << power) {
1207 case MMC_VDD_165_195:
1208 pwr = SDHCI_POWER_180;
1209 break;
1210 case MMC_VDD_29_30:
1211 case MMC_VDD_30_31:
1212 pwr = SDHCI_POWER_300;
1213 break;
1214 case MMC_VDD_32_33:
1215 case MMC_VDD_33_34:
1216 pwr = SDHCI_POWER_330;
1217 break;
1218 default:
1219 BUG();
1220 }
1221 }
1222
1223 if (host->pwr == pwr)
ceb6143b 1224 return -1;
146ad66e 1225
ae628903
PO		 1226 host->pwr = pwr;
1227
1228 if (pwr == 0) {
4e4141a5 1229 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ceb6143b 1230 return 0;
9e9dc5f2
DS		 1231 }
1232
1233 /*
1234 * Spec says that we should clear the power reg before setting
1235 * a new value. Some controllers don't seem to like this though.
1236 */
b8c86fc5 1237 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1238 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1239
e08c1694 1240 /*
c71f6512 1241 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1242 * and set turn on power at the same time, so set the voltage first.
1243 */
11a2f1b7 1244 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1245 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1246
ae628903 1247 pwr |= SDHCI_POWER_ON;
146ad66e 1248
ae628903 1249 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1250
1251 /*
1252 * Some controllers need an extra 10ms delay of 10ms before they
1253 * can apply clock after applying power
1254 */
11a2f1b7 1255 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1256 mdelay(10);
ceb6143b
AH		 1257
1258 return power;
146ad66e
PO		 1259}
1260
d129bceb
PO		 1261/*****************************************************************************\
1262 * *
1263 * MMC callbacks *
1264 * *
1265\*****************************************************************************/
1266
1267static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1268{
1269 struct sdhci_host *host;
505a8680 1270 int present;
d129bceb 1271 unsigned long flags;
473b095a 1272 u32 tuning_opcode;
d129bceb
PO		 1273
1274 host = mmc_priv(mmc);
1275
66fd8ad5
AH		 1276 sdhci_runtime_pm_get(host);
1277
d129bceb
PO		 1278 spin_lock_irqsave(&host->lock, flags);
1279
1280 WARN_ON(host->mrq != NULL);
1281
f9134319 1282#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1283 sdhci_activate_led(host);
2f730fec 1284#endif
e89d456f
AW		 1285
1286 /*
1287 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1288 * requests if Auto-CMD12 is enabled.
1289 */
1290 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1291 if (mrq->stop) {
1292 mrq->data->stop = NULL;
1293 mrq->stop = NULL;
1294 }
1295 }
d129bceb
PO		 1296
1297 host->mrq = mrq;
1298
505a8680
SG		 1299 /*
1300 * Firstly check card presence from cd-gpio. The return could
1301 * be one of the following possibilities:
1302 * negative: cd-gpio is not available
1303 * zero: cd-gpio is used, and card is removed
1304 * one: cd-gpio is used, and card is present
1305 */
1306 present = mmc_gpio_get_cd(host->mmc);
1307 if (present < 0) {
1308 /* If polling, assume that the card is always present. */
1309 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1310 present = 1;
1311 else
1312 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1313 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1314 }
1315
68d1fb7e 1316 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1317 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1318 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1319 } else {
1320 u32 present_state;
1321
1322 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1323 /*
1324 * Check if the re-tuning timer has already expired and there
1325 * is no on-going data transfer. If so, we need to execute
1326 * tuning procedure before sending command.
1327 */
1328 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1329 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1330 if (mmc->card) {
1331 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1332 tuning_opcode =
1333 mmc->card->type == MMC_TYPE_MMC ?
1334 MMC_SEND_TUNING_BLOCK_HS200 :
1335 MMC_SEND_TUNING_BLOCK;
1336 spin_unlock_irqrestore(&host->lock, flags);
1337 sdhci_execute_tuning(mmc, tuning_opcode);
1338 spin_lock_irqsave(&host->lock, flags);
1339
1340 /* Restore original mmc_request structure */
1341 host->mrq = mrq;
1342 }
cf2b5eea
AN		 1343 }
1344
8edf6371 1345 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1346 sdhci_send_command(host, mrq->sbc);
1347 else
1348 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1349 }
d129bceb 1350
5f25a66f 1351 mmiowb();
d129bceb
PO		 1352 spin_unlock_irqrestore(&host->lock, flags);
1353}
1354
66fd8ad5 1355static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1356{
d129bceb 1357 unsigned long flags;
ceb6143b 1358 int vdd_bit = -1;
d129bceb
PO		 1359 u8 ctrl;
1360
d129bceb
PO		 1361 spin_lock_irqsave(&host->lock, flags);
1362
ceb6143b
AH		 1363 if (host->flags & SDHCI_DEVICE_DEAD) {
1364 spin_unlock_irqrestore(&host->lock, flags);
1365 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1366 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1367 return;
1368 }
1e72859e 1369
d129bceb
PO		 1370 /*
1371 * Reset the chip on each power off.
1372 * Should clear out any weird states.
1373 */
1374 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1375 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1376 sdhci_reinit(host);
d129bceb
PO		 1377 }
1378
1379 sdhci_set_clock(host, ios->clock);
1380
1381 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1382 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1383 else
ceb6143b
AH		 1384 vdd_bit = sdhci_set_power(host, ios->vdd);
1385
1386 if (host->vmmc && vdd_bit != -1) {
1387 spin_unlock_irqrestore(&host->lock, flags);
1388 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1389 spin_lock_irqsave(&host->lock, flags);
1390 }
d129bceb 1391
643a81ff
PR		 1392 if (host->ops->platform_send_init_74_clocks)
1393 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1394
15ec4461
PR		 1395 /*
1396 * If your platform has 8-bit width support but is not a v3 controller,
1397 * or if it requires special setup code, you should implement that in
7bc088d3 1398 * platform_bus_width().
15ec4461 1399 */
7bc088d3
SH		 1400 if (host->ops->platform_bus_width) {
1401 host->ops->platform_bus_width(host, ios->bus_width);
1402 } else {
15ec4461
PR		 1403 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1404 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1405 ctrl &= ~SDHCI_CTRL_4BITBUS;
1406 if (host->version >= SDHCI_SPEC_300)
1407 ctrl |= SDHCI_CTRL_8BITBUS;
1408 } else {
1409 if (host->version >= SDHCI_SPEC_300)
1410 ctrl &= ~SDHCI_CTRL_8BITBUS;
1411 if (ios->bus_width == MMC_BUS_WIDTH_4)
1412 ctrl |= SDHCI_CTRL_4BITBUS;
1413 else
1414 ctrl &= ~SDHCI_CTRL_4BITBUS;
1415 }
1416 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1417 }
ae6d6c92 1418
15ec4461 1419 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1420
3ab9c8da
PR		 1421 if ((ios->timing == MMC_TIMING_SD_HS ||
1422 ios->timing == MMC_TIMING_MMC_HS)
1423 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1424 ctrl |= SDHCI_CTRL_HISPD;
1425 else
1426 ctrl &= ~SDHCI_CTRL_HISPD;
1427
d6d50a15 1428 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1429 u16 clk, ctrl_2;
49c468fc
AN		 1430
1431 /* In case of UHS-I modes, set High Speed Enable */
069c9f14
G		 1432 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1433 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1434 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1435 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1436 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1437 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1438
1439 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1440 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1441 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1442 /*
1443 * We only need to set Driver Strength if the
1444 * preset value enable is not set.
1445 */
1446 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1447 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1448 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1449 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1450 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1451
1452 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1453 } else {
1454 /*
1455 * According to SDHC Spec v3.00, if the Preset Value
1456 * Enable in the Host Control 2 register is set, we
1457 * need to reset SD Clock Enable before changing High
1458 * Speed Enable to avoid generating clock gliches.
1459 */
758535c4
AN		 1460
1461 /* Reset SD Clock Enable */
1462 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1463 clk &= ~SDHCI_CLOCK_CARD_EN;
1464 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1465
1466 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1467
1468 /* Re-enable SD Clock */
8213af3b 1469 sdhci_update_clock(host);
d6d50a15 1470 }
49c468fc 1471
49c468fc
AN		 1472
1473 /* Reset SD Clock Enable */
1474 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1475 clk &= ~SDHCI_CLOCK_CARD_EN;
1476 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1477
6322cdd0
PR		 1478 if (host->ops->set_uhs_signaling)
1479 host->ops->set_uhs_signaling(host, ios->timing);
1480 else {
1481 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1482 /* Select Bus Speed Mode for host */
1483 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
069c9f14
G		 1484 if (ios->timing == MMC_TIMING_MMC_HS200)
1485 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1486 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1487 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1488 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1489 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1490 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1491 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1492 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1493 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1494 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1495 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1496 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1497 }
49c468fc
AN		 1498
1499 /* Re-enable SD Clock */
8213af3b 1500 sdhci_update_clock(host);
758535c4
AN		 1501 } else
1502 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1503
b8352260
LD		 1504 /*
1505 * Some (ENE) controllers go apeshit on some ios operation,
1506 * signalling timeout and CRC errors even on CMD0. Resetting
1507 * it on each ios seems to solve the problem.
1508 */
b8c86fc5 1509 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1510 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1511
5f25a66f 1512 mmiowb();
d129bceb
PO		 1513 spin_unlock_irqrestore(&host->lock, flags);
1514}
1515
66fd8ad5
AH		 1516static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1517{
1518 struct sdhci_host *host = mmc_priv(mmc);
1519
1520 sdhci_runtime_pm_get(host);
1521 sdhci_do_set_ios(host, ios);
1522 sdhci_runtime_pm_put(host);
1523}
1524
1525static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1526{
d129bceb 1527 unsigned long flags;
2dfb579c 1528 int is_readonly;
d129bceb 1529
d129bceb
PO		 1530 spin_lock_irqsave(&host->lock, flags);
1531
1e72859e 1532 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1533 is_readonly = 0;
1534 else if (host->ops->get_ro)
1535 is_readonly = host->ops->get_ro(host);
1e72859e 1536 else
2dfb579c
WS		 1537 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1538 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1539
1540 spin_unlock_irqrestore(&host->lock, flags);
1541
2dfb579c
WS		 1542 /* This quirk needs to be replaced by a callback-function later */
1543 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1544 !is_readonly : is_readonly;
d129bceb
PO		 1545}
1546
82b0e23a
TI		 1547#define SAMPLE_COUNT 5
1548
66fd8ad5 1549static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1550{
82b0e23a
TI		 1551 int i, ro_count;
1552
82b0e23a 1553 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1554 return sdhci_check_ro(host);
82b0e23a
TI		 1555
1556 ro_count = 0;
1557 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1558 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1559 if (++ro_count > SAMPLE_COUNT / 2)
1560 return 1;
1561 }
1562 msleep(30);
1563 }
1564 return 0;
1565}
1566
20758b66
AH		 1567static void sdhci_hw_reset(struct mmc_host *mmc)
1568{
1569 struct sdhci_host *host = mmc_priv(mmc);
1570
1571 if (host->ops && host->ops->hw_reset)
1572 host->ops->hw_reset(host);
1573}
1574
66fd8ad5 1575static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1576{
66fd8ad5
AH		 1577 struct sdhci_host *host = mmc_priv(mmc);
1578 int ret;
f75979b7 1579
66fd8ad5
AH		 1580 sdhci_runtime_pm_get(host);
1581 ret = sdhci_do_get_ro(host);
1582 sdhci_runtime_pm_put(host);
1583 return ret;
1584}
f75979b7 1585
66fd8ad5
AH		 1586static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1587{
1e72859e
PO		 1588 if (host->flags & SDHCI_DEVICE_DEAD)
1589 goto out;
1590
66fd8ad5
AH		 1591 if (enable)
1592 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1593 else
1594 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1595
1596 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1597 if (host->runtime_suspended)
1598 goto out;
1599
f75979b7 1600 if (enable)
7260cf5e
AV		 1601 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1602 else
1603 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1604out:
f75979b7 1605 mmiowb();
66fd8ad5
AH		 1606}
1607
1608static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1609{
1610 struct sdhci_host *host = mmc_priv(mmc);
1611 unsigned long flags;
f75979b7 1612
66fd8ad5
AH		 1613 spin_lock_irqsave(&host->lock, flags);
1614 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1615 spin_unlock_irqrestore(&host->lock, flags);
1616}
1617
6231f3de
PR		 1618static int sdhci_do_3_3v_signal_voltage_switch(struct sdhci_host *host,
1619 u16 ctrl)
f2119df6 1620{
6231f3de 1621 int ret;
f2119df6 1622
6231f3de
PR		 1623 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1624 ctrl &= ~SDHCI_CTRL_VDD_180;
1625 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1626
6231f3de 1627 if (host->vqmmc) {
cec2e216 1628 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
6231f3de
PR		 1629 if (ret) {
1630 pr_warning("%s: Switching to 3.3V signalling voltage "
1631 " failed\n", mmc_hostname(host->mmc));
1632 return -EIO;
1633 }
1634 }
1635 /* Wait for 5ms */
1636 usleep_range(5000, 5500);
1637
1638 /* 3.3V regulator output should be stable within 5 ms */
f2119df6 1639 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
6231f3de
PR		 1640 if (!(ctrl & SDHCI_CTRL_VDD_180))
1641 return 0;
f2119df6 1642
6231f3de
PR		 1643 pr_warning("%s: 3.3V regulator output did not became stable\n",
1644 mmc_hostname(host->mmc));
f2119df6 1645
6231f3de
PR		 1646 return -EIO;
1647}
f2119df6 1648
6231f3de
PR		 1649static int sdhci_do_1_8v_signal_voltage_switch(struct sdhci_host *host,
1650 u16 ctrl)
1651{
1652 u8 pwr;
1653 u16 clk;
1654 u32 present_state;
1655 int ret;
1656
1657 /* Stop SDCLK */
1658 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1659 clk &= ~SDHCI_CLOCK_CARD_EN;
1660 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1661
1662 /* Check whether DAT[3:0] is 0000 */
1663 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1664 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1665 SDHCI_DATA_LVL_SHIFT)) {
1666 /*
1667 * Enable 1.8V Signal Enable in the Host Control2
1668 * register
1669 */
1670 if (host->vqmmc)
1671 ret = regulator_set_voltage(host->vqmmc,
cec2e216 1672 1700000, 1950000);
6231f3de
PR		 1673 else
1674 ret = 0;
1675
1676 if (!ret) {
f2119df6
AN		 1677 ctrl |= SDHCI_CTRL_VDD_180;
1678 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1679
1680 /* Wait for 5ms */
1681 usleep_range(5000, 5500);
1682
1683 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1684 if (ctrl & SDHCI_CTRL_VDD_180) {
6231f3de 1685 /* Provide SDCLK again and wait for 1ms */
f2119df6
AN		 1686 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1687 clk |= SDHCI_CLOCK_CARD_EN;
1688 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1689 usleep_range(1000, 1500);
1690
1691 /*
1692 * If DAT[3:0] level is 1111b, then the card
1693 * was successfully switched to 1.8V signaling.
1694 */
1695 present_state = sdhci_readl(host,
1696 SDHCI_PRESENT_STATE);
1697 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1698 SDHCI_DATA_LVL_MASK)
1699 return 0;
1700 }
1701 }
6231f3de 1702 }
f2119df6 1703
6231f3de
PR		 1704 /*
1705 * If we are here, that means the switch to 1.8V signaling
1706 * failed. We power cycle the card, and retry initialization
1707 * sequence by setting S18R to 0.
1708 */
1709 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1710 pwr &= ~SDHCI_POWER_ON;
1711 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1712 if (host->vmmc)
1713 regulator_disable(host->vmmc);
f2119df6 1714
6231f3de
PR		 1715 /* Wait for 1ms as per the spec */
1716 usleep_range(1000, 1500);
1717 pwr |= SDHCI_POWER_ON;
1718 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1719 if (host->vmmc)
1720 regulator_enable(host->vmmc);
f2119df6 1721
6231f3de
PR		 1722 pr_warning("%s: Switching to 1.8V signalling voltage failed, "
1723 "retrying with S18R set to 0\n", mmc_hostname(host->mmc));
1724
1725 return -EAGAIN;
1726}
1727
1728static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1729 struct mmc_ios *ios)
1730{
1731 u16 ctrl;
1732
1733 /*
1734 * Signal Voltage Switching is only applicable for Host Controllers
1735 * v3.00 and above.
1736 */
1737 if (host->version < SDHCI_SPEC_300)
1738 return 0;
1739
1740 /*
1741 * We first check whether the request is to set signalling voltage
1742 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1743 */
1744 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1745 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1746 return sdhci_do_3_3v_signal_voltage_switch(host, ctrl);
1747 else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1748 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180))
1749 return sdhci_do_1_8v_signal_voltage_switch(host, ctrl);
1750 else
f2119df6
AN		 1751 /* No signal voltage switch required */
1752 return 0;
1753}
1754
66fd8ad5
AH		 1755static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1756 struct mmc_ios *ios)
1757{
1758 struct sdhci_host *host = mmc_priv(mmc);
1759 int err;
1760
1761 if (host->version < SDHCI_SPEC_300)
1762 return 0;
1763 sdhci_runtime_pm_get(host);
1764 err = sdhci_do_start_signal_voltage_switch(host, ios);
1765 sdhci_runtime_pm_put(host);
1766 return err;
1767}
1768
069c9f14 1769static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1770{
1771 struct sdhci_host *host;
1772 u16 ctrl;
1773 u32 ier;
1774 int tuning_loop_counter = MAX_TUNING_LOOP;
1775 unsigned long timeout;
1776 int err = 0;
069c9f14 1777 bool requires_tuning_nonuhs = false;
b513ea25
AN		 1778
1779 host = mmc_priv(mmc);
1780
66fd8ad5 1781 sdhci_runtime_pm_get(host);
b513ea25
AN		 1782 disable_irq(host->irq);
1783 spin_lock(&host->lock);
1784
1785 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1786
1787 /*
069c9f14
G		 1788 * The Host Controller needs tuning only in case of SDR104 mode
1789 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1790 * Capabilities register.
069c9f14
G		 1791 * If the Host Controller supports the HS200 mode then the
1792 * tuning function has to be executed.
b513ea25 1793 */
069c9f14
G		 1794 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1795 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1796 host->flags & SDHCI_HS200_NEEDS_TUNING))
1797 requires_tuning_nonuhs = true;
1798
b513ea25 1799 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1800 requires_tuning_nonuhs)
b513ea25
AN		 1801 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1802 else {
1803 spin_unlock(&host->lock);
1804 enable_irq(host->irq);
66fd8ad5 1805 sdhci_runtime_pm_put(host);
b513ea25
AN		 1806 return 0;
1807 }
1808
1809 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1810
1811 /*
1812 * As per the Host Controller spec v3.00, tuning command
1813 * generates Buffer Read Ready interrupt, so enable that.
1814 *
1815 * Note: The spec clearly says that when tuning sequence
1816 * is being performed, the controller does not generate
1817 * interrupts other than Buffer Read Ready interrupt. But
1818 * to make sure we don't hit a controller bug, we _only_
1819 * enable Buffer Read Ready interrupt here.
1820 */
1821 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1822 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1823
1824 /*
1825 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1826 * of loops reaches 40 times or a timeout of 150ms occurs.
1827 */
1828 timeout = 150;
1829 do {
1830 struct mmc_command cmd = {0};
66fd8ad5 1831 struct mmc_request mrq = {NULL};
b513ea25
AN		 1832
1833 if (!tuning_loop_counter && !timeout)
1834 break;
1835
069c9f14 1836 cmd.opcode = opcode;
b513ea25
AN		 1837 cmd.arg = 0;
1838 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1839 cmd.retries = 0;
1840 cmd.data = NULL;
1841 cmd.error = 0;
1842
1843 mrq.cmd = &cmd;
1844 host->mrq = &mrq;
1845
1846 /*
1847 * In response to CMD19, the card sends 64 bytes of tuning
1848 * block to the Host Controller. So we set the block size
1849 * to 64 here.
1850 */
069c9f14
G		 1851 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1852 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1853 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1854 SDHCI_BLOCK_SIZE);
1855 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1856 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1857 SDHCI_BLOCK_SIZE);
1858 } else {
1859 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1860 SDHCI_BLOCK_SIZE);
1861 }
b513ea25
AN		 1862
1863 /*
1864 * The tuning block is sent by the card to the host controller.
1865 * So we set the TRNS_READ bit in the Transfer Mode register.
1866 * This also takes care of setting DMA Enable and Multi Block
1867 * Select in the same register to 0.
1868 */
1869 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1870
1871 sdhci_send_command(host, &cmd);
1872
1873 host->cmd = NULL;
1874 host->mrq = NULL;
1875
1876 spin_unlock(&host->lock);
1877 enable_irq(host->irq);
1878
1879 /* Wait for Buffer Read Ready interrupt */
1880 wait_event_interruptible_timeout(host->buf_ready_int,
1881 (host->tuning_done == 1),
1882 msecs_to_jiffies(50));
1883 disable_irq(host->irq);
1884 spin_lock(&host->lock);
1885
1886 if (!host->tuning_done) {
a3c76eb9 1887 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1888 "Buffer Read Ready interrupt during tuning "
1889 "procedure, falling back to fixed sampling "
1890 "clock\n");
1891 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1892 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1893 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1894 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1895
1896 err = -EIO;
1897 goto out;
1898 }
1899
1900 host->tuning_done = 0;
1901
1902 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1903 tuning_loop_counter--;
1904 timeout--;
1905 mdelay(1);
1906 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1907
1908 /*
1909 * The Host Driver has exhausted the maximum number of loops allowed,
1910 * so use fixed sampling frequency.
1911 */
1912 if (!tuning_loop_counter || !timeout) {
1913 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1914 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1915 } else {
1916 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1917 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1918 " failed, falling back to fixed sampling"
1919 " clock\n");
1920 err = -EIO;
1921 }
1922 }
1923
1924out:
cf2b5eea
AN		 1925 /*
1926 * If this is the very first time we are here, we start the retuning
1927 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1928 * flag won't be set, we check this condition before actually starting
1929 * the timer.
1930 */
1931 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1932 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 1933 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 1934 mod_timer(&host->tuning_timer, jiffies +
1935 host->tuning_count * HZ);
1936 /* Tuning mode 1 limits the maximum data length to 4MB */
1937 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1938 } else {
1939 host->flags &= ~SDHCI_NEEDS_RETUNING;
1940 /* Reload the new initial value for timer */
1941 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1942 mod_timer(&host->tuning_timer, jiffies +
1943 host->tuning_count * HZ);
1944 }
1945
1946 /*
1947 * In case tuning fails, host controllers which support re-tuning can
1948 * try tuning again at a later time, when the re-tuning timer expires.
1949 * So for these controllers, we return 0. Since there might be other
1950 * controllers who do not have this capability, we return error for
973905fe
AL		 1951 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
1952 * a retuning timer to do the retuning for the card.
cf2b5eea 1953 */
973905fe 1954 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 1955 err = 0;
1956
b513ea25
AN		 1957 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1958 spin_unlock(&host->lock);
1959 enable_irq(host->irq);
66fd8ad5 1960 sdhci_runtime_pm_put(host);
b513ea25
AN		 1961
1962 return err;
1963}
1964
66fd8ad5 1965static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 1966{
4d55c5a1
AN		 1967 u16 ctrl;
1968 unsigned long flags;
1969
4d55c5a1
AN		 1970 /* Host Controller v3.00 defines preset value registers */
1971 if (host->version < SDHCI_SPEC_300)
1972 return;
1973
1974 spin_lock_irqsave(&host->lock, flags);
1975
1976 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1977
1978 /*
1979 * We only enable or disable Preset Value if they are not already
1980 * enabled or disabled respectively. Otherwise, we bail out.
1981 */
1982 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1983 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1984 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1985 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 1986 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1987 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1988 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1989 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1
AN		 1990 }
1991
1992 spin_unlock_irqrestore(&host->lock, flags);
1993}
1994
66fd8ad5
AH		 1995static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1996{
1997 struct sdhci_host *host = mmc_priv(mmc);
1998
1999 sdhci_runtime_pm_get(host);
2000 sdhci_do_enable_preset_value(host, enable);
2001 sdhci_runtime_pm_put(host);
2002}
2003
71e69211 2004static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2005{
71e69211 2006 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2007 unsigned long flags;
2008
d129bceb
PO		 2009 spin_lock_irqsave(&host->lock, flags);
2010
66fd8ad5
AH		 2011 /* Check host->mrq first in case we are runtime suspended */
2012 if (host->mrq &&
2013 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
a3c76eb9 2014 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2015 mmc_hostname(host->mmc));
a3c76eb9 2016 pr_err("%s: Resetting controller.\n",
66fd8ad5 2017 mmc_hostname(host->mmc));
d129bceb 2018
66fd8ad5
AH		 2019 sdhci_reset(host, SDHCI_RESET_CMD);
2020 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 2021
66fd8ad5
AH		 2022 host->mrq->cmd->error = -ENOMEDIUM;
2023 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2024 }
2025
2026 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2027}
2028
2029static const struct mmc_host_ops sdhci_ops = {
2030 .request = sdhci_request,
2031 .set_ios = sdhci_set_ios,
2032 .get_ro = sdhci_get_ro,
2033 .hw_reset = sdhci_hw_reset,
2034 .enable_sdio_irq = sdhci_enable_sdio_irq,
2035 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2036 .execute_tuning = sdhci_execute_tuning,
2037 .enable_preset_value = sdhci_enable_preset_value,
2038 .card_event = sdhci_card_event,
2039};
2040
2041/*****************************************************************************\
2042 * *
2043 * Tasklets *
2044 * *
2045\*****************************************************************************/
2046
2047static void sdhci_tasklet_card(unsigned long param)
2048{
2049 struct sdhci_host *host = (struct sdhci_host*)param;
2050
2051 sdhci_card_event(host->mmc);
d129bceb 2052
04cf585d 2053 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 2054}
2055
2056static void sdhci_tasklet_finish(unsigned long param)
2057{
2058 struct sdhci_host *host;
2059 unsigned long flags;
2060 struct mmc_request *mrq;
2061
2062 host = (struct sdhci_host*)param;
2063
66fd8ad5
AH		 2064 spin_lock_irqsave(&host->lock, flags);
2065
0c9c99a7
CB		 2066 /*
2067 * If this tasklet gets rescheduled while running, it will
2068 * be run again afterwards but without any active request.
2069 */
66fd8ad5
AH		 2070 if (!host->mrq) {
2071 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2072 return;
66fd8ad5 2073 }
d129bceb
PO		 2074
2075 del_timer(&host->timer);
2076
2077 mrq = host->mrq;
2078
d129bceb
PO		 2079 /*
2080 * The controller needs a reset of internal state machines
2081 * upon error conditions.
2082 */
1e72859e 2083 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2084 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2085 (mrq->data && (mrq->data->error ||
2086 (mrq->data->stop && mrq->data->stop->error))) ||
2087 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2088
2089 /* Some controllers need this kick or reset won't work here */
8213af3b 2090 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2091 /* This is to force an update */
8213af3b 2092 sdhci_update_clock(host);
645289dc
PO		 2093
2094 /* Spec says we should do both at the same time, but Ricoh
2095 controllers do not like that. */
d129bceb
PO		 2096 sdhci_reset(host, SDHCI_RESET_CMD);
2097 sdhci_reset(host, SDHCI_RESET_DATA);
2098 }
2099
2100 host->mrq = NULL;
2101 host->cmd = NULL;
2102 host->data = NULL;
2103
f9134319 2104#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2105 sdhci_deactivate_led(host);
2f730fec 2106#endif
d129bceb 2107
5f25a66f 2108 mmiowb();
d129bceb
PO		 2109 spin_unlock_irqrestore(&host->lock, flags);
2110
2111 mmc_request_done(host->mmc, mrq);
66fd8ad5 2112 sdhci_runtime_pm_put(host);
d129bceb
PO		 2113}
2114
2115static void sdhci_timeout_timer(unsigned long data)
2116{
2117 struct sdhci_host *host;
2118 unsigned long flags;
2119
2120 host = (struct sdhci_host*)data;
2121
2122 spin_lock_irqsave(&host->lock, flags);
2123
2124 if (host->mrq) {
a3c76eb9 2125 pr_err("%s: Timeout waiting for hardware "
acf1da45 2126 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2127 sdhci_dumpregs(host);
2128
2129 if (host->data) {
17b0429d 2130 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2131 sdhci_finish_data(host);
2132 } else {
2133 if (host->cmd)
17b0429d 2134 host->cmd->error = -ETIMEDOUT;
d129bceb 2135 else
17b0429d 2136 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2137
2138 tasklet_schedule(&host->finish_tasklet);
2139 }
2140 }
2141
5f25a66f 2142 mmiowb();
d129bceb
PO		 2143 spin_unlock_irqrestore(&host->lock, flags);
2144}
2145
cf2b5eea
AN		 2146static void sdhci_tuning_timer(unsigned long data)
2147{
2148 struct sdhci_host *host;
2149 unsigned long flags;
2150
2151 host = (struct sdhci_host *)data;
2152
2153 spin_lock_irqsave(&host->lock, flags);
2154
2155 host->flags |= SDHCI_NEEDS_RETUNING;
2156
2157 spin_unlock_irqrestore(&host->lock, flags);
2158}
2159
d129bceb
PO		 2160/*****************************************************************************\
2161 * *
2162 * Interrupt handling *
2163 * *
2164\*****************************************************************************/
2165
2166static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2167{
2168 BUG_ON(intmask == 0);
2169
2170 if (!host->cmd) {
a3c76eb9 2171 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2172 "though no command operation was in progress.\n",
2173 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2174 sdhci_dumpregs(host);
2175 return;
2176 }
2177
43b58b36 2178 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2179 host->cmd->error = -ETIMEDOUT;
2180 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2181 SDHCI_INT_INDEX))
2182 host->cmd->error = -EILSEQ;
43b58b36 2183
e809517f 2184 if (host->cmd->error) {
d129bceb 2185 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2186 return;
2187 }
2188
2189 /*
2190 * The host can send and interrupt when the busy state has
2191 * ended, allowing us to wait without wasting CPU cycles.
2192 * Unfortunately this is overloaded on the "data complete"
2193 * interrupt, so we need to take some care when handling
2194 * it.
2195 *
2196 * Note: The 1.0 specification is a bit ambiguous about this
2197 * feature so there might be some problems with older
2198 * controllers.
2199 */
2200 if (host->cmd->flags & MMC_RSP_BUSY) {
2201 if (host->cmd->data)
2202 DBG("Cannot wait for busy signal when also "
2203 "doing a data transfer");
f945405c 2204 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2205 return;
f945405c
BD		 2206
2207 /* The controller does not support the end-of-busy IRQ,
2208 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2209 }
2210
2211 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2212 sdhci_finish_command(host);
d129bceb
PO		 2213}
2214
0957c333 2215#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2216static void sdhci_show_adma_error(struct sdhci_host *host)
2217{
2218 const char *name = mmc_hostname(host->mmc);
2219 u8 *desc = host->adma_desc;
2220 __le32 *dma;
2221 __le16 *len;
2222 u8 attr;
2223
2224 sdhci_dumpregs(host);
2225
2226 while (true) {
2227 dma = (__le32 *)(desc + 4);
2228 len = (__le16 *)(desc + 2);
2229 attr = *desc;
2230
2231 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2232 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2233
2234 desc += 8;
2235
2236 if (attr & 2)
2237 break;
2238 }
2239}
2240#else
2241static void sdhci_show_adma_error(struct sdhci_host *host) { }
2242#endif
2243
d129bceb
PO		 2244static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2245{
069c9f14 2246 u32 command;
d129bceb
PO		 2247 BUG_ON(intmask == 0);
2248
b513ea25
AN		 2249 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2250 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2251 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2252 if (command == MMC_SEND_TUNING_BLOCK ||
2253 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2254 host->tuning_done = 1;
2255 wake_up(&host->buf_ready_int);
2256 return;
2257 }
2258 }
2259
d129bceb
PO		 2260 if (!host->data) {
2261 /*
e809517f
PO		 2262 * The "data complete" interrupt is also used to
2263 * indicate that a busy state has ended. See comment
2264 * above in sdhci_cmd_irq().
d129bceb 2265 */
e809517f
PO		 2266 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2267 if (intmask & SDHCI_INT_DATA_END) {
2268 sdhci_finish_command(host);
2269 return;
2270 }
2271 }
d129bceb 2272
a3c76eb9 2273 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2274 "though no data operation was in progress.\n",
2275 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2276 sdhci_dumpregs(host);
2277
2278 return;
2279 }
2280
2281 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2282 host->data->error = -ETIMEDOUT;
22113efd
AL		 2283 else if (intmask & SDHCI_INT_DATA_END_BIT)
2284 host->data->error = -EILSEQ;
2285 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2286 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2287 != MMC_BUS_TEST_R)
17b0429d 2288 host->data->error = -EILSEQ;
6882a8c0 2289 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2290 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2291 sdhci_show_adma_error(host);
2134a922 2292 host->data->error = -EIO;
a4071fbb
HZ		 2293 if (host->ops->adma_workaround)
2294 host->ops->adma_workaround(host, intmask);
6882a8c0 2295 }
d129bceb 2296
17b0429d 2297 if (host->data->error)
d129bceb
PO		 2298 sdhci_finish_data(host);
2299 else {
a406f5a3 2300 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2301 sdhci_transfer_pio(host);
2302
6ba736a1
PO		 2303 /*
2304 * We currently don't do anything fancy with DMA
2305 * boundaries, but as we can't disable the feature
2306 * we need to at least restart the transfer.
f6a03cbf
MV		 2307 *
2308 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2309 * should return a valid address to continue from, but as
2310 * some controllers are faulty, don't trust them.
6ba736a1 2311 */
f6a03cbf
MV		 2312 if (intmask & SDHCI_INT_DMA_END) {
2313 u32 dmastart, dmanow;
2314 dmastart = sg_dma_address(host->data->sg);
2315 dmanow = dmastart + host->data->bytes_xfered;
2316 /*
2317 * Force update to the next DMA block boundary.
2318 */
2319 dmanow = (dmanow &
2320 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2321 SDHCI_DEFAULT_BOUNDARY_SIZE;
2322 host->data->bytes_xfered = dmanow - dmastart;
2323 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2324 " next 0x%08x\n",
2325 mmc_hostname(host->mmc), dmastart,
2326 host->data->bytes_xfered, dmanow);
2327 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2328 }
6ba736a1 2329
e538fbe8
PO		 2330 if (intmask & SDHCI_INT_DATA_END) {
2331 if (host->cmd) {
2332 /*
2333 * Data managed to finish before the
2334 * command completed. Make sure we do
2335 * things in the proper order.
2336 */
2337 host->data_early = 1;
2338 } else {
2339 sdhci_finish_data(host);
2340 }
2341 }
d129bceb
PO		 2342 }
2343}
2344
7d12e780 2345static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2346{
2347 irqreturn_t result;
66fd8ad5 2348 struct sdhci_host *host = dev_id;
6379b237
AS		 2349 u32 intmask, unexpected = 0;
2350 int cardint = 0, max_loops = 16;
d129bceb
PO		 2351
2352 spin_lock(&host->lock);
2353
66fd8ad5
AH		 2354 if (host->runtime_suspended) {
2355 spin_unlock(&host->lock);
a3c76eb9 2356 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2357 mmc_hostname(host->mmc));
2358 return IRQ_HANDLED;
2359 }
2360
4e4141a5 2361 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2362
62df67a5 2363 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2364 result = IRQ_NONE;
2365 goto out;
2366 }
2367
6379b237 2368again:
b69c9058
PO		 2369 DBG("*** %s got interrupt: 0x%08x\n",
2370 mmc_hostname(host->mmc), intmask);
d129bceb 2371
3192a28f 2372 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2373 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2374 SDHCI_CARD_PRESENT;
2375
2376 /*
2377 * There is a observation on i.mx esdhc. INSERT bit will be
2378 * immediately set again when it gets cleared, if a card is
2379 * inserted. We have to mask the irq to prevent interrupt
2380 * storm which will freeze the system. And the REMOVE gets
2381 * the same situation.
2382 *
2383 * More testing are needed here to ensure it works for other
2384 * platforms though.
2385 */
2386 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2387 SDHCI_INT_CARD_REMOVE);
2388 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2389 SDHCI_INT_CARD_INSERT);
2390
4e4141a5 2391 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2392 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2393 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2394 tasklet_schedule(&host->card_tasklet);
3192a28f 2395 }
d129bceb 2396
3192a28f 2397 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2398 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2399 SDHCI_INT_STATUS);
3192a28f 2400 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2401 }
2402
2403 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2404 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2405 SDHCI_INT_STATUS);
3192a28f 2406 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2407 }
2408
2409 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2410
964f9ce2
PO		 2411 intmask &= ~SDHCI_INT_ERROR;
2412
d129bceb 2413 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2414 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2415 mmc_hostname(host->mmc));
4e4141a5 2416 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2417 }
2418
9d26a5d3 2419 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2420
f75979b7
PO		 2421 if (intmask & SDHCI_INT_CARD_INT)
2422 cardint = 1;
2423
2424 intmask &= ~SDHCI_INT_CARD_INT;
2425
3192a28f 2426 if (intmask) {
6379b237 2427 unexpected |= intmask;
4e4141a5 2428 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2429 }
d129bceb
PO		 2430
2431 result = IRQ_HANDLED;
2432
6379b237
AS		 2433 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2434 if (intmask && --max_loops)
2435 goto again;
d129bceb
PO		 2436out:
2437 spin_unlock(&host->lock);
2438
6379b237
AS		 2439 if (unexpected) {
2440 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2441 mmc_hostname(host->mmc), unexpected);
2442 sdhci_dumpregs(host);
2443 }
f75979b7
PO		 2444 /*
2445 * We have to delay this as it calls back into the driver.
2446 */
2447 if (cardint)
2448 mmc_signal_sdio_irq(host->mmc);
2449
d129bceb
PO		 2450 return result;
2451}
2452
2453/*****************************************************************************\
2454 * *
2455 * Suspend/resume *
2456 * *
2457\*****************************************************************************/
2458
2459#ifdef CONFIG_PM
ad080d79
KL		 2460void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2461{
2462 u8 val;
2463 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2464 | SDHCI_WAKE_ON_INT;
2465
2466 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2467 val |= mask ;
2468 /* Avoid fake wake up */
2469 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2470 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2471 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2472}
2473EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2474
2475void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2476{
2477 u8 val;
2478 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2479 | SDHCI_WAKE_ON_INT;
2480
2481 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2482 val &= ~mask;
2483 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2484}
2485EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2486
29495aa0 2487int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2488{
b8c86fc5 2489 int ret;
a715dfc7 2490
a1b13b4e
CB		 2491 if (host->ops->platform_suspend)
2492 host->ops->platform_suspend(host);
2493
7260cf5e
AV		 2494 sdhci_disable_card_detection(host);
2495
cf2b5eea 2496 /* Disable tuning since we are suspending */
973905fe 2497 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2498 del_timer_sync(&host->tuning_timer);
cf2b5eea 2499 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2500 }
2501
1a13f8fa 2502 ret = mmc_suspend_host(host->mmc);
38a60ea2 2503 if (ret) {
973905fe 2504 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
38a60ea2
AL		 2505 host->flags |= SDHCI_NEEDS_RETUNING;
2506 mod_timer(&host->tuning_timer, jiffies +
2507 host->tuning_count * HZ);
2508 }
2509
2510 sdhci_enable_card_detection(host);
2511
b8c86fc5 2512 return ret;
38a60ea2 2513 }
a715dfc7 2514
ad080d79
KL		 2515 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2516 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2517 free_irq(host->irq, host);
2518 } else {
2519 sdhci_enable_irq_wakeups(host);
2520 enable_irq_wake(host->irq);
2521 }
9bea3c85 2522 return ret;
d129bceb
PO		 2523}
2524
b8c86fc5 2525EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2526
b8c86fc5
PO		 2527int sdhci_resume_host(struct sdhci_host *host)
2528{
2529 int ret;
d129bceb 2530
a13abc7b 2531 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2532 if (host->ops->enable_dma)
2533 host->ops->enable_dma(host);
2534 }
d129bceb 2535
ad080d79
KL		 2536 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2537 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2538 mmc_hostname(host->mmc), host);
2539 if (ret)
2540 return ret;
2541 } else {
2542 sdhci_disable_irq_wakeups(host);
2543 disable_irq_wake(host->irq);
2544 }
d129bceb 2545
6308d290
AH		 2546 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2547 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2548 /* Card keeps power but host controller does not */
2549 sdhci_init(host, 0);
2550 host->pwr = 0;
2551 host->clock = 0;
2552 sdhci_do_set_ios(host, &host->mmc->ios);
2553 } else {
2554 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2555 mmiowb();
2556 }
b8c86fc5
PO		 2557
2558 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2559 sdhci_enable_card_detection(host);
2560
a1b13b4e
CB		 2561 if (host->ops->platform_resume)
2562 host->ops->platform_resume(host);
2563
cf2b5eea 2564 /* Set the re-tuning expiration flag */
973905fe 2565 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2566 host->flags |= SDHCI_NEEDS_RETUNING;
2567
2f4cbb3d 2568 return ret;
d129bceb
PO		 2569}
2570
b8c86fc5 2571EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2572#endif /* CONFIG_PM */
2573
66fd8ad5
AH		 2574#ifdef CONFIG_PM_RUNTIME
2575
2576static int sdhci_runtime_pm_get(struct sdhci_host *host)
2577{
2578 return pm_runtime_get_sync(host->mmc->parent);
2579}
2580
2581static int sdhci_runtime_pm_put(struct sdhci_host *host)
2582{
2583 pm_runtime_mark_last_busy(host->mmc->parent);
2584 return pm_runtime_put_autosuspend(host->mmc->parent);
2585}
2586
2587int sdhci_runtime_suspend_host(struct sdhci_host *host)
2588{
2589 unsigned long flags;
2590 int ret = 0;
2591
2592 /* Disable tuning since we are suspending */
973905fe 2593 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2594 del_timer_sync(&host->tuning_timer);
2595 host->flags &= ~SDHCI_NEEDS_RETUNING;
2596 }
2597
2598 spin_lock_irqsave(&host->lock, flags);
2599 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2600 spin_unlock_irqrestore(&host->lock, flags);
2601
2602 synchronize_irq(host->irq);
2603
2604 spin_lock_irqsave(&host->lock, flags);
2605 host->runtime_suspended = true;
2606 spin_unlock_irqrestore(&host->lock, flags);
2607
2608 return ret;
2609}
2610EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2611
2612int sdhci_runtime_resume_host(struct sdhci_host *host)
2613{
2614 unsigned long flags;
2615 int ret = 0, host_flags = host->flags;
2616
2617 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2618 if (host->ops->enable_dma)
2619 host->ops->enable_dma(host);
2620 }
2621
2622 sdhci_init(host, 0);
2623
2624 /* Force clock and power re-program */
2625 host->pwr = 0;
2626 host->clock = 0;
2627 sdhci_do_set_ios(host, &host->mmc->ios);
2628
2629 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2630 if (host_flags & SDHCI_PV_ENABLED)
2631 sdhci_do_enable_preset_value(host, true);
2632
2633 /* Set the re-tuning expiration flag */
973905fe 2634 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2635 host->flags |= SDHCI_NEEDS_RETUNING;
2636
2637 spin_lock_irqsave(&host->lock, flags);
2638
2639 host->runtime_suspended = false;
2640
2641 /* Enable SDIO IRQ */
2642 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2643 sdhci_enable_sdio_irq_nolock(host, true);
2644
2645 /* Enable Card Detection */
2646 sdhci_enable_card_detection(host);
2647
2648 spin_unlock_irqrestore(&host->lock, flags);
2649
2650 return ret;
2651}
2652EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2653
2654#endif
2655
d129bceb
PO		 2656/*****************************************************************************\
2657 * *
b8c86fc5 2658 * Device allocation/registration *
d129bceb
PO		 2659 * *
2660\*****************************************************************************/
2661
b8c86fc5
PO		 2662struct sdhci_host *sdhci_alloc_host(struct device *dev,
2663 size_t priv_size)
d129bceb 2664{
d129bceb
PO		 2665 struct mmc_host *mmc;
2666 struct sdhci_host *host;
2667
b8c86fc5 2668 WARN_ON(dev == NULL);
d129bceb 2669
b8c86fc5 2670 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2671 if (!mmc)
b8c86fc5 2672 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2673
2674 host = mmc_priv(mmc);
2675 host->mmc = mmc;
2676
b8c86fc5
PO		 2677 return host;
2678}
8a4da143 2679
b8c86fc5 2680EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2681
b8c86fc5
PO		 2682int sdhci_add_host(struct sdhci_host *host)
2683{
2684 struct mmc_host *mmc;
bd6a8c30 2685 u32 caps[2] = {0, 0};
f2119df6
AN		 2686 u32 max_current_caps;
2687 unsigned int ocr_avail;
b8c86fc5 2688 int ret;
d129bceb 2689
b8c86fc5
PO		 2690 WARN_ON(host == NULL);
2691 if (host == NULL)
2692 return -EINVAL;
d129bceb 2693
b8c86fc5 2694 mmc = host->mmc;
d129bceb 2695
b8c86fc5
PO		 2696 if (debug_quirks)
2697 host->quirks = debug_quirks;
66fd8ad5
AH		 2698 if (debug_quirks2)
2699 host->quirks2 = debug_quirks2;
d129bceb 2700
d96649ed
PO		 2701 sdhci_reset(host, SDHCI_RESET_ALL);
2702
4e4141a5 2703 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2704 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2705 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2706 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2707 pr_err("%s: Unknown controller version (%d). "
b69c9058 2708 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2709 host->version);
4a965505
PO		 2710 }
2711
f2119df6 2712 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2713 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2714
bd6a8c30
PR		 2715 if (host->version >= SDHCI_SPEC_300)
2716 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2717 host->caps1 :
2718 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2719
b8c86fc5 2720 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2721 host->flags |= SDHCI_USE_SDMA;
f2119df6 2722 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2723 DBG("Controller doesn't have SDMA capability\n");
67435274 2724 else
a13abc7b 2725 host->flags |= SDHCI_USE_SDMA;
d129bceb 2726
b8c86fc5 2727 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2728 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2729 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2730 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2731 }
2732
f2119df6
AN		 2733 if ((host->version >= SDHCI_SPEC_200) &&
2734 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2735 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2736
2737 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2738 (host->flags & SDHCI_USE_ADMA)) {
2739 DBG("Disabling ADMA as it is marked broken\n");
2740 host->flags &= ~SDHCI_USE_ADMA;
2741 }
2742
a13abc7b 2743 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2744 if (host->ops->enable_dma) {
2745 if (host->ops->enable_dma(host)) {
a3c76eb9 2746 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2747 "available. Falling back to PIO.\n",
2748 mmc_hostname(mmc));
a13abc7b
RR		 2749 host->flags &=
2750 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2751 }
d129bceb
PO		 2752 }
2753 }
2754
2134a922
PO		 2755 if (host->flags & SDHCI_USE_ADMA) {
2756 /*
2757 * We need to allocate descriptors for all sg entries
2758 * (128) and potentially one alignment transfer for
2759 * each of those entries.
2760 */
2761 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2762 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2763 if (!host->adma_desc || !host->align_buffer) {
2764 kfree(host->adma_desc);
2765 kfree(host->align_buffer);
a3c76eb9 2766 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2767 "buffers. Falling back to standard DMA.\n",
2768 mmc_hostname(mmc));
2769 host->flags &= ~SDHCI_USE_ADMA;
2770 }
2771 }
2772
7659150c
PO		 2773 /*
2774 * If we use DMA, then it's up to the caller to set the DMA
2775 * mask, but PIO does not need the hw shim so we set a new
2776 * mask here in that case.
2777 */
a13abc7b 2778 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2779 host->dma_mask = DMA_BIT_MASK(64);
2780 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2781 }
d129bceb 2782
c4687d5f 2783 if (host->version >= SDHCI_SPEC_300)
f2119df6 2784 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2785 >> SDHCI_CLOCK_BASE_SHIFT;
2786 else
f2119df6 2787 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2788 >> SDHCI_CLOCK_BASE_SHIFT;
2789
4240ff0a 2790 host->max_clk *= 1000000;
f27f47ef
AV		 2791 if (host->max_clk == 0 || host->quirks &
2792 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2793 if (!host->ops->get_max_clock) {
a3c76eb9 2794 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2795 "frequency.\n", mmc_hostname(mmc));
2796 return -ENODEV;
2797 }
2798 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2799 }
d129bceb 2800
c3ed3877
AN		 2801 /*
2802 * In case of Host Controller v3.00, find out whether clock
2803 * multiplier is supported.
2804 */
2805 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2806 SDHCI_CLOCK_MUL_SHIFT;
2807
2808 /*
2809 * In case the value in Clock Multiplier is 0, then programmable
2810 * clock mode is not supported, otherwise the actual clock
2811 * multiplier is one more than the value of Clock Multiplier
2812 * in the Capabilities Register.
2813 */
2814 if (host->clk_mul)
2815 host->clk_mul += 1;
2816
d129bceb
PO		 2817 /*
2818 * Set host parameters.
2819 */
2820 mmc->ops = &sdhci_ops;
c3ed3877 2821 mmc->f_max = host->max_clk;
ce5f036b 2822 if (host->ops->get_min_clock)
a9e58f25 2823 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2824 else if (host->version >= SDHCI_SPEC_300) {
2825 if (host->clk_mul) {
2826 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2827 mmc->f_max = host->max_clk * host->clk_mul;
2828 } else
2829 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2830 } else
0397526d 2831 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2832
272308ca
AS		 2833 host->timeout_clk =
2834 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2835 if (host->timeout_clk == 0) {
2836 if (host->ops->get_timeout_clock) {
2837 host->timeout_clk = host->ops->get_timeout_clock(host);
2838 } else if (!(host->quirks &
2839 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2840 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2841 "frequency.\n", mmc_hostname(mmc));
2842 return -ENODEV;
2843 }
2844 }
2845 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2846 host->timeout_clk *= 1000;
2847
2848 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2849 host->timeout_clk = mmc->f_max / 1000;
272308ca 2850
65be3fef 2851 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2852
e89d456f
AW		 2853 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2854
2855 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2856 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2857
8edf6371 2858 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2859 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2860 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2861 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2862 host->flags |= SDHCI_AUTO_CMD23;
2863 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2864 } else {
2865 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2866 }
2867
15ec4461
PR		 2868 /*
2869 * A controller may support 8-bit width, but the board itself
2870 * might not have the pins brought out. Boards that support
2871 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2872 * their platform code before calling sdhci_add_host(), and we
2873 * won't assume 8-bit width for hosts without that CAP.
2874 */
5fe23c7f 2875 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2876 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2877
63ef5d8c
JH		 2878 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2879 mmc->caps &= ~MMC_CAP_CMD23;
2880
f2119df6 2881 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2882 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2883
176d1ed4 2884 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2885 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2886 mmc->caps |= MMC_CAP_NEEDS_POLL;
2887
6231f3de
PR		 2888 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2889 host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2890 if (IS_ERR_OR_NULL(host->vqmmc)) {
2891 if (PTR_ERR(host->vqmmc) < 0) {
2892 pr_info("%s: no vqmmc regulator found\n",
2893 mmc_hostname(mmc));
2894 host->vqmmc = NULL;
2895 }
8363c374 2896 } else {
6231f3de 2897 regulator_enable(host->vqmmc);
cec2e216
KL		 2898 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2899 1950000))
8363c374
KL		 2900 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2901 SDHCI_SUPPORT_SDR50 |
2902 SDHCI_SUPPORT_DDR50);
2903 }
6231f3de 2904
6a66180a
DD		 2905 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2906 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2907 SDHCI_SUPPORT_DDR50);
2908
4188bba0
AC		 2909 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2910 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2911 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 2912 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2913
2914 /* SDR104 supports also implies SDR50 support */
2915 if (caps[1] & SDHCI_SUPPORT_SDR104)
2916 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2917 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2918 mmc->caps |= MMC_CAP_UHS_SDR50;
2919
2920 if (caps[1] & SDHCI_SUPPORT_DDR50)
2921 mmc->caps |= MMC_CAP_UHS_DDR50;
2922
069c9f14 2923 /* Does the host need tuning for SDR50? */
b513ea25
AN		 2924 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2925 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2926
069c9f14
G		 2927 /* Does the host need tuning for HS200? */
2928 if (mmc->caps2 & MMC_CAP2_HS200)
2929 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2930
d6d50a15
AN		 2931 /* Driver Type(s) (A, C, D) supported by the host */
2932 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2933 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2934 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2935 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2936 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2937 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2938
cf2b5eea
AN		 2939 /* Initial value for re-tuning timer count */
2940 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2941 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2942
2943 /*
2944 * In case Re-tuning Timer is not disabled, the actual value of
2945 * re-tuning timer will be 2 ^ (n - 1).
2946 */
2947 if (host->tuning_count)
2948 host->tuning_count = 1 << (host->tuning_count - 1);
2949
2950 /* Re-tuning mode supported by the Host Controller */
2951 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2952 SDHCI_RETUNING_MODE_SHIFT;
2953
8f230f45 2954 ocr_avail = 0;
bad37e1a
PR		 2955
2956 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
657d5982
KL		 2957 if (IS_ERR_OR_NULL(host->vmmc)) {
2958 if (PTR_ERR(host->vmmc) < 0) {
2959 pr_info("%s: no vmmc regulator found\n",
2960 mmc_hostname(mmc));
2961 host->vmmc = NULL;
2962 }
8363c374 2963 }
bad37e1a 2964
68737043
PR		 2965#ifdef CONFIG_REGULATOR
2966 if (host->vmmc) {
cec2e216
KL		 2967 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
2968 3600000);
68737043
PR		 2969 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
2970 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 2971 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
2972 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 2973 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
2974 1950000);
68737043
PR		 2975 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
2976 caps[0] &= ~SDHCI_CAN_VDD_180;
2977 }
2978#endif /* CONFIG_REGULATOR */
2979
f2119df6
AN		 2980 /*
2981 * According to SD Host Controller spec v3.00, if the Host System
2982 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2983 * the value is meaningful only if Voltage Support in the Capabilities
2984 * register is set. The actual current value is 4 times the register
2985 * value.
2986 */
2987 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 2988 if (!max_current_caps && host->vmmc) {
2989 u32 curr = regulator_get_current_limit(host->vmmc);
2990 if (curr > 0) {
2991
2992 /* convert to SDHCI_MAX_CURRENT format */
2993 curr = curr/1000; /* convert to mA */
2994 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
2995
2996 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
2997 max_current_caps =
2998 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
2999 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3000 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3001 }
3002 }
f2119df6
AN		 3003
3004 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3005 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3006
55c4665e 3007 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3008 SDHCI_MAX_CURRENT_330_MASK) >>
3009 SDHCI_MAX_CURRENT_330_SHIFT) *
3010 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3011 }
3012 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3013 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3014
55c4665e 3015 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3016 SDHCI_MAX_CURRENT_300_MASK) >>
3017 SDHCI_MAX_CURRENT_300_SHIFT) *
3018 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3019 }
3020 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3021 ocr_avail |= MMC_VDD_165_195;
3022
55c4665e 3023 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3024 SDHCI_MAX_CURRENT_180_MASK) >>
3025 SDHCI_MAX_CURRENT_180_SHIFT) *
3026 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3027 }
3028
8f230f45
TI		 3029 mmc->ocr_avail = ocr_avail;
3030 mmc->ocr_avail_sdio = ocr_avail;
3031 if (host->ocr_avail_sdio)
3032 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3033 mmc->ocr_avail_sd = ocr_avail;
3034 if (host->ocr_avail_sd)
3035 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3036 else /* normal SD controllers don't support 1.8V */
3037 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3038 mmc->ocr_avail_mmc = ocr_avail;
3039 if (host->ocr_avail_mmc)
3040 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3041
3042 if (mmc->ocr_avail == 0) {
a3c76eb9 3043 pr_err("%s: Hardware doesn't report any "
b69c9058 3044 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3045 return -ENODEV;
146ad66e
PO		 3046 }
3047
d129bceb
PO		 3048 spin_lock_init(&host->lock);
3049
3050 /*
2134a922
PO		 3051 * Maximum number of segments. Depends on if the hardware
3052 * can do scatter/gather or not.
d129bceb 3053 */
2134a922 3054 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3055 mmc->max_segs = 128;
a13abc7b 3056 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3057 mmc->max_segs = 1;
2134a922 3058 else /* PIO */
a36274e0 3059 mmc->max_segs = 128;
d129bceb
PO		 3060
3061 /*
bab76961 3062 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3063 * size (512KiB).
d129bceb 3064 */
55db890a 3065 mmc->max_req_size = 524288;
d129bceb
PO		 3066
3067 /*
3068 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3069 * of bytes. When doing hardware scatter/gather, each entry cannot
3070 * be larger than 64 KiB though.
d129bceb 3071 */
30652aa3
OJ		 3072 if (host->flags & SDHCI_USE_ADMA) {
3073 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3074 mmc->max_seg_size = 65535;
3075 else
3076 mmc->max_seg_size = 65536;
3077 } else {
2134a922 3078 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3079 }
d129bceb 3080
fe4a3c7a
PO		 3081 /*
3082 * Maximum block size. This varies from controller to controller and
3083 * is specified in the capabilities register.
3084 */
0633f654
AV		 3085 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3086 mmc->max_blk_size = 2;
3087 } else {
f2119df6 3088 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3089 SDHCI_MAX_BLOCK_SHIFT;
3090 if (mmc->max_blk_size >= 3) {
a3c76eb9 3091 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3092 "assuming 512 bytes\n", mmc_hostname(mmc));
3093 mmc->max_blk_size = 0;
3094 }
3095 }
3096
3097 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3098
55db890a
PO		 3099 /*
3100 * Maximum block count.
3101 */
1388eefd 3102 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3103
d129bceb
PO		 3104 /*
3105 * Init tasklets.
3106 */
3107 tasklet_init(&host->card_tasklet,
3108 sdhci_tasklet_card, (unsigned long)host);
3109 tasklet_init(&host->finish_tasklet,
3110 sdhci_tasklet_finish, (unsigned long)host);
3111
e4cad1b5 3112 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3113
cf2b5eea 3114 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3115 init_waitqueue_head(&host->buf_ready_int);
3116
cf2b5eea
AN		 3117 /* Initialize re-tuning timer */
3118 init_timer(&host->tuning_timer);
3119 host->tuning_timer.data = (unsigned long)host;
3120 host->tuning_timer.function = sdhci_tuning_timer;
3121 }
3122
dace1453 3123 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 3124 mmc_hostname(mmc), host);
0fc81ee3
MB		 3125 if (ret) {
3126 pr_err("%s: Failed to request IRQ %d: %d\n",
3127 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3128 goto untasklet;
0fc81ee3 3129 }
d129bceb 3130
2f4cbb3d 3131 sdhci_init(host, 0);
d129bceb
PO		 3132
3133#ifdef CONFIG_MMC_DEBUG
3134 sdhci_dumpregs(host);
3135#endif
3136
f9134319 3137#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3138 snprintf(host->led_name, sizeof(host->led_name),
3139 "%s::", mmc_hostname(mmc));
3140 host->led.name = host->led_name;
2f730fec
PO		 3141 host->led.brightness = LED_OFF;
3142 host->led.default_trigger = mmc_hostname(mmc);
3143 host->led.brightness_set = sdhci_led_control;
3144
b8c86fc5 3145 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3146 if (ret) {
3147 pr_err("%s: Failed to register LED device: %d\n",
3148 mmc_hostname(mmc), ret);
2f730fec 3149 goto reset;
0fc81ee3 3150 }
2f730fec
PO		 3151#endif
3152
5f25a66f
PO		 3153 mmiowb();
3154
d129bceb
PO		 3155 mmc_add_host(mmc);
3156
a3c76eb9 3157 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3158 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3159 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3160 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3161
7260cf5e
AV		 3162 sdhci_enable_card_detection(host);
3163
d129bceb
PO		 3164 return 0;
3165
f9134319 3166#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3167reset:
3168 sdhci_reset(host, SDHCI_RESET_ALL);
b0a8dece 3169 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2f730fec
PO		 3170 free_irq(host->irq, host);
3171#endif
8ef1a143 3172untasklet:
d129bceb
PO		 3173 tasklet_kill(&host->card_tasklet);
3174 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3175
3176 return ret;
3177}
3178
b8c86fc5 3179EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3180
1e72859e 3181void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3182{
1e72859e
PO		 3183 unsigned long flags;
3184
3185 if (dead) {
3186 spin_lock_irqsave(&host->lock, flags);
3187
3188 host->flags |= SDHCI_DEVICE_DEAD;
3189
3190 if (host->mrq) {
a3c76eb9 3191 pr_err("%s: Controller removed during "
1e72859e
PO		 3192 " transfer!\n", mmc_hostname(host->mmc));
3193
3194 host->mrq->cmd->error = -ENOMEDIUM;
3195 tasklet_schedule(&host->finish_tasklet);
3196 }
3197
3198 spin_unlock_irqrestore(&host->lock, flags);
3199 }
3200
7260cf5e
AV		 3201 sdhci_disable_card_detection(host);
3202
b8c86fc5 3203 mmc_remove_host(host->mmc);
d129bceb 3204
f9134319 3205#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3206 led_classdev_unregister(&host->led);
3207#endif
3208
1e72859e
PO		 3209 if (!dead)
3210 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 3211
b0a8dece 3212 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
d129bceb
PO		 3213 free_irq(host->irq, host);
3214
3215 del_timer_sync(&host->timer);
3216
3217 tasklet_kill(&host->card_tasklet);
3218 tasklet_kill(&host->finish_tasklet);
2134a922 3219
77dcb3f4
PR		 3220 if (host->vmmc) {
3221 regulator_disable(host->vmmc);
9bea3c85 3222 regulator_put(host->vmmc);
77dcb3f4 3223 }
9bea3c85 3224
6231f3de
PR		 3225 if (host->vqmmc) {
3226 regulator_disable(host->vqmmc);
3227 regulator_put(host->vqmmc);
3228 }
3229
2134a922
PO		 3230 kfree(host->adma_desc);
3231 kfree(host->align_buffer);
3232
3233 host->adma_desc = NULL;
3234 host->align_buffer = NULL;
d129bceb
PO		 3235}
3236
b8c86fc5 3237EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3238
b8c86fc5 3239void sdhci_free_host(struct sdhci_host *host)
d129bceb 3240{
b8c86fc5 3241 mmc_free_host(host->mmc);
d129bceb
PO		 3242}
3243
b8c86fc5 3244EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3245
3246/*****************************************************************************\
3247 * *
3248 * Driver init/exit *
3249 * *
3250\*****************************************************************************/
3251
3252static int __init sdhci_drv_init(void)
3253{
a3c76eb9 3254 pr_info(DRIVER_NAME
52fbf9c9 3255 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3256 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3257
b8c86fc5 3258 return 0;
d129bceb
PO		 3259}
3260
3261static void __exit sdhci_drv_exit(void)
3262{
d129bceb
PO		 3263}
3264
3265module_init(sdhci_drv_init);
3266module_exit(sdhci_drv_exit);
3267
df673b22 3268module_param(debug_quirks, uint, 0444);
66fd8ad5 3269module_param(debug_quirks2, uint, 0444);
67435274 3270
32710e8f 3271MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3272MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3273MODULE_LICENSE("GPL");
67435274 3274
df673b22 3275MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3276MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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