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mmc: sdhci: set_uhs_signaling() need not return a value
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
d1e49f77
RK		 47#define ADMA_SIZE ((128 * 2 + 1) * 4)
48
df673b22 49static unsigned int debug_quirks = 0;
66fd8ad5 50static unsigned int debug_quirks2;
67435274 51
d129bceb
PO		 52static void sdhci_finish_data(struct sdhci_host *);
53
d129bceb 54static void sdhci_finish_command(struct sdhci_host *);
069c9f14 55static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 56static void sdhci_tuning_timer(unsigned long data);
52983382 57static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 58
66fd8ad5
AH		 59#ifdef CONFIG_PM_RUNTIME
60static int sdhci_runtime_pm_get(struct sdhci_host *host);
61static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 62static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
63static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 64#else
65static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
66{
67 return 0;
68}
69static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
70{
71 return 0;
72}
f0710a55
AH		 73static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
74{
75}
76static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
77{
78}
66fd8ad5
AH		 79#endif
80
d129bceb
PO		 81static void sdhci_dumpregs(struct sdhci_host *host)
82{
a3c76eb9 83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 84 mmc_hostname(host->mmc));
d129bceb 85
a3c76eb9 86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readl(host, SDHCI_DMA_ADDRESS),
88 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readw(host, SDHCI_BLOCK_SIZE),
91 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readl(host, SDHCI_ARGUMENT),
94 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readl(host, SDHCI_PRESENT_STATE),
97 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readb(host, SDHCI_POWER_CONTROL),
100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
103 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
106 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 108 sdhci_readl(host, SDHCI_INT_ENABLE),
109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 111 sdhci_readw(host, SDHCI_ACMD12_ERR),
112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 114 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 115 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 117 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 118 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 120 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 121
be3f4ae0 122 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126
a3c76eb9 127 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 128}
129
130/*****************************************************************************\
131 * *
132 * Low level functions *
133 * *
134\*****************************************************************************/
135
7260cf5e
AV		 136static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
137{
5b4f1f6c 138 u32 present;
7260cf5e 139
c79396c1 140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 141 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 142 return;
143
5b4f1f6c
RK		 144 if (enable) {
145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
146 SDHCI_CARD_PRESENT;
d25928d1 147
5b4f1f6c
RK		 148 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
149 SDHCI_INT_CARD_INSERT;
150 } else {
151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
152 }
b537f94c
RK		 153
154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 156}
157
158static void sdhci_enable_card_detection(struct sdhci_host *host)
159{
160 sdhci_set_card_detection(host, true);
161}
162
163static void sdhci_disable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, false);
166}
167
03231f9b 168void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 169{
e16514d8 170 unsigned long timeout;
393c1a34 171
4e4141a5 172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 173
f0710a55 174 if (mask & SDHCI_RESET_ALL) {
d129bceb 175 host->clock = 0;
f0710a55
AH		 176 /* Reset-all turns off SD Bus Power */
177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
178 sdhci_runtime_pm_bus_off(host);
179 }
d129bceb 180
e16514d8
PO		 181 /* Wait max 100 ms */
182 timeout = 100;
183
184 /* hw clears the bit when it's done */
4e4141a5 185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 186 if (timeout == 0) {
a3c76eb9 187 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 188 mmc_hostname(host->mmc), (int)mask);
189 sdhci_dumpregs(host);
190 return;
191 }
192 timeout--;
193 mdelay(1);
d129bceb 194 }
03231f9b
RK		 195}
196EXPORT_SYMBOL_GPL(sdhci_reset);
197
198static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
199{
200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
202 SDHCI_CARD_PRESENT))
203 return;
204 }
063a9dbb 205
03231f9b 206 host->ops->reset(host, mask);
393c1a34 207
3abc1e80
SX		 208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
209 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
210 host->ops->enable_dma(host);
211 }
d129bceb
PO		 212}
213
2f4cbb3d
NP		 214static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
215
216static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 217{
2f4cbb3d 218 if (soft)
03231f9b 219 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 220 else
03231f9b 221 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 222
b537f94c
RK		 223 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
224 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
225 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
226 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
227 SDHCI_INT_RESPONSE;
228
229 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
230 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 231
232 if (soft) {
233 /* force clock reconfiguration */
234 host->clock = 0;
235 sdhci_set_ios(host->mmc, &host->mmc->ios);
236 }
7260cf5e 237}
d129bceb 238
7260cf5e
AV		 239static void sdhci_reinit(struct sdhci_host *host)
240{
2f4cbb3d 241 sdhci_init(host, 0);
b67c6b41
AL		 242 /*
243 * Retuning stuffs are affected by different cards inserted and only
244 * applicable to UHS-I cards. So reset these fields to their initial
245 * value when card is removed.
246 */
973905fe
AL		 247 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
248 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
249
b67c6b41
AL		 250 del_timer_sync(&host->tuning_timer);
251 host->flags &= ~SDHCI_NEEDS_RETUNING;
252 host->mmc->max_blk_count =
253 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
254 }
7260cf5e 255 sdhci_enable_card_detection(host);
d129bceb
PO		 256}
257
258static void sdhci_activate_led(struct sdhci_host *host)
259{
260 u8 ctrl;
261
4e4141a5 262 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 263 ctrl |= SDHCI_CTRL_LED;
4e4141a5 264 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 265}
266
267static void sdhci_deactivate_led(struct sdhci_host *host)
268{
269 u8 ctrl;
270
4e4141a5 271 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 272 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 273 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 274}
275
f9134319 276#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 277static void sdhci_led_control(struct led_classdev *led,
278 enum led_brightness brightness)
279{
280 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
281 unsigned long flags;
282
283 spin_lock_irqsave(&host->lock, flags);
284
66fd8ad5
AH		 285 if (host->runtime_suspended)
286 goto out;
287
2f730fec
PO		 288 if (brightness == LED_OFF)
289 sdhci_deactivate_led(host);
290 else
291 sdhci_activate_led(host);
66fd8ad5 292out:
2f730fec
PO		 293 spin_unlock_irqrestore(&host->lock, flags);
294}
295#endif
296
d129bceb
PO		 297/*****************************************************************************\
298 * *
299 * Core functions *
300 * *
301\*****************************************************************************/
302
a406f5a3 303static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 304{
7659150c
PO		 305 unsigned long flags;
306 size_t blksize, len, chunk;
7244b85b 307 u32 uninitialized_var(scratch);
7659150c 308 u8 *buf;
d129bceb 309
a406f5a3 310 DBG("PIO reading\n");
d129bceb 311
a406f5a3 312 blksize = host->data->blksz;
7659150c 313 chunk = 0;
d129bceb 314
7659150c 315 local_irq_save(flags);
d129bceb 316
a406f5a3 317 while (blksize) {
7659150c
PO		 318 if (!sg_miter_next(&host->sg_miter))
319 BUG();
d129bceb 320
7659150c 321 len = min(host->sg_miter.length, blksize);
d129bceb 322
7659150c
PO		 323 blksize -= len;
324 host->sg_miter.consumed = len;
14d836e7 325
7659150c 326 buf = host->sg_miter.addr;
d129bceb 327
7659150c
PO		 328 while (len) {
329 if (chunk == 0) {
4e4141a5 330 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 331 chunk = 4;
a406f5a3 332 }
7659150c
PO		 333
334 *buf = scratch & 0xFF;
335
336 buf++;
337 scratch >>= 8;
338 chunk--;
339 len--;
d129bceb 340 }
a406f5a3 341 }
7659150c
PO		 342
343 sg_miter_stop(&host->sg_miter);
344
345 local_irq_restore(flags);
a406f5a3 346}
d129bceb 347
a406f5a3
PO		 348static void sdhci_write_block_pio(struct sdhci_host *host)
349{
7659150c
PO		 350 unsigned long flags;
351 size_t blksize, len, chunk;
352 u32 scratch;
353 u8 *buf;
d129bceb 354
a406f5a3
PO		 355 DBG("PIO writing\n");
356
357 blksize = host->data->blksz;
7659150c
PO		 358 chunk = 0;
359 scratch = 0;
d129bceb 360
7659150c 361 local_irq_save(flags);
d129bceb 362
a406f5a3 363 while (blksize) {
7659150c
PO		 364 if (!sg_miter_next(&host->sg_miter))
365 BUG();
a406f5a3 366
7659150c
PO		 367 len = min(host->sg_miter.length, blksize);
368
369 blksize -= len;
370 host->sg_miter.consumed = len;
371
372 buf = host->sg_miter.addr;
d129bceb 373
7659150c
PO		 374 while (len) {
375 scratch |= (u32)*buf << (chunk * 8);
376
377 buf++;
378 chunk++;
379 len--;
380
381 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 382 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 383 chunk = 0;
384 scratch = 0;
d129bceb 385 }
d129bceb
PO		 386 }
387 }
7659150c
PO		 388
389 sg_miter_stop(&host->sg_miter);
390
391 local_irq_restore(flags);
a406f5a3
PO		 392}
393
394static void sdhci_transfer_pio(struct sdhci_host *host)
395{
396 u32 mask;
397
398 BUG_ON(!host->data);
399
7659150c 400 if (host->blocks == 0)
a406f5a3
PO		 401 return;
402
403 if (host->data->flags & MMC_DATA_READ)
404 mask = SDHCI_DATA_AVAILABLE;
405 else
406 mask = SDHCI_SPACE_AVAILABLE;
407
4a3cba32
PO		 408 /*
409 * Some controllers (JMicron JMB38x) mess up the buffer bits
410 * for transfers < 4 bytes. As long as it is just one block,
411 * we can ignore the bits.
412 */
413 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
414 (host->data->blocks == 1))
415 mask = ~0;
416
4e4141a5 417 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 418 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
419 udelay(100);
420
a406f5a3
PO		 421 if (host->data->flags & MMC_DATA_READ)
422 sdhci_read_block_pio(host);
423 else
424 sdhci_write_block_pio(host);
d129bceb 425
7659150c
PO		 426 host->blocks--;
427 if (host->blocks == 0)
a406f5a3 428 break;
a406f5a3 429 }
d129bceb 430
a406f5a3 431 DBG("PIO transfer complete.\n");
d129bceb
PO		 432}
433
2134a922
PO		 434static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
435{
436 local_irq_save(*flags);
482fce99 437 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 438}
439
440static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
441{
482fce99 442 kunmap_atomic(buffer);
2134a922
PO		 443 local_irq_restore(*flags);
444}
445
118cd17d
BD		 446static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
447{
9e506f35
BD		 448 __le32 *dataddr = (__le32 __force *)(desc + 4);
449 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 450
9e506f35
BD		 451 /* SDHCI specification says ADMA descriptors should be 4 byte
452 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 453
9e506f35
BD		 454 cmdlen[0] = cpu_to_le16(cmd);
455 cmdlen[1] = cpu_to_le16(len);
456
457 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 458}
459
8f1934ce 460static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 461 struct mmc_data *data)
462{
463 int direction;
464
465 u8 *desc;
466 u8 *align;
467 dma_addr_t addr;
468 dma_addr_t align_addr;
469 int len, offset;
470
471 struct scatterlist *sg;
472 int i;
473 char *buffer;
474 unsigned long flags;
475
476 /*
477 * The spec does not specify endianness of descriptor table.
478 * We currently guess that it is LE.
479 */
480
481 if (data->flags & MMC_DATA_READ)
482 direction = DMA_FROM_DEVICE;
483 else
484 direction = DMA_TO_DEVICE;
485
2134a922
PO		 486 host->align_addr = dma_map_single(mmc_dev(host->mmc),
487 host->align_buffer, 128 * 4, direction);
8d8bb39b 488 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 489 goto fail;
2134a922
PO		 490 BUG_ON(host->align_addr & 0x3);
491
492 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
493 data->sg, data->sg_len, direction);
8f1934ce
PO		 494 if (host->sg_count == 0)
495 goto unmap_align;
2134a922
PO		 496
497 desc = host->adma_desc;
498 align = host->align_buffer;
499
500 align_addr = host->align_addr;
501
502 for_each_sg(data->sg, sg, host->sg_count, i) {
503 addr = sg_dma_address(sg);
504 len = sg_dma_len(sg);
505
506 /*
507 * The SDHCI specification states that ADMA
508 * addresses must be 32-bit aligned. If they
509 * aren't, then we use a bounce buffer for
510 * the (up to three) bytes that screw up the
511 * alignment.
512 */
513 offset = (4 - (addr & 0x3)) & 0x3;
514 if (offset) {
515 if (data->flags & MMC_DATA_WRITE) {
516 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 517 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 518 memcpy(align, buffer, offset);
519 sdhci_kunmap_atomic(buffer, &flags);
520 }
521
118cd17d
BD		 522 /* tran, valid */
523 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 524
525 BUG_ON(offset > 65536);
526
2134a922
PO		 527 align += 4;
528 align_addr += 4;
529
530 desc += 8;
531
532 addr += offset;
533 len -= offset;
534 }
535
2134a922
PO		 536 BUG_ON(len > 65536);
537
118cd17d
BD		 538 /* tran, valid */
539 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 540 desc += 8;
541
542 /*
543 * If this triggers then we have a calculation bug
544 * somewhere. :/
545 */
d1e49f77 546 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
2134a922
PO		 547 }
548
70764a90
TA		 549 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
550 /*
551 * Mark the last descriptor as the terminating descriptor
552 */
553 if (desc != host->adma_desc) {
554 desc -= 8;
555 desc[0] |= 0x2; /* end */
556 }
557 } else {
558 /*
559 * Add a terminating entry.
560 */
2134a922 561
70764a90
TA		 562 /* nop, end, valid */
563 sdhci_set_adma_desc(desc, 0, 0, 0x3);
564 }
2134a922
PO		 565
566 /*
567 * Resync align buffer as we might have changed it.
568 */
569 if (data->flags & MMC_DATA_WRITE) {
570 dma_sync_single_for_device(mmc_dev(host->mmc),
571 host->align_addr, 128 * 4, direction);
572 }
573
8f1934ce
PO		 574 return 0;
575
8f1934ce
PO		 576unmap_align:
577 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
578 128 * 4, direction);
579fail:
580 return -EINVAL;
2134a922
PO		 581}
582
583static void sdhci_adma_table_post(struct sdhci_host *host,
584 struct mmc_data *data)
585{
586 int direction;
587
588 struct scatterlist *sg;
589 int i, size;
590 u8 *align;
591 char *buffer;
592 unsigned long flags;
de0b65a7 593 bool has_unaligned;
2134a922
PO		 594
595 if (data->flags & MMC_DATA_READ)
596 direction = DMA_FROM_DEVICE;
597 else
598 direction = DMA_TO_DEVICE;
599
2134a922
PO		 600 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
601 128 * 4, direction);
602
de0b65a7
RK		 603 /* Do a quick scan of the SG list for any unaligned mappings */
604 has_unaligned = false;
605 for_each_sg(data->sg, sg, host->sg_count, i)
606 if (sg_dma_address(sg) & 3) {
607 has_unaligned = true;
608 break;
609 }
610
611 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 612 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
613 data->sg_len, direction);
614
615 align = host->align_buffer;
616
617 for_each_sg(data->sg, sg, host->sg_count, i) {
618 if (sg_dma_address(sg) & 0x3) {
619 size = 4 - (sg_dma_address(sg) & 0x3);
620
621 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 622 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 623 memcpy(buffer, align, size);
624 sdhci_kunmap_atomic(buffer, &flags);
625
626 align += 4;
627 }
628 }
629 }
630
631 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
632 data->sg_len, direction);
633}
634
a3c7778f 635static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 636{
1c8cde92 637 u8 count;
a3c7778f 638 struct mmc_data *data = cmd->data;
1c8cde92 639 unsigned target_timeout, current_timeout;
d129bceb 640
ee53ab5d
PO		 641 /*
642 * If the host controller provides us with an incorrect timeout
643 * value, just skip the check and use 0xE. The hardware may take
644 * longer to time out, but that's much better than having a too-short
645 * timeout value.
646 */
11a2f1b7 647 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 648 return 0xE;
e538fbe8 649
a3c7778f 650 /* Unspecified timeout, assume max */
1d4d7744 651 if (!data && !cmd->busy_timeout)
a3c7778f 652 return 0xE;
d129bceb 653
a3c7778f
AW		 654 /* timeout in us */
655 if (!data)
1d4d7744 656 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 657 else {
658 target_timeout = data->timeout_ns / 1000;
659 if (host->clock)
660 target_timeout += data->timeout_clks / host->clock;
661 }
81b39802 662
1c8cde92
PO		 663 /*
664 * Figure out needed cycles.
665 * We do this in steps in order to fit inside a 32 bit int.
666 * The first step is the minimum timeout, which will have a
667 * minimum resolution of 6 bits:
668 * (1) 2^13*1000 > 2^22,
669 * (2) host->timeout_clk < 2^16
670 * =>
671 * (1) / (2) > 2^6
672 */
673 count = 0;
674 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
675 while (current_timeout < target_timeout) {
676 count++;
677 current_timeout <<= 1;
678 if (count >= 0xF)
679 break;
680 }
681
682 if (count >= 0xF) {
09eeff52
CB		 683 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
684 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 685 count = 0xE;
686 }
687
ee53ab5d
PO		 688 return count;
689}
690
6aa943ab
AV		 691static void sdhci_set_transfer_irqs(struct sdhci_host *host)
692{
693 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
694 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
695
696 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 697 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 698 else
b537f94c
RK		 699 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
700
701 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
702 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 703}
704
a3c7778f 705static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 706{
707 u8 count;
2134a922 708 u8 ctrl;
a3c7778f 709 struct mmc_data *data = cmd->data;
8f1934ce 710 int ret;
ee53ab5d
PO		 711
712 WARN_ON(host->data);
713
a3c7778f
AW		 714 if (data || (cmd->flags & MMC_RSP_BUSY)) {
715 count = sdhci_calc_timeout(host, cmd);
716 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
717 }
718
719 if (!data)
ee53ab5d
PO		 720 return;
721
722 /* Sanity checks */
723 BUG_ON(data->blksz * data->blocks > 524288);
724 BUG_ON(data->blksz > host->mmc->max_blk_size);
725 BUG_ON(data->blocks > 65535);
726
727 host->data = data;
728 host->data_early = 0;
f6a03cbf 729 host->data->bytes_xfered = 0;
ee53ab5d 730
a13abc7b 731 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 732 host->flags |= SDHCI_REQ_USE_DMA;
733
2134a922
PO		 734 /*
735 * FIXME: This doesn't account for merging when mapping the
736 * scatterlist.
737 */
738 if (host->flags & SDHCI_REQ_USE_DMA) {
739 int broken, i;
740 struct scatterlist *sg;
741
742 broken = 0;
743 if (host->flags & SDHCI_USE_ADMA) {
744 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
745 broken = 1;
746 } else {
747 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
748 broken = 1;
749 }
750
751 if (unlikely(broken)) {
752 for_each_sg(data->sg, sg, data->sg_len, i) {
753 if (sg->length & 0x3) {
754 DBG("Reverting to PIO because of "
755 "transfer size (%d)\n",
756 sg->length);
757 host->flags &= ~SDHCI_REQ_USE_DMA;
758 break;
759 }
760 }
761 }
c9fddbc4
PO		 762 }
763
764 /*
765 * The assumption here being that alignment is the same after
766 * translation to device address space.
767 */
2134a922
PO		 768 if (host->flags & SDHCI_REQ_USE_DMA) {
769 int broken, i;
770 struct scatterlist *sg;
771
772 broken = 0;
773 if (host->flags & SDHCI_USE_ADMA) {
774 /*
775 * As we use 3 byte chunks to work around
776 * alignment problems, we need to check this
777 * quirk.
778 */
779 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
780 broken = 1;
781 } else {
782 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
783 broken = 1;
784 }
785
786 if (unlikely(broken)) {
787 for_each_sg(data->sg, sg, data->sg_len, i) {
788 if (sg->offset & 0x3) {
789 DBG("Reverting to PIO because of "
790 "bad alignment\n");
791 host->flags &= ~SDHCI_REQ_USE_DMA;
792 break;
793 }
794 }
795 }
796 }
797
8f1934ce
PO		 798 if (host->flags & SDHCI_REQ_USE_DMA) {
799 if (host->flags & SDHCI_USE_ADMA) {
800 ret = sdhci_adma_table_pre(host, data);
801 if (ret) {
802 /*
803 * This only happens when someone fed
804 * us an invalid request.
805 */
806 WARN_ON(1);
ebd6d357 807 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 808 } else {
4e4141a5
AV		 809 sdhci_writel(host, host->adma_addr,
810 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 811 }
812 } else {
c8b3e02e 813 int sg_cnt;
8f1934ce 814
c8b3e02e 815 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 816 data->sg, data->sg_len,
817 (data->flags & MMC_DATA_READ) ?
818 DMA_FROM_DEVICE :
819 DMA_TO_DEVICE);
c8b3e02e 820 if (sg_cnt == 0) {
8f1934ce
PO		 821 /*
822 * This only happens when someone fed
823 * us an invalid request.
824 */
825 WARN_ON(1);
ebd6d357 826 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 827 } else {
719a61b4 828 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 829 sdhci_writel(host, sg_dma_address(data->sg),
830 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 831 }
832 }
833 }
834
2134a922
PO		 835 /*
836 * Always adjust the DMA selection as some controllers
837 * (e.g. JMicron) can't do PIO properly when the selection
838 * is ADMA.
839 */
840 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 841 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 842 ctrl &= ~SDHCI_CTRL_DMA_MASK;
843 if ((host->flags & SDHCI_REQ_USE_DMA) &&
844 (host->flags & SDHCI_USE_ADMA))
845 ctrl |= SDHCI_CTRL_ADMA32;
846 else
847 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 848 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 849 }
850
8f1934ce 851 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 852 int flags;
853
854 flags = SG_MITER_ATOMIC;
855 if (host->data->flags & MMC_DATA_READ)
856 flags |= SG_MITER_TO_SG;
857 else
858 flags |= SG_MITER_FROM_SG;
859 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 860 host->blocks = data->blocks;
d129bceb 861 }
c7fa9963 862
6aa943ab
AV		 863 sdhci_set_transfer_irqs(host);
864
f6a03cbf
MV		 865 /* Set the DMA boundary value and block size */
866 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
867 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 868 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 869}
870
871static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 872 struct mmc_command *cmd)
c7fa9963
PO		 873{
874 u16 mode;
e89d456f 875 struct mmc_data *data = cmd->data;
c7fa9963 876
2b558c13
DA		 877 if (data == NULL) {
878 /* clear Auto CMD settings for no data CMDs */
879 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
880 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
881 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
c7fa9963 882 return;
2b558c13 883 }
c7fa9963 884
e538fbe8
PO		 885 WARN_ON(!host->data);
886
c7fa9963 887 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 888 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
889 mode |= SDHCI_TRNS_MULTI;
890 /*
891 * If we are sending CMD23, CMD12 never gets sent
892 * on successful completion (so no Auto-CMD12).
893 */
894 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
895 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 896 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
897 mode |= SDHCI_TRNS_AUTO_CMD23;
898 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
899 }
c4512f79 900 }
8edf6371 901
c7fa9963
PO		 902 if (data->flags & MMC_DATA_READ)
903 mode |= SDHCI_TRNS_READ;
c9fddbc4 904 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 905 mode |= SDHCI_TRNS_DMA;
906
4e4141a5 907 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 908}
909
910static void sdhci_finish_data(struct sdhci_host *host)
911{
912 struct mmc_data *data;
d129bceb
PO		 913
914 BUG_ON(!host->data);
915
916 data = host->data;
917 host->data = NULL;
918
c9fddbc4 919 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 920 if (host->flags & SDHCI_USE_ADMA)
921 sdhci_adma_table_post(host, data);
922 else {
923 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
924 data->sg_len, (data->flags & MMC_DATA_READ) ?
925 DMA_FROM_DEVICE : DMA_TO_DEVICE);
926 }
d129bceb
PO		 927 }
928
929 /*
c9b74c5b
PO		 930 * The specification states that the block count register must
931 * be updated, but it does not specify at what point in the
932 * data flow. That makes the register entirely useless to read
933 * back so we have to assume that nothing made it to the card
934 * in the event of an error.
d129bceb 935 */
c9b74c5b
PO		 936 if (data->error)
937 data->bytes_xfered = 0;
d129bceb 938 else
c9b74c5b 939 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 940
e89d456f
AW		 941 /*
942 * Need to send CMD12 if -
943 * a) open-ended multiblock transfer (no CMD23)
944 * b) error in multiblock transfer
945 */
946 if (data->stop &&
947 (data->error ||
948 !host->mrq->sbc)) {
949
d129bceb
PO		 950 /*
951 * The controller needs a reset of internal state machines
952 * upon error conditions.
953 */
17b0429d 954 if (data->error) {
03231f9b
RK		 955 sdhci_do_reset(host, SDHCI_RESET_CMD);
956 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 957 }
958
959 sdhci_send_command(host, data->stop);
960 } else
961 tasklet_schedule(&host->finish_tasklet);
962}
963
c0e55129 964void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 965{
966 int flags;
fd2208d7 967 u32 mask;
7cb2c76f 968 unsigned long timeout;
d129bceb
PO		 969
970 WARN_ON(host->cmd);
971
d129bceb 972 /* Wait max 10 ms */
7cb2c76f 973 timeout = 10;
fd2208d7
PO		 974
975 mask = SDHCI_CMD_INHIBIT;
976 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
977 mask |= SDHCI_DATA_INHIBIT;
978
979 /* We shouldn't wait for data inihibit for stop commands, even
980 though they might use busy signaling */
981 if (host->mrq->data && (cmd == host->mrq->data->stop))
982 mask &= ~SDHCI_DATA_INHIBIT;
983
4e4141a5 984 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 985 if (timeout == 0) {
a3c76eb9 986 pr_err("%s: Controller never released "
acf1da45 987 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 988 sdhci_dumpregs(host);
17b0429d 989 cmd->error = -EIO;
d129bceb
PO		 990 tasklet_schedule(&host->finish_tasklet);
991 return;
992 }
7cb2c76f
PO		 993 timeout--;
994 mdelay(1);
995 }
d129bceb 996
3e1a6892 997 timeout = jiffies;
1d4d7744
UH		 998 if (!cmd->data && cmd->busy_timeout > 9000)
999 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1000 else
1001 timeout += 10 * HZ;
1002 mod_timer(&host->timer, timeout);
d129bceb
PO		 1003
1004 host->cmd = cmd;
1005
a3c7778f 1006 sdhci_prepare_data(host, cmd);
d129bceb 1007
4e4141a5 1008 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1009
e89d456f 1010 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1011
d129bceb 1012 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1013 pr_err("%s: Unsupported response type!\n",
d129bceb 1014 mmc_hostname(host->mmc));
17b0429d 1015 cmd->error = -EINVAL;
d129bceb
PO		 1016 tasklet_schedule(&host->finish_tasklet);
1017 return;
1018 }
1019
1020 if (!(cmd->flags & MMC_RSP_PRESENT))
1021 flags = SDHCI_CMD_RESP_NONE;
1022 else if (cmd->flags & MMC_RSP_136)
1023 flags = SDHCI_CMD_RESP_LONG;
1024 else if (cmd->flags & MMC_RSP_BUSY)
1025 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1026 else
1027 flags = SDHCI_CMD_RESP_SHORT;
1028
1029 if (cmd->flags & MMC_RSP_CRC)
1030 flags |= SDHCI_CMD_CRC;
1031 if (cmd->flags & MMC_RSP_OPCODE)
1032 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1033
1034 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1035 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1036 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1037 flags |= SDHCI_CMD_DATA;
1038
4e4141a5 1039 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1040}
c0e55129 1041EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1042
1043static void sdhci_finish_command(struct sdhci_host *host)
1044{
1045 int i;
1046
1047 BUG_ON(host->cmd == NULL);
1048
1049 if (host->cmd->flags & MMC_RSP_PRESENT) {
1050 if (host->cmd->flags & MMC_RSP_136) {
1051 /* CRC is stripped so we need to do some shifting. */
1052 for (i = 0;i < 4;i++) {
4e4141a5 1053 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1054 SDHCI_RESPONSE + (3-i)*4) << 8;
1055 if (i != 3)
1056 host->cmd->resp[i] |=
4e4141a5 1057 sdhci_readb(host,
d129bceb
PO		 1058 SDHCI_RESPONSE + (3-i)*4-1);
1059 }
1060 } else {
4e4141a5 1061 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1062 }
1063 }
1064
17b0429d 1065 host->cmd->error = 0;
d129bceb 1066
e89d456f
AW		 1067 /* Finished CMD23, now send actual command. */
1068 if (host->cmd == host->mrq->sbc) {
1069 host->cmd = NULL;
1070 sdhci_send_command(host, host->mrq->cmd);
1071 } else {
e538fbe8 1072
e89d456f
AW		 1073 /* Processed actual command. */
1074 if (host->data && host->data_early)
1075 sdhci_finish_data(host);
d129bceb 1076
e89d456f
AW		 1077 if (!host->cmd->data)
1078 tasklet_schedule(&host->finish_tasklet);
1079
1080 host->cmd = NULL;
1081 }
d129bceb
PO		 1082}
1083
52983382
KL		 1084static u16 sdhci_get_preset_value(struct sdhci_host *host)
1085{
1086 u16 ctrl, preset = 0;
1087
1088 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1089
1090 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1091 case SDHCI_CTRL_UHS_SDR12:
1092 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1093 break;
1094 case SDHCI_CTRL_UHS_SDR25:
1095 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1096 break;
1097 case SDHCI_CTRL_UHS_SDR50:
1098 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1099 break;
1100 case SDHCI_CTRL_UHS_SDR104:
1101 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1102 break;
1103 case SDHCI_CTRL_UHS_DDR50:
1104 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1105 break;
1106 default:
1107 pr_warn("%s: Invalid UHS-I mode selected\n",
1108 mmc_hostname(host->mmc));
1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1110 break;
1111 }
1112 return preset;
1113}
1114
1771059c 1115void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1116{
c3ed3877 1117 int div = 0; /* Initialized for compiler warning */
df16219f 1118 int real_div = div, clk_mul = 1;
c3ed3877 1119 u16 clk = 0;
7cb2c76f 1120 unsigned long timeout;
d129bceb 1121
1650d0c7
RK		 1122 host->mmc->actual_clock = 0;
1123
4e4141a5 1124 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1125
1126 if (clock == 0)
373073ef 1127 return;
d129bceb 1128
85105c53 1129 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1130 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1131 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1132 u16 pre_val;
1133
1134 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1135 pre_val = sdhci_get_preset_value(host);
1136 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1137 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1138 if (host->clk_mul &&
1139 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1140 clk = SDHCI_PROG_CLOCK_MODE;
1141 real_div = div + 1;
1142 clk_mul = host->clk_mul;
1143 } else {
1144 real_div = max_t(int, 1, div << 1);
1145 }
1146 goto clock_set;
1147 }
1148
c3ed3877
AN		 1149 /*
1150 * Check if the Host Controller supports Programmable Clock
1151 * Mode.
1152 */
1153 if (host->clk_mul) {
52983382
KL		 1154 for (div = 1; div <= 1024; div++) {
1155 if ((host->max_clk * host->clk_mul / div)
1156 <= clock)
1157 break;
1158 }
c3ed3877 1159 /*
52983382
KL		 1160 * Set Programmable Clock Mode in the Clock
1161 * Control register.
c3ed3877 1162 */
52983382
KL		 1163 clk = SDHCI_PROG_CLOCK_MODE;
1164 real_div = div;
1165 clk_mul = host->clk_mul;
1166 div--;
c3ed3877
AN		 1167 } else {
1168 /* Version 3.00 divisors must be a multiple of 2. */
1169 if (host->max_clk <= clock)
1170 div = 1;
1171 else {
1172 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1173 div += 2) {
1174 if ((host->max_clk / div) <= clock)
1175 break;
1176 }
85105c53 1177 }
df16219f 1178 real_div = div;
c3ed3877 1179 div >>= 1;
85105c53
ZG		 1180 }
1181 } else {
1182 /* Version 2.00 divisors must be a power of 2. */
0397526d 1183 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1184 if ((host->max_clk / div) <= clock)
1185 break;
1186 }
df16219f 1187 real_div = div;
c3ed3877 1188 div >>= 1;
d129bceb 1189 }
d129bceb 1190
52983382 1191clock_set:
df16219f
GC		 1192 if (real_div)
1193 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1194
c3ed3877 1195 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1196 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1197 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1198 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1199 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1200
27f6cb16
CB		 1201 /* Wait max 20 ms */
1202 timeout = 20;
4e4141a5 1203 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1204 & SDHCI_CLOCK_INT_STABLE)) {
1205 if (timeout == 0) {
a3c76eb9 1206 pr_err("%s: Internal clock never "
acf1da45 1207 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1208 sdhci_dumpregs(host);
1209 return;
1210 }
7cb2c76f
PO		 1211 timeout--;
1212 mdelay(1);
1213 }
d129bceb
PO		 1214
1215 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1216 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1217}
1771059c 1218EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1219
ceb6143b 1220static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1221{
8364248a 1222 u8 pwr = 0;
146ad66e 1223
8364248a 1224 if (power != (unsigned short)-1) {
ae628903
PO		 1225 switch (1 << power) {
1226 case MMC_VDD_165_195:
1227 pwr = SDHCI_POWER_180;
1228 break;
1229 case MMC_VDD_29_30:
1230 case MMC_VDD_30_31:
1231 pwr = SDHCI_POWER_300;
1232 break;
1233 case MMC_VDD_32_33:
1234 case MMC_VDD_33_34:
1235 pwr = SDHCI_POWER_330;
1236 break;
1237 default:
1238 BUG();
1239 }
1240 }
1241
1242 if (host->pwr == pwr)
ceb6143b 1243 return -1;
146ad66e 1244
ae628903
PO		 1245 host->pwr = pwr;
1246
1247 if (pwr == 0) {
4e4141a5 1248 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1249 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1250 sdhci_runtime_pm_bus_off(host);
ceb6143b 1251 return 0;
9e9dc5f2
DS		 1252 }
1253
1254 /*
1255 * Spec says that we should clear the power reg before setting
1256 * a new value. Some controllers don't seem to like this though.
1257 */
b8c86fc5 1258 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1259 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1260
e08c1694 1261 /*
c71f6512 1262 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1263 * and set turn on power at the same time, so set the voltage first.
1264 */
11a2f1b7 1265 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1266 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1267
ae628903 1268 pwr |= SDHCI_POWER_ON;
146ad66e 1269
ae628903 1270 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1271
f0710a55
AH		 1272 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1273 sdhci_runtime_pm_bus_on(host);
1274
557b0697
HW		 1275 /*
1276 * Some controllers need an extra 10ms delay of 10ms before they
1277 * can apply clock after applying power
1278 */
11a2f1b7 1279 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1280 mdelay(10);
ceb6143b
AH		 1281
1282 return power;
146ad66e
PO		 1283}
1284
d129bceb
PO		 1285/*****************************************************************************\
1286 * *
1287 * MMC callbacks *
1288 * *
1289\*****************************************************************************/
1290
1291static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1292{
1293 struct sdhci_host *host;
505a8680 1294 int present;
d129bceb 1295 unsigned long flags;
473b095a 1296 u32 tuning_opcode;
d129bceb
PO		 1297
1298 host = mmc_priv(mmc);
1299
66fd8ad5
AH		 1300 sdhci_runtime_pm_get(host);
1301
d129bceb
PO		 1302 spin_lock_irqsave(&host->lock, flags);
1303
1304 WARN_ON(host->mrq != NULL);
1305
f9134319 1306#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1307 sdhci_activate_led(host);
2f730fec 1308#endif
e89d456f
AW		 1309
1310 /*
1311 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1312 * requests if Auto-CMD12 is enabled.
1313 */
1314 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1315 if (mrq->stop) {
1316 mrq->data->stop = NULL;
1317 mrq->stop = NULL;
1318 }
1319 }
d129bceb
PO		 1320
1321 host->mrq = mrq;
1322
505a8680
SG		 1323 /*
1324 * Firstly check card presence from cd-gpio. The return could
1325 * be one of the following possibilities:
1326 * negative: cd-gpio is not available
1327 * zero: cd-gpio is used, and card is removed
1328 * one: cd-gpio is used, and card is present
1329 */
1330 present = mmc_gpio_get_cd(host->mmc);
1331 if (present < 0) {
1332 /* If polling, assume that the card is always present. */
1333 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1334 present = 1;
1335 else
1336 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1337 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1338 }
1339
68d1fb7e 1340 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1341 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1342 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1343 } else {
1344 u32 present_state;
1345
1346 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1347 /*
1348 * Check if the re-tuning timer has already expired and there
1349 * is no on-going data transfer. If so, we need to execute
1350 * tuning procedure before sending command.
1351 */
1352 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1353 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1354 if (mmc->card) {
1355 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1356 tuning_opcode =
1357 mmc->card->type == MMC_TYPE_MMC ?
1358 MMC_SEND_TUNING_BLOCK_HS200 :
1359 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1360
1361 /* Here we need to set the host->mrq to NULL,
1362 * in case the pending finish_tasklet
1363 * finishes it incorrectly.
1364 */
1365 host->mrq = NULL;
1366
14efd957
CB		 1367 spin_unlock_irqrestore(&host->lock, flags);
1368 sdhci_execute_tuning(mmc, tuning_opcode);
1369 spin_lock_irqsave(&host->lock, flags);
1370
1371 /* Restore original mmc_request structure */
1372 host->mrq = mrq;
1373 }
cf2b5eea
AN		 1374 }
1375
8edf6371 1376 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1377 sdhci_send_command(host, mrq->sbc);
1378 else
1379 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1380 }
d129bceb 1381
5f25a66f 1382 mmiowb();
d129bceb
PO		 1383 spin_unlock_irqrestore(&host->lock, flags);
1384}
1385
2317f56c
RK		 1386void sdhci_set_bus_width(struct sdhci_host *host, int width)
1387{
1388 u8 ctrl;
1389
1390 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1391 if (width == MMC_BUS_WIDTH_8) {
1392 ctrl &= ~SDHCI_CTRL_4BITBUS;
1393 if (host->version >= SDHCI_SPEC_300)
1394 ctrl |= SDHCI_CTRL_8BITBUS;
1395 } else {
1396 if (host->version >= SDHCI_SPEC_300)
1397 ctrl &= ~SDHCI_CTRL_8BITBUS;
1398 if (width == MMC_BUS_WIDTH_4)
1399 ctrl |= SDHCI_CTRL_4BITBUS;
1400 else
1401 ctrl &= ~SDHCI_CTRL_4BITBUS;
1402 }
1403 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1404}
1405EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1406
66fd8ad5 1407static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1408{
d129bceb 1409 unsigned long flags;
ceb6143b 1410 int vdd_bit = -1;
d129bceb
PO		 1411 u8 ctrl;
1412
d129bceb
PO		 1413 spin_lock_irqsave(&host->lock, flags);
1414
ceb6143b
AH		 1415 if (host->flags & SDHCI_DEVICE_DEAD) {
1416 spin_unlock_irqrestore(&host->lock, flags);
1417 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1418 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1419 return;
1420 }
1e72859e 1421
d129bceb
PO		 1422 /*
1423 * Reset the chip on each power off.
1424 * Should clear out any weird states.
1425 */
1426 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1427 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1428 sdhci_reinit(host);
d129bceb
PO		 1429 }
1430
52983382 1431 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1432 (ios->power_mode == MMC_POWER_UP) &&
1433 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1434 sdhci_enable_preset_value(host, false);
1435
373073ef 1436 if (!ios->clock || ios->clock != host->clock) {
1771059c 1437 host->ops->set_clock(host, ios->clock);
373073ef
RK		 1438 host->clock = ios->clock;
1439 }
d129bceb
PO		 1440
1441 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1442 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1443 else
ceb6143b
AH		 1444 vdd_bit = sdhci_set_power(host, ios->vdd);
1445
1446 if (host->vmmc && vdd_bit != -1) {
1447 spin_unlock_irqrestore(&host->lock, flags);
1448 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1449 spin_lock_irqsave(&host->lock, flags);
1450 }
d129bceb 1451
643a81ff
PR		 1452 if (host->ops->platform_send_init_74_clocks)
1453 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1454
2317f56c 1455 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1456
15ec4461 1457 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1458
3ab9c8da
PR		 1459 if ((ios->timing == MMC_TIMING_SD_HS ||
1460 ios->timing == MMC_TIMING_MMC_HS)
1461 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1462 ctrl |= SDHCI_CTRL_HISPD;
1463 else
1464 ctrl &= ~SDHCI_CTRL_HISPD;
1465
d6d50a15 1466 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1467 u16 clk, ctrl_2;
49c468fc
AN		 1468
1469 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1470 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1471 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1472 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1473 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1474 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1475 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1476 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1477
1478 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1479 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1480 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1481 /*
1482 * We only need to set Driver Strength if the
1483 * preset value enable is not set.
1484 */
1485 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1486 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1487 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1488 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1489 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1490
1491 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1492 } else {
1493 /*
1494 * According to SDHC Spec v3.00, if the Preset Value
1495 * Enable in the Host Control 2 register is set, we
1496 * need to reset SD Clock Enable before changing High
1497 * Speed Enable to avoid generating clock gliches.
1498 */
758535c4
AN		 1499
1500 /* Reset SD Clock Enable */
1501 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1502 clk &= ~SDHCI_CLOCK_CARD_EN;
1503 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1504
1505 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1506
1507 /* Re-enable SD Clock */
1771059c 1508 host->ops->set_clock(host, host->clock);
d6d50a15 1509 }
49c468fc 1510
49c468fc
AN		 1511
1512 /* Reset SD Clock Enable */
1513 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1514 clk &= ~SDHCI_CLOCK_CARD_EN;
1515 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1516
6322cdd0
PR		 1517 if (host->ops->set_uhs_signaling)
1518 host->ops->set_uhs_signaling(host, ios->timing);
1519 else {
1520 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1521 /* Select Bus Speed Mode for host */
1522 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
59911568
GC		 1523 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1524 (ios->timing == MMC_TIMING_UHS_SDR104))
1525 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
069c9f14 1526 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1527 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1528 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1529 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1530 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1531 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
bb8175a8
SJ		 1532 else if ((ios->timing == MMC_TIMING_UHS_DDR50) ||
1533 (ios->timing == MMC_TIMING_MMC_DDR52))
6322cdd0
PR		 1534 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1535 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1536 }
49c468fc 1537
52983382
KL		 1538 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1539 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1540 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1541 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1542 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1543 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1544 u16 preset;
1545
1546 sdhci_enable_preset_value(host, true);
1547 preset = sdhci_get_preset_value(host);
1548 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1549 >> SDHCI_PRESET_DRV_SHIFT;
1550 }
1551
49c468fc 1552 /* Re-enable SD Clock */
1771059c 1553 host->ops->set_clock(host, host->clock);
758535c4
AN		 1554 } else
1555 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1556
b8352260
LD		 1557 /*
1558 * Some (ENE) controllers go apeshit on some ios operation,
1559 * signalling timeout and CRC errors even on CMD0. Resetting
1560 * it on each ios seems to solve the problem.
1561 */
b8c86fc5 1562 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1563 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1564
5f25a66f 1565 mmiowb();
d129bceb
PO		 1566 spin_unlock_irqrestore(&host->lock, flags);
1567}
1568
66fd8ad5
AH		 1569static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1570{
1571 struct sdhci_host *host = mmc_priv(mmc);
1572
1573 sdhci_runtime_pm_get(host);
1574 sdhci_do_set_ios(host, ios);
1575 sdhci_runtime_pm_put(host);
1576}
1577
94144a46
KL		 1578static int sdhci_do_get_cd(struct sdhci_host *host)
1579{
1580 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1581
1582 if (host->flags & SDHCI_DEVICE_DEAD)
1583 return 0;
1584
1585 /* If polling/nonremovable, assume that the card is always present. */
1586 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1587 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1588 return 1;
1589
1590 /* Try slot gpio detect */
1591 if (!IS_ERR_VALUE(gpio_cd))
1592 return !!gpio_cd;
1593
1594 /* Host native card detect */
1595 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1596}
1597
1598static int sdhci_get_cd(struct mmc_host *mmc)
1599{
1600 struct sdhci_host *host = mmc_priv(mmc);
1601 int ret;
1602
1603 sdhci_runtime_pm_get(host);
1604 ret = sdhci_do_get_cd(host);
1605 sdhci_runtime_pm_put(host);
1606 return ret;
1607}
1608
66fd8ad5 1609static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1610{
d129bceb 1611 unsigned long flags;
2dfb579c 1612 int is_readonly;
d129bceb 1613
d129bceb
PO		 1614 spin_lock_irqsave(&host->lock, flags);
1615
1e72859e 1616 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1617 is_readonly = 0;
1618 else if (host->ops->get_ro)
1619 is_readonly = host->ops->get_ro(host);
1e72859e 1620 else
2dfb579c
WS		 1621 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1622 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1623
1624 spin_unlock_irqrestore(&host->lock, flags);
1625
2dfb579c
WS		 1626 /* This quirk needs to be replaced by a callback-function later */
1627 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1628 !is_readonly : is_readonly;
d129bceb
PO		 1629}
1630
82b0e23a
TI		 1631#define SAMPLE_COUNT 5
1632
66fd8ad5 1633static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1634{
82b0e23a
TI		 1635 int i, ro_count;
1636
82b0e23a 1637 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1638 return sdhci_check_ro(host);
82b0e23a
TI		 1639
1640 ro_count = 0;
1641 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1642 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1643 if (++ro_count > SAMPLE_COUNT / 2)
1644 return 1;
1645 }
1646 msleep(30);
1647 }
1648 return 0;
1649}
1650
20758b66
AH		 1651static void sdhci_hw_reset(struct mmc_host *mmc)
1652{
1653 struct sdhci_host *host = mmc_priv(mmc);
1654
1655 if (host->ops && host->ops->hw_reset)
1656 host->ops->hw_reset(host);
1657}
1658
66fd8ad5 1659static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1660{
66fd8ad5
AH		 1661 struct sdhci_host *host = mmc_priv(mmc);
1662 int ret;
f75979b7 1663
66fd8ad5
AH		 1664 sdhci_runtime_pm_get(host);
1665 ret = sdhci_do_get_ro(host);
1666 sdhci_runtime_pm_put(host);
1667 return ret;
1668}
f75979b7 1669
66fd8ad5
AH		 1670static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1671{
be138554 1672 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1673 if (enable)
b537f94c 1674 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1675 else
b537f94c
RK		 1676 host->ier &= ~SDHCI_INT_CARD_INT;
1677
1678 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1679 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1680 mmiowb();
1681 }
66fd8ad5
AH		 1682}
1683
1684static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1685{
1686 struct sdhci_host *host = mmc_priv(mmc);
1687 unsigned long flags;
f75979b7 1688
ef104333
RK		 1689 sdhci_runtime_pm_get(host);
1690
66fd8ad5 1691 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1692 if (enable)
1693 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1694 else
1695 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1696
66fd8ad5 1697 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1698 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1699
1700 sdhci_runtime_pm_put(host);
f75979b7
PO		 1701}
1702
20b92a30 1703static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1704 struct mmc_ios *ios)
f2119df6 1705{
20b92a30 1706 u16 ctrl;
6231f3de 1707 int ret;
f2119df6 1708
20b92a30
KL		 1709 /*
1710 * Signal Voltage Switching is only applicable for Host Controllers
1711 * v3.00 and above.
1712 */
1713 if (host->version < SDHCI_SPEC_300)
1714 return 0;
6231f3de 1715
f2119df6 1716 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1717
21f5998f 1718 switch (ios->signal_voltage) {
20b92a30
KL		 1719 case MMC_SIGNAL_VOLTAGE_330:
1720 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1721 ctrl &= ~SDHCI_CTRL_VDD_180;
1722 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1723
20b92a30
KL		 1724 if (host->vqmmc) {
1725 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1726 if (ret) {
1727 pr_warning("%s: Switching to 3.3V signalling voltage "
1728 " failed\n", mmc_hostname(host->mmc));
1729 return -EIO;
1730 }
1731 }
1732 /* Wait for 5ms */
1733 usleep_range(5000, 5500);
f2119df6 1734
20b92a30
KL		 1735 /* 3.3V regulator output should be stable within 5 ms */
1736 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1737 if (!(ctrl & SDHCI_CTRL_VDD_180))
1738 return 0;
6231f3de 1739
20b92a30
KL		 1740 pr_warning("%s: 3.3V regulator output did not became stable\n",
1741 mmc_hostname(host->mmc));
1742
1743 return -EAGAIN;
1744 case MMC_SIGNAL_VOLTAGE_180:
1745 if (host->vqmmc) {
1746 ret = regulator_set_voltage(host->vqmmc,
1747 1700000, 1950000);
1748 if (ret) {
1749 pr_warning("%s: Switching to 1.8V signalling voltage "
1750 " failed\n", mmc_hostname(host->mmc));
1751 return -EIO;
1752 }
1753 }
6231f3de 1754
6231f3de
PR		 1755 /*
1756 * Enable 1.8V Signal Enable in the Host Control2
1757 * register
1758 */
20b92a30
KL		 1759 ctrl |= SDHCI_CTRL_VDD_180;
1760 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1761
20b92a30
KL		 1762 /* Wait for 5ms */
1763 usleep_range(5000, 5500);
f2119df6 1764
20b92a30
KL		 1765 /* 1.8V regulator output should be stable within 5 ms */
1766 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1767 if (ctrl & SDHCI_CTRL_VDD_180)
1768 return 0;
f2119df6 1769
20b92a30
KL		 1770 pr_warning("%s: 1.8V regulator output did not became stable\n",
1771 mmc_hostname(host->mmc));
f2119df6 1772
20b92a30
KL		 1773 return -EAGAIN;
1774 case MMC_SIGNAL_VOLTAGE_120:
1775 if (host->vqmmc) {
1776 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1777 if (ret) {
1778 pr_warning("%s: Switching to 1.2V signalling voltage "
1779 " failed\n", mmc_hostname(host->mmc));
1780 return -EIO;
f2119df6
AN		 1781 }
1782 }
6231f3de 1783 return 0;
20b92a30 1784 default:
f2119df6
AN		 1785 /* No signal voltage switch required */
1786 return 0;
20b92a30 1787 }
f2119df6
AN		 1788}
1789
66fd8ad5 1790static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1791 struct mmc_ios *ios)
66fd8ad5
AH		 1792{
1793 struct sdhci_host *host = mmc_priv(mmc);
1794 int err;
1795
1796 if (host->version < SDHCI_SPEC_300)
1797 return 0;
1798 sdhci_runtime_pm_get(host);
21f5998f 1799 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1800 sdhci_runtime_pm_put(host);
1801 return err;
1802}
1803
20b92a30
KL		 1804static int sdhci_card_busy(struct mmc_host *mmc)
1805{
1806 struct sdhci_host *host = mmc_priv(mmc);
1807 u32 present_state;
1808
1809 sdhci_runtime_pm_get(host);
1810 /* Check whether DAT[3:0] is 0000 */
1811 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1812 sdhci_runtime_pm_put(host);
1813
1814 return !(present_state & SDHCI_DATA_LVL_MASK);
1815}
1816
069c9f14 1817static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1818{
1819 struct sdhci_host *host;
1820 u16 ctrl;
b513ea25
AN		 1821 int tuning_loop_counter = MAX_TUNING_LOOP;
1822 unsigned long timeout;
1823 int err = 0;
069c9f14 1824 bool requires_tuning_nonuhs = false;
2b35bd83 1825 unsigned long flags;
b513ea25
AN		 1826
1827 host = mmc_priv(mmc);
1828
66fd8ad5 1829 sdhci_runtime_pm_get(host);
2b35bd83 1830 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1831
1832 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1833
1834 /*
069c9f14
G		 1835 * The Host Controller needs tuning only in case of SDR104 mode
1836 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1837 * Capabilities register.
069c9f14
G		 1838 * If the Host Controller supports the HS200 mode then the
1839 * tuning function has to be executed.
b513ea25 1840 */
069c9f14
G		 1841 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1842 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
156e14b1 1843 host->flags & SDHCI_SDR104_NEEDS_TUNING))
069c9f14
G		 1844 requires_tuning_nonuhs = true;
1845
b513ea25 1846 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1847 requires_tuning_nonuhs)
b513ea25
AN		 1848 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1849 else {
2b35bd83 1850 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1851 sdhci_runtime_pm_put(host);
b513ea25
AN		 1852 return 0;
1853 }
1854
45251812 1855 if (host->ops->platform_execute_tuning) {
2b35bd83 1856 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1857 err = host->ops->platform_execute_tuning(host, opcode);
1858 sdhci_runtime_pm_put(host);
1859 return err;
1860 }
1861
b513ea25
AN		 1862 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1863
1864 /*
1865 * As per the Host Controller spec v3.00, tuning command
1866 * generates Buffer Read Ready interrupt, so enable that.
1867 *
1868 * Note: The spec clearly says that when tuning sequence
1869 * is being performed, the controller does not generate
1870 * interrupts other than Buffer Read Ready interrupt. But
1871 * to make sure we don't hit a controller bug, we _only_
1872 * enable Buffer Read Ready interrupt here.
1873 */
b537f94c
RK		 1874 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1875 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1876
1877 /*
1878 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1879 * of loops reaches 40 times or a timeout of 150ms occurs.
1880 */
1881 timeout = 150;
1882 do {
1883 struct mmc_command cmd = {0};
66fd8ad5 1884 struct mmc_request mrq = {NULL};
b513ea25
AN		 1885
1886 if (!tuning_loop_counter && !timeout)
1887 break;
1888
069c9f14 1889 cmd.opcode = opcode;
b513ea25
AN		 1890 cmd.arg = 0;
1891 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1892 cmd.retries = 0;
1893 cmd.data = NULL;
1894 cmd.error = 0;
1895
1896 mrq.cmd = &cmd;
1897 host->mrq = &mrq;
1898
1899 /*
1900 * In response to CMD19, the card sends 64 bytes of tuning
1901 * block to the Host Controller. So we set the block size
1902 * to 64 here.
1903 */
069c9f14
G		 1904 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1905 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1906 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1907 SDHCI_BLOCK_SIZE);
1908 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1909 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1910 SDHCI_BLOCK_SIZE);
1911 } else {
1912 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1913 SDHCI_BLOCK_SIZE);
1914 }
b513ea25
AN		 1915
1916 /*
1917 * The tuning block is sent by the card to the host controller.
1918 * So we set the TRNS_READ bit in the Transfer Mode register.
1919 * This also takes care of setting DMA Enable and Multi Block
1920 * Select in the same register to 0.
1921 */
1922 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1923
1924 sdhci_send_command(host, &cmd);
1925
1926 host->cmd = NULL;
1927 host->mrq = NULL;
1928
2b35bd83 1929 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1930 /* Wait for Buffer Read Ready interrupt */
1931 wait_event_interruptible_timeout(host->buf_ready_int,
1932 (host->tuning_done == 1),
1933 msecs_to_jiffies(50));
2b35bd83 1934 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1935
1936 if (!host->tuning_done) {
a3c76eb9 1937 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1938 "Buffer Read Ready interrupt during tuning "
1939 "procedure, falling back to fixed sampling "
1940 "clock\n");
1941 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1942 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1943 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1944 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1945
1946 err = -EIO;
1947 goto out;
1948 }
1949
1950 host->tuning_done = 0;
1951
1952 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1953 tuning_loop_counter--;
1954 timeout--;
197160d5
NS		 1955
1956 /* eMMC spec does not require a delay between tuning cycles */
1957 if (opcode == MMC_SEND_TUNING_BLOCK)
1958 mdelay(1);
b513ea25
AN		 1959 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1960
1961 /*
1962 * The Host Driver has exhausted the maximum number of loops allowed,
1963 * so use fixed sampling frequency.
1964 */
1965 if (!tuning_loop_counter || !timeout) {
1966 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1967 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
114f2bf6 1968 err = -EIO;
b513ea25
AN		 1969 } else {
1970 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1971 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1972 " failed, falling back to fixed sampling"
1973 " clock\n");
1974 err = -EIO;
1975 }
1976 }
1977
1978out:
cf2b5eea
AN		 1979 /*
1980 * If this is the very first time we are here, we start the retuning
1981 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1982 * flag won't be set, we check this condition before actually starting
1983 * the timer.
1984 */
1985 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1986 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 1987 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 1988 mod_timer(&host->tuning_timer, jiffies +
1989 host->tuning_count * HZ);
1990 /* Tuning mode 1 limits the maximum data length to 4MB */
1991 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 1992 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 1993 host->flags &= ~SDHCI_NEEDS_RETUNING;
1994 /* Reload the new initial value for timer */
2bc02485
AS		 1995 mod_timer(&host->tuning_timer, jiffies +
1996 host->tuning_count * HZ);
cf2b5eea
AN		 1997 }
1998
1999 /*
2000 * In case tuning fails, host controllers which support re-tuning can
2001 * try tuning again at a later time, when the re-tuning timer expires.
2002 * So for these controllers, we return 0. Since there might be other
2003 * controllers who do not have this capability, we return error for
973905fe
AL		 2004 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2005 * a retuning timer to do the retuning for the card.
cf2b5eea 2006 */
973905fe 2007 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2008 err = 0;
2009
b537f94c
RK		 2010 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2011 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2b35bd83 2012 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2013 sdhci_runtime_pm_put(host);
b513ea25
AN		 2014
2015 return err;
2016}
2017
52983382
KL		 2018
2019static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2020{
4d55c5a1 2021 u16 ctrl;
4d55c5a1 2022
4d55c5a1
AN		 2023 /* Host Controller v3.00 defines preset value registers */
2024 if (host->version < SDHCI_SPEC_300)
2025 return;
2026
4d55c5a1
AN		 2027 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2028
2029 /*
2030 * We only enable or disable Preset Value if they are not already
2031 * enabled or disabled respectively. Otherwise, we bail out.
2032 */
2033 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2034 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2035 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2036 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2037 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2038 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2039 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2040 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2041 }
66fd8ad5
AH		 2042}
2043
71e69211 2044static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2045{
71e69211 2046 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2047 unsigned long flags;
2048
722e1280
CD		 2049 /* First check if client has provided their own card event */
2050 if (host->ops->card_event)
2051 host->ops->card_event(host);
2052
d129bceb
PO		 2053 spin_lock_irqsave(&host->lock, flags);
2054
66fd8ad5 2055 /* Check host->mrq first in case we are runtime suspended */
9668d765 2056 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2057 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2058 mmc_hostname(host->mmc));
a3c76eb9 2059 pr_err("%s: Resetting controller.\n",
66fd8ad5 2060 mmc_hostname(host->mmc));
d129bceb 2061
03231f9b
RK		 2062 sdhci_do_reset(host, SDHCI_RESET_CMD);
2063 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2064
66fd8ad5
AH		 2065 host->mrq->cmd->error = -ENOMEDIUM;
2066 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2067 }
2068
2069 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2070}
2071
2072static const struct mmc_host_ops sdhci_ops = {
2073 .request = sdhci_request,
2074 .set_ios = sdhci_set_ios,
94144a46 2075 .get_cd = sdhci_get_cd,
71e69211
GL		 2076 .get_ro = sdhci_get_ro,
2077 .hw_reset = sdhci_hw_reset,
2078 .enable_sdio_irq = sdhci_enable_sdio_irq,
2079 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2080 .execute_tuning = sdhci_execute_tuning,
71e69211 2081 .card_event = sdhci_card_event,
20b92a30 2082 .card_busy = sdhci_card_busy,
71e69211
GL		 2083};
2084
2085/*****************************************************************************\
2086 * *
2087 * Tasklets *
2088 * *
2089\*****************************************************************************/
2090
d129bceb
PO		 2091static void sdhci_tasklet_finish(unsigned long param)
2092{
2093 struct sdhci_host *host;
2094 unsigned long flags;
2095 struct mmc_request *mrq;
2096
2097 host = (struct sdhci_host*)param;
2098
66fd8ad5
AH		 2099 spin_lock_irqsave(&host->lock, flags);
2100
0c9c99a7
CB		 2101 /*
2102 * If this tasklet gets rescheduled while running, it will
2103 * be run again afterwards but without any active request.
2104 */
66fd8ad5
AH		 2105 if (!host->mrq) {
2106 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2107 return;
66fd8ad5 2108 }
d129bceb
PO		 2109
2110 del_timer(&host->timer);
2111
2112 mrq = host->mrq;
2113
d129bceb
PO		 2114 /*
2115 * The controller needs a reset of internal state machines
2116 * upon error conditions.
2117 */
1e72859e 2118 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2119 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2120 (mrq->data && (mrq->data->error ||
2121 (mrq->data->stop && mrq->data->stop->error))) ||
2122 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2123
2124 /* Some controllers need this kick or reset won't work here */
8213af3b 2125 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2126 /* This is to force an update */
1771059c 2127 host->ops->set_clock(host, host->clock);
645289dc
PO		 2128
2129 /* Spec says we should do both at the same time, but Ricoh
2130 controllers do not like that. */
03231f9b
RK		 2131 sdhci_do_reset(host, SDHCI_RESET_CMD);
2132 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2133 }
2134
2135 host->mrq = NULL;
2136 host->cmd = NULL;
2137 host->data = NULL;
2138
f9134319 2139#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2140 sdhci_deactivate_led(host);
2f730fec 2141#endif
d129bceb 2142
5f25a66f 2143 mmiowb();
d129bceb
PO		 2144 spin_unlock_irqrestore(&host->lock, flags);
2145
2146 mmc_request_done(host->mmc, mrq);
66fd8ad5 2147 sdhci_runtime_pm_put(host);
d129bceb
PO		 2148}
2149
2150static void sdhci_timeout_timer(unsigned long data)
2151{
2152 struct sdhci_host *host;
2153 unsigned long flags;
2154
2155 host = (struct sdhci_host*)data;
2156
2157 spin_lock_irqsave(&host->lock, flags);
2158
2159 if (host->mrq) {
a3c76eb9 2160 pr_err("%s: Timeout waiting for hardware "
acf1da45 2161 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2162 sdhci_dumpregs(host);
2163
2164 if (host->data) {
17b0429d 2165 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2166 sdhci_finish_data(host);
2167 } else {
2168 if (host->cmd)
17b0429d 2169 host->cmd->error = -ETIMEDOUT;
d129bceb 2170 else
17b0429d 2171 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2172
2173 tasklet_schedule(&host->finish_tasklet);
2174 }
2175 }
2176
5f25a66f 2177 mmiowb();
d129bceb
PO		 2178 spin_unlock_irqrestore(&host->lock, flags);
2179}
2180
cf2b5eea
AN		 2181static void sdhci_tuning_timer(unsigned long data)
2182{
2183 struct sdhci_host *host;
2184 unsigned long flags;
2185
2186 host = (struct sdhci_host *)data;
2187
2188 spin_lock_irqsave(&host->lock, flags);
2189
2190 host->flags |= SDHCI_NEEDS_RETUNING;
2191
2192 spin_unlock_irqrestore(&host->lock, flags);
2193}
2194
d129bceb
PO		 2195/*****************************************************************************\
2196 * *
2197 * Interrupt handling *
2198 * *
2199\*****************************************************************************/
2200
2201static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2202{
2203 BUG_ON(intmask == 0);
2204
2205 if (!host->cmd) {
a3c76eb9 2206 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2207 "though no command operation was in progress.\n",
2208 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2209 sdhci_dumpregs(host);
2210 return;
2211 }
2212
43b58b36 2213 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2214 host->cmd->error = -ETIMEDOUT;
2215 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2216 SDHCI_INT_INDEX))
2217 host->cmd->error = -EILSEQ;
43b58b36 2218
e809517f 2219 if (host->cmd->error) {
d129bceb 2220 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2221 return;
2222 }
2223
2224 /*
2225 * The host can send and interrupt when the busy state has
2226 * ended, allowing us to wait without wasting CPU cycles.
2227 * Unfortunately this is overloaded on the "data complete"
2228 * interrupt, so we need to take some care when handling
2229 * it.
2230 *
2231 * Note: The 1.0 specification is a bit ambiguous about this
2232 * feature so there might be some problems with older
2233 * controllers.
2234 */
2235 if (host->cmd->flags & MMC_RSP_BUSY) {
2236 if (host->cmd->data)
2237 DBG("Cannot wait for busy signal when also "
2238 "doing a data transfer");
f945405c 2239 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2240 return;
f945405c
BD		 2241
2242 /* The controller does not support the end-of-busy IRQ,
2243 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2244 }
2245
2246 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2247 sdhci_finish_command(host);
d129bceb
PO		 2248}
2249
0957c333 2250#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2251static void sdhci_show_adma_error(struct sdhci_host *host)
2252{
2253 const char *name = mmc_hostname(host->mmc);
2254 u8 *desc = host->adma_desc;
2255 __le32 *dma;
2256 __le16 *len;
2257 u8 attr;
2258
2259 sdhci_dumpregs(host);
2260
2261 while (true) {
2262 dma = (__le32 *)(desc + 4);
2263 len = (__le16 *)(desc + 2);
2264 attr = *desc;
2265
2266 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2267 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2268
2269 desc += 8;
2270
2271 if (attr & 2)
2272 break;
2273 }
2274}
2275#else
2276static void sdhci_show_adma_error(struct sdhci_host *host) { }
2277#endif
2278
d129bceb
PO		 2279static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2280{
069c9f14 2281 u32 command;
d129bceb
PO		 2282 BUG_ON(intmask == 0);
2283
b513ea25
AN		 2284 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2285 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2286 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2287 if (command == MMC_SEND_TUNING_BLOCK ||
2288 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2289 host->tuning_done = 1;
2290 wake_up(&host->buf_ready_int);
2291 return;
2292 }
2293 }
2294
d129bceb
PO		 2295 if (!host->data) {
2296 /*
e809517f
PO		 2297 * The "data complete" interrupt is also used to
2298 * indicate that a busy state has ended. See comment
2299 * above in sdhci_cmd_irq().
d129bceb 2300 */
e809517f
PO		 2301 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2302 if (intmask & SDHCI_INT_DATA_END) {
2303 sdhci_finish_command(host);
2304 return;
2305 }
2306 }
d129bceb 2307
a3c76eb9 2308 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2309 "though no data operation was in progress.\n",
2310 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2311 sdhci_dumpregs(host);
2312
2313 return;
2314 }
2315
2316 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2317 host->data->error = -ETIMEDOUT;
22113efd
AL		 2318 else if (intmask & SDHCI_INT_DATA_END_BIT)
2319 host->data->error = -EILSEQ;
2320 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2321 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2322 != MMC_BUS_TEST_R)
17b0429d 2323 host->data->error = -EILSEQ;
6882a8c0 2324 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2325 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2326 sdhci_show_adma_error(host);
2134a922 2327 host->data->error = -EIO;
a4071fbb
HZ		 2328 if (host->ops->adma_workaround)
2329 host->ops->adma_workaround(host, intmask);
6882a8c0 2330 }
d129bceb 2331
17b0429d 2332 if (host->data->error)
d129bceb
PO		 2333 sdhci_finish_data(host);
2334 else {
a406f5a3 2335 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2336 sdhci_transfer_pio(host);
2337
6ba736a1
PO		 2338 /*
2339 * We currently don't do anything fancy with DMA
2340 * boundaries, but as we can't disable the feature
2341 * we need to at least restart the transfer.
f6a03cbf
MV		 2342 *
2343 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2344 * should return a valid address to continue from, but as
2345 * some controllers are faulty, don't trust them.
6ba736a1 2346 */
f6a03cbf
MV		 2347 if (intmask & SDHCI_INT_DMA_END) {
2348 u32 dmastart, dmanow;
2349 dmastart = sg_dma_address(host->data->sg);
2350 dmanow = dmastart + host->data->bytes_xfered;
2351 /*
2352 * Force update to the next DMA block boundary.
2353 */
2354 dmanow = (dmanow &
2355 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2356 SDHCI_DEFAULT_BOUNDARY_SIZE;
2357 host->data->bytes_xfered = dmanow - dmastart;
2358 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2359 " next 0x%08x\n",
2360 mmc_hostname(host->mmc), dmastart,
2361 host->data->bytes_xfered, dmanow);
2362 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2363 }
6ba736a1 2364
e538fbe8
PO		 2365 if (intmask & SDHCI_INT_DATA_END) {
2366 if (host->cmd) {
2367 /*
2368 * Data managed to finish before the
2369 * command completed. Make sure we do
2370 * things in the proper order.
2371 */
2372 host->data_early = 1;
2373 } else {
2374 sdhci_finish_data(host);
2375 }
2376 }
d129bceb
PO		 2377 }
2378}
2379
7d12e780 2380static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2381{
781e989c 2382 irqreturn_t result = IRQ_NONE;
66fd8ad5 2383 struct sdhci_host *host = dev_id;
41005003 2384 u32 intmask, mask, unexpected = 0;
781e989c 2385 int max_loops = 16;
d129bceb
PO		 2386
2387 spin_lock(&host->lock);
2388
be138554 2389 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2390 spin_unlock(&host->lock);
655bca76 2391 return IRQ_NONE;
66fd8ad5
AH		 2392 }
2393
4e4141a5 2394 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2395 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2396 result = IRQ_NONE;
2397 goto out;
2398 }
2399
41005003
RK		 2400 do {
2401 /* Clear selected interrupts. */
2402 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2403 SDHCI_INT_BUS_POWER);
2404 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2405
41005003
RK		 2406 DBG("*** %s got interrupt: 0x%08x\n",
2407 mmc_hostname(host->mmc), intmask);
d129bceb 2408
41005003
RK		 2409 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2410 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2411 SDHCI_CARD_PRESENT;
d129bceb 2412
41005003
RK		 2413 /*
2414 * There is a observation on i.mx esdhc. INSERT
2415 * bit will be immediately set again when it gets
2416 * cleared, if a card is inserted. We have to mask
2417 * the irq to prevent interrupt storm which will
2418 * freeze the system. And the REMOVE gets the
2419 * same situation.
2420 *
2421 * More testing are needed here to ensure it works
2422 * for other platforms though.
2423 */
b537f94c
RK		 2424 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2425 SDHCI_INT_CARD_REMOVE);
2426 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2427 SDHCI_INT_CARD_INSERT;
2428 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2429 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2430
2431 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2432 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2433
2434 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2435 SDHCI_INT_CARD_REMOVE);
2436 result = IRQ_WAKE_THREAD;
41005003 2437 }
d129bceb 2438
41005003
RK		 2439 if (intmask & SDHCI_INT_CMD_MASK)
2440 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2441
41005003
RK		 2442 if (intmask & SDHCI_INT_DATA_MASK)
2443 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2444
41005003
RK		 2445 if (intmask & SDHCI_INT_BUS_POWER)
2446 pr_err("%s: Card is consuming too much power!\n",
2447 mmc_hostname(host->mmc));
3192a28f 2448
781e989c
RK		 2449 if (intmask & SDHCI_INT_CARD_INT) {
2450 sdhci_enable_sdio_irq_nolock(host, false);
2451 host->thread_isr |= SDHCI_INT_CARD_INT;
2452 result = IRQ_WAKE_THREAD;
2453 }
f75979b7 2454
41005003
RK		 2455 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2456 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2457 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2458 SDHCI_INT_CARD_INT);
f75979b7 2459
41005003
RK		 2460 if (intmask) {
2461 unexpected |= intmask;
2462 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2463 }
d129bceb 2464
781e989c
RK		 2465 if (result == IRQ_NONE)
2466 result = IRQ_HANDLED;
d129bceb 2467
41005003 2468 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2469 } while (intmask && --max_loops);
d129bceb
PO		 2470out:
2471 spin_unlock(&host->lock);
2472
6379b237
AS		 2473 if (unexpected) {
2474 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2475 mmc_hostname(host->mmc), unexpected);
2476 sdhci_dumpregs(host);
2477 }
f75979b7 2478
d129bceb
PO		 2479 return result;
2480}
2481
781e989c
RK		 2482static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2483{
2484 struct sdhci_host *host = dev_id;
2485 unsigned long flags;
2486 u32 isr;
2487
2488 spin_lock_irqsave(&host->lock, flags);
2489 isr = host->thread_isr;
2490 host->thread_isr = 0;
2491 spin_unlock_irqrestore(&host->lock, flags);
2492
3560db8e
RK		 2493 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2494 sdhci_card_event(host->mmc);
2495 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2496 }
2497
781e989c
RK		 2498 if (isr & SDHCI_INT_CARD_INT) {
2499 sdio_run_irqs(host->mmc);
2500
2501 spin_lock_irqsave(&host->lock, flags);
2502 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2503 sdhci_enable_sdio_irq_nolock(host, true);
2504 spin_unlock_irqrestore(&host->lock, flags);
2505 }
2506
2507 return isr ? IRQ_HANDLED : IRQ_NONE;
2508}
2509
d129bceb
PO		 2510/*****************************************************************************\
2511 * *
2512 * Suspend/resume *
2513 * *
2514\*****************************************************************************/
2515
2516#ifdef CONFIG_PM
ad080d79
KL		 2517void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2518{
2519 u8 val;
2520 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2521 | SDHCI_WAKE_ON_INT;
2522
2523 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2524 val |= mask ;
2525 /* Avoid fake wake up */
2526 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2527 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2528 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2529}
2530EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2531
2532void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2533{
2534 u8 val;
2535 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2536 | SDHCI_WAKE_ON_INT;
2537
2538 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2539 val &= ~mask;
2540 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2541}
2542EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2543
29495aa0 2544int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2545{
a1b13b4e
CB		 2546 if (host->ops->platform_suspend)
2547 host->ops->platform_suspend(host);
2548
7260cf5e
AV		 2549 sdhci_disable_card_detection(host);
2550
cf2b5eea 2551 /* Disable tuning since we are suspending */
973905fe 2552 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2553 del_timer_sync(&host->tuning_timer);
cf2b5eea 2554 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2555 }
2556
ad080d79 2557 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2558 host->ier = 0;
2559 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2560 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2561 free_irq(host->irq, host);
2562 } else {
2563 sdhci_enable_irq_wakeups(host);
2564 enable_irq_wake(host->irq);
2565 }
4ee14ec6 2566 return 0;
d129bceb
PO		 2567}
2568
b8c86fc5 2569EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2570
b8c86fc5
PO		 2571int sdhci_resume_host(struct sdhci_host *host)
2572{
4ee14ec6 2573 int ret = 0;
d129bceb 2574
a13abc7b 2575 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2576 if (host->ops->enable_dma)
2577 host->ops->enable_dma(host);
2578 }
d129bceb 2579
ad080d79 2580 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2581 ret = request_threaded_irq(host->irq, sdhci_irq,
2582 sdhci_thread_irq, IRQF_SHARED,
2583 mmc_hostname(host->mmc), host);
ad080d79
KL		 2584 if (ret)
2585 return ret;
2586 } else {
2587 sdhci_disable_irq_wakeups(host);
2588 disable_irq_wake(host->irq);
2589 }
d129bceb 2590
6308d290
AH		 2591 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2592 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2593 /* Card keeps power but host controller does not */
2594 sdhci_init(host, 0);
2595 host->pwr = 0;
2596 host->clock = 0;
2597 sdhci_do_set_ios(host, &host->mmc->ios);
2598 } else {
2599 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2600 mmiowb();
2601 }
b8c86fc5 2602
7260cf5e
AV		 2603 sdhci_enable_card_detection(host);
2604
a1b13b4e
CB		 2605 if (host->ops->platform_resume)
2606 host->ops->platform_resume(host);
2607
cf2b5eea 2608 /* Set the re-tuning expiration flag */
973905fe 2609 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2610 host->flags |= SDHCI_NEEDS_RETUNING;
2611
2f4cbb3d 2612 return ret;
d129bceb
PO		 2613}
2614
b8c86fc5 2615EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2616#endif /* CONFIG_PM */
2617
66fd8ad5
AH		 2618#ifdef CONFIG_PM_RUNTIME
2619
2620static int sdhci_runtime_pm_get(struct sdhci_host *host)
2621{
2622 return pm_runtime_get_sync(host->mmc->parent);
2623}
2624
2625static int sdhci_runtime_pm_put(struct sdhci_host *host)
2626{
2627 pm_runtime_mark_last_busy(host->mmc->parent);
2628 return pm_runtime_put_autosuspend(host->mmc->parent);
2629}
2630
f0710a55
AH		 2631static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2632{
2633 if (host->runtime_suspended || host->bus_on)
2634 return;
2635 host->bus_on = true;
2636 pm_runtime_get_noresume(host->mmc->parent);
2637}
2638
2639static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2640{
2641 if (host->runtime_suspended || !host->bus_on)
2642 return;
2643 host->bus_on = false;
2644 pm_runtime_put_noidle(host->mmc->parent);
2645}
2646
66fd8ad5
AH		 2647int sdhci_runtime_suspend_host(struct sdhci_host *host)
2648{
2649 unsigned long flags;
2650 int ret = 0;
2651
2652 /* Disable tuning since we are suspending */
973905fe 2653 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2654 del_timer_sync(&host->tuning_timer);
2655 host->flags &= ~SDHCI_NEEDS_RETUNING;
2656 }
2657
2658 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2659 host->ier &= SDHCI_INT_CARD_INT;
2660 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2661 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2662 spin_unlock_irqrestore(&host->lock, flags);
2663
781e989c 2664 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2665
2666 spin_lock_irqsave(&host->lock, flags);
2667 host->runtime_suspended = true;
2668 spin_unlock_irqrestore(&host->lock, flags);
2669
2670 return ret;
2671}
2672EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2673
2674int sdhci_runtime_resume_host(struct sdhci_host *host)
2675{
2676 unsigned long flags;
2677 int ret = 0, host_flags = host->flags;
2678
2679 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2680 if (host->ops->enable_dma)
2681 host->ops->enable_dma(host);
2682 }
2683
2684 sdhci_init(host, 0);
2685
2686 /* Force clock and power re-program */
2687 host->pwr = 0;
2688 host->clock = 0;
2689 sdhci_do_set_ios(host, &host->mmc->ios);
2690
2691 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2692 if ((host_flags & SDHCI_PV_ENABLED) &&
2693 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2694 spin_lock_irqsave(&host->lock, flags);
2695 sdhci_enable_preset_value(host, true);
2696 spin_unlock_irqrestore(&host->lock, flags);
2697 }
66fd8ad5
AH		 2698
2699 /* Set the re-tuning expiration flag */
973905fe 2700 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2701 host->flags |= SDHCI_NEEDS_RETUNING;
2702
2703 spin_lock_irqsave(&host->lock, flags);
2704
2705 host->runtime_suspended = false;
2706
2707 /* Enable SDIO IRQ */
ef104333 2708 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2709 sdhci_enable_sdio_irq_nolock(host, true);
2710
2711 /* Enable Card Detection */
2712 sdhci_enable_card_detection(host);
2713
2714 spin_unlock_irqrestore(&host->lock, flags);
2715
2716 return ret;
2717}
2718EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2719
2720#endif
2721
d129bceb
PO		 2722/*****************************************************************************\
2723 * *
b8c86fc5 2724 * Device allocation/registration *
d129bceb
PO		 2725 * *
2726\*****************************************************************************/
2727
b8c86fc5
PO		 2728struct sdhci_host *sdhci_alloc_host(struct device *dev,
2729 size_t priv_size)
d129bceb 2730{
d129bceb
PO		 2731 struct mmc_host *mmc;
2732 struct sdhci_host *host;
2733
b8c86fc5 2734 WARN_ON(dev == NULL);
d129bceb 2735
b8c86fc5 2736 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2737 if (!mmc)
b8c86fc5 2738 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2739
2740 host = mmc_priv(mmc);
2741 host->mmc = mmc;
2742
b8c86fc5
PO		 2743 return host;
2744}
8a4da143 2745
b8c86fc5 2746EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2747
b8c86fc5
PO		 2748int sdhci_add_host(struct sdhci_host *host)
2749{
2750 struct mmc_host *mmc;
bd6a8c30 2751 u32 caps[2] = {0, 0};
f2119df6
AN		 2752 u32 max_current_caps;
2753 unsigned int ocr_avail;
b8c86fc5 2754 int ret;
d129bceb 2755
b8c86fc5
PO		 2756 WARN_ON(host == NULL);
2757 if (host == NULL)
2758 return -EINVAL;
d129bceb 2759
b8c86fc5 2760 mmc = host->mmc;
d129bceb 2761
b8c86fc5
PO		 2762 if (debug_quirks)
2763 host->quirks = debug_quirks;
66fd8ad5
AH		 2764 if (debug_quirks2)
2765 host->quirks2 = debug_quirks2;
d129bceb 2766
03231f9b 2767 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2768
4e4141a5 2769 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2770 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2771 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2772 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2773 pr_err("%s: Unknown controller version (%d). "
b69c9058 2774 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2775 host->version);
4a965505
PO		 2776 }
2777
f2119df6 2778 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2779 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2780
bd6a8c30
PR		 2781 if (host->version >= SDHCI_SPEC_300)
2782 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2783 host->caps1 :
2784 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2785
b8c86fc5 2786 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2787 host->flags |= SDHCI_USE_SDMA;
f2119df6 2788 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2789 DBG("Controller doesn't have SDMA capability\n");
67435274 2790 else
a13abc7b 2791 host->flags |= SDHCI_USE_SDMA;
d129bceb 2792
b8c86fc5 2793 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2794 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2795 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2796 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2797 }
2798
f2119df6
AN		 2799 if ((host->version >= SDHCI_SPEC_200) &&
2800 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2801 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2802
2803 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2804 (host->flags & SDHCI_USE_ADMA)) {
2805 DBG("Disabling ADMA as it is marked broken\n");
2806 host->flags &= ~SDHCI_USE_ADMA;
2807 }
2808
a13abc7b 2809 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2810 if (host->ops->enable_dma) {
2811 if (host->ops->enable_dma(host)) {
a3c76eb9 2812 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2813 "available. Falling back to PIO.\n",
2814 mmc_hostname(mmc));
a13abc7b
RR		 2815 host->flags &=
2816 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2817 }
d129bceb
PO		 2818 }
2819 }
2820
2134a922
PO		 2821 if (host->flags & SDHCI_USE_ADMA) {
2822 /*
2823 * We need to allocate descriptors for all sg entries
2824 * (128) and potentially one alignment transfer for
2825 * each of those entries.
2826 */
d1e49f77
RK		 2827 host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc),
2828 ADMA_SIZE, &host->adma_addr,
2829 GFP_KERNEL);
2134a922
PO		 2830 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2831 if (!host->adma_desc || !host->align_buffer) {
d1e49f77
RK		 2832 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2833 host->adma_desc, host->adma_addr);
2134a922 2834 kfree(host->align_buffer);
a3c76eb9 2835 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2836 "buffers. Falling back to standard DMA.\n",
2837 mmc_hostname(mmc));
2838 host->flags &= ~SDHCI_USE_ADMA;
d1e49f77
RK		 2839 host->adma_desc = NULL;
2840 host->align_buffer = NULL;
2841 } else if (host->adma_addr & 3) {
2842 pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2843 mmc_hostname(mmc));
2844 host->flags &= ~SDHCI_USE_ADMA;
2845 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2846 host->adma_desc, host->adma_addr);
2847 kfree(host->align_buffer);
2848 host->adma_desc = NULL;
2849 host->align_buffer = NULL;
2134a922
PO		 2850 }
2851 }
2852
7659150c
PO		 2853 /*
2854 * If we use DMA, then it's up to the caller to set the DMA
2855 * mask, but PIO does not need the hw shim so we set a new
2856 * mask here in that case.
2857 */
a13abc7b 2858 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2859 host->dma_mask = DMA_BIT_MASK(64);
2860 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2861 }
d129bceb 2862
c4687d5f 2863 if (host->version >= SDHCI_SPEC_300)
f2119df6 2864 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2865 >> SDHCI_CLOCK_BASE_SHIFT;
2866 else
f2119df6 2867 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2868 >> SDHCI_CLOCK_BASE_SHIFT;
2869
4240ff0a 2870 host->max_clk *= 1000000;
f27f47ef
AV		 2871 if (host->max_clk == 0 || host->quirks &
2872 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2873 if (!host->ops->get_max_clock) {
a3c76eb9 2874 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2875 "frequency.\n", mmc_hostname(mmc));
2876 return -ENODEV;
2877 }
2878 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2879 }
d129bceb 2880
c3ed3877
AN		 2881 /*
2882 * In case of Host Controller v3.00, find out whether clock
2883 * multiplier is supported.
2884 */
2885 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2886 SDHCI_CLOCK_MUL_SHIFT;
2887
2888 /*
2889 * In case the value in Clock Multiplier is 0, then programmable
2890 * clock mode is not supported, otherwise the actual clock
2891 * multiplier is one more than the value of Clock Multiplier
2892 * in the Capabilities Register.
2893 */
2894 if (host->clk_mul)
2895 host->clk_mul += 1;
2896
d129bceb
PO		 2897 /*
2898 * Set host parameters.
2899 */
2900 mmc->ops = &sdhci_ops;
c3ed3877 2901 mmc->f_max = host->max_clk;
ce5f036b 2902 if (host->ops->get_min_clock)
a9e58f25 2903 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2904 else if (host->version >= SDHCI_SPEC_300) {
2905 if (host->clk_mul) {
2906 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2907 mmc->f_max = host->max_clk * host->clk_mul;
2908 } else
2909 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2910 } else
0397526d 2911 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2912
272308ca
AS		 2913 host->timeout_clk =
2914 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2915 if (host->timeout_clk == 0) {
2916 if (host->ops->get_timeout_clock) {
2917 host->timeout_clk = host->ops->get_timeout_clock(host);
2918 } else if (!(host->quirks &
2919 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2920 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2921 "frequency.\n", mmc_hostname(mmc));
2922 return -ENODEV;
2923 }
2924 }
2925 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2926 host->timeout_clk *= 1000;
2927
2928 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2929 host->timeout_clk = mmc->f_max / 1000;
272308ca 2930
68eb80e0 2931 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
58d1246d 2932
e89d456f 2933 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 2934 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 2935
2936 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2937 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2938
8edf6371 2939 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2940 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2941 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2942 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2943 host->flags |= SDHCI_AUTO_CMD23;
2944 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2945 } else {
2946 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2947 }
2948
15ec4461
PR		 2949 /*
2950 * A controller may support 8-bit width, but the board itself
2951 * might not have the pins brought out. Boards that support
2952 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2953 * their platform code before calling sdhci_add_host(), and we
2954 * won't assume 8-bit width for hosts without that CAP.
2955 */
5fe23c7f 2956 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2957 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2958
63ef5d8c
JH		 2959 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2960 mmc->caps &= ~MMC_CAP_CMD23;
2961
f2119df6 2962 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2963 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2964
176d1ed4 2965 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2966 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2967 mmc->caps |= MMC_CAP_NEEDS_POLL;
2968
6231f3de 2969 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
462849aa 2970 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2971 if (IS_ERR_OR_NULL(host->vqmmc)) {
2972 if (PTR_ERR(host->vqmmc) < 0) {
2973 pr_info("%s: no vqmmc regulator found\n",
2974 mmc_hostname(mmc));
2975 host->vqmmc = NULL;
2976 }
8363c374 2977 } else {
a3361aba 2978 ret = regulator_enable(host->vqmmc);
cec2e216
KL		 2979 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2980 1950000))
8363c374
KL		 2981 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2982 SDHCI_SUPPORT_SDR50 |
2983 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 2984 if (ret) {
2985 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2986 mmc_hostname(mmc), ret);
2987 host->vqmmc = NULL;
2988 }
8363c374 2989 }
6231f3de 2990
6a66180a
DD		 2991 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2992 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2993 SDHCI_SUPPORT_DDR50);
2994
4188bba0
AC		 2995 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2996 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2997 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 2998 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2999
3000 /* SDR104 supports also implies SDR50 support */
156e14b1 3001 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3002 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3003 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3004 * field can be promoted to support HS200.
3005 */
13868bf2
DC		 3006 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3007 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3008 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3009 mmc->caps |= MMC_CAP_UHS_SDR50;
3010
9107ebbf
MC		 3011 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3012 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3013 mmc->caps |= MMC_CAP_UHS_DDR50;
3014
069c9f14 3015 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3016 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3017 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3018
156e14b1 3019 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3020 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3021 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3022
d6d50a15
AN		 3023 /* Driver Type(s) (A, C, D) supported by the host */
3024 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3025 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3026 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3027 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3028 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3029 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3030
cf2b5eea
AN		 3031 /* Initial value for re-tuning timer count */
3032 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3033 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3034
3035 /*
3036 * In case Re-tuning Timer is not disabled, the actual value of
3037 * re-tuning timer will be 2 ^ (n - 1).
3038 */
3039 if (host->tuning_count)
3040 host->tuning_count = 1 << (host->tuning_count - 1);
3041
3042 /* Re-tuning mode supported by the Host Controller */
3043 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3044 SDHCI_RETUNING_MODE_SHIFT;
3045
8f230f45 3046 ocr_avail = 0;
bad37e1a 3047
462849aa 3048 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
657d5982
KL		 3049 if (IS_ERR_OR_NULL(host->vmmc)) {
3050 if (PTR_ERR(host->vmmc) < 0) {
3051 pr_info("%s: no vmmc regulator found\n",
3052 mmc_hostname(mmc));
3053 host->vmmc = NULL;
3054 }
8363c374 3055 }
bad37e1a 3056
68737043 3057#ifdef CONFIG_REGULATOR
a4f8f257
MS		 3058 /*
3059 * Voltage range check makes sense only if regulator reports
3060 * any voltage value.
3061 */
3062 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 3063 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3064 3600000);
68737043
PR		 3065 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3066 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 3067 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3068 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 3069 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3070 1950000);
68737043
PR		 3071 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3072 caps[0] &= ~SDHCI_CAN_VDD_180;
3073 }
3074#endif /* CONFIG_REGULATOR */
3075
f2119df6
AN		 3076 /*
3077 * According to SD Host Controller spec v3.00, if the Host System
3078 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3079 * the value is meaningful only if Voltage Support in the Capabilities
3080 * register is set. The actual current value is 4 times the register
3081 * value.
3082 */
3083 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3084 if (!max_current_caps && host->vmmc) {
3085 u32 curr = regulator_get_current_limit(host->vmmc);
3086 if (curr > 0) {
3087
3088 /* convert to SDHCI_MAX_CURRENT format */
3089 curr = curr/1000; /* convert to mA */
3090 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3091
3092 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3093 max_current_caps =
3094 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3095 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3096 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3097 }
3098 }
f2119df6
AN		 3099
3100 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3101 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3102
55c4665e 3103 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3104 SDHCI_MAX_CURRENT_330_MASK) >>
3105 SDHCI_MAX_CURRENT_330_SHIFT) *
3106 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3107 }
3108 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3109 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3110
55c4665e 3111 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3112 SDHCI_MAX_CURRENT_300_MASK) >>
3113 SDHCI_MAX_CURRENT_300_SHIFT) *
3114 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3115 }
3116 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3117 ocr_avail |= MMC_VDD_165_195;
3118
55c4665e 3119 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3120 SDHCI_MAX_CURRENT_180_MASK) >>
3121 SDHCI_MAX_CURRENT_180_SHIFT) *
3122 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3123 }
3124
c0b887b6
HZ		 3125 if (host->ocr_mask)
3126 ocr_avail = host->ocr_mask;
3127
8f230f45
TI		 3128 mmc->ocr_avail = ocr_avail;
3129 mmc->ocr_avail_sdio = ocr_avail;
3130 if (host->ocr_avail_sdio)
3131 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3132 mmc->ocr_avail_sd = ocr_avail;
3133 if (host->ocr_avail_sd)
3134 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3135 else /* normal SD controllers don't support 1.8V */
3136 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3137 mmc->ocr_avail_mmc = ocr_avail;
3138 if (host->ocr_avail_mmc)
3139 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3140
3141 if (mmc->ocr_avail == 0) {
a3c76eb9 3142 pr_err("%s: Hardware doesn't report any "
b69c9058 3143 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3144 return -ENODEV;
146ad66e
PO		 3145 }
3146
d129bceb
PO		 3147 spin_lock_init(&host->lock);
3148
3149 /*
2134a922
PO		 3150 * Maximum number of segments. Depends on if the hardware
3151 * can do scatter/gather or not.
d129bceb 3152 */
2134a922 3153 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3154 mmc->max_segs = 128;
a13abc7b 3155 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3156 mmc->max_segs = 1;
2134a922 3157 else /* PIO */
a36274e0 3158 mmc->max_segs = 128;
d129bceb
PO		 3159
3160 /*
bab76961 3161 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3162 * size (512KiB).
d129bceb 3163 */
55db890a 3164 mmc->max_req_size = 524288;
d129bceb
PO		 3165
3166 /*
3167 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3168 * of bytes. When doing hardware scatter/gather, each entry cannot
3169 * be larger than 64 KiB though.
d129bceb 3170 */
30652aa3
OJ		 3171 if (host->flags & SDHCI_USE_ADMA) {
3172 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3173 mmc->max_seg_size = 65535;
3174 else
3175 mmc->max_seg_size = 65536;
3176 } else {
2134a922 3177 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3178 }
d129bceb 3179
fe4a3c7a
PO		 3180 /*
3181 * Maximum block size. This varies from controller to controller and
3182 * is specified in the capabilities register.
3183 */
0633f654
AV		 3184 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3185 mmc->max_blk_size = 2;
3186 } else {
f2119df6 3187 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3188 SDHCI_MAX_BLOCK_SHIFT;
3189 if (mmc->max_blk_size >= 3) {
a3c76eb9 3190 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3191 "assuming 512 bytes\n", mmc_hostname(mmc));
3192 mmc->max_blk_size = 0;
3193 }
3194 }
3195
3196 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3197
55db890a
PO		 3198 /*
3199 * Maximum block count.
3200 */
1388eefd 3201 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3202
d129bceb
PO		 3203 /*
3204 * Init tasklets.
3205 */
d129bceb
PO		 3206 tasklet_init(&host->finish_tasklet,
3207 sdhci_tasklet_finish, (unsigned long)host);
3208
e4cad1b5 3209 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3210
cf2b5eea 3211 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3212 init_waitqueue_head(&host->buf_ready_int);
3213
cf2b5eea
AN		 3214 /* Initialize re-tuning timer */
3215 init_timer(&host->tuning_timer);
3216 host->tuning_timer.data = (unsigned long)host;
3217 host->tuning_timer.function = sdhci_tuning_timer;
3218 }
3219
2af502ca
SG		 3220 sdhci_init(host, 0);
3221
781e989c
RK		 3222 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3223 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3224 if (ret) {
3225 pr_err("%s: Failed to request IRQ %d: %d\n",
3226 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3227 goto untasklet;
0fc81ee3 3228 }
d129bceb 3229
d129bceb
PO		 3230#ifdef CONFIG_MMC_DEBUG
3231 sdhci_dumpregs(host);
3232#endif
3233
f9134319 3234#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3235 snprintf(host->led_name, sizeof(host->led_name),
3236 "%s::", mmc_hostname(mmc));
3237 host->led.name = host->led_name;
2f730fec
PO		 3238 host->led.brightness = LED_OFF;
3239 host->led.default_trigger = mmc_hostname(mmc);
3240 host->led.brightness_set = sdhci_led_control;
3241
b8c86fc5 3242 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3243 if (ret) {
3244 pr_err("%s: Failed to register LED device: %d\n",
3245 mmc_hostname(mmc), ret);
2f730fec 3246 goto reset;
0fc81ee3 3247 }
2f730fec
PO		 3248#endif
3249
5f25a66f
PO		 3250 mmiowb();
3251
d129bceb
PO		 3252 mmc_add_host(mmc);
3253
a3c76eb9 3254 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3255 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3256 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3257 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3258
7260cf5e
AV		 3259 sdhci_enable_card_detection(host);
3260
d129bceb
PO		 3261 return 0;
3262
f9134319 3263#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3264reset:
03231f9b 3265 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3266 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3267 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3268 free_irq(host->irq, host);
3269#endif
8ef1a143 3270untasklet:
d129bceb 3271 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3272
3273 return ret;
3274}
3275
b8c86fc5 3276EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3277
1e72859e 3278void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3279{
1e72859e
PO		 3280 unsigned long flags;
3281
3282 if (dead) {
3283 spin_lock_irqsave(&host->lock, flags);
3284
3285 host->flags |= SDHCI_DEVICE_DEAD;
3286
3287 if (host->mrq) {
a3c76eb9 3288 pr_err("%s: Controller removed during "
1e72859e
PO		 3289 " transfer!\n", mmc_hostname(host->mmc));
3290
3291 host->mrq->cmd->error = -ENOMEDIUM;
3292 tasklet_schedule(&host->finish_tasklet);
3293 }
3294
3295 spin_unlock_irqrestore(&host->lock, flags);
3296 }
3297
7260cf5e
AV		 3298 sdhci_disable_card_detection(host);
3299
b8c86fc5 3300 mmc_remove_host(host->mmc);
d129bceb 3301
f9134319 3302#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3303 led_classdev_unregister(&host->led);
3304#endif
3305
1e72859e 3306 if (!dead)
03231f9b 3307 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3308
b537f94c
RK		 3309 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3310 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3311 free_irq(host->irq, host);
3312
3313 del_timer_sync(&host->timer);
3314
d129bceb 3315 tasklet_kill(&host->finish_tasklet);
2134a922 3316
77dcb3f4
PR		 3317 if (host->vmmc) {
3318 regulator_disable(host->vmmc);
9bea3c85 3319 regulator_put(host->vmmc);
77dcb3f4 3320 }
9bea3c85 3321
6231f3de
PR		 3322 if (host->vqmmc) {
3323 regulator_disable(host->vqmmc);
3324 regulator_put(host->vqmmc);
3325 }
3326
d1e49f77
RK		 3327 if (host->adma_desc)
3328 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
3329 host->adma_desc, host->adma_addr);
2134a922
PO		 3330 kfree(host->align_buffer);
3331
3332 host->adma_desc = NULL;
3333 host->align_buffer = NULL;
d129bceb
PO		 3334}
3335
b8c86fc5 3336EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3337
b8c86fc5 3338void sdhci_free_host(struct sdhci_host *host)
d129bceb 3339{
b8c86fc5 3340 mmc_free_host(host->mmc);
d129bceb
PO		 3341}
3342
b8c86fc5 3343EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3344
3345/*****************************************************************************\
3346 * *
3347 * Driver init/exit *
3348 * *
3349\*****************************************************************************/
3350
3351static int __init sdhci_drv_init(void)
3352{
a3c76eb9 3353 pr_info(DRIVER_NAME
52fbf9c9 3354 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3355 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3356
b8c86fc5 3357 return 0;
d129bceb
PO		 3358}
3359
3360static void __exit sdhci_drv_exit(void)
3361{
d129bceb
PO		 3362}
3363
3364module_init(sdhci_drv_init);
3365module_exit(sdhci_drv_exit);
3366
df673b22 3367module_param(debug_quirks, uint, 0444);
66fd8ad5 3368module_param(debug_quirks2, uint, 0444);
67435274 3369
32710e8f 3370MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3371MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3372MODULE_LICENSE("GPL");
67435274 3373
df673b22 3374MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3375MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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