projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: wmt-sdmmc: Use resource_size()
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
52static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 55static void sdhci_tuning_timer(unsigned long data);
52983382 56static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 57
66fd8ad5
AH		 58#ifdef CONFIG_PM_RUNTIME
59static int sdhci_runtime_pm_get(struct sdhci_host *host);
60static int sdhci_runtime_pm_put(struct sdhci_host *host);
61#else
62static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
63{
64 return 0;
65}
66static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
67{
68 return 0;
69}
70#endif
71
d129bceb
PO		 72static void sdhci_dumpregs(struct sdhci_host *host)
73{
a3c76eb9 74 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 75 mmc_hostname(host->mmc));
d129bceb 76
a3c76eb9 77 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readl(host, SDHCI_DMA_ADDRESS),
79 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 80 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 81 sdhci_readw(host, SDHCI_BLOCK_SIZE),
82 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 83 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 84 sdhci_readl(host, SDHCI_ARGUMENT),
85 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 86 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readl(host, SDHCI_PRESENT_STATE),
88 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readb(host, SDHCI_POWER_CONTROL),
91 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
94 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
97 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 98 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readl(host, SDHCI_INT_ENABLE),
100 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 101 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 102 sdhci_readw(host, SDHCI_ACMD12_ERR),
103 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 105 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 106 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 108 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 109 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 110 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 111 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 112
be3f4ae0 113 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 114 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 115 readl(host->ioaddr + SDHCI_ADMA_ERROR),
116 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
117
a3c76eb9 118 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 119}
120
121/*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125\*****************************************************************************/
126
7260cf5e
AV		 127static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
128{
129 u32 ier;
130
131 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
132 ier &= ~clear;
133 ier |= set;
134 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
135 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
136}
137
138static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
139{
140 sdhci_clear_set_irqs(host, 0, irqs);
141}
142
143static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
144{
145 sdhci_clear_set_irqs(host, irqs, 0);
146}
147
148static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
149{
d25928d1 150 u32 present, irqs;
7260cf5e 151
c79396c1 152 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 153 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 154 return;
155
d25928d1
SG		 156 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
157 SDHCI_CARD_PRESENT;
158 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
159
7260cf5e
AV		 160 if (enable)
161 sdhci_unmask_irqs(host, irqs);
162 else
163 sdhci_mask_irqs(host, irqs);
164}
165
166static void sdhci_enable_card_detection(struct sdhci_host *host)
167{
168 sdhci_set_card_detection(host, true);
169}
170
171static void sdhci_disable_card_detection(struct sdhci_host *host)
172{
173 sdhci_set_card_detection(host, false);
174}
175
d129bceb
PO		 176static void sdhci_reset(struct sdhci_host *host, u8 mask)
177{
e16514d8 178 unsigned long timeout;
063a9dbb 179 u32 uninitialized_var(ier);
e16514d8 180
b8c86fc5 181 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 182 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 183 SDHCI_CARD_PRESENT))
184 return;
185 }
186
063a9dbb
AV		 187 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
188 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
189
393c1a34
PR		 190 if (host->ops->platform_reset_enter)
191 host->ops->platform_reset_enter(host, mask);
192
4e4141a5 193 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 194
e16514d8 195 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 196 host->clock = 0;
197
e16514d8
PO		 198 /* Wait max 100 ms */
199 timeout = 100;
200
201 /* hw clears the bit when it's done */
4e4141a5 202 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 203 if (timeout == 0) {
a3c76eb9 204 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 205 mmc_hostname(host->mmc), (int)mask);
206 sdhci_dumpregs(host);
207 return;
208 }
209 timeout--;
210 mdelay(1);
d129bceb 211 }
063a9dbb 212
393c1a34
PR		 213 if (host->ops->platform_reset_exit)
214 host->ops->platform_reset_exit(host, mask);
215
063a9dbb
AV		 216 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
217 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
3abc1e80
SX		 218
219 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
220 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
221 host->ops->enable_dma(host);
222 }
d129bceb
PO		 223}
224
2f4cbb3d
NP		 225static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
226
227static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 228{
2f4cbb3d
NP		 229 if (soft)
230 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
231 else
232 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 233
7260cf5e
AV		 234 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
235 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
237 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 238 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 239
240 if (soft) {
241 /* force clock reconfiguration */
242 host->clock = 0;
243 sdhci_set_ios(host->mmc, &host->mmc->ios);
244 }
7260cf5e 245}
d129bceb 246
7260cf5e
AV		 247static void sdhci_reinit(struct sdhci_host *host)
248{
2f4cbb3d 249 sdhci_init(host, 0);
b67c6b41
AL		 250 /*
251 * Retuning stuffs are affected by different cards inserted and only
252 * applicable to UHS-I cards. So reset these fields to their initial
253 * value when card is removed.
254 */
973905fe
AL		 255 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
256 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
257
b67c6b41
AL		 258 del_timer_sync(&host->tuning_timer);
259 host->flags &= ~SDHCI_NEEDS_RETUNING;
260 host->mmc->max_blk_count =
261 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
262 }
7260cf5e 263 sdhci_enable_card_detection(host);
d129bceb
PO		 264}
265
266static void sdhci_activate_led(struct sdhci_host *host)
267{
268 u8 ctrl;
269
4e4141a5 270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 271 ctrl |= SDHCI_CTRL_LED;
4e4141a5 272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 273}
274
275static void sdhci_deactivate_led(struct sdhci_host *host)
276{
277 u8 ctrl;
278
4e4141a5 279 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 280 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 281 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 282}
283
f9134319 284#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 285static void sdhci_led_control(struct led_classdev *led,
286 enum led_brightness brightness)
287{
288 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
289 unsigned long flags;
290
291 spin_lock_irqsave(&host->lock, flags);
292
66fd8ad5
AH		 293 if (host->runtime_suspended)
294 goto out;
295
2f730fec
PO		 296 if (brightness == LED_OFF)
297 sdhci_deactivate_led(host);
298 else
299 sdhci_activate_led(host);
66fd8ad5 300out:
2f730fec
PO		 301 spin_unlock_irqrestore(&host->lock, flags);
302}
303#endif
304
d129bceb
PO		 305/*****************************************************************************\
306 * *
307 * Core functions *
308 * *
309\*****************************************************************************/
310
a406f5a3 311static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 312{
7659150c
PO		 313 unsigned long flags;
314 size_t blksize, len, chunk;
7244b85b 315 u32 uninitialized_var(scratch);
7659150c 316 u8 *buf;
d129bceb 317
a406f5a3 318 DBG("PIO reading\n");
d129bceb 319
a406f5a3 320 blksize = host->data->blksz;
7659150c 321 chunk = 0;
d129bceb 322
7659150c 323 local_irq_save(flags);
d129bceb 324
a406f5a3 325 while (blksize) {
7659150c
PO		 326 if (!sg_miter_next(&host->sg_miter))
327 BUG();
d129bceb 328
7659150c 329 len = min(host->sg_miter.length, blksize);
d129bceb 330
7659150c
PO		 331 blksize -= len;
332 host->sg_miter.consumed = len;
14d836e7 333
7659150c 334 buf = host->sg_miter.addr;
d129bceb 335
7659150c
PO		 336 while (len) {
337 if (chunk == 0) {
4e4141a5 338 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 339 chunk = 4;
a406f5a3 340 }
7659150c
PO		 341
342 *buf = scratch & 0xFF;
343
344 buf++;
345 scratch >>= 8;
346 chunk--;
347 len--;
d129bceb 348 }
a406f5a3 349 }
7659150c
PO		 350
351 sg_miter_stop(&host->sg_miter);
352
353 local_irq_restore(flags);
a406f5a3 354}
d129bceb 355
a406f5a3
PO		 356static void sdhci_write_block_pio(struct sdhci_host *host)
357{
7659150c
PO		 358 unsigned long flags;
359 size_t blksize, len, chunk;
360 u32 scratch;
361 u8 *buf;
d129bceb 362
a406f5a3
PO		 363 DBG("PIO writing\n");
364
365 blksize = host->data->blksz;
7659150c
PO		 366 chunk = 0;
367 scratch = 0;
d129bceb 368
7659150c 369 local_irq_save(flags);
d129bceb 370
a406f5a3 371 while (blksize) {
7659150c
PO		 372 if (!sg_miter_next(&host->sg_miter))
373 BUG();
a406f5a3 374
7659150c
PO		 375 len = min(host->sg_miter.length, blksize);
376
377 blksize -= len;
378 host->sg_miter.consumed = len;
379
380 buf = host->sg_miter.addr;
d129bceb 381
7659150c
PO		 382 while (len) {
383 scratch |= (u32)*buf << (chunk * 8);
384
385 buf++;
386 chunk++;
387 len--;
388
389 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 390 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 391 chunk = 0;
392 scratch = 0;
d129bceb 393 }
d129bceb
PO		 394 }
395 }
7659150c
PO		 396
397 sg_miter_stop(&host->sg_miter);
398
399 local_irq_restore(flags);
a406f5a3
PO		 400}
401
402static void sdhci_transfer_pio(struct sdhci_host *host)
403{
404 u32 mask;
405
406 BUG_ON(!host->data);
407
7659150c 408 if (host->blocks == 0)
a406f5a3
PO		 409 return;
410
411 if (host->data->flags & MMC_DATA_READ)
412 mask = SDHCI_DATA_AVAILABLE;
413 else
414 mask = SDHCI_SPACE_AVAILABLE;
415
4a3cba32
PO		 416 /*
417 * Some controllers (JMicron JMB38x) mess up the buffer bits
418 * for transfers < 4 bytes. As long as it is just one block,
419 * we can ignore the bits.
420 */
421 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
422 (host->data->blocks == 1))
423 mask = ~0;
424
4e4141a5 425 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 426 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
427 udelay(100);
428
a406f5a3
PO		 429 if (host->data->flags & MMC_DATA_READ)
430 sdhci_read_block_pio(host);
431 else
432 sdhci_write_block_pio(host);
d129bceb 433
7659150c
PO		 434 host->blocks--;
435 if (host->blocks == 0)
a406f5a3 436 break;
a406f5a3 437 }
d129bceb 438
a406f5a3 439 DBG("PIO transfer complete.\n");
d129bceb
PO		 440}
441
2134a922
PO		 442static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
443{
444 local_irq_save(*flags);
482fce99 445 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 446}
447
448static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
449{
482fce99 450 kunmap_atomic(buffer);
2134a922
PO		 451 local_irq_restore(*flags);
452}
453
118cd17d
BD		 454static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
455{
9e506f35
BD		 456 __le32 *dataddr = (__le32 __force *)(desc + 4);
457 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 458
9e506f35
BD		 459 /* SDHCI specification says ADMA descriptors should be 4 byte
460 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 461
9e506f35
BD		 462 cmdlen[0] = cpu_to_le16(cmd);
463 cmdlen[1] = cpu_to_le16(len);
464
465 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 466}
467
8f1934ce 468static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 469 struct mmc_data *data)
470{
471 int direction;
472
473 u8 *desc;
474 u8 *align;
475 dma_addr_t addr;
476 dma_addr_t align_addr;
477 int len, offset;
478
479 struct scatterlist *sg;
480 int i;
481 char *buffer;
482 unsigned long flags;
483
484 /*
485 * The spec does not specify endianness of descriptor table.
486 * We currently guess that it is LE.
487 */
488
489 if (data->flags & MMC_DATA_READ)
490 direction = DMA_FROM_DEVICE;
491 else
492 direction = DMA_TO_DEVICE;
493
494 /*
495 * The ADMA descriptor table is mapped further down as we
496 * need to fill it with data first.
497 */
498
499 host->align_addr = dma_map_single(mmc_dev(host->mmc),
500 host->align_buffer, 128 * 4, direction);
8d8bb39b 501 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 502 goto fail;
2134a922
PO		 503 BUG_ON(host->align_addr & 0x3);
504
505 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
506 data->sg, data->sg_len, direction);
8f1934ce
PO		 507 if (host->sg_count == 0)
508 goto unmap_align;
2134a922
PO		 509
510 desc = host->adma_desc;
511 align = host->align_buffer;
512
513 align_addr = host->align_addr;
514
515 for_each_sg(data->sg, sg, host->sg_count, i) {
516 addr = sg_dma_address(sg);
517 len = sg_dma_len(sg);
518
519 /*
520 * The SDHCI specification states that ADMA
521 * addresses must be 32-bit aligned. If they
522 * aren't, then we use a bounce buffer for
523 * the (up to three) bytes that screw up the
524 * alignment.
525 */
526 offset = (4 - (addr & 0x3)) & 0x3;
527 if (offset) {
528 if (data->flags & MMC_DATA_WRITE) {
529 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 530 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 531 memcpy(align, buffer, offset);
532 sdhci_kunmap_atomic(buffer, &flags);
533 }
534
118cd17d
BD		 535 /* tran, valid */
536 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 537
538 BUG_ON(offset > 65536);
539
2134a922
PO		 540 align += 4;
541 align_addr += 4;
542
543 desc += 8;
544
545 addr += offset;
546 len -= offset;
547 }
548
2134a922
PO		 549 BUG_ON(len > 65536);
550
118cd17d
BD		 551 /* tran, valid */
552 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 553 desc += 8;
554
555 /*
556 * If this triggers then we have a calculation bug
557 * somewhere. :/
558 */
559 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
560 }
561
70764a90
TA		 562 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
563 /*
564 * Mark the last descriptor as the terminating descriptor
565 */
566 if (desc != host->adma_desc) {
567 desc -= 8;
568 desc[0] |= 0x2; /* end */
569 }
570 } else {
571 /*
572 * Add a terminating entry.
573 */
2134a922 574
70764a90
TA		 575 /* nop, end, valid */
576 sdhci_set_adma_desc(desc, 0, 0, 0x3);
577 }
2134a922
PO		 578
579 /*
580 * Resync align buffer as we might have changed it.
581 */
582 if (data->flags & MMC_DATA_WRITE) {
583 dma_sync_single_for_device(mmc_dev(host->mmc),
584 host->align_addr, 128 * 4, direction);
585 }
586
587 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
588 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 589 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 590 goto unmap_entries;
2134a922 591 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 592
593 return 0;
594
595unmap_entries:
596 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
597 data->sg_len, direction);
598unmap_align:
599 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
600 128 * 4, direction);
601fail:
602 return -EINVAL;
2134a922
PO		 603}
604
605static void sdhci_adma_table_post(struct sdhci_host *host,
606 struct mmc_data *data)
607{
608 int direction;
609
610 struct scatterlist *sg;
611 int i, size;
612 u8 *align;
613 char *buffer;
614 unsigned long flags;
615
616 if (data->flags & MMC_DATA_READ)
617 direction = DMA_FROM_DEVICE;
618 else
619 direction = DMA_TO_DEVICE;
620
621 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
622 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
623
624 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
625 128 * 4, direction);
626
627 if (data->flags & MMC_DATA_READ) {
628 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
629 data->sg_len, direction);
630
631 align = host->align_buffer;
632
633 for_each_sg(data->sg, sg, host->sg_count, i) {
634 if (sg_dma_address(sg) & 0x3) {
635 size = 4 - (sg_dma_address(sg) & 0x3);
636
637 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 638 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 639 memcpy(buffer, align, size);
640 sdhci_kunmap_atomic(buffer, &flags);
641
642 align += 4;
643 }
644 }
645 }
646
647 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
648 data->sg_len, direction);
649}
650
a3c7778f 651static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 652{
1c8cde92 653 u8 count;
a3c7778f 654 struct mmc_data *data = cmd->data;
1c8cde92 655 unsigned target_timeout, current_timeout;
d129bceb 656
ee53ab5d
PO		 657 /*
658 * If the host controller provides us with an incorrect timeout
659 * value, just skip the check and use 0xE. The hardware may take
660 * longer to time out, but that's much better than having a too-short
661 * timeout value.
662 */
11a2f1b7 663 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 664 return 0xE;
e538fbe8 665
a3c7778f
AW		 666 /* Unspecified timeout, assume max */
667 if (!data && !cmd->cmd_timeout_ms)
668 return 0xE;
d129bceb 669
a3c7778f
AW		 670 /* timeout in us */
671 if (!data)
672 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 673 else {
674 target_timeout = data->timeout_ns / 1000;
675 if (host->clock)
676 target_timeout += data->timeout_clks / host->clock;
677 }
81b39802 678
1c8cde92
PO		 679 /*
680 * Figure out needed cycles.
681 * We do this in steps in order to fit inside a 32 bit int.
682 * The first step is the minimum timeout, which will have a
683 * minimum resolution of 6 bits:
684 * (1) 2^13*1000 > 2^22,
685 * (2) host->timeout_clk < 2^16
686 * =>
687 * (1) / (2) > 2^6
688 */
689 count = 0;
690 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
691 while (current_timeout < target_timeout) {
692 count++;
693 current_timeout <<= 1;
694 if (count >= 0xF)
695 break;
696 }
697
698 if (count >= 0xF) {
09eeff52
CB		 699 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
700 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 701 count = 0xE;
702 }
703
ee53ab5d
PO		 704 return count;
705}
706
6aa943ab
AV		 707static void sdhci_set_transfer_irqs(struct sdhci_host *host)
708{
709 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
710 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
711
712 if (host->flags & SDHCI_REQ_USE_DMA)
713 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
714 else
715 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
716}
717
a3c7778f 718static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 719{
720 u8 count;
2134a922 721 u8 ctrl;
a3c7778f 722 struct mmc_data *data = cmd->data;
8f1934ce 723 int ret;
ee53ab5d
PO		 724
725 WARN_ON(host->data);
726
a3c7778f
AW		 727 if (data || (cmd->flags & MMC_RSP_BUSY)) {
728 count = sdhci_calc_timeout(host, cmd);
729 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
730 }
731
732 if (!data)
ee53ab5d
PO		 733 return;
734
735 /* Sanity checks */
736 BUG_ON(data->blksz * data->blocks > 524288);
737 BUG_ON(data->blksz > host->mmc->max_blk_size);
738 BUG_ON(data->blocks > 65535);
739
740 host->data = data;
741 host->data_early = 0;
f6a03cbf 742 host->data->bytes_xfered = 0;
ee53ab5d 743
a13abc7b 744 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 745 host->flags |= SDHCI_REQ_USE_DMA;
746
2134a922
PO		 747 /*
748 * FIXME: This doesn't account for merging when mapping the
749 * scatterlist.
750 */
751 if (host->flags & SDHCI_REQ_USE_DMA) {
752 int broken, i;
753 struct scatterlist *sg;
754
755 broken = 0;
756 if (host->flags & SDHCI_USE_ADMA) {
757 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
758 broken = 1;
759 } else {
760 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
761 broken = 1;
762 }
763
764 if (unlikely(broken)) {
765 for_each_sg(data->sg, sg, data->sg_len, i) {
766 if (sg->length & 0x3) {
767 DBG("Reverting to PIO because of "
768 "transfer size (%d)\n",
769 sg->length);
770 host->flags &= ~SDHCI_REQ_USE_DMA;
771 break;
772 }
773 }
774 }
c9fddbc4
PO		 775 }
776
777 /*
778 * The assumption here being that alignment is the same after
779 * translation to device address space.
780 */
2134a922
PO		 781 if (host->flags & SDHCI_REQ_USE_DMA) {
782 int broken, i;
783 struct scatterlist *sg;
784
785 broken = 0;
786 if (host->flags & SDHCI_USE_ADMA) {
787 /*
788 * As we use 3 byte chunks to work around
789 * alignment problems, we need to check this
790 * quirk.
791 */
792 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
793 broken = 1;
794 } else {
795 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
796 broken = 1;
797 }
798
799 if (unlikely(broken)) {
800 for_each_sg(data->sg, sg, data->sg_len, i) {
801 if (sg->offset & 0x3) {
802 DBG("Reverting to PIO because of "
803 "bad alignment\n");
804 host->flags &= ~SDHCI_REQ_USE_DMA;
805 break;
806 }
807 }
808 }
809 }
810
8f1934ce
PO		 811 if (host->flags & SDHCI_REQ_USE_DMA) {
812 if (host->flags & SDHCI_USE_ADMA) {
813 ret = sdhci_adma_table_pre(host, data);
814 if (ret) {
815 /*
816 * This only happens when someone fed
817 * us an invalid request.
818 */
819 WARN_ON(1);
ebd6d357 820 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 821 } else {
4e4141a5
AV		 822 sdhci_writel(host, host->adma_addr,
823 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 824 }
825 } else {
c8b3e02e 826 int sg_cnt;
8f1934ce 827
c8b3e02e 828 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 829 data->sg, data->sg_len,
830 (data->flags & MMC_DATA_READ) ?
831 DMA_FROM_DEVICE :
832 DMA_TO_DEVICE);
c8b3e02e 833 if (sg_cnt == 0) {
8f1934ce
PO		 834 /*
835 * This only happens when someone fed
836 * us an invalid request.
837 */
838 WARN_ON(1);
ebd6d357 839 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 840 } else {
719a61b4 841 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 842 sdhci_writel(host, sg_dma_address(data->sg),
843 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 844 }
845 }
846 }
847
2134a922
PO		 848 /*
849 * Always adjust the DMA selection as some controllers
850 * (e.g. JMicron) can't do PIO properly when the selection
851 * is ADMA.
852 */
853 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 854 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 855 ctrl &= ~SDHCI_CTRL_DMA_MASK;
856 if ((host->flags & SDHCI_REQ_USE_DMA) &&
857 (host->flags & SDHCI_USE_ADMA))
858 ctrl |= SDHCI_CTRL_ADMA32;
859 else
860 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 861 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 862 }
863
8f1934ce 864 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 865 int flags;
866
867 flags = SG_MITER_ATOMIC;
868 if (host->data->flags & MMC_DATA_READ)
869 flags |= SG_MITER_TO_SG;
870 else
871 flags |= SG_MITER_FROM_SG;
872 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 873 host->blocks = data->blocks;
d129bceb 874 }
c7fa9963 875
6aa943ab
AV		 876 sdhci_set_transfer_irqs(host);
877
f6a03cbf
MV		 878 /* Set the DMA boundary value and block size */
879 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
880 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 881 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 882}
883
884static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 885 struct mmc_command *cmd)
c7fa9963
PO		 886{
887 u16 mode;
e89d456f 888 struct mmc_data *data = cmd->data;
c7fa9963 889
c7fa9963
PO		 890 if (data == NULL)
891 return;
892
e538fbe8
PO		 893 WARN_ON(!host->data);
894
c7fa9963 895 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 896 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
897 mode |= SDHCI_TRNS_MULTI;
898 /*
899 * If we are sending CMD23, CMD12 never gets sent
900 * on successful completion (so no Auto-CMD12).
901 */
902 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
903 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 904 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
905 mode |= SDHCI_TRNS_AUTO_CMD23;
906 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
907 }
c4512f79 908 }
8edf6371 909
c7fa9963
PO		 910 if (data->flags & MMC_DATA_READ)
911 mode |= SDHCI_TRNS_READ;
c9fddbc4 912 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 913 mode |= SDHCI_TRNS_DMA;
914
4e4141a5 915 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 916}
917
918static void sdhci_finish_data(struct sdhci_host *host)
919{
920 struct mmc_data *data;
d129bceb
PO		 921
922 BUG_ON(!host->data);
923
924 data = host->data;
925 host->data = NULL;
926
c9fddbc4 927 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 928 if (host->flags & SDHCI_USE_ADMA)
929 sdhci_adma_table_post(host, data);
930 else {
931 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
932 data->sg_len, (data->flags & MMC_DATA_READ) ?
933 DMA_FROM_DEVICE : DMA_TO_DEVICE);
934 }
d129bceb
PO		 935 }
936
937 /*
c9b74c5b
PO		 938 * The specification states that the block count register must
939 * be updated, but it does not specify at what point in the
940 * data flow. That makes the register entirely useless to read
941 * back so we have to assume that nothing made it to the card
942 * in the event of an error.
d129bceb 943 */
c9b74c5b
PO		 944 if (data->error)
945 data->bytes_xfered = 0;
d129bceb 946 else
c9b74c5b 947 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 948
e89d456f
AW		 949 /*
950 * Need to send CMD12 if -
951 * a) open-ended multiblock transfer (no CMD23)
952 * b) error in multiblock transfer
953 */
954 if (data->stop &&
955 (data->error ||
956 !host->mrq->sbc)) {
957
d129bceb
PO		 958 /*
959 * The controller needs a reset of internal state machines
960 * upon error conditions.
961 */
17b0429d 962 if (data->error) {
d129bceb
PO		 963 sdhci_reset(host, SDHCI_RESET_CMD);
964 sdhci_reset(host, SDHCI_RESET_DATA);
965 }
966
967 sdhci_send_command(host, data->stop);
968 } else
969 tasklet_schedule(&host->finish_tasklet);
970}
971
972static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
973{
974 int flags;
fd2208d7 975 u32 mask;
7cb2c76f 976 unsigned long timeout;
d129bceb
PO		 977
978 WARN_ON(host->cmd);
979
d129bceb 980 /* Wait max 10 ms */
7cb2c76f 981 timeout = 10;
fd2208d7
PO		 982
983 mask = SDHCI_CMD_INHIBIT;
984 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
985 mask |= SDHCI_DATA_INHIBIT;
986
987 /* We shouldn't wait for data inihibit for stop commands, even
988 though they might use busy signaling */
989 if (host->mrq->data && (cmd == host->mrq->data->stop))
990 mask &= ~SDHCI_DATA_INHIBIT;
991
4e4141a5 992 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 993 if (timeout == 0) {
a3c76eb9 994 pr_err("%s: Controller never released "
acf1da45 995 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 996 sdhci_dumpregs(host);
17b0429d 997 cmd->error = -EIO;
d129bceb
PO		 998 tasklet_schedule(&host->finish_tasklet);
999 return;
1000 }
7cb2c76f
PO		 1001 timeout--;
1002 mdelay(1);
1003 }
d129bceb
PO		 1004
1005 mod_timer(&host->timer, jiffies + 10 * HZ);
1006
1007 host->cmd = cmd;
1008
a3c7778f 1009 sdhci_prepare_data(host, cmd);
d129bceb 1010
4e4141a5 1011 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1012
e89d456f 1013 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1014
d129bceb 1015 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1016 pr_err("%s: Unsupported response type!\n",
d129bceb 1017 mmc_hostname(host->mmc));
17b0429d 1018 cmd->error = -EINVAL;
d129bceb
PO		 1019 tasklet_schedule(&host->finish_tasklet);
1020 return;
1021 }
1022
1023 if (!(cmd->flags & MMC_RSP_PRESENT))
1024 flags = SDHCI_CMD_RESP_NONE;
1025 else if (cmd->flags & MMC_RSP_136)
1026 flags = SDHCI_CMD_RESP_LONG;
1027 else if (cmd->flags & MMC_RSP_BUSY)
1028 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1029 else
1030 flags = SDHCI_CMD_RESP_SHORT;
1031
1032 if (cmd->flags & MMC_RSP_CRC)
1033 flags |= SDHCI_CMD_CRC;
1034 if (cmd->flags & MMC_RSP_OPCODE)
1035 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1036
1037 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1038 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1039 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1040 flags |= SDHCI_CMD_DATA;
1041
4e4141a5 1042 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1043}
1044
1045static void sdhci_finish_command(struct sdhci_host *host)
1046{
1047 int i;
1048
1049 BUG_ON(host->cmd == NULL);
1050
1051 if (host->cmd->flags & MMC_RSP_PRESENT) {
1052 if (host->cmd->flags & MMC_RSP_136) {
1053 /* CRC is stripped so we need to do some shifting. */
1054 for (i = 0;i < 4;i++) {
4e4141a5 1055 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1056 SDHCI_RESPONSE + (3-i)*4) << 8;
1057 if (i != 3)
1058 host->cmd->resp[i] |=
4e4141a5 1059 sdhci_readb(host,
d129bceb
PO		 1060 SDHCI_RESPONSE + (3-i)*4-1);
1061 }
1062 } else {
4e4141a5 1063 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1064 }
1065 }
1066
17b0429d 1067 host->cmd->error = 0;
d129bceb 1068
e89d456f
AW		 1069 /* Finished CMD23, now send actual command. */
1070 if (host->cmd == host->mrq->sbc) {
1071 host->cmd = NULL;
1072 sdhci_send_command(host, host->mrq->cmd);
1073 } else {
e538fbe8 1074
e89d456f
AW		 1075 /* Processed actual command. */
1076 if (host->data && host->data_early)
1077 sdhci_finish_data(host);
d129bceb 1078
e89d456f
AW		 1079 if (!host->cmd->data)
1080 tasklet_schedule(&host->finish_tasklet);
1081
1082 host->cmd = NULL;
1083 }
d129bceb
PO		 1084}
1085
52983382
KL		 1086static u16 sdhci_get_preset_value(struct sdhci_host *host)
1087{
1088 u16 ctrl, preset = 0;
1089
1090 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1091
1092 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1093 case SDHCI_CTRL_UHS_SDR12:
1094 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1095 break;
1096 case SDHCI_CTRL_UHS_SDR25:
1097 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1098 break;
1099 case SDHCI_CTRL_UHS_SDR50:
1100 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1101 break;
1102 case SDHCI_CTRL_UHS_SDR104:
1103 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1104 break;
1105 case SDHCI_CTRL_UHS_DDR50:
1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1107 break;
1108 default:
1109 pr_warn("%s: Invalid UHS-I mode selected\n",
1110 mmc_hostname(host->mmc));
1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1112 break;
1113 }
1114 return preset;
1115}
1116
d129bceb
PO		 1117static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1118{
c3ed3877 1119 int div = 0; /* Initialized for compiler warning */
df16219f 1120 int real_div = div, clk_mul = 1;
c3ed3877 1121 u16 clk = 0;
7cb2c76f 1122 unsigned long timeout;
d129bceb 1123
30832ab5 1124 if (clock && clock == host->clock)
d129bceb
PO		 1125 return;
1126
df16219f
GC		 1127 host->mmc->actual_clock = 0;
1128
8114634c
AV		 1129 if (host->ops->set_clock) {
1130 host->ops->set_clock(host, clock);
1131 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1132 return;
1133 }
1134
4e4141a5 1135 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1136
1137 if (clock == 0)
1138 goto out;
1139
85105c53 1140 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1141 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1142 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1143 u16 pre_val;
1144
1145 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1146 pre_val = sdhci_get_preset_value(host);
1147 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1148 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1149 if (host->clk_mul &&
1150 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1151 clk = SDHCI_PROG_CLOCK_MODE;
1152 real_div = div + 1;
1153 clk_mul = host->clk_mul;
1154 } else {
1155 real_div = max_t(int, 1, div << 1);
1156 }
1157 goto clock_set;
1158 }
1159
c3ed3877
AN		 1160 /*
1161 * Check if the Host Controller supports Programmable Clock
1162 * Mode.
1163 */
1164 if (host->clk_mul) {
52983382
KL		 1165 for (div = 1; div <= 1024; div++) {
1166 if ((host->max_clk * host->clk_mul / div)
1167 <= clock)
1168 break;
1169 }
c3ed3877 1170 /*
52983382
KL		 1171 * Set Programmable Clock Mode in the Clock
1172 * Control register.
c3ed3877 1173 */
52983382
KL		 1174 clk = SDHCI_PROG_CLOCK_MODE;
1175 real_div = div;
1176 clk_mul = host->clk_mul;
1177 div--;
c3ed3877
AN		 1178 } else {
1179 /* Version 3.00 divisors must be a multiple of 2. */
1180 if (host->max_clk <= clock)
1181 div = 1;
1182 else {
1183 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1184 div += 2) {
1185 if ((host->max_clk / div) <= clock)
1186 break;
1187 }
85105c53 1188 }
df16219f 1189 real_div = div;
c3ed3877 1190 div >>= 1;
85105c53
ZG		 1191 }
1192 } else {
1193 /* Version 2.00 divisors must be a power of 2. */
0397526d 1194 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1195 if ((host->max_clk / div) <= clock)
1196 break;
1197 }
df16219f 1198 real_div = div;
c3ed3877 1199 div >>= 1;
d129bceb 1200 }
d129bceb 1201
52983382 1202clock_set:
df16219f
GC		 1203 if (real_div)
1204 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1205
c3ed3877 1206 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1207 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1208 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1209 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1210 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1211
27f6cb16
CB		 1212 /* Wait max 20 ms */
1213 timeout = 20;
4e4141a5 1214 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1215 & SDHCI_CLOCK_INT_STABLE)) {
1216 if (timeout == 0) {
a3c76eb9 1217 pr_err("%s: Internal clock never "
acf1da45 1218 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1219 sdhci_dumpregs(host);
1220 return;
1221 }
7cb2c76f
PO		 1222 timeout--;
1223 mdelay(1);
1224 }
d129bceb
PO		 1225
1226 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1227 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1228
1229out:
1230 host->clock = clock;
1231}
1232
8213af3b
AS		 1233static inline void sdhci_update_clock(struct sdhci_host *host)
1234{
1235 unsigned int clock;
1236
1237 clock = host->clock;
1238 host->clock = 0;
1239 sdhci_set_clock(host, clock);
1240}
1241
ceb6143b 1242static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1243{
8364248a 1244 u8 pwr = 0;
146ad66e 1245
8364248a 1246 if (power != (unsigned short)-1) {
ae628903
PO		 1247 switch (1 << power) {
1248 case MMC_VDD_165_195:
1249 pwr = SDHCI_POWER_180;
1250 break;
1251 case MMC_VDD_29_30:
1252 case MMC_VDD_30_31:
1253 pwr = SDHCI_POWER_300;
1254 break;
1255 case MMC_VDD_32_33:
1256 case MMC_VDD_33_34:
1257 pwr = SDHCI_POWER_330;
1258 break;
1259 default:
1260 BUG();
1261 }
1262 }
1263
1264 if (host->pwr == pwr)
ceb6143b 1265 return -1;
146ad66e 1266
ae628903
PO		 1267 host->pwr = pwr;
1268
1269 if (pwr == 0) {
4e4141a5 1270 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ceb6143b 1271 return 0;
9e9dc5f2
DS		 1272 }
1273
1274 /*
1275 * Spec says that we should clear the power reg before setting
1276 * a new value. Some controllers don't seem to like this though.
1277 */
b8c86fc5 1278 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1279 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1280
e08c1694 1281 /*
c71f6512 1282 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1283 * and set turn on power at the same time, so set the voltage first.
1284 */
11a2f1b7 1285 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1286 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1287
ae628903 1288 pwr |= SDHCI_POWER_ON;
146ad66e 1289
ae628903 1290 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1291
1292 /*
1293 * Some controllers need an extra 10ms delay of 10ms before they
1294 * can apply clock after applying power
1295 */
11a2f1b7 1296 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1297 mdelay(10);
ceb6143b
AH		 1298
1299 return power;
146ad66e
PO		 1300}
1301
d129bceb
PO		 1302/*****************************************************************************\
1303 * *
1304 * MMC callbacks *
1305 * *
1306\*****************************************************************************/
1307
1308static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1309{
1310 struct sdhci_host *host;
505a8680 1311 int present;
d129bceb 1312 unsigned long flags;
473b095a 1313 u32 tuning_opcode;
d129bceb
PO		 1314
1315 host = mmc_priv(mmc);
1316
66fd8ad5
AH		 1317 sdhci_runtime_pm_get(host);
1318
d129bceb
PO		 1319 spin_lock_irqsave(&host->lock, flags);
1320
1321 WARN_ON(host->mrq != NULL);
1322
f9134319 1323#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1324 sdhci_activate_led(host);
2f730fec 1325#endif
e89d456f
AW		 1326
1327 /*
1328 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1329 * requests if Auto-CMD12 is enabled.
1330 */
1331 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1332 if (mrq->stop) {
1333 mrq->data->stop = NULL;
1334 mrq->stop = NULL;
1335 }
1336 }
d129bceb
PO		 1337
1338 host->mrq = mrq;
1339
505a8680
SG		 1340 /*
1341 * Firstly check card presence from cd-gpio. The return could
1342 * be one of the following possibilities:
1343 * negative: cd-gpio is not available
1344 * zero: cd-gpio is used, and card is removed
1345 * one: cd-gpio is used, and card is present
1346 */
1347 present = mmc_gpio_get_cd(host->mmc);
1348 if (present < 0) {
1349 /* If polling, assume that the card is always present. */
1350 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1351 present = 1;
1352 else
1353 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1354 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1355 }
1356
68d1fb7e 1357 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1358 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1359 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1360 } else {
1361 u32 present_state;
1362
1363 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1364 /*
1365 * Check if the re-tuning timer has already expired and there
1366 * is no on-going data transfer. If so, we need to execute
1367 * tuning procedure before sending command.
1368 */
1369 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1370 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1371 if (mmc->card) {
1372 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1373 tuning_opcode =
1374 mmc->card->type == MMC_TYPE_MMC ?
1375 MMC_SEND_TUNING_BLOCK_HS200 :
1376 MMC_SEND_TUNING_BLOCK;
1377 spin_unlock_irqrestore(&host->lock, flags);
1378 sdhci_execute_tuning(mmc, tuning_opcode);
1379 spin_lock_irqsave(&host->lock, flags);
1380
1381 /* Restore original mmc_request structure */
1382 host->mrq = mrq;
1383 }
cf2b5eea
AN		 1384 }
1385
8edf6371 1386 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1387 sdhci_send_command(host, mrq->sbc);
1388 else
1389 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1390 }
d129bceb 1391
5f25a66f 1392 mmiowb();
d129bceb
PO		 1393 spin_unlock_irqrestore(&host->lock, flags);
1394}
1395
66fd8ad5 1396static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1397{
d129bceb 1398 unsigned long flags;
ceb6143b 1399 int vdd_bit = -1;
d129bceb
PO		 1400 u8 ctrl;
1401
d129bceb
PO		 1402 spin_lock_irqsave(&host->lock, flags);
1403
ceb6143b
AH		 1404 if (host->flags & SDHCI_DEVICE_DEAD) {
1405 spin_unlock_irqrestore(&host->lock, flags);
1406 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1407 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1408 return;
1409 }
1e72859e 1410
d129bceb
PO		 1411 /*
1412 * Reset the chip on each power off.
1413 * Should clear out any weird states.
1414 */
1415 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1416 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1417 sdhci_reinit(host);
d129bceb
PO		 1418 }
1419
52983382
KL		 1420 if (host->version >= SDHCI_SPEC_300 &&
1421 (ios->power_mode == MMC_POWER_UP))
1422 sdhci_enable_preset_value(host, false);
1423
d129bceb
PO		 1424 sdhci_set_clock(host, ios->clock);
1425
1426 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1427 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1428 else
ceb6143b
AH		 1429 vdd_bit = sdhci_set_power(host, ios->vdd);
1430
1431 if (host->vmmc && vdd_bit != -1) {
1432 spin_unlock_irqrestore(&host->lock, flags);
1433 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1434 spin_lock_irqsave(&host->lock, flags);
1435 }
d129bceb 1436
643a81ff
PR		 1437 if (host->ops->platform_send_init_74_clocks)
1438 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1439
15ec4461
PR		 1440 /*
1441 * If your platform has 8-bit width support but is not a v3 controller,
1442 * or if it requires special setup code, you should implement that in
7bc088d3 1443 * platform_bus_width().
15ec4461 1444 */
7bc088d3
SH		 1445 if (host->ops->platform_bus_width) {
1446 host->ops->platform_bus_width(host, ios->bus_width);
1447 } else {
15ec4461
PR		 1448 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1449 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1450 ctrl &= ~SDHCI_CTRL_4BITBUS;
1451 if (host->version >= SDHCI_SPEC_300)
1452 ctrl |= SDHCI_CTRL_8BITBUS;
1453 } else {
1454 if (host->version >= SDHCI_SPEC_300)
1455 ctrl &= ~SDHCI_CTRL_8BITBUS;
1456 if (ios->bus_width == MMC_BUS_WIDTH_4)
1457 ctrl |= SDHCI_CTRL_4BITBUS;
1458 else
1459 ctrl &= ~SDHCI_CTRL_4BITBUS;
1460 }
1461 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1462 }
ae6d6c92 1463
15ec4461 1464 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1465
3ab9c8da
PR		 1466 if ((ios->timing == MMC_TIMING_SD_HS ||
1467 ios->timing == MMC_TIMING_MMC_HS)
1468 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1469 ctrl |= SDHCI_CTRL_HISPD;
1470 else
1471 ctrl &= ~SDHCI_CTRL_HISPD;
1472
d6d50a15 1473 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1474 u16 clk, ctrl_2;
49c468fc
AN		 1475
1476 /* In case of UHS-I modes, set High Speed Enable */
069c9f14
G		 1477 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1478 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1479 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1480 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1481 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1482 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1483
1484 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1485 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1486 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1487 /*
1488 * We only need to set Driver Strength if the
1489 * preset value enable is not set.
1490 */
1491 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1492 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1493 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1494 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1495 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1496
1497 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1498 } else {
1499 /*
1500 * According to SDHC Spec v3.00, if the Preset Value
1501 * Enable in the Host Control 2 register is set, we
1502 * need to reset SD Clock Enable before changing High
1503 * Speed Enable to avoid generating clock gliches.
1504 */
758535c4
AN		 1505
1506 /* Reset SD Clock Enable */
1507 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1508 clk &= ~SDHCI_CLOCK_CARD_EN;
1509 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1510
1511 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1512
1513 /* Re-enable SD Clock */
8213af3b 1514 sdhci_update_clock(host);
d6d50a15 1515 }
49c468fc 1516
49c468fc
AN		 1517
1518 /* Reset SD Clock Enable */
1519 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1520 clk &= ~SDHCI_CLOCK_CARD_EN;
1521 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1522
6322cdd0
PR		 1523 if (host->ops->set_uhs_signaling)
1524 host->ops->set_uhs_signaling(host, ios->timing);
1525 else {
1526 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1527 /* Select Bus Speed Mode for host */
1528 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
069c9f14
G		 1529 if (ios->timing == MMC_TIMING_MMC_HS200)
1530 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1531 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1532 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1533 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1534 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1535 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1536 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1537 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1538 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1539 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1540 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1541 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1542 }
49c468fc 1543
52983382
KL		 1544 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1545 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1546 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1547 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1548 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1549 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1550 u16 preset;
1551
1552 sdhci_enable_preset_value(host, true);
1553 preset = sdhci_get_preset_value(host);
1554 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1555 >> SDHCI_PRESET_DRV_SHIFT;
1556 }
1557
49c468fc 1558 /* Re-enable SD Clock */
8213af3b 1559 sdhci_update_clock(host);
758535c4
AN		 1560 } else
1561 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1562
b8352260
LD		 1563 /*
1564 * Some (ENE) controllers go apeshit on some ios operation,
1565 * signalling timeout and CRC errors even on CMD0. Resetting
1566 * it on each ios seems to solve the problem.
1567 */
b8c86fc5 1568 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1569 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1570
5f25a66f 1571 mmiowb();
d129bceb
PO		 1572 spin_unlock_irqrestore(&host->lock, flags);
1573}
1574
66fd8ad5
AH		 1575static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1576{
1577 struct sdhci_host *host = mmc_priv(mmc);
1578
1579 sdhci_runtime_pm_get(host);
1580 sdhci_do_set_ios(host, ios);
1581 sdhci_runtime_pm_put(host);
1582}
1583
94144a46
KL		 1584static int sdhci_do_get_cd(struct sdhci_host *host)
1585{
1586 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1587
1588 if (host->flags & SDHCI_DEVICE_DEAD)
1589 return 0;
1590
1591 /* If polling/nonremovable, assume that the card is always present. */
1592 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1593 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1594 return 1;
1595
1596 /* Try slot gpio detect */
1597 if (!IS_ERR_VALUE(gpio_cd))
1598 return !!gpio_cd;
1599
1600 /* Host native card detect */
1601 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1602}
1603
1604static int sdhci_get_cd(struct mmc_host *mmc)
1605{
1606 struct sdhci_host *host = mmc_priv(mmc);
1607 int ret;
1608
1609 sdhci_runtime_pm_get(host);
1610 ret = sdhci_do_get_cd(host);
1611 sdhci_runtime_pm_put(host);
1612 return ret;
1613}
1614
66fd8ad5 1615static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1616{
d129bceb 1617 unsigned long flags;
2dfb579c 1618 int is_readonly;
d129bceb 1619
d129bceb
PO		 1620 spin_lock_irqsave(&host->lock, flags);
1621
1e72859e 1622 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1623 is_readonly = 0;
1624 else if (host->ops->get_ro)
1625 is_readonly = host->ops->get_ro(host);
1e72859e 1626 else
2dfb579c
WS		 1627 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1628 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1629
1630 spin_unlock_irqrestore(&host->lock, flags);
1631
2dfb579c
WS		 1632 /* This quirk needs to be replaced by a callback-function later */
1633 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1634 !is_readonly : is_readonly;
d129bceb
PO		 1635}
1636
82b0e23a
TI		 1637#define SAMPLE_COUNT 5
1638
66fd8ad5 1639static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1640{
82b0e23a
TI		 1641 int i, ro_count;
1642
82b0e23a 1643 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1644 return sdhci_check_ro(host);
82b0e23a
TI		 1645
1646 ro_count = 0;
1647 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1648 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1649 if (++ro_count > SAMPLE_COUNT / 2)
1650 return 1;
1651 }
1652 msleep(30);
1653 }
1654 return 0;
1655}
1656
20758b66
AH		 1657static void sdhci_hw_reset(struct mmc_host *mmc)
1658{
1659 struct sdhci_host *host = mmc_priv(mmc);
1660
1661 if (host->ops && host->ops->hw_reset)
1662 host->ops->hw_reset(host);
1663}
1664
66fd8ad5 1665static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1666{
66fd8ad5
AH		 1667 struct sdhci_host *host = mmc_priv(mmc);
1668 int ret;
f75979b7 1669
66fd8ad5
AH		 1670 sdhci_runtime_pm_get(host);
1671 ret = sdhci_do_get_ro(host);
1672 sdhci_runtime_pm_put(host);
1673 return ret;
1674}
f75979b7 1675
66fd8ad5
AH		 1676static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1677{
1e72859e
PO		 1678 if (host->flags & SDHCI_DEVICE_DEAD)
1679 goto out;
1680
66fd8ad5
AH		 1681 if (enable)
1682 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1683 else
1684 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1685
1686 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1687 if (host->runtime_suspended)
1688 goto out;
1689
f75979b7 1690 if (enable)
7260cf5e
AV		 1691 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1692 else
1693 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1694out:
f75979b7 1695 mmiowb();
66fd8ad5
AH		 1696}
1697
1698static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1699{
1700 struct sdhci_host *host = mmc_priv(mmc);
1701 unsigned long flags;
f75979b7 1702
66fd8ad5
AH		 1703 spin_lock_irqsave(&host->lock, flags);
1704 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1705 spin_unlock_irqrestore(&host->lock, flags);
1706}
1707
20b92a30 1708static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1709 struct mmc_ios *ios)
f2119df6 1710{
20b92a30 1711 u16 ctrl;
6231f3de 1712 int ret;
f2119df6 1713
20b92a30
KL		 1714 /*
1715 * Signal Voltage Switching is only applicable for Host Controllers
1716 * v3.00 and above.
1717 */
1718 if (host->version < SDHCI_SPEC_300)
1719 return 0;
6231f3de 1720
f2119df6 1721 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1722
21f5998f 1723 switch (ios->signal_voltage) {
20b92a30
KL		 1724 case MMC_SIGNAL_VOLTAGE_330:
1725 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1726 ctrl &= ~SDHCI_CTRL_VDD_180;
1727 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1728
20b92a30
KL		 1729 if (host->vqmmc) {
1730 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1731 if (ret) {
1732 pr_warning("%s: Switching to 3.3V signalling voltage "
1733 " failed\n", mmc_hostname(host->mmc));
1734 return -EIO;
1735 }
1736 }
1737 /* Wait for 5ms */
1738 usleep_range(5000, 5500);
f2119df6 1739
20b92a30
KL		 1740 /* 3.3V regulator output should be stable within 5 ms */
1741 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1742 if (!(ctrl & SDHCI_CTRL_VDD_180))
1743 return 0;
6231f3de 1744
20b92a30
KL		 1745 pr_warning("%s: 3.3V regulator output did not became stable\n",
1746 mmc_hostname(host->mmc));
1747
1748 return -EAGAIN;
1749 case MMC_SIGNAL_VOLTAGE_180:
1750 if (host->vqmmc) {
1751 ret = regulator_set_voltage(host->vqmmc,
1752 1700000, 1950000);
1753 if (ret) {
1754 pr_warning("%s: Switching to 1.8V signalling voltage "
1755 " failed\n", mmc_hostname(host->mmc));
1756 return -EIO;
1757 }
1758 }
6231f3de 1759
6231f3de
PR		 1760 /*
1761 * Enable 1.8V Signal Enable in the Host Control2
1762 * register
1763 */
20b92a30
KL		 1764 ctrl |= SDHCI_CTRL_VDD_180;
1765 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1766
20b92a30
KL		 1767 /* Wait for 5ms */
1768 usleep_range(5000, 5500);
f2119df6 1769
20b92a30
KL		 1770 /* 1.8V regulator output should be stable within 5 ms */
1771 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1772 if (ctrl & SDHCI_CTRL_VDD_180)
1773 return 0;
f2119df6 1774
20b92a30
KL		 1775 pr_warning("%s: 1.8V regulator output did not became stable\n",
1776 mmc_hostname(host->mmc));
f2119df6 1777
20b92a30
KL		 1778 return -EAGAIN;
1779 case MMC_SIGNAL_VOLTAGE_120:
1780 if (host->vqmmc) {
1781 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1782 if (ret) {
1783 pr_warning("%s: Switching to 1.2V signalling voltage "
1784 " failed\n", mmc_hostname(host->mmc));
1785 return -EIO;
f2119df6
AN		 1786 }
1787 }
6231f3de 1788 return 0;
20b92a30 1789 default:
f2119df6
AN		 1790 /* No signal voltage switch required */
1791 return 0;
20b92a30 1792 }
f2119df6
AN		 1793}
1794
66fd8ad5 1795static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1796 struct mmc_ios *ios)
66fd8ad5
AH		 1797{
1798 struct sdhci_host *host = mmc_priv(mmc);
1799 int err;
1800
1801 if (host->version < SDHCI_SPEC_300)
1802 return 0;
1803 sdhci_runtime_pm_get(host);
21f5998f 1804 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1805 sdhci_runtime_pm_put(host);
1806 return err;
1807}
1808
20b92a30
KL		 1809static int sdhci_card_busy(struct mmc_host *mmc)
1810{
1811 struct sdhci_host *host = mmc_priv(mmc);
1812 u32 present_state;
1813
1814 sdhci_runtime_pm_get(host);
1815 /* Check whether DAT[3:0] is 0000 */
1816 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1817 sdhci_runtime_pm_put(host);
1818
1819 return !(present_state & SDHCI_DATA_LVL_MASK);
1820}
1821
069c9f14 1822static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1823{
1824 struct sdhci_host *host;
1825 u16 ctrl;
1826 u32 ier;
1827 int tuning_loop_counter = MAX_TUNING_LOOP;
1828 unsigned long timeout;
1829 int err = 0;
069c9f14 1830 bool requires_tuning_nonuhs = false;
b513ea25
AN		 1831
1832 host = mmc_priv(mmc);
1833
66fd8ad5 1834 sdhci_runtime_pm_get(host);
b513ea25
AN		 1835 disable_irq(host->irq);
1836 spin_lock(&host->lock);
1837
1838 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1839
1840 /*
069c9f14
G		 1841 * The Host Controller needs tuning only in case of SDR104 mode
1842 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1843 * Capabilities register.
069c9f14
G		 1844 * If the Host Controller supports the HS200 mode then the
1845 * tuning function has to be executed.
b513ea25 1846 */
069c9f14
G		 1847 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1848 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1849 host->flags & SDHCI_HS200_NEEDS_TUNING))
1850 requires_tuning_nonuhs = true;
1851
b513ea25 1852 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1853 requires_tuning_nonuhs)
b513ea25
AN		 1854 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1855 else {
1856 spin_unlock(&host->lock);
1857 enable_irq(host->irq);
66fd8ad5 1858 sdhci_runtime_pm_put(host);
b513ea25
AN		 1859 return 0;
1860 }
1861
1862 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1863
1864 /*
1865 * As per the Host Controller spec v3.00, tuning command
1866 * generates Buffer Read Ready interrupt, so enable that.
1867 *
1868 * Note: The spec clearly says that when tuning sequence
1869 * is being performed, the controller does not generate
1870 * interrupts other than Buffer Read Ready interrupt. But
1871 * to make sure we don't hit a controller bug, we _only_
1872 * enable Buffer Read Ready interrupt here.
1873 */
1874 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1875 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1876
1877 /*
1878 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1879 * of loops reaches 40 times or a timeout of 150ms occurs.
1880 */
1881 timeout = 150;
1882 do {
1883 struct mmc_command cmd = {0};
66fd8ad5 1884 struct mmc_request mrq = {NULL};
b513ea25
AN		 1885
1886 if (!tuning_loop_counter && !timeout)
1887 break;
1888
069c9f14 1889 cmd.opcode = opcode;
b513ea25
AN		 1890 cmd.arg = 0;
1891 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1892 cmd.retries = 0;
1893 cmd.data = NULL;
1894 cmd.error = 0;
1895
1896 mrq.cmd = &cmd;
1897 host->mrq = &mrq;
1898
1899 /*
1900 * In response to CMD19, the card sends 64 bytes of tuning
1901 * block to the Host Controller. So we set the block size
1902 * to 64 here.
1903 */
069c9f14
G		 1904 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1905 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1906 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1907 SDHCI_BLOCK_SIZE);
1908 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1909 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1910 SDHCI_BLOCK_SIZE);
1911 } else {
1912 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1913 SDHCI_BLOCK_SIZE);
1914 }
b513ea25
AN		 1915
1916 /*
1917 * The tuning block is sent by the card to the host controller.
1918 * So we set the TRNS_READ bit in the Transfer Mode register.
1919 * This also takes care of setting DMA Enable and Multi Block
1920 * Select in the same register to 0.
1921 */
1922 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1923
1924 sdhci_send_command(host, &cmd);
1925
1926 host->cmd = NULL;
1927 host->mrq = NULL;
1928
1929 spin_unlock(&host->lock);
1930 enable_irq(host->irq);
1931
1932 /* Wait for Buffer Read Ready interrupt */
1933 wait_event_interruptible_timeout(host->buf_ready_int,
1934 (host->tuning_done == 1),
1935 msecs_to_jiffies(50));
1936 disable_irq(host->irq);
1937 spin_lock(&host->lock);
1938
1939 if (!host->tuning_done) {
a3c76eb9 1940 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1941 "Buffer Read Ready interrupt during tuning "
1942 "procedure, falling back to fixed sampling "
1943 "clock\n");
1944 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1945 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1946 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1947 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1948
1949 err = -EIO;
1950 goto out;
1951 }
1952
1953 host->tuning_done = 0;
1954
1955 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1956 tuning_loop_counter--;
1957 timeout--;
1958 mdelay(1);
1959 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1960
1961 /*
1962 * The Host Driver has exhausted the maximum number of loops allowed,
1963 * so use fixed sampling frequency.
1964 */
1965 if (!tuning_loop_counter || !timeout) {
1966 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1967 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1968 } else {
1969 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1970 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1971 " failed, falling back to fixed sampling"
1972 " clock\n");
1973 err = -EIO;
1974 }
1975 }
1976
1977out:
cf2b5eea
AN		 1978 /*
1979 * If this is the very first time we are here, we start the retuning
1980 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1981 * flag won't be set, we check this condition before actually starting
1982 * the timer.
1983 */
1984 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1985 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 1986 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 1987 mod_timer(&host->tuning_timer, jiffies +
1988 host->tuning_count * HZ);
1989 /* Tuning mode 1 limits the maximum data length to 4MB */
1990 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1991 } else {
1992 host->flags &= ~SDHCI_NEEDS_RETUNING;
1993 /* Reload the new initial value for timer */
1994 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1995 mod_timer(&host->tuning_timer, jiffies +
1996 host->tuning_count * HZ);
1997 }
1998
1999 /*
2000 * In case tuning fails, host controllers which support re-tuning can
2001 * try tuning again at a later time, when the re-tuning timer expires.
2002 * So for these controllers, we return 0. Since there might be other
2003 * controllers who do not have this capability, we return error for
973905fe
AL		 2004 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2005 * a retuning timer to do the retuning for the card.
cf2b5eea 2006 */
973905fe 2007 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2008 err = 0;
2009
b513ea25
AN		 2010 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2011 spin_unlock(&host->lock);
2012 enable_irq(host->irq);
66fd8ad5 2013 sdhci_runtime_pm_put(host);
b513ea25
AN		 2014
2015 return err;
2016}
2017
52983382
KL		 2018
2019static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2020{
4d55c5a1 2021 u16 ctrl;
4d55c5a1 2022
4d55c5a1
AN		 2023 /* Host Controller v3.00 defines preset value registers */
2024 if (host->version < SDHCI_SPEC_300)
2025 return;
2026
4d55c5a1
AN		 2027 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2028
2029 /*
2030 * We only enable or disable Preset Value if they are not already
2031 * enabled or disabled respectively. Otherwise, we bail out.
2032 */
2033 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2034 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2035 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2036 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2037 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2038 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2039 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2040 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2041 }
66fd8ad5
AH		 2042}
2043
71e69211 2044static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2045{
71e69211 2046 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2047 unsigned long flags;
2048
d129bceb
PO		 2049 spin_lock_irqsave(&host->lock, flags);
2050
66fd8ad5
AH		 2051 /* Check host->mrq first in case we are runtime suspended */
2052 if (host->mrq &&
2053 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
a3c76eb9 2054 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2055 mmc_hostname(host->mmc));
a3c76eb9 2056 pr_err("%s: Resetting controller.\n",
66fd8ad5 2057 mmc_hostname(host->mmc));
d129bceb 2058
66fd8ad5
AH		 2059 sdhci_reset(host, SDHCI_RESET_CMD);
2060 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 2061
66fd8ad5
AH		 2062 host->mrq->cmd->error = -ENOMEDIUM;
2063 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2064 }
2065
2066 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2067}
2068
2069static const struct mmc_host_ops sdhci_ops = {
2070 .request = sdhci_request,
2071 .set_ios = sdhci_set_ios,
94144a46 2072 .get_cd = sdhci_get_cd,
71e69211
GL		 2073 .get_ro = sdhci_get_ro,
2074 .hw_reset = sdhci_hw_reset,
2075 .enable_sdio_irq = sdhci_enable_sdio_irq,
2076 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2077 .execute_tuning = sdhci_execute_tuning,
71e69211 2078 .card_event = sdhci_card_event,
20b92a30 2079 .card_busy = sdhci_card_busy,
71e69211
GL		 2080};
2081
2082/*****************************************************************************\
2083 * *
2084 * Tasklets *
2085 * *
2086\*****************************************************************************/
2087
2088static void sdhci_tasklet_card(unsigned long param)
2089{
2090 struct sdhci_host *host = (struct sdhci_host*)param;
2091
2092 sdhci_card_event(host->mmc);
d129bceb 2093
04cf585d 2094 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 2095}
2096
2097static void sdhci_tasklet_finish(unsigned long param)
2098{
2099 struct sdhci_host *host;
2100 unsigned long flags;
2101 struct mmc_request *mrq;
2102
2103 host = (struct sdhci_host*)param;
2104
66fd8ad5
AH		 2105 spin_lock_irqsave(&host->lock, flags);
2106
0c9c99a7
CB		 2107 /*
2108 * If this tasklet gets rescheduled while running, it will
2109 * be run again afterwards but without any active request.
2110 */
66fd8ad5
AH		 2111 if (!host->mrq) {
2112 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2113 return;
66fd8ad5 2114 }
d129bceb
PO		 2115
2116 del_timer(&host->timer);
2117
2118 mrq = host->mrq;
2119
d129bceb
PO		 2120 /*
2121 * The controller needs a reset of internal state machines
2122 * upon error conditions.
2123 */
1e72859e 2124 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2125 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2126 (mrq->data && (mrq->data->error ||
2127 (mrq->data->stop && mrq->data->stop->error))) ||
2128 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2129
2130 /* Some controllers need this kick or reset won't work here */
8213af3b 2131 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2132 /* This is to force an update */
8213af3b 2133 sdhci_update_clock(host);
645289dc
PO		 2134
2135 /* Spec says we should do both at the same time, but Ricoh
2136 controllers do not like that. */
d129bceb
PO		 2137 sdhci_reset(host, SDHCI_RESET_CMD);
2138 sdhci_reset(host, SDHCI_RESET_DATA);
2139 }
2140
2141 host->mrq = NULL;
2142 host->cmd = NULL;
2143 host->data = NULL;
2144
f9134319 2145#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2146 sdhci_deactivate_led(host);
2f730fec 2147#endif
d129bceb 2148
5f25a66f 2149 mmiowb();
d129bceb
PO		 2150 spin_unlock_irqrestore(&host->lock, flags);
2151
2152 mmc_request_done(host->mmc, mrq);
66fd8ad5 2153 sdhci_runtime_pm_put(host);
d129bceb
PO		 2154}
2155
2156static void sdhci_timeout_timer(unsigned long data)
2157{
2158 struct sdhci_host *host;
2159 unsigned long flags;
2160
2161 host = (struct sdhci_host*)data;
2162
2163 spin_lock_irqsave(&host->lock, flags);
2164
2165 if (host->mrq) {
a3c76eb9 2166 pr_err("%s: Timeout waiting for hardware "
acf1da45 2167 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2168 sdhci_dumpregs(host);
2169
2170 if (host->data) {
17b0429d 2171 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2172 sdhci_finish_data(host);
2173 } else {
2174 if (host->cmd)
17b0429d 2175 host->cmd->error = -ETIMEDOUT;
d129bceb 2176 else
17b0429d 2177 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2178
2179 tasklet_schedule(&host->finish_tasklet);
2180 }
2181 }
2182
5f25a66f 2183 mmiowb();
d129bceb
PO		 2184 spin_unlock_irqrestore(&host->lock, flags);
2185}
2186
cf2b5eea
AN		 2187static void sdhci_tuning_timer(unsigned long data)
2188{
2189 struct sdhci_host *host;
2190 unsigned long flags;
2191
2192 host = (struct sdhci_host *)data;
2193
2194 spin_lock_irqsave(&host->lock, flags);
2195
2196 host->flags |= SDHCI_NEEDS_RETUNING;
2197
2198 spin_unlock_irqrestore(&host->lock, flags);
2199}
2200
d129bceb
PO		 2201/*****************************************************************************\
2202 * *
2203 * Interrupt handling *
2204 * *
2205\*****************************************************************************/
2206
2207static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2208{
2209 BUG_ON(intmask == 0);
2210
2211 if (!host->cmd) {
a3c76eb9 2212 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2213 "though no command operation was in progress.\n",
2214 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2215 sdhci_dumpregs(host);
2216 return;
2217 }
2218
43b58b36 2219 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2220 host->cmd->error = -ETIMEDOUT;
2221 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2222 SDHCI_INT_INDEX))
2223 host->cmd->error = -EILSEQ;
43b58b36 2224
e809517f 2225 if (host->cmd->error) {
d129bceb 2226 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2227 return;
2228 }
2229
2230 /*
2231 * The host can send and interrupt when the busy state has
2232 * ended, allowing us to wait without wasting CPU cycles.
2233 * Unfortunately this is overloaded on the "data complete"
2234 * interrupt, so we need to take some care when handling
2235 * it.
2236 *
2237 * Note: The 1.0 specification is a bit ambiguous about this
2238 * feature so there might be some problems with older
2239 * controllers.
2240 */
2241 if (host->cmd->flags & MMC_RSP_BUSY) {
2242 if (host->cmd->data)
2243 DBG("Cannot wait for busy signal when also "
2244 "doing a data transfer");
f945405c 2245 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2246 return;
f945405c
BD		 2247
2248 /* The controller does not support the end-of-busy IRQ,
2249 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2250 }
2251
2252 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2253 sdhci_finish_command(host);
d129bceb
PO		 2254}
2255
0957c333 2256#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2257static void sdhci_show_adma_error(struct sdhci_host *host)
2258{
2259 const char *name = mmc_hostname(host->mmc);
2260 u8 *desc = host->adma_desc;
2261 __le32 *dma;
2262 __le16 *len;
2263 u8 attr;
2264
2265 sdhci_dumpregs(host);
2266
2267 while (true) {
2268 dma = (__le32 *)(desc + 4);
2269 len = (__le16 *)(desc + 2);
2270 attr = *desc;
2271
2272 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2273 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2274
2275 desc += 8;
2276
2277 if (attr & 2)
2278 break;
2279 }
2280}
2281#else
2282static void sdhci_show_adma_error(struct sdhci_host *host) { }
2283#endif
2284
d129bceb
PO		 2285static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2286{
069c9f14 2287 u32 command;
d129bceb
PO		 2288 BUG_ON(intmask == 0);
2289
b513ea25
AN		 2290 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2291 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2292 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2293 if (command == MMC_SEND_TUNING_BLOCK ||
2294 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2295 host->tuning_done = 1;
2296 wake_up(&host->buf_ready_int);
2297 return;
2298 }
2299 }
2300
d129bceb
PO		 2301 if (!host->data) {
2302 /*
e809517f
PO		 2303 * The "data complete" interrupt is also used to
2304 * indicate that a busy state has ended. See comment
2305 * above in sdhci_cmd_irq().
d129bceb 2306 */
e809517f
PO		 2307 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2308 if (intmask & SDHCI_INT_DATA_END) {
2309 sdhci_finish_command(host);
2310 return;
2311 }
2312 }
d129bceb 2313
a3c76eb9 2314 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2315 "though no data operation was in progress.\n",
2316 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2317 sdhci_dumpregs(host);
2318
2319 return;
2320 }
2321
2322 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2323 host->data->error = -ETIMEDOUT;
22113efd
AL		 2324 else if (intmask & SDHCI_INT_DATA_END_BIT)
2325 host->data->error = -EILSEQ;
2326 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2327 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2328 != MMC_BUS_TEST_R)
17b0429d 2329 host->data->error = -EILSEQ;
6882a8c0 2330 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2331 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2332 sdhci_show_adma_error(host);
2134a922 2333 host->data->error = -EIO;
a4071fbb
HZ		 2334 if (host->ops->adma_workaround)
2335 host->ops->adma_workaround(host, intmask);
6882a8c0 2336 }
d129bceb 2337
17b0429d 2338 if (host->data->error)
d129bceb
PO		 2339 sdhci_finish_data(host);
2340 else {
a406f5a3 2341 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2342 sdhci_transfer_pio(host);
2343
6ba736a1
PO		 2344 /*
2345 * We currently don't do anything fancy with DMA
2346 * boundaries, but as we can't disable the feature
2347 * we need to at least restart the transfer.
f6a03cbf
MV		 2348 *
2349 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2350 * should return a valid address to continue from, but as
2351 * some controllers are faulty, don't trust them.
6ba736a1 2352 */
f6a03cbf
MV		 2353 if (intmask & SDHCI_INT_DMA_END) {
2354 u32 dmastart, dmanow;
2355 dmastart = sg_dma_address(host->data->sg);
2356 dmanow = dmastart + host->data->bytes_xfered;
2357 /*
2358 * Force update to the next DMA block boundary.
2359 */
2360 dmanow = (dmanow &
2361 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2362 SDHCI_DEFAULT_BOUNDARY_SIZE;
2363 host->data->bytes_xfered = dmanow - dmastart;
2364 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2365 " next 0x%08x\n",
2366 mmc_hostname(host->mmc), dmastart,
2367 host->data->bytes_xfered, dmanow);
2368 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2369 }
6ba736a1 2370
e538fbe8
PO		 2371 if (intmask & SDHCI_INT_DATA_END) {
2372 if (host->cmd) {
2373 /*
2374 * Data managed to finish before the
2375 * command completed. Make sure we do
2376 * things in the proper order.
2377 */
2378 host->data_early = 1;
2379 } else {
2380 sdhci_finish_data(host);
2381 }
2382 }
d129bceb
PO		 2383 }
2384}
2385
7d12e780 2386static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2387{
2388 irqreturn_t result;
66fd8ad5 2389 struct sdhci_host *host = dev_id;
6379b237
AS		 2390 u32 intmask, unexpected = 0;
2391 int cardint = 0, max_loops = 16;
d129bceb
PO		 2392
2393 spin_lock(&host->lock);
2394
66fd8ad5
AH		 2395 if (host->runtime_suspended) {
2396 spin_unlock(&host->lock);
a3c76eb9 2397 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2398 mmc_hostname(host->mmc));
2399 return IRQ_HANDLED;
2400 }
2401
4e4141a5 2402 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2403
62df67a5 2404 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2405 result = IRQ_NONE;
2406 goto out;
2407 }
2408
6379b237 2409again:
b69c9058
PO		 2410 DBG("*** %s got interrupt: 0x%08x\n",
2411 mmc_hostname(host->mmc), intmask);
d129bceb 2412
3192a28f 2413 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2414 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2415 SDHCI_CARD_PRESENT;
2416
2417 /*
2418 * There is a observation on i.mx esdhc. INSERT bit will be
2419 * immediately set again when it gets cleared, if a card is
2420 * inserted. We have to mask the irq to prevent interrupt
2421 * storm which will freeze the system. And the REMOVE gets
2422 * the same situation.
2423 *
2424 * More testing are needed here to ensure it works for other
2425 * platforms though.
2426 */
2427 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2428 SDHCI_INT_CARD_REMOVE);
2429 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2430 SDHCI_INT_CARD_INSERT);
2431
4e4141a5 2432 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2433 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2434 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2435 tasklet_schedule(&host->card_tasklet);
3192a28f 2436 }
d129bceb 2437
3192a28f 2438 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2439 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2440 SDHCI_INT_STATUS);
3192a28f 2441 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2442 }
2443
2444 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2445 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2446 SDHCI_INT_STATUS);
3192a28f 2447 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2448 }
2449
2450 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2451
964f9ce2
PO		 2452 intmask &= ~SDHCI_INT_ERROR;
2453
d129bceb 2454 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2455 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2456 mmc_hostname(host->mmc));
4e4141a5 2457 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2458 }
2459
9d26a5d3 2460 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2461
f75979b7
PO		 2462 if (intmask & SDHCI_INT_CARD_INT)
2463 cardint = 1;
2464
2465 intmask &= ~SDHCI_INT_CARD_INT;
2466
3192a28f 2467 if (intmask) {
6379b237 2468 unexpected |= intmask;
4e4141a5 2469 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2470 }
d129bceb
PO		 2471
2472 result = IRQ_HANDLED;
2473
6379b237
AS		 2474 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2475 if (intmask && --max_loops)
2476 goto again;
d129bceb
PO		 2477out:
2478 spin_unlock(&host->lock);
2479
6379b237
AS		 2480 if (unexpected) {
2481 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2482 mmc_hostname(host->mmc), unexpected);
2483 sdhci_dumpregs(host);
2484 }
f75979b7
PO		 2485 /*
2486 * We have to delay this as it calls back into the driver.
2487 */
2488 if (cardint)
2489 mmc_signal_sdio_irq(host->mmc);
2490
d129bceb
PO		 2491 return result;
2492}
2493
2494/*****************************************************************************\
2495 * *
2496 * Suspend/resume *
2497 * *
2498\*****************************************************************************/
2499
2500#ifdef CONFIG_PM
ad080d79
KL		 2501void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2502{
2503 u8 val;
2504 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2505 | SDHCI_WAKE_ON_INT;
2506
2507 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2508 val |= mask ;
2509 /* Avoid fake wake up */
2510 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2511 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2512 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2513}
2514EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2515
2516void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2517{
2518 u8 val;
2519 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2520 | SDHCI_WAKE_ON_INT;
2521
2522 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2523 val &= ~mask;
2524 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2525}
2526EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2527
29495aa0 2528int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2529{
b8c86fc5 2530 int ret;
a715dfc7 2531
a1b13b4e
CB		 2532 if (host->ops->platform_suspend)
2533 host->ops->platform_suspend(host);
2534
7260cf5e
AV		 2535 sdhci_disable_card_detection(host);
2536
cf2b5eea 2537 /* Disable tuning since we are suspending */
973905fe 2538 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2539 del_timer_sync(&host->tuning_timer);
cf2b5eea 2540 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2541 }
2542
1a13f8fa 2543 ret = mmc_suspend_host(host->mmc);
38a60ea2 2544 if (ret) {
973905fe 2545 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
38a60ea2
AL		 2546 host->flags |= SDHCI_NEEDS_RETUNING;
2547 mod_timer(&host->tuning_timer, jiffies +
2548 host->tuning_count * HZ);
2549 }
2550
2551 sdhci_enable_card_detection(host);
2552
b8c86fc5 2553 return ret;
38a60ea2 2554 }
a715dfc7 2555
ad080d79
KL		 2556 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2557 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2558 free_irq(host->irq, host);
2559 } else {
2560 sdhci_enable_irq_wakeups(host);
2561 enable_irq_wake(host->irq);
2562 }
9bea3c85 2563 return ret;
d129bceb
PO		 2564}
2565
b8c86fc5 2566EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2567
b8c86fc5
PO		 2568int sdhci_resume_host(struct sdhci_host *host)
2569{
2570 int ret;
d129bceb 2571
a13abc7b 2572 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2573 if (host->ops->enable_dma)
2574 host->ops->enable_dma(host);
2575 }
d129bceb 2576
ad080d79
KL		 2577 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2578 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2579 mmc_hostname(host->mmc), host);
2580 if (ret)
2581 return ret;
2582 } else {
2583 sdhci_disable_irq_wakeups(host);
2584 disable_irq_wake(host->irq);
2585 }
d129bceb 2586
6308d290
AH		 2587 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2588 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2589 /* Card keeps power but host controller does not */
2590 sdhci_init(host, 0);
2591 host->pwr = 0;
2592 host->clock = 0;
2593 sdhci_do_set_ios(host, &host->mmc->ios);
2594 } else {
2595 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2596 mmiowb();
2597 }
b8c86fc5
PO		 2598
2599 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2600 sdhci_enable_card_detection(host);
2601
a1b13b4e
CB		 2602 if (host->ops->platform_resume)
2603 host->ops->platform_resume(host);
2604
cf2b5eea 2605 /* Set the re-tuning expiration flag */
973905fe 2606 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2607 host->flags |= SDHCI_NEEDS_RETUNING;
2608
2f4cbb3d 2609 return ret;
d129bceb
PO		 2610}
2611
b8c86fc5 2612EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2613#endif /* CONFIG_PM */
2614
66fd8ad5
AH		 2615#ifdef CONFIG_PM_RUNTIME
2616
2617static int sdhci_runtime_pm_get(struct sdhci_host *host)
2618{
2619 return pm_runtime_get_sync(host->mmc->parent);
2620}
2621
2622static int sdhci_runtime_pm_put(struct sdhci_host *host)
2623{
2624 pm_runtime_mark_last_busy(host->mmc->parent);
2625 return pm_runtime_put_autosuspend(host->mmc->parent);
2626}
2627
2628int sdhci_runtime_suspend_host(struct sdhci_host *host)
2629{
2630 unsigned long flags;
2631 int ret = 0;
2632
2633 /* Disable tuning since we are suspending */
973905fe 2634 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2635 del_timer_sync(&host->tuning_timer);
2636 host->flags &= ~SDHCI_NEEDS_RETUNING;
2637 }
2638
2639 spin_lock_irqsave(&host->lock, flags);
2640 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2641 spin_unlock_irqrestore(&host->lock, flags);
2642
2643 synchronize_irq(host->irq);
2644
2645 spin_lock_irqsave(&host->lock, flags);
2646 host->runtime_suspended = true;
2647 spin_unlock_irqrestore(&host->lock, flags);
2648
2649 return ret;
2650}
2651EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2652
2653int sdhci_runtime_resume_host(struct sdhci_host *host)
2654{
2655 unsigned long flags;
2656 int ret = 0, host_flags = host->flags;
2657
2658 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2659 if (host->ops->enable_dma)
2660 host->ops->enable_dma(host);
2661 }
2662
2663 sdhci_init(host, 0);
2664
2665 /* Force clock and power re-program */
2666 host->pwr = 0;
2667 host->clock = 0;
2668 sdhci_do_set_ios(host, &host->mmc->ios);
2669
2670 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2671 if ((host_flags & SDHCI_PV_ENABLED) &&
2672 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2673 spin_lock_irqsave(&host->lock, flags);
2674 sdhci_enable_preset_value(host, true);
2675 spin_unlock_irqrestore(&host->lock, flags);
2676 }
66fd8ad5
AH		 2677
2678 /* Set the re-tuning expiration flag */
973905fe 2679 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2680 host->flags |= SDHCI_NEEDS_RETUNING;
2681
2682 spin_lock_irqsave(&host->lock, flags);
2683
2684 host->runtime_suspended = false;
2685
2686 /* Enable SDIO IRQ */
2687 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2688 sdhci_enable_sdio_irq_nolock(host, true);
2689
2690 /* Enable Card Detection */
2691 sdhci_enable_card_detection(host);
2692
2693 spin_unlock_irqrestore(&host->lock, flags);
2694
2695 return ret;
2696}
2697EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2698
2699#endif
2700
d129bceb
PO		 2701/*****************************************************************************\
2702 * *
b8c86fc5 2703 * Device allocation/registration *
d129bceb
PO		 2704 * *
2705\*****************************************************************************/
2706
b8c86fc5
PO		 2707struct sdhci_host *sdhci_alloc_host(struct device *dev,
2708 size_t priv_size)
d129bceb 2709{
d129bceb
PO		 2710 struct mmc_host *mmc;
2711 struct sdhci_host *host;
2712
b8c86fc5 2713 WARN_ON(dev == NULL);
d129bceb 2714
b8c86fc5 2715 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2716 if (!mmc)
b8c86fc5 2717 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2718
2719 host = mmc_priv(mmc);
2720 host->mmc = mmc;
2721
b8c86fc5
PO		 2722 return host;
2723}
8a4da143 2724
b8c86fc5 2725EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2726
b8c86fc5
PO		 2727int sdhci_add_host(struct sdhci_host *host)
2728{
2729 struct mmc_host *mmc;
bd6a8c30 2730 u32 caps[2] = {0, 0};
f2119df6
AN		 2731 u32 max_current_caps;
2732 unsigned int ocr_avail;
b8c86fc5 2733 int ret;
d129bceb 2734
b8c86fc5
PO		 2735 WARN_ON(host == NULL);
2736 if (host == NULL)
2737 return -EINVAL;
d129bceb 2738
b8c86fc5 2739 mmc = host->mmc;
d129bceb 2740
b8c86fc5
PO		 2741 if (debug_quirks)
2742 host->quirks = debug_quirks;
66fd8ad5
AH		 2743 if (debug_quirks2)
2744 host->quirks2 = debug_quirks2;
d129bceb 2745
d96649ed
PO		 2746 sdhci_reset(host, SDHCI_RESET_ALL);
2747
4e4141a5 2748 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2749 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2750 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2751 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2752 pr_err("%s: Unknown controller version (%d). "
b69c9058 2753 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2754 host->version);
4a965505
PO		 2755 }
2756
f2119df6 2757 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2758 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2759
bd6a8c30
PR		 2760 if (host->version >= SDHCI_SPEC_300)
2761 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2762 host->caps1 :
2763 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2764
b8c86fc5 2765 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2766 host->flags |= SDHCI_USE_SDMA;
f2119df6 2767 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2768 DBG("Controller doesn't have SDMA capability\n");
67435274 2769 else
a13abc7b 2770 host->flags |= SDHCI_USE_SDMA;
d129bceb 2771
b8c86fc5 2772 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2773 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2774 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2775 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2776 }
2777
f2119df6
AN		 2778 if ((host->version >= SDHCI_SPEC_200) &&
2779 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2780 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2781
2782 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2783 (host->flags & SDHCI_USE_ADMA)) {
2784 DBG("Disabling ADMA as it is marked broken\n");
2785 host->flags &= ~SDHCI_USE_ADMA;
2786 }
2787
a13abc7b 2788 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2789 if (host->ops->enable_dma) {
2790 if (host->ops->enable_dma(host)) {
a3c76eb9 2791 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2792 "available. Falling back to PIO.\n",
2793 mmc_hostname(mmc));
a13abc7b
RR		 2794 host->flags &=
2795 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2796 }
d129bceb
PO		 2797 }
2798 }
2799
2134a922
PO		 2800 if (host->flags & SDHCI_USE_ADMA) {
2801 /*
2802 * We need to allocate descriptors for all sg entries
2803 * (128) and potentially one alignment transfer for
2804 * each of those entries.
2805 */
2806 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2807 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2808 if (!host->adma_desc || !host->align_buffer) {
2809 kfree(host->adma_desc);
2810 kfree(host->align_buffer);
a3c76eb9 2811 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2812 "buffers. Falling back to standard DMA.\n",
2813 mmc_hostname(mmc));
2814 host->flags &= ~SDHCI_USE_ADMA;
2815 }
2816 }
2817
7659150c
PO		 2818 /*
2819 * If we use DMA, then it's up to the caller to set the DMA
2820 * mask, but PIO does not need the hw shim so we set a new
2821 * mask here in that case.
2822 */
a13abc7b 2823 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2824 host->dma_mask = DMA_BIT_MASK(64);
2825 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2826 }
d129bceb 2827
c4687d5f 2828 if (host->version >= SDHCI_SPEC_300)
f2119df6 2829 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2830 >> SDHCI_CLOCK_BASE_SHIFT;
2831 else
f2119df6 2832 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2833 >> SDHCI_CLOCK_BASE_SHIFT;
2834
4240ff0a 2835 host->max_clk *= 1000000;
f27f47ef
AV		 2836 if (host->max_clk == 0 || host->quirks &
2837 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2838 if (!host->ops->get_max_clock) {
a3c76eb9 2839 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2840 "frequency.\n", mmc_hostname(mmc));
2841 return -ENODEV;
2842 }
2843 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2844 }
d129bceb 2845
c3ed3877
AN		 2846 /*
2847 * In case of Host Controller v3.00, find out whether clock
2848 * multiplier is supported.
2849 */
2850 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2851 SDHCI_CLOCK_MUL_SHIFT;
2852
2853 /*
2854 * In case the value in Clock Multiplier is 0, then programmable
2855 * clock mode is not supported, otherwise the actual clock
2856 * multiplier is one more than the value of Clock Multiplier
2857 * in the Capabilities Register.
2858 */
2859 if (host->clk_mul)
2860 host->clk_mul += 1;
2861
d129bceb
PO		 2862 /*
2863 * Set host parameters.
2864 */
2865 mmc->ops = &sdhci_ops;
c3ed3877 2866 mmc->f_max = host->max_clk;
ce5f036b 2867 if (host->ops->get_min_clock)
a9e58f25 2868 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2869 else if (host->version >= SDHCI_SPEC_300) {
2870 if (host->clk_mul) {
2871 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2872 mmc->f_max = host->max_clk * host->clk_mul;
2873 } else
2874 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2875 } else
0397526d 2876 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2877
272308ca
AS		 2878 host->timeout_clk =
2879 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2880 if (host->timeout_clk == 0) {
2881 if (host->ops->get_timeout_clock) {
2882 host->timeout_clk = host->ops->get_timeout_clock(host);
2883 } else if (!(host->quirks &
2884 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2885 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2886 "frequency.\n", mmc_hostname(mmc));
2887 return -ENODEV;
2888 }
2889 }
2890 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2891 host->timeout_clk *= 1000;
2892
2893 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2894 host->timeout_clk = mmc->f_max / 1000;
272308ca 2895
65be3fef 2896 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2897
e89d456f
AW		 2898 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2899
2900 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2901 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2902
8edf6371 2903 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2904 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2905 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2906 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2907 host->flags |= SDHCI_AUTO_CMD23;
2908 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2909 } else {
2910 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2911 }
2912
15ec4461
PR		 2913 /*
2914 * A controller may support 8-bit width, but the board itself
2915 * might not have the pins brought out. Boards that support
2916 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2917 * their platform code before calling sdhci_add_host(), and we
2918 * won't assume 8-bit width for hosts without that CAP.
2919 */
5fe23c7f 2920 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2921 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2922
63ef5d8c
JH		 2923 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2924 mmc->caps &= ~MMC_CAP_CMD23;
2925
f2119df6 2926 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2927 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2928
176d1ed4 2929 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2930 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2931 mmc->caps |= MMC_CAP_NEEDS_POLL;
2932
6231f3de
PR		 2933 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2934 host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2935 if (IS_ERR_OR_NULL(host->vqmmc)) {
2936 if (PTR_ERR(host->vqmmc) < 0) {
2937 pr_info("%s: no vqmmc regulator found\n",
2938 mmc_hostname(mmc));
2939 host->vqmmc = NULL;
2940 }
8363c374 2941 } else {
6231f3de 2942 regulator_enable(host->vqmmc);
cec2e216
KL		 2943 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2944 1950000))
8363c374
KL		 2945 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2946 SDHCI_SUPPORT_SDR50 |
2947 SDHCI_SUPPORT_DDR50);
2948 }
6231f3de 2949
6a66180a
DD		 2950 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2951 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2952 SDHCI_SUPPORT_DDR50);
2953
4188bba0
AC		 2954 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2955 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2956 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 2957 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2958
2959 /* SDR104 supports also implies SDR50 support */
2960 if (caps[1] & SDHCI_SUPPORT_SDR104)
2961 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2962 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2963 mmc->caps |= MMC_CAP_UHS_SDR50;
2964
2965 if (caps[1] & SDHCI_SUPPORT_DDR50)
2966 mmc->caps |= MMC_CAP_UHS_DDR50;
2967
069c9f14 2968 /* Does the host need tuning for SDR50? */
b513ea25
AN		 2969 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2970 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2971
069c9f14
G		 2972 /* Does the host need tuning for HS200? */
2973 if (mmc->caps2 & MMC_CAP2_HS200)
2974 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2975
d6d50a15
AN		 2976 /* Driver Type(s) (A, C, D) supported by the host */
2977 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2978 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2979 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2980 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2981 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2982 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2983
cf2b5eea
AN		 2984 /* Initial value for re-tuning timer count */
2985 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2986 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2987
2988 /*
2989 * In case Re-tuning Timer is not disabled, the actual value of
2990 * re-tuning timer will be 2 ^ (n - 1).
2991 */
2992 if (host->tuning_count)
2993 host->tuning_count = 1 << (host->tuning_count - 1);
2994
2995 /* Re-tuning mode supported by the Host Controller */
2996 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2997 SDHCI_RETUNING_MODE_SHIFT;
2998
8f230f45 2999 ocr_avail = 0;
bad37e1a
PR		 3000
3001 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
657d5982
KL		 3002 if (IS_ERR_OR_NULL(host->vmmc)) {
3003 if (PTR_ERR(host->vmmc) < 0) {
3004 pr_info("%s: no vmmc regulator found\n",
3005 mmc_hostname(mmc));
3006 host->vmmc = NULL;
3007 }
8363c374 3008 }
bad37e1a 3009
68737043 3010#ifdef CONFIG_REGULATOR
a4f8f257
MS		 3011 /*
3012 * Voltage range check makes sense only if regulator reports
3013 * any voltage value.
3014 */
3015 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 3016 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3017 3600000);
68737043
PR		 3018 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3019 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 3020 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3021 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 3022 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3023 1950000);
68737043
PR		 3024 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3025 caps[0] &= ~SDHCI_CAN_VDD_180;
3026 }
3027#endif /* CONFIG_REGULATOR */
3028
f2119df6
AN		 3029 /*
3030 * According to SD Host Controller spec v3.00, if the Host System
3031 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3032 * the value is meaningful only if Voltage Support in the Capabilities
3033 * register is set. The actual current value is 4 times the register
3034 * value.
3035 */
3036 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3037 if (!max_current_caps && host->vmmc) {
3038 u32 curr = regulator_get_current_limit(host->vmmc);
3039 if (curr > 0) {
3040
3041 /* convert to SDHCI_MAX_CURRENT format */
3042 curr = curr/1000; /* convert to mA */
3043 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3044
3045 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3046 max_current_caps =
3047 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3048 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3049 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3050 }
3051 }
f2119df6
AN		 3052
3053 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3054 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3055
55c4665e 3056 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3057 SDHCI_MAX_CURRENT_330_MASK) >>
3058 SDHCI_MAX_CURRENT_330_SHIFT) *
3059 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3060 }
3061 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3062 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3063
55c4665e 3064 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3065 SDHCI_MAX_CURRENT_300_MASK) >>
3066 SDHCI_MAX_CURRENT_300_SHIFT) *
3067 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3068 }
3069 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3070 ocr_avail |= MMC_VDD_165_195;
3071
55c4665e 3072 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3073 SDHCI_MAX_CURRENT_180_MASK) >>
3074 SDHCI_MAX_CURRENT_180_SHIFT) *
3075 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3076 }
3077
8f230f45
TI		 3078 mmc->ocr_avail = ocr_avail;
3079 mmc->ocr_avail_sdio = ocr_avail;
3080 if (host->ocr_avail_sdio)
3081 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3082 mmc->ocr_avail_sd = ocr_avail;
3083 if (host->ocr_avail_sd)
3084 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3085 else /* normal SD controllers don't support 1.8V */
3086 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3087 mmc->ocr_avail_mmc = ocr_avail;
3088 if (host->ocr_avail_mmc)
3089 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3090
3091 if (mmc->ocr_avail == 0) {
a3c76eb9 3092 pr_err("%s: Hardware doesn't report any "
b69c9058 3093 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3094 return -ENODEV;
146ad66e
PO		 3095 }
3096
d129bceb
PO		 3097 spin_lock_init(&host->lock);
3098
3099 /*
2134a922
PO		 3100 * Maximum number of segments. Depends on if the hardware
3101 * can do scatter/gather or not.
d129bceb 3102 */
2134a922 3103 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3104 mmc->max_segs = 128;
a13abc7b 3105 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3106 mmc->max_segs = 1;
2134a922 3107 else /* PIO */
a36274e0 3108 mmc->max_segs = 128;
d129bceb
PO		 3109
3110 /*
bab76961 3111 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3112 * size (512KiB).
d129bceb 3113 */
55db890a 3114 mmc->max_req_size = 524288;
d129bceb
PO		 3115
3116 /*
3117 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3118 * of bytes. When doing hardware scatter/gather, each entry cannot
3119 * be larger than 64 KiB though.
d129bceb 3120 */
30652aa3
OJ		 3121 if (host->flags & SDHCI_USE_ADMA) {
3122 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3123 mmc->max_seg_size = 65535;
3124 else
3125 mmc->max_seg_size = 65536;
3126 } else {
2134a922 3127 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3128 }
d129bceb 3129
fe4a3c7a
PO		 3130 /*
3131 * Maximum block size. This varies from controller to controller and
3132 * is specified in the capabilities register.
3133 */
0633f654
AV		 3134 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3135 mmc->max_blk_size = 2;
3136 } else {
f2119df6 3137 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3138 SDHCI_MAX_BLOCK_SHIFT;
3139 if (mmc->max_blk_size >= 3) {
a3c76eb9 3140 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3141 "assuming 512 bytes\n", mmc_hostname(mmc));
3142 mmc->max_blk_size = 0;
3143 }
3144 }
3145
3146 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3147
55db890a
PO		 3148 /*
3149 * Maximum block count.
3150 */
1388eefd 3151 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3152
d129bceb
PO		 3153 /*
3154 * Init tasklets.
3155 */
3156 tasklet_init(&host->card_tasklet,
3157 sdhci_tasklet_card, (unsigned long)host);
3158 tasklet_init(&host->finish_tasklet,
3159 sdhci_tasklet_finish, (unsigned long)host);
3160
e4cad1b5 3161 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3162
cf2b5eea 3163 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3164 init_waitqueue_head(&host->buf_ready_int);
3165
cf2b5eea
AN		 3166 /* Initialize re-tuning timer */
3167 init_timer(&host->tuning_timer);
3168 host->tuning_timer.data = (unsigned long)host;
3169 host->tuning_timer.function = sdhci_tuning_timer;
3170 }
3171
dace1453 3172 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 3173 mmc_hostname(mmc), host);
0fc81ee3
MB		 3174 if (ret) {
3175 pr_err("%s: Failed to request IRQ %d: %d\n",
3176 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3177 goto untasklet;
0fc81ee3 3178 }
d129bceb 3179
2f4cbb3d 3180 sdhci_init(host, 0);
d129bceb
PO		 3181
3182#ifdef CONFIG_MMC_DEBUG
3183 sdhci_dumpregs(host);
3184#endif
3185
f9134319 3186#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3187 snprintf(host->led_name, sizeof(host->led_name),
3188 "%s::", mmc_hostname(mmc));
3189 host->led.name = host->led_name;
2f730fec
PO		 3190 host->led.brightness = LED_OFF;
3191 host->led.default_trigger = mmc_hostname(mmc);
3192 host->led.brightness_set = sdhci_led_control;
3193
b8c86fc5 3194 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3195 if (ret) {
3196 pr_err("%s: Failed to register LED device: %d\n",
3197 mmc_hostname(mmc), ret);
2f730fec 3198 goto reset;
0fc81ee3 3199 }
2f730fec
PO		 3200#endif
3201
5f25a66f
PO		 3202 mmiowb();
3203
d129bceb
PO		 3204 mmc_add_host(mmc);
3205
a3c76eb9 3206 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3207 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3208 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3209 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3210
7260cf5e
AV		 3211 sdhci_enable_card_detection(host);
3212
d129bceb
PO		 3213 return 0;
3214
f9134319 3215#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3216reset:
3217 sdhci_reset(host, SDHCI_RESET_ALL);
b0a8dece 3218 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2f730fec
PO		 3219 free_irq(host->irq, host);
3220#endif
8ef1a143 3221untasklet:
d129bceb
PO		 3222 tasklet_kill(&host->card_tasklet);
3223 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3224
3225 return ret;
3226}
3227
b8c86fc5 3228EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3229
1e72859e 3230void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3231{
1e72859e
PO		 3232 unsigned long flags;
3233
3234 if (dead) {
3235 spin_lock_irqsave(&host->lock, flags);
3236
3237 host->flags |= SDHCI_DEVICE_DEAD;
3238
3239 if (host->mrq) {
a3c76eb9 3240 pr_err("%s: Controller removed during "
1e72859e
PO		 3241 " transfer!\n", mmc_hostname(host->mmc));
3242
3243 host->mrq->cmd->error = -ENOMEDIUM;
3244 tasklet_schedule(&host->finish_tasklet);
3245 }
3246
3247 spin_unlock_irqrestore(&host->lock, flags);
3248 }
3249
7260cf5e
AV		 3250 sdhci_disable_card_detection(host);
3251
b8c86fc5 3252 mmc_remove_host(host->mmc);
d129bceb 3253
f9134319 3254#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3255 led_classdev_unregister(&host->led);
3256#endif
3257
1e72859e
PO		 3258 if (!dead)
3259 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 3260
b0a8dece 3261 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
d129bceb
PO		 3262 free_irq(host->irq, host);
3263
3264 del_timer_sync(&host->timer);
3265
3266 tasklet_kill(&host->card_tasklet);
3267 tasklet_kill(&host->finish_tasklet);
2134a922 3268
77dcb3f4
PR		 3269 if (host->vmmc) {
3270 regulator_disable(host->vmmc);
9bea3c85 3271 regulator_put(host->vmmc);
77dcb3f4 3272 }
9bea3c85 3273
6231f3de
PR		 3274 if (host->vqmmc) {
3275 regulator_disable(host->vqmmc);
3276 regulator_put(host->vqmmc);
3277 }
3278
2134a922
PO		 3279 kfree(host->adma_desc);
3280 kfree(host->align_buffer);
3281
3282 host->adma_desc = NULL;
3283 host->align_buffer = NULL;
d129bceb
PO		 3284}
3285
b8c86fc5 3286EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3287
b8c86fc5 3288void sdhci_free_host(struct sdhci_host *host)
d129bceb 3289{
b8c86fc5 3290 mmc_free_host(host->mmc);
d129bceb
PO		 3291}
3292
b8c86fc5 3293EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3294
3295/*****************************************************************************\
3296 * *
3297 * Driver init/exit *
3298 * *
3299\*****************************************************************************/
3300
3301static int __init sdhci_drv_init(void)
3302{
a3c76eb9 3303 pr_info(DRIVER_NAME
52fbf9c9 3304 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3305 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3306
b8c86fc5 3307 return 0;
d129bceb
PO		 3308}
3309
3310static void __exit sdhci_drv_exit(void)
3311{
d129bceb
PO		 3312}
3313
3314module_init(sdhci_drv_init);
3315module_exit(sdhci_drv_exit);
3316
df673b22 3317module_param(debug_quirks, uint, 0444);
66fd8ad5 3318module_param(debug_quirks2, uint, 0444);
67435274 3319
32710e8f 3320MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3321MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3322MODULE_LICENSE("GPL");
67435274 3323
df673b22 3324MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3325MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
This page took 0.810515 seconds and 5 git commands to generate.