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mmc: sdhci: add hooks for platform specific tuning
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
52static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 55static void sdhci_tuning_timer(unsigned long data);
52983382 56static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 57
66fd8ad5
AH		 58#ifdef CONFIG_PM_RUNTIME
59static int sdhci_runtime_pm_get(struct sdhci_host *host);
60static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 61static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
62static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 63#else
64static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
65{
66 return 0;
67}
68static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
69{
70 return 0;
71}
f0710a55
AH		 72static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
73{
74}
75static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
76{
77}
66fd8ad5
AH		 78#endif
79
d129bceb
PO		 80static void sdhci_dumpregs(struct sdhci_host *host)
81{
a3c76eb9 82 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 83 mmc_hostname(host->mmc));
d129bceb 84
a3c76eb9 85 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 86 sdhci_readl(host, SDHCI_DMA_ADDRESS),
87 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 88 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readw(host, SDHCI_BLOCK_SIZE),
90 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readl(host, SDHCI_ARGUMENT),
93 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readl(host, SDHCI_PRESENT_STATE),
96 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readb(host, SDHCI_POWER_CONTROL),
99 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 100 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
102 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 104 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
105 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 107 sdhci_readl(host, SDHCI_INT_ENABLE),
108 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 109 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 110 sdhci_readw(host, SDHCI_ACMD12_ERR),
111 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 112 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 113 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 114 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 115 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 116 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 117 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 118 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 119 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 120
be3f4ae0 121 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 122 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 123 readl(host->ioaddr + SDHCI_ADMA_ERROR),
124 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
125
a3c76eb9 126 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 127}
128
129/*****************************************************************************\
130 * *
131 * Low level functions *
132 * *
133\*****************************************************************************/
134
7260cf5e
AV		 135static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
136{
137 u32 ier;
138
139 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
140 ier &= ~clear;
141 ier |= set;
142 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
143 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
144}
145
146static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
147{
148 sdhci_clear_set_irqs(host, 0, irqs);
149}
150
151static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
152{
153 sdhci_clear_set_irqs(host, irqs, 0);
154}
155
156static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
157{
d25928d1 158 u32 present, irqs;
7260cf5e 159
c79396c1 160 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 161 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 162 return;
163
d25928d1
SG		 164 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
165 SDHCI_CARD_PRESENT;
166 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
167
7260cf5e
AV		 168 if (enable)
169 sdhci_unmask_irqs(host, irqs);
170 else
171 sdhci_mask_irqs(host, irqs);
172}
173
174static void sdhci_enable_card_detection(struct sdhci_host *host)
175{
176 sdhci_set_card_detection(host, true);
177}
178
179static void sdhci_disable_card_detection(struct sdhci_host *host)
180{
181 sdhci_set_card_detection(host, false);
182}
183
d129bceb
PO		 184static void sdhci_reset(struct sdhci_host *host, u8 mask)
185{
e16514d8 186 unsigned long timeout;
063a9dbb 187 u32 uninitialized_var(ier);
e16514d8 188
b8c86fc5 189 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 190 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 191 SDHCI_CARD_PRESENT))
192 return;
193 }
194
063a9dbb
AV		 195 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
196 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
197
393c1a34
PR		 198 if (host->ops->platform_reset_enter)
199 host->ops->platform_reset_enter(host, mask);
200
4e4141a5 201 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 202
f0710a55 203 if (mask & SDHCI_RESET_ALL) {
d129bceb 204 host->clock = 0;
f0710a55
AH		 205 /* Reset-all turns off SD Bus Power */
206 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
207 sdhci_runtime_pm_bus_off(host);
208 }
d129bceb 209
e16514d8
PO		 210 /* Wait max 100 ms */
211 timeout = 100;
212
213 /* hw clears the bit when it's done */
4e4141a5 214 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 215 if (timeout == 0) {
a3c76eb9 216 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 217 mmc_hostname(host->mmc), (int)mask);
218 sdhci_dumpregs(host);
219 return;
220 }
221 timeout--;
222 mdelay(1);
d129bceb 223 }
063a9dbb 224
393c1a34
PR		 225 if (host->ops->platform_reset_exit)
226 host->ops->platform_reset_exit(host, mask);
227
063a9dbb
AV		 228 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
229 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
3abc1e80
SX		 230
231 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
232 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
233 host->ops->enable_dma(host);
234 }
d129bceb
PO		 235}
236
2f4cbb3d
NP		 237static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
238
239static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 240{
2f4cbb3d
NP		 241 if (soft)
242 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
243 else
244 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 245
7260cf5e
AV		 246 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
247 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 248 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
249 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 250 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 251
252 if (soft) {
253 /* force clock reconfiguration */
254 host->clock = 0;
255 sdhci_set_ios(host->mmc, &host->mmc->ios);
256 }
7260cf5e 257}
d129bceb 258
7260cf5e
AV		 259static void sdhci_reinit(struct sdhci_host *host)
260{
2f4cbb3d 261 sdhci_init(host, 0);
b67c6b41
AL		 262 /*
263 * Retuning stuffs are affected by different cards inserted and only
264 * applicable to UHS-I cards. So reset these fields to their initial
265 * value when card is removed.
266 */
973905fe
AL		 267 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
268 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
269
b67c6b41
AL		 270 del_timer_sync(&host->tuning_timer);
271 host->flags &= ~SDHCI_NEEDS_RETUNING;
272 host->mmc->max_blk_count =
273 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
274 }
7260cf5e 275 sdhci_enable_card_detection(host);
d129bceb
PO		 276}
277
278static void sdhci_activate_led(struct sdhci_host *host)
279{
280 u8 ctrl;
281
4e4141a5 282 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 283 ctrl |= SDHCI_CTRL_LED;
4e4141a5 284 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 285}
286
287static void sdhci_deactivate_led(struct sdhci_host *host)
288{
289 u8 ctrl;
290
4e4141a5 291 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 292 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 293 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 294}
295
f9134319 296#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 297static void sdhci_led_control(struct led_classdev *led,
298 enum led_brightness brightness)
299{
300 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
301 unsigned long flags;
302
303 spin_lock_irqsave(&host->lock, flags);
304
66fd8ad5
AH		 305 if (host->runtime_suspended)
306 goto out;
307
2f730fec
PO		 308 if (brightness == LED_OFF)
309 sdhci_deactivate_led(host);
310 else
311 sdhci_activate_led(host);
66fd8ad5 312out:
2f730fec
PO		 313 spin_unlock_irqrestore(&host->lock, flags);
314}
315#endif
316
d129bceb
PO		 317/*****************************************************************************\
318 * *
319 * Core functions *
320 * *
321\*****************************************************************************/
322
a406f5a3 323static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 324{
7659150c
PO		 325 unsigned long flags;
326 size_t blksize, len, chunk;
7244b85b 327 u32 uninitialized_var(scratch);
7659150c 328 u8 *buf;
d129bceb 329
a406f5a3 330 DBG("PIO reading\n");
d129bceb 331
a406f5a3 332 blksize = host->data->blksz;
7659150c 333 chunk = 0;
d129bceb 334
7659150c 335 local_irq_save(flags);
d129bceb 336
a406f5a3 337 while (blksize) {
7659150c
PO		 338 if (!sg_miter_next(&host->sg_miter))
339 BUG();
d129bceb 340
7659150c 341 len = min(host->sg_miter.length, blksize);
d129bceb 342
7659150c
PO		 343 blksize -= len;
344 host->sg_miter.consumed = len;
14d836e7 345
7659150c 346 buf = host->sg_miter.addr;
d129bceb 347
7659150c
PO		 348 while (len) {
349 if (chunk == 0) {
4e4141a5 350 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 351 chunk = 4;
a406f5a3 352 }
7659150c
PO		 353
354 *buf = scratch & 0xFF;
355
356 buf++;
357 scratch >>= 8;
358 chunk--;
359 len--;
d129bceb 360 }
a406f5a3 361 }
7659150c
PO		 362
363 sg_miter_stop(&host->sg_miter);
364
365 local_irq_restore(flags);
a406f5a3 366}
d129bceb 367
a406f5a3
PO		 368static void sdhci_write_block_pio(struct sdhci_host *host)
369{
7659150c
PO		 370 unsigned long flags;
371 size_t blksize, len, chunk;
372 u32 scratch;
373 u8 *buf;
d129bceb 374
a406f5a3
PO		 375 DBG("PIO writing\n");
376
377 blksize = host->data->blksz;
7659150c
PO		 378 chunk = 0;
379 scratch = 0;
d129bceb 380
7659150c 381 local_irq_save(flags);
d129bceb 382
a406f5a3 383 while (blksize) {
7659150c
PO		 384 if (!sg_miter_next(&host->sg_miter))
385 BUG();
a406f5a3 386
7659150c
PO		 387 len = min(host->sg_miter.length, blksize);
388
389 blksize -= len;
390 host->sg_miter.consumed = len;
391
392 buf = host->sg_miter.addr;
d129bceb 393
7659150c
PO		 394 while (len) {
395 scratch |= (u32)*buf << (chunk * 8);
396
397 buf++;
398 chunk++;
399 len--;
400
401 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 402 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 403 chunk = 0;
404 scratch = 0;
d129bceb 405 }
d129bceb
PO		 406 }
407 }
7659150c
PO		 408
409 sg_miter_stop(&host->sg_miter);
410
411 local_irq_restore(flags);
a406f5a3
PO		 412}
413
414static void sdhci_transfer_pio(struct sdhci_host *host)
415{
416 u32 mask;
417
418 BUG_ON(!host->data);
419
7659150c 420 if (host->blocks == 0)
a406f5a3
PO		 421 return;
422
423 if (host->data->flags & MMC_DATA_READ)
424 mask = SDHCI_DATA_AVAILABLE;
425 else
426 mask = SDHCI_SPACE_AVAILABLE;
427
4a3cba32
PO		 428 /*
429 * Some controllers (JMicron JMB38x) mess up the buffer bits
430 * for transfers < 4 bytes. As long as it is just one block,
431 * we can ignore the bits.
432 */
433 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
434 (host->data->blocks == 1))
435 mask = ~0;
436
4e4141a5 437 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 438 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
439 udelay(100);
440
a406f5a3
PO		 441 if (host->data->flags & MMC_DATA_READ)
442 sdhci_read_block_pio(host);
443 else
444 sdhci_write_block_pio(host);
d129bceb 445
7659150c
PO		 446 host->blocks--;
447 if (host->blocks == 0)
a406f5a3 448 break;
a406f5a3 449 }
d129bceb 450
a406f5a3 451 DBG("PIO transfer complete.\n");
d129bceb
PO		 452}
453
2134a922
PO		 454static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
455{
456 local_irq_save(*flags);
482fce99 457 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 458}
459
460static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
461{
482fce99 462 kunmap_atomic(buffer);
2134a922
PO		 463 local_irq_restore(*flags);
464}
465
118cd17d
BD		 466static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
467{
9e506f35
BD		 468 __le32 *dataddr = (__le32 __force *)(desc + 4);
469 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 470
9e506f35
BD		 471 /* SDHCI specification says ADMA descriptors should be 4 byte
472 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 473
9e506f35
BD		 474 cmdlen[0] = cpu_to_le16(cmd);
475 cmdlen[1] = cpu_to_le16(len);
476
477 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 478}
479
8f1934ce 480static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 481 struct mmc_data *data)
482{
483 int direction;
484
485 u8 *desc;
486 u8 *align;
487 dma_addr_t addr;
488 dma_addr_t align_addr;
489 int len, offset;
490
491 struct scatterlist *sg;
492 int i;
493 char *buffer;
494 unsigned long flags;
495
496 /*
497 * The spec does not specify endianness of descriptor table.
498 * We currently guess that it is LE.
499 */
500
501 if (data->flags & MMC_DATA_READ)
502 direction = DMA_FROM_DEVICE;
503 else
504 direction = DMA_TO_DEVICE;
505
506 /*
507 * The ADMA descriptor table is mapped further down as we
508 * need to fill it with data first.
509 */
510
511 host->align_addr = dma_map_single(mmc_dev(host->mmc),
512 host->align_buffer, 128 * 4, direction);
8d8bb39b 513 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 514 goto fail;
2134a922
PO		 515 BUG_ON(host->align_addr & 0x3);
516
517 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
518 data->sg, data->sg_len, direction);
8f1934ce
PO		 519 if (host->sg_count == 0)
520 goto unmap_align;
2134a922
PO		 521
522 desc = host->adma_desc;
523 align = host->align_buffer;
524
525 align_addr = host->align_addr;
526
527 for_each_sg(data->sg, sg, host->sg_count, i) {
528 addr = sg_dma_address(sg);
529 len = sg_dma_len(sg);
530
531 /*
532 * The SDHCI specification states that ADMA
533 * addresses must be 32-bit aligned. If they
534 * aren't, then we use a bounce buffer for
535 * the (up to three) bytes that screw up the
536 * alignment.
537 */
538 offset = (4 - (addr & 0x3)) & 0x3;
539 if (offset) {
540 if (data->flags & MMC_DATA_WRITE) {
541 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 542 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 543 memcpy(align, buffer, offset);
544 sdhci_kunmap_atomic(buffer, &flags);
545 }
546
118cd17d
BD		 547 /* tran, valid */
548 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 549
550 BUG_ON(offset > 65536);
551
2134a922
PO		 552 align += 4;
553 align_addr += 4;
554
555 desc += 8;
556
557 addr += offset;
558 len -= offset;
559 }
560
2134a922
PO		 561 BUG_ON(len > 65536);
562
118cd17d
BD		 563 /* tran, valid */
564 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 565 desc += 8;
566
567 /*
568 * If this triggers then we have a calculation bug
569 * somewhere. :/
570 */
571 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
572 }
573
70764a90
TA		 574 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
575 /*
576 * Mark the last descriptor as the terminating descriptor
577 */
578 if (desc != host->adma_desc) {
579 desc -= 8;
580 desc[0] |= 0x2; /* end */
581 }
582 } else {
583 /*
584 * Add a terminating entry.
585 */
2134a922 586
70764a90
TA		 587 /* nop, end, valid */
588 sdhci_set_adma_desc(desc, 0, 0, 0x3);
589 }
2134a922
PO		 590
591 /*
592 * Resync align buffer as we might have changed it.
593 */
594 if (data->flags & MMC_DATA_WRITE) {
595 dma_sync_single_for_device(mmc_dev(host->mmc),
596 host->align_addr, 128 * 4, direction);
597 }
598
599 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
600 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 601 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 602 goto unmap_entries;
2134a922 603 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 604
605 return 0;
606
607unmap_entries:
608 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
609 data->sg_len, direction);
610unmap_align:
611 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
612 128 * 4, direction);
613fail:
614 return -EINVAL;
2134a922
PO		 615}
616
617static void sdhci_adma_table_post(struct sdhci_host *host,
618 struct mmc_data *data)
619{
620 int direction;
621
622 struct scatterlist *sg;
623 int i, size;
624 u8 *align;
625 char *buffer;
626 unsigned long flags;
627
628 if (data->flags & MMC_DATA_READ)
629 direction = DMA_FROM_DEVICE;
630 else
631 direction = DMA_TO_DEVICE;
632
633 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
634 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
635
636 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
637 128 * 4, direction);
638
639 if (data->flags & MMC_DATA_READ) {
640 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
641 data->sg_len, direction);
642
643 align = host->align_buffer;
644
645 for_each_sg(data->sg, sg, host->sg_count, i) {
646 if (sg_dma_address(sg) & 0x3) {
647 size = 4 - (sg_dma_address(sg) & 0x3);
648
649 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 650 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 651 memcpy(buffer, align, size);
652 sdhci_kunmap_atomic(buffer, &flags);
653
654 align += 4;
655 }
656 }
657 }
658
659 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
660 data->sg_len, direction);
661}
662
a3c7778f 663static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 664{
1c8cde92 665 u8 count;
a3c7778f 666 struct mmc_data *data = cmd->data;
1c8cde92 667 unsigned target_timeout, current_timeout;
d129bceb 668
ee53ab5d
PO		 669 /*
670 * If the host controller provides us with an incorrect timeout
671 * value, just skip the check and use 0xE. The hardware may take
672 * longer to time out, but that's much better than having a too-short
673 * timeout value.
674 */
11a2f1b7 675 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 676 return 0xE;
e538fbe8 677
a3c7778f
AW		 678 /* Unspecified timeout, assume max */
679 if (!data && !cmd->cmd_timeout_ms)
680 return 0xE;
d129bceb 681
a3c7778f
AW		 682 /* timeout in us */
683 if (!data)
684 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 685 else {
686 target_timeout = data->timeout_ns / 1000;
687 if (host->clock)
688 target_timeout += data->timeout_clks / host->clock;
689 }
81b39802 690
1c8cde92
PO		 691 /*
692 * Figure out needed cycles.
693 * We do this in steps in order to fit inside a 32 bit int.
694 * The first step is the minimum timeout, which will have a
695 * minimum resolution of 6 bits:
696 * (1) 2^13*1000 > 2^22,
697 * (2) host->timeout_clk < 2^16
698 * =>
699 * (1) / (2) > 2^6
700 */
701 count = 0;
702 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
703 while (current_timeout < target_timeout) {
704 count++;
705 current_timeout <<= 1;
706 if (count >= 0xF)
707 break;
708 }
709
710 if (count >= 0xF) {
09eeff52
CB		 711 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
712 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 713 count = 0xE;
714 }
715
ee53ab5d
PO		 716 return count;
717}
718
6aa943ab
AV		 719static void sdhci_set_transfer_irqs(struct sdhci_host *host)
720{
721 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
722 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
723
724 if (host->flags & SDHCI_REQ_USE_DMA)
725 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
726 else
727 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
728}
729
a3c7778f 730static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 731{
732 u8 count;
2134a922 733 u8 ctrl;
a3c7778f 734 struct mmc_data *data = cmd->data;
8f1934ce 735 int ret;
ee53ab5d
PO		 736
737 WARN_ON(host->data);
738
a3c7778f
AW		 739 if (data || (cmd->flags & MMC_RSP_BUSY)) {
740 count = sdhci_calc_timeout(host, cmd);
741 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
742 }
743
744 if (!data)
ee53ab5d
PO		 745 return;
746
747 /* Sanity checks */
748 BUG_ON(data->blksz * data->blocks > 524288);
749 BUG_ON(data->blksz > host->mmc->max_blk_size);
750 BUG_ON(data->blocks > 65535);
751
752 host->data = data;
753 host->data_early = 0;
f6a03cbf 754 host->data->bytes_xfered = 0;
ee53ab5d 755
a13abc7b 756 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 757 host->flags |= SDHCI_REQ_USE_DMA;
758
2134a922
PO		 759 /*
760 * FIXME: This doesn't account for merging when mapping the
761 * scatterlist.
762 */
763 if (host->flags & SDHCI_REQ_USE_DMA) {
764 int broken, i;
765 struct scatterlist *sg;
766
767 broken = 0;
768 if (host->flags & SDHCI_USE_ADMA) {
769 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
770 broken = 1;
771 } else {
772 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
773 broken = 1;
774 }
775
776 if (unlikely(broken)) {
777 for_each_sg(data->sg, sg, data->sg_len, i) {
778 if (sg->length & 0x3) {
779 DBG("Reverting to PIO because of "
780 "transfer size (%d)\n",
781 sg->length);
782 host->flags &= ~SDHCI_REQ_USE_DMA;
783 break;
784 }
785 }
786 }
c9fddbc4
PO		 787 }
788
789 /*
790 * The assumption here being that alignment is the same after
791 * translation to device address space.
792 */
2134a922
PO		 793 if (host->flags & SDHCI_REQ_USE_DMA) {
794 int broken, i;
795 struct scatterlist *sg;
796
797 broken = 0;
798 if (host->flags & SDHCI_USE_ADMA) {
799 /*
800 * As we use 3 byte chunks to work around
801 * alignment problems, we need to check this
802 * quirk.
803 */
804 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
805 broken = 1;
806 } else {
807 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
808 broken = 1;
809 }
810
811 if (unlikely(broken)) {
812 for_each_sg(data->sg, sg, data->sg_len, i) {
813 if (sg->offset & 0x3) {
814 DBG("Reverting to PIO because of "
815 "bad alignment\n");
816 host->flags &= ~SDHCI_REQ_USE_DMA;
817 break;
818 }
819 }
820 }
821 }
822
8f1934ce
PO		 823 if (host->flags & SDHCI_REQ_USE_DMA) {
824 if (host->flags & SDHCI_USE_ADMA) {
825 ret = sdhci_adma_table_pre(host, data);
826 if (ret) {
827 /*
828 * This only happens when someone fed
829 * us an invalid request.
830 */
831 WARN_ON(1);
ebd6d357 832 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 833 } else {
4e4141a5
AV		 834 sdhci_writel(host, host->adma_addr,
835 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 836 }
837 } else {
c8b3e02e 838 int sg_cnt;
8f1934ce 839
c8b3e02e 840 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 841 data->sg, data->sg_len,
842 (data->flags & MMC_DATA_READ) ?
843 DMA_FROM_DEVICE :
844 DMA_TO_DEVICE);
c8b3e02e 845 if (sg_cnt == 0) {
8f1934ce
PO		 846 /*
847 * This only happens when someone fed
848 * us an invalid request.
849 */
850 WARN_ON(1);
ebd6d357 851 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 852 } else {
719a61b4 853 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 854 sdhci_writel(host, sg_dma_address(data->sg),
855 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 856 }
857 }
858 }
859
2134a922
PO		 860 /*
861 * Always adjust the DMA selection as some controllers
862 * (e.g. JMicron) can't do PIO properly when the selection
863 * is ADMA.
864 */
865 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 866 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 867 ctrl &= ~SDHCI_CTRL_DMA_MASK;
868 if ((host->flags & SDHCI_REQ_USE_DMA) &&
869 (host->flags & SDHCI_USE_ADMA))
870 ctrl |= SDHCI_CTRL_ADMA32;
871 else
872 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 873 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 874 }
875
8f1934ce 876 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 877 int flags;
878
879 flags = SG_MITER_ATOMIC;
880 if (host->data->flags & MMC_DATA_READ)
881 flags |= SG_MITER_TO_SG;
882 else
883 flags |= SG_MITER_FROM_SG;
884 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 885 host->blocks = data->blocks;
d129bceb 886 }
c7fa9963 887
6aa943ab
AV		 888 sdhci_set_transfer_irqs(host);
889
f6a03cbf
MV		 890 /* Set the DMA boundary value and block size */
891 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
892 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 893 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 894}
895
896static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 897 struct mmc_command *cmd)
c7fa9963
PO		 898{
899 u16 mode;
e89d456f 900 struct mmc_data *data = cmd->data;
c7fa9963 901
c7fa9963
PO		 902 if (data == NULL)
903 return;
904
e538fbe8
PO		 905 WARN_ON(!host->data);
906
c7fa9963 907 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 908 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
909 mode |= SDHCI_TRNS_MULTI;
910 /*
911 * If we are sending CMD23, CMD12 never gets sent
912 * on successful completion (so no Auto-CMD12).
913 */
914 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
915 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 916 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
917 mode |= SDHCI_TRNS_AUTO_CMD23;
918 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
919 }
c4512f79 920 }
8edf6371 921
c7fa9963
PO		 922 if (data->flags & MMC_DATA_READ)
923 mode |= SDHCI_TRNS_READ;
c9fddbc4 924 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 925 mode |= SDHCI_TRNS_DMA;
926
4e4141a5 927 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 928}
929
930static void sdhci_finish_data(struct sdhci_host *host)
931{
932 struct mmc_data *data;
d129bceb
PO		 933
934 BUG_ON(!host->data);
935
936 data = host->data;
937 host->data = NULL;
938
c9fddbc4 939 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 940 if (host->flags & SDHCI_USE_ADMA)
941 sdhci_adma_table_post(host, data);
942 else {
943 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
944 data->sg_len, (data->flags & MMC_DATA_READ) ?
945 DMA_FROM_DEVICE : DMA_TO_DEVICE);
946 }
d129bceb
PO		 947 }
948
949 /*
c9b74c5b
PO		 950 * The specification states that the block count register must
951 * be updated, but it does not specify at what point in the
952 * data flow. That makes the register entirely useless to read
953 * back so we have to assume that nothing made it to the card
954 * in the event of an error.
d129bceb 955 */
c9b74c5b
PO		 956 if (data->error)
957 data->bytes_xfered = 0;
d129bceb 958 else
c9b74c5b 959 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 960
e89d456f
AW		 961 /*
962 * Need to send CMD12 if -
963 * a) open-ended multiblock transfer (no CMD23)
964 * b) error in multiblock transfer
965 */
966 if (data->stop &&
967 (data->error ||
968 !host->mrq->sbc)) {
969
d129bceb
PO		 970 /*
971 * The controller needs a reset of internal state machines
972 * upon error conditions.
973 */
17b0429d 974 if (data->error) {
d129bceb
PO		 975 sdhci_reset(host, SDHCI_RESET_CMD);
976 sdhci_reset(host, SDHCI_RESET_DATA);
977 }
978
979 sdhci_send_command(host, data->stop);
980 } else
981 tasklet_schedule(&host->finish_tasklet);
982}
983
984static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
985{
986 int flags;
fd2208d7 987 u32 mask;
7cb2c76f 988 unsigned long timeout;
d129bceb
PO		 989
990 WARN_ON(host->cmd);
991
d129bceb 992 /* Wait max 10 ms */
7cb2c76f 993 timeout = 10;
fd2208d7
PO		 994
995 mask = SDHCI_CMD_INHIBIT;
996 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
997 mask |= SDHCI_DATA_INHIBIT;
998
999 /* We shouldn't wait for data inihibit for stop commands, even
1000 though they might use busy signaling */
1001 if (host->mrq->data && (cmd == host->mrq->data->stop))
1002 mask &= ~SDHCI_DATA_INHIBIT;
1003
4e4141a5 1004 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1005 if (timeout == 0) {
a3c76eb9 1006 pr_err("%s: Controller never released "
acf1da45 1007 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1008 sdhci_dumpregs(host);
17b0429d 1009 cmd->error = -EIO;
d129bceb
PO		 1010 tasklet_schedule(&host->finish_tasklet);
1011 return;
1012 }
7cb2c76f
PO		 1013 timeout--;
1014 mdelay(1);
1015 }
d129bceb
PO		 1016
1017 mod_timer(&host->timer, jiffies + 10 * HZ);
1018
1019 host->cmd = cmd;
1020
a3c7778f 1021 sdhci_prepare_data(host, cmd);
d129bceb 1022
4e4141a5 1023 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1024
e89d456f 1025 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1026
d129bceb 1027 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1028 pr_err("%s: Unsupported response type!\n",
d129bceb 1029 mmc_hostname(host->mmc));
17b0429d 1030 cmd->error = -EINVAL;
d129bceb
PO		 1031 tasklet_schedule(&host->finish_tasklet);
1032 return;
1033 }
1034
1035 if (!(cmd->flags & MMC_RSP_PRESENT))
1036 flags = SDHCI_CMD_RESP_NONE;
1037 else if (cmd->flags & MMC_RSP_136)
1038 flags = SDHCI_CMD_RESP_LONG;
1039 else if (cmd->flags & MMC_RSP_BUSY)
1040 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1041 else
1042 flags = SDHCI_CMD_RESP_SHORT;
1043
1044 if (cmd->flags & MMC_RSP_CRC)
1045 flags |= SDHCI_CMD_CRC;
1046 if (cmd->flags & MMC_RSP_OPCODE)
1047 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1048
1049 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1050 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1051 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1052 flags |= SDHCI_CMD_DATA;
1053
4e4141a5 1054 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1055}
1056
1057static void sdhci_finish_command(struct sdhci_host *host)
1058{
1059 int i;
1060
1061 BUG_ON(host->cmd == NULL);
1062
1063 if (host->cmd->flags & MMC_RSP_PRESENT) {
1064 if (host->cmd->flags & MMC_RSP_136) {
1065 /* CRC is stripped so we need to do some shifting. */
1066 for (i = 0;i < 4;i++) {
4e4141a5 1067 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1068 SDHCI_RESPONSE + (3-i)*4) << 8;
1069 if (i != 3)
1070 host->cmd->resp[i] |=
4e4141a5 1071 sdhci_readb(host,
d129bceb
PO		 1072 SDHCI_RESPONSE + (3-i)*4-1);
1073 }
1074 } else {
4e4141a5 1075 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1076 }
1077 }
1078
17b0429d 1079 host->cmd->error = 0;
d129bceb 1080
e89d456f
AW		 1081 /* Finished CMD23, now send actual command. */
1082 if (host->cmd == host->mrq->sbc) {
1083 host->cmd = NULL;
1084 sdhci_send_command(host, host->mrq->cmd);
1085 } else {
e538fbe8 1086
e89d456f
AW		 1087 /* Processed actual command. */
1088 if (host->data && host->data_early)
1089 sdhci_finish_data(host);
d129bceb 1090
e89d456f
AW		 1091 if (!host->cmd->data)
1092 tasklet_schedule(&host->finish_tasklet);
1093
1094 host->cmd = NULL;
1095 }
d129bceb
PO		 1096}
1097
52983382
KL		 1098static u16 sdhci_get_preset_value(struct sdhci_host *host)
1099{
1100 u16 ctrl, preset = 0;
1101
1102 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1103
1104 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1105 case SDHCI_CTRL_UHS_SDR12:
1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1107 break;
1108 case SDHCI_CTRL_UHS_SDR25:
1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1110 break;
1111 case SDHCI_CTRL_UHS_SDR50:
1112 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1113 break;
1114 case SDHCI_CTRL_UHS_SDR104:
1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1116 break;
1117 case SDHCI_CTRL_UHS_DDR50:
1118 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1119 break;
1120 default:
1121 pr_warn("%s: Invalid UHS-I mode selected\n",
1122 mmc_hostname(host->mmc));
1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1124 break;
1125 }
1126 return preset;
1127}
1128
d129bceb
PO		 1129static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1130{
c3ed3877 1131 int div = 0; /* Initialized for compiler warning */
df16219f 1132 int real_div = div, clk_mul = 1;
c3ed3877 1133 u16 clk = 0;
7cb2c76f 1134 unsigned long timeout;
d129bceb 1135
30832ab5 1136 if (clock && clock == host->clock)
d129bceb
PO		 1137 return;
1138
df16219f
GC		 1139 host->mmc->actual_clock = 0;
1140
8114634c
AV		 1141 if (host->ops->set_clock) {
1142 host->ops->set_clock(host, clock);
1143 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1144 return;
1145 }
1146
4e4141a5 1147 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1148
1149 if (clock == 0)
1150 goto out;
1151
85105c53 1152 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1153 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1154 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1155 u16 pre_val;
1156
1157 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1158 pre_val = sdhci_get_preset_value(host);
1159 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1160 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1161 if (host->clk_mul &&
1162 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1163 clk = SDHCI_PROG_CLOCK_MODE;
1164 real_div = div + 1;
1165 clk_mul = host->clk_mul;
1166 } else {
1167 real_div = max_t(int, 1, div << 1);
1168 }
1169 goto clock_set;
1170 }
1171
c3ed3877
AN		 1172 /*
1173 * Check if the Host Controller supports Programmable Clock
1174 * Mode.
1175 */
1176 if (host->clk_mul) {
52983382
KL		 1177 for (div = 1; div <= 1024; div++) {
1178 if ((host->max_clk * host->clk_mul / div)
1179 <= clock)
1180 break;
1181 }
c3ed3877 1182 /*
52983382
KL		 1183 * Set Programmable Clock Mode in the Clock
1184 * Control register.
c3ed3877 1185 */
52983382
KL		 1186 clk = SDHCI_PROG_CLOCK_MODE;
1187 real_div = div;
1188 clk_mul = host->clk_mul;
1189 div--;
c3ed3877
AN		 1190 } else {
1191 /* Version 3.00 divisors must be a multiple of 2. */
1192 if (host->max_clk <= clock)
1193 div = 1;
1194 else {
1195 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1196 div += 2) {
1197 if ((host->max_clk / div) <= clock)
1198 break;
1199 }
85105c53 1200 }
df16219f 1201 real_div = div;
c3ed3877 1202 div >>= 1;
85105c53
ZG		 1203 }
1204 } else {
1205 /* Version 2.00 divisors must be a power of 2. */
0397526d 1206 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1207 if ((host->max_clk / div) <= clock)
1208 break;
1209 }
df16219f 1210 real_div = div;
c3ed3877 1211 div >>= 1;
d129bceb 1212 }
d129bceb 1213
52983382 1214clock_set:
df16219f
GC		 1215 if (real_div)
1216 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1217
c3ed3877 1218 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1219 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1220 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1221 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1222 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1223
27f6cb16
CB		 1224 /* Wait max 20 ms */
1225 timeout = 20;
4e4141a5 1226 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1227 & SDHCI_CLOCK_INT_STABLE)) {
1228 if (timeout == 0) {
a3c76eb9 1229 pr_err("%s: Internal clock never "
acf1da45 1230 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1231 sdhci_dumpregs(host);
1232 return;
1233 }
7cb2c76f
PO		 1234 timeout--;
1235 mdelay(1);
1236 }
d129bceb
PO		 1237
1238 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1239 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1240
1241out:
1242 host->clock = clock;
1243}
1244
8213af3b
AS		 1245static inline void sdhci_update_clock(struct sdhci_host *host)
1246{
1247 unsigned int clock;
1248
1249 clock = host->clock;
1250 host->clock = 0;
1251 sdhci_set_clock(host, clock);
1252}
1253
ceb6143b 1254static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1255{
8364248a 1256 u8 pwr = 0;
146ad66e 1257
8364248a 1258 if (power != (unsigned short)-1) {
ae628903
PO		 1259 switch (1 << power) {
1260 case MMC_VDD_165_195:
1261 pwr = SDHCI_POWER_180;
1262 break;
1263 case MMC_VDD_29_30:
1264 case MMC_VDD_30_31:
1265 pwr = SDHCI_POWER_300;
1266 break;
1267 case MMC_VDD_32_33:
1268 case MMC_VDD_33_34:
1269 pwr = SDHCI_POWER_330;
1270 break;
1271 default:
1272 BUG();
1273 }
1274 }
1275
1276 if (host->pwr == pwr)
ceb6143b 1277 return -1;
146ad66e 1278
ae628903
PO		 1279 host->pwr = pwr;
1280
1281 if (pwr == 0) {
4e4141a5 1282 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1283 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1284 sdhci_runtime_pm_bus_off(host);
ceb6143b 1285 return 0;
9e9dc5f2
DS		 1286 }
1287
1288 /*
1289 * Spec says that we should clear the power reg before setting
1290 * a new value. Some controllers don't seem to like this though.
1291 */
b8c86fc5 1292 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1293 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1294
e08c1694 1295 /*
c71f6512 1296 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1297 * and set turn on power at the same time, so set the voltage first.
1298 */
11a2f1b7 1299 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1300 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1301
ae628903 1302 pwr |= SDHCI_POWER_ON;
146ad66e 1303
ae628903 1304 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1305
f0710a55
AH		 1306 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1307 sdhci_runtime_pm_bus_on(host);
1308
557b0697
HW		 1309 /*
1310 * Some controllers need an extra 10ms delay of 10ms before they
1311 * can apply clock after applying power
1312 */
11a2f1b7 1313 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1314 mdelay(10);
ceb6143b
AH		 1315
1316 return power;
146ad66e
PO		 1317}
1318
d129bceb
PO		 1319/*****************************************************************************\
1320 * *
1321 * MMC callbacks *
1322 * *
1323\*****************************************************************************/
1324
1325static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1326{
1327 struct sdhci_host *host;
505a8680 1328 int present;
d129bceb 1329 unsigned long flags;
473b095a 1330 u32 tuning_opcode;
d129bceb
PO		 1331
1332 host = mmc_priv(mmc);
1333
66fd8ad5
AH		 1334 sdhci_runtime_pm_get(host);
1335
d129bceb
PO		 1336 spin_lock_irqsave(&host->lock, flags);
1337
1338 WARN_ON(host->mrq != NULL);
1339
f9134319 1340#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1341 sdhci_activate_led(host);
2f730fec 1342#endif
e89d456f
AW		 1343
1344 /*
1345 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1346 * requests if Auto-CMD12 is enabled.
1347 */
1348 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1349 if (mrq->stop) {
1350 mrq->data->stop = NULL;
1351 mrq->stop = NULL;
1352 }
1353 }
d129bceb
PO		 1354
1355 host->mrq = mrq;
1356
505a8680
SG		 1357 /*
1358 * Firstly check card presence from cd-gpio. The return could
1359 * be one of the following possibilities:
1360 * negative: cd-gpio is not available
1361 * zero: cd-gpio is used, and card is removed
1362 * one: cd-gpio is used, and card is present
1363 */
1364 present = mmc_gpio_get_cd(host->mmc);
1365 if (present < 0) {
1366 /* If polling, assume that the card is always present. */
1367 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1368 present = 1;
1369 else
1370 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1371 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1372 }
1373
68d1fb7e 1374 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1375 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1376 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1377 } else {
1378 u32 present_state;
1379
1380 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1381 /*
1382 * Check if the re-tuning timer has already expired and there
1383 * is no on-going data transfer. If so, we need to execute
1384 * tuning procedure before sending command.
1385 */
1386 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1387 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1388 if (mmc->card) {
1389 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1390 tuning_opcode =
1391 mmc->card->type == MMC_TYPE_MMC ?
1392 MMC_SEND_TUNING_BLOCK_HS200 :
1393 MMC_SEND_TUNING_BLOCK;
1394 spin_unlock_irqrestore(&host->lock, flags);
1395 sdhci_execute_tuning(mmc, tuning_opcode);
1396 spin_lock_irqsave(&host->lock, flags);
1397
1398 /* Restore original mmc_request structure */
1399 host->mrq = mrq;
1400 }
cf2b5eea
AN		 1401 }
1402
8edf6371 1403 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1404 sdhci_send_command(host, mrq->sbc);
1405 else
1406 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1407 }
d129bceb 1408
5f25a66f 1409 mmiowb();
d129bceb
PO		 1410 spin_unlock_irqrestore(&host->lock, flags);
1411}
1412
66fd8ad5 1413static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1414{
d129bceb 1415 unsigned long flags;
ceb6143b 1416 int vdd_bit = -1;
d129bceb
PO		 1417 u8 ctrl;
1418
d129bceb
PO		 1419 spin_lock_irqsave(&host->lock, flags);
1420
ceb6143b
AH		 1421 if (host->flags & SDHCI_DEVICE_DEAD) {
1422 spin_unlock_irqrestore(&host->lock, flags);
1423 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1424 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1425 return;
1426 }
1e72859e 1427
d129bceb
PO		 1428 /*
1429 * Reset the chip on each power off.
1430 * Should clear out any weird states.
1431 */
1432 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1433 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1434 sdhci_reinit(host);
d129bceb
PO		 1435 }
1436
52983382
KL		 1437 if (host->version >= SDHCI_SPEC_300 &&
1438 (ios->power_mode == MMC_POWER_UP))
1439 sdhci_enable_preset_value(host, false);
1440
d129bceb
PO		 1441 sdhci_set_clock(host, ios->clock);
1442
1443 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1444 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1445 else
ceb6143b
AH		 1446 vdd_bit = sdhci_set_power(host, ios->vdd);
1447
1448 if (host->vmmc && vdd_bit != -1) {
1449 spin_unlock_irqrestore(&host->lock, flags);
1450 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1451 spin_lock_irqsave(&host->lock, flags);
1452 }
d129bceb 1453
643a81ff
PR		 1454 if (host->ops->platform_send_init_74_clocks)
1455 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1456
15ec4461
PR		 1457 /*
1458 * If your platform has 8-bit width support but is not a v3 controller,
1459 * or if it requires special setup code, you should implement that in
7bc088d3 1460 * platform_bus_width().
15ec4461 1461 */
7bc088d3
SH		 1462 if (host->ops->platform_bus_width) {
1463 host->ops->platform_bus_width(host, ios->bus_width);
1464 } else {
15ec4461
PR		 1465 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1466 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1467 ctrl &= ~SDHCI_CTRL_4BITBUS;
1468 if (host->version >= SDHCI_SPEC_300)
1469 ctrl |= SDHCI_CTRL_8BITBUS;
1470 } else {
1471 if (host->version >= SDHCI_SPEC_300)
1472 ctrl &= ~SDHCI_CTRL_8BITBUS;
1473 if (ios->bus_width == MMC_BUS_WIDTH_4)
1474 ctrl |= SDHCI_CTRL_4BITBUS;
1475 else
1476 ctrl &= ~SDHCI_CTRL_4BITBUS;
1477 }
1478 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1479 }
ae6d6c92 1480
15ec4461 1481 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1482
3ab9c8da
PR		 1483 if ((ios->timing == MMC_TIMING_SD_HS ||
1484 ios->timing == MMC_TIMING_MMC_HS)
1485 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1486 ctrl |= SDHCI_CTRL_HISPD;
1487 else
1488 ctrl &= ~SDHCI_CTRL_HISPD;
1489
d6d50a15 1490 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1491 u16 clk, ctrl_2;
49c468fc
AN		 1492
1493 /* In case of UHS-I modes, set High Speed Enable */
069c9f14
G		 1494 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1495 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1496 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1497 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1498 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1499 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1500
1501 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1502 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1503 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1504 /*
1505 * We only need to set Driver Strength if the
1506 * preset value enable is not set.
1507 */
1508 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1509 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1510 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1511 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1512 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1513
1514 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1515 } else {
1516 /*
1517 * According to SDHC Spec v3.00, if the Preset Value
1518 * Enable in the Host Control 2 register is set, we
1519 * need to reset SD Clock Enable before changing High
1520 * Speed Enable to avoid generating clock gliches.
1521 */
758535c4
AN		 1522
1523 /* Reset SD Clock Enable */
1524 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1525 clk &= ~SDHCI_CLOCK_CARD_EN;
1526 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1527
1528 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1529
1530 /* Re-enable SD Clock */
8213af3b 1531 sdhci_update_clock(host);
d6d50a15 1532 }
49c468fc 1533
49c468fc
AN		 1534
1535 /* Reset SD Clock Enable */
1536 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1537 clk &= ~SDHCI_CLOCK_CARD_EN;
1538 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1539
6322cdd0
PR		 1540 if (host->ops->set_uhs_signaling)
1541 host->ops->set_uhs_signaling(host, ios->timing);
1542 else {
1543 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1544 /* Select Bus Speed Mode for host */
1545 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
59911568
GC		 1546 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1547 (ios->timing == MMC_TIMING_UHS_SDR104))
1548 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
069c9f14 1549 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1550 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1551 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1552 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1553 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1554 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
6322cdd0
PR		 1555 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1556 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1557 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1558 }
49c468fc 1559
52983382
KL		 1560 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1561 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1562 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1563 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1564 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1565 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1566 u16 preset;
1567
1568 sdhci_enable_preset_value(host, true);
1569 preset = sdhci_get_preset_value(host);
1570 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1571 >> SDHCI_PRESET_DRV_SHIFT;
1572 }
1573
49c468fc 1574 /* Re-enable SD Clock */
8213af3b 1575 sdhci_update_clock(host);
758535c4
AN		 1576 } else
1577 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1578
b8352260
LD		 1579 /*
1580 * Some (ENE) controllers go apeshit on some ios operation,
1581 * signalling timeout and CRC errors even on CMD0. Resetting
1582 * it on each ios seems to solve the problem.
1583 */
b8c86fc5 1584 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1585 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1586
5f25a66f 1587 mmiowb();
d129bceb
PO		 1588 spin_unlock_irqrestore(&host->lock, flags);
1589}
1590
66fd8ad5
AH		 1591static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1592{
1593 struct sdhci_host *host = mmc_priv(mmc);
1594
1595 sdhci_runtime_pm_get(host);
1596 sdhci_do_set_ios(host, ios);
1597 sdhci_runtime_pm_put(host);
1598}
1599
94144a46
KL		 1600static int sdhci_do_get_cd(struct sdhci_host *host)
1601{
1602 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1603
1604 if (host->flags & SDHCI_DEVICE_DEAD)
1605 return 0;
1606
1607 /* If polling/nonremovable, assume that the card is always present. */
1608 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1609 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1610 return 1;
1611
1612 /* Try slot gpio detect */
1613 if (!IS_ERR_VALUE(gpio_cd))
1614 return !!gpio_cd;
1615
1616 /* Host native card detect */
1617 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1618}
1619
1620static int sdhci_get_cd(struct mmc_host *mmc)
1621{
1622 struct sdhci_host *host = mmc_priv(mmc);
1623 int ret;
1624
1625 sdhci_runtime_pm_get(host);
1626 ret = sdhci_do_get_cd(host);
1627 sdhci_runtime_pm_put(host);
1628 return ret;
1629}
1630
66fd8ad5 1631static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1632{
d129bceb 1633 unsigned long flags;
2dfb579c 1634 int is_readonly;
d129bceb 1635
d129bceb
PO		 1636 spin_lock_irqsave(&host->lock, flags);
1637
1e72859e 1638 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1639 is_readonly = 0;
1640 else if (host->ops->get_ro)
1641 is_readonly = host->ops->get_ro(host);
1e72859e 1642 else
2dfb579c
WS		 1643 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1644 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1645
1646 spin_unlock_irqrestore(&host->lock, flags);
1647
2dfb579c
WS		 1648 /* This quirk needs to be replaced by a callback-function later */
1649 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1650 !is_readonly : is_readonly;
d129bceb
PO		 1651}
1652
82b0e23a
TI		 1653#define SAMPLE_COUNT 5
1654
66fd8ad5 1655static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1656{
82b0e23a
TI		 1657 int i, ro_count;
1658
82b0e23a 1659 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1660 return sdhci_check_ro(host);
82b0e23a
TI		 1661
1662 ro_count = 0;
1663 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1664 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1665 if (++ro_count > SAMPLE_COUNT / 2)
1666 return 1;
1667 }
1668 msleep(30);
1669 }
1670 return 0;
1671}
1672
20758b66
AH		 1673static void sdhci_hw_reset(struct mmc_host *mmc)
1674{
1675 struct sdhci_host *host = mmc_priv(mmc);
1676
1677 if (host->ops && host->ops->hw_reset)
1678 host->ops->hw_reset(host);
1679}
1680
66fd8ad5 1681static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1682{
66fd8ad5
AH		 1683 struct sdhci_host *host = mmc_priv(mmc);
1684 int ret;
f75979b7 1685
66fd8ad5
AH		 1686 sdhci_runtime_pm_get(host);
1687 ret = sdhci_do_get_ro(host);
1688 sdhci_runtime_pm_put(host);
1689 return ret;
1690}
f75979b7 1691
66fd8ad5
AH		 1692static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1693{
1e72859e
PO		 1694 if (host->flags & SDHCI_DEVICE_DEAD)
1695 goto out;
1696
66fd8ad5
AH		 1697 if (enable)
1698 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1699 else
1700 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1701
1702 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1703 if (host->runtime_suspended)
1704 goto out;
1705
f75979b7 1706 if (enable)
7260cf5e
AV		 1707 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1708 else
1709 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1710out:
f75979b7 1711 mmiowb();
66fd8ad5
AH		 1712}
1713
1714static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1715{
1716 struct sdhci_host *host = mmc_priv(mmc);
1717 unsigned long flags;
f75979b7 1718
66fd8ad5
AH		 1719 spin_lock_irqsave(&host->lock, flags);
1720 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1721 spin_unlock_irqrestore(&host->lock, flags);
1722}
1723
20b92a30 1724static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1725 struct mmc_ios *ios)
f2119df6 1726{
20b92a30 1727 u16 ctrl;
6231f3de 1728 int ret;
f2119df6 1729
20b92a30
KL		 1730 /*
1731 * Signal Voltage Switching is only applicable for Host Controllers
1732 * v3.00 and above.
1733 */
1734 if (host->version < SDHCI_SPEC_300)
1735 return 0;
6231f3de 1736
f2119df6 1737 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1738
21f5998f 1739 switch (ios->signal_voltage) {
20b92a30
KL		 1740 case MMC_SIGNAL_VOLTAGE_330:
1741 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1742 ctrl &= ~SDHCI_CTRL_VDD_180;
1743 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1744
20b92a30
KL		 1745 if (host->vqmmc) {
1746 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1747 if (ret) {
1748 pr_warning("%s: Switching to 3.3V signalling voltage "
1749 " failed\n", mmc_hostname(host->mmc));
1750 return -EIO;
1751 }
1752 }
1753 /* Wait for 5ms */
1754 usleep_range(5000, 5500);
f2119df6 1755
20b92a30
KL		 1756 /* 3.3V regulator output should be stable within 5 ms */
1757 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1758 if (!(ctrl & SDHCI_CTRL_VDD_180))
1759 return 0;
6231f3de 1760
20b92a30
KL		 1761 pr_warning("%s: 3.3V regulator output did not became stable\n",
1762 mmc_hostname(host->mmc));
1763
1764 return -EAGAIN;
1765 case MMC_SIGNAL_VOLTAGE_180:
1766 if (host->vqmmc) {
1767 ret = regulator_set_voltage(host->vqmmc,
1768 1700000, 1950000);
1769 if (ret) {
1770 pr_warning("%s: Switching to 1.8V signalling voltage "
1771 " failed\n", mmc_hostname(host->mmc));
1772 return -EIO;
1773 }
1774 }
6231f3de 1775
6231f3de
PR		 1776 /*
1777 * Enable 1.8V Signal Enable in the Host Control2
1778 * register
1779 */
20b92a30
KL		 1780 ctrl |= SDHCI_CTRL_VDD_180;
1781 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1782
20b92a30
KL		 1783 /* Wait for 5ms */
1784 usleep_range(5000, 5500);
f2119df6 1785
20b92a30
KL		 1786 /* 1.8V regulator output should be stable within 5 ms */
1787 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1788 if (ctrl & SDHCI_CTRL_VDD_180)
1789 return 0;
f2119df6 1790
20b92a30
KL		 1791 pr_warning("%s: 1.8V regulator output did not became stable\n",
1792 mmc_hostname(host->mmc));
f2119df6 1793
20b92a30
KL		 1794 return -EAGAIN;
1795 case MMC_SIGNAL_VOLTAGE_120:
1796 if (host->vqmmc) {
1797 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1798 if (ret) {
1799 pr_warning("%s: Switching to 1.2V signalling voltage "
1800 " failed\n", mmc_hostname(host->mmc));
1801 return -EIO;
f2119df6
AN		 1802 }
1803 }
6231f3de 1804 return 0;
20b92a30 1805 default:
f2119df6
AN		 1806 /* No signal voltage switch required */
1807 return 0;
20b92a30 1808 }
f2119df6
AN		 1809}
1810
66fd8ad5 1811static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1812 struct mmc_ios *ios)
66fd8ad5
AH		 1813{
1814 struct sdhci_host *host = mmc_priv(mmc);
1815 int err;
1816
1817 if (host->version < SDHCI_SPEC_300)
1818 return 0;
1819 sdhci_runtime_pm_get(host);
21f5998f 1820 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1821 sdhci_runtime_pm_put(host);
1822 return err;
1823}
1824
20b92a30
KL		 1825static int sdhci_card_busy(struct mmc_host *mmc)
1826{
1827 struct sdhci_host *host = mmc_priv(mmc);
1828 u32 present_state;
1829
1830 sdhci_runtime_pm_get(host);
1831 /* Check whether DAT[3:0] is 0000 */
1832 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1833 sdhci_runtime_pm_put(host);
1834
1835 return !(present_state & SDHCI_DATA_LVL_MASK);
1836}
1837
069c9f14 1838static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1839{
1840 struct sdhci_host *host;
1841 u16 ctrl;
1842 u32 ier;
1843 int tuning_loop_counter = MAX_TUNING_LOOP;
1844 unsigned long timeout;
1845 int err = 0;
069c9f14 1846 bool requires_tuning_nonuhs = false;
b513ea25
AN		 1847
1848 host = mmc_priv(mmc);
1849
66fd8ad5 1850 sdhci_runtime_pm_get(host);
b513ea25
AN		 1851 disable_irq(host->irq);
1852 spin_lock(&host->lock);
1853
1854 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1855
1856 /*
069c9f14
G		 1857 * The Host Controller needs tuning only in case of SDR104 mode
1858 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1859 * Capabilities register.
069c9f14
G		 1860 * If the Host Controller supports the HS200 mode then the
1861 * tuning function has to be executed.
b513ea25 1862 */
069c9f14
G		 1863 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1864 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
156e14b1 1865 host->flags & SDHCI_SDR104_NEEDS_TUNING))
069c9f14
G		 1866 requires_tuning_nonuhs = true;
1867
b513ea25 1868 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1869 requires_tuning_nonuhs)
b513ea25
AN		 1870 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1871 else {
1872 spin_unlock(&host->lock);
1873 enable_irq(host->irq);
66fd8ad5 1874 sdhci_runtime_pm_put(host);
b513ea25
AN		 1875 return 0;
1876 }
1877
45251812
DA		 1878 if (host->ops->platform_execute_tuning) {
1879 spin_unlock(&host->lock);
1880 enable_irq(host->irq);
1881 err = host->ops->platform_execute_tuning(host, opcode);
1882 sdhci_runtime_pm_put(host);
1883 return err;
1884 }
1885
b513ea25
AN		 1886 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1887
1888 /*
1889 * As per the Host Controller spec v3.00, tuning command
1890 * generates Buffer Read Ready interrupt, so enable that.
1891 *
1892 * Note: The spec clearly says that when tuning sequence
1893 * is being performed, the controller does not generate
1894 * interrupts other than Buffer Read Ready interrupt. But
1895 * to make sure we don't hit a controller bug, we _only_
1896 * enable Buffer Read Ready interrupt here.
1897 */
1898 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1899 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1900
1901 /*
1902 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1903 * of loops reaches 40 times or a timeout of 150ms occurs.
1904 */
1905 timeout = 150;
1906 do {
1907 struct mmc_command cmd = {0};
66fd8ad5 1908 struct mmc_request mrq = {NULL};
b513ea25
AN		 1909
1910 if (!tuning_loop_counter && !timeout)
1911 break;
1912
069c9f14 1913 cmd.opcode = opcode;
b513ea25
AN		 1914 cmd.arg = 0;
1915 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1916 cmd.retries = 0;
1917 cmd.data = NULL;
1918 cmd.error = 0;
1919
1920 mrq.cmd = &cmd;
1921 host->mrq = &mrq;
1922
1923 /*
1924 * In response to CMD19, the card sends 64 bytes of tuning
1925 * block to the Host Controller. So we set the block size
1926 * to 64 here.
1927 */
069c9f14
G		 1928 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1929 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1930 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1931 SDHCI_BLOCK_SIZE);
1932 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1933 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1934 SDHCI_BLOCK_SIZE);
1935 } else {
1936 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1937 SDHCI_BLOCK_SIZE);
1938 }
b513ea25
AN		 1939
1940 /*
1941 * The tuning block is sent by the card to the host controller.
1942 * So we set the TRNS_READ bit in the Transfer Mode register.
1943 * This also takes care of setting DMA Enable and Multi Block
1944 * Select in the same register to 0.
1945 */
1946 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1947
1948 sdhci_send_command(host, &cmd);
1949
1950 host->cmd = NULL;
1951 host->mrq = NULL;
1952
1953 spin_unlock(&host->lock);
1954 enable_irq(host->irq);
1955
1956 /* Wait for Buffer Read Ready interrupt */
1957 wait_event_interruptible_timeout(host->buf_ready_int,
1958 (host->tuning_done == 1),
1959 msecs_to_jiffies(50));
1960 disable_irq(host->irq);
1961 spin_lock(&host->lock);
1962
1963 if (!host->tuning_done) {
a3c76eb9 1964 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1965 "Buffer Read Ready interrupt during tuning "
1966 "procedure, falling back to fixed sampling "
1967 "clock\n");
1968 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1969 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1970 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1971 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1972
1973 err = -EIO;
1974 goto out;
1975 }
1976
1977 host->tuning_done = 0;
1978
1979 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1980 tuning_loop_counter--;
1981 timeout--;
1982 mdelay(1);
1983 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1984
1985 /*
1986 * The Host Driver has exhausted the maximum number of loops allowed,
1987 * so use fixed sampling frequency.
1988 */
1989 if (!tuning_loop_counter || !timeout) {
1990 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1991 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1992 } else {
1993 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1994 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1995 " failed, falling back to fixed sampling"
1996 " clock\n");
1997 err = -EIO;
1998 }
1999 }
2000
2001out:
cf2b5eea
AN		 2002 /*
2003 * If this is the very first time we are here, we start the retuning
2004 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2005 * flag won't be set, we check this condition before actually starting
2006 * the timer.
2007 */
2008 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2009 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 2010 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 2011 mod_timer(&host->tuning_timer, jiffies +
2012 host->tuning_count * HZ);
2013 /* Tuning mode 1 limits the maximum data length to 4MB */
2014 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2015 } else {
2016 host->flags &= ~SDHCI_NEEDS_RETUNING;
2017 /* Reload the new initial value for timer */
2018 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2019 mod_timer(&host->tuning_timer, jiffies +
2020 host->tuning_count * HZ);
2021 }
2022
2023 /*
2024 * In case tuning fails, host controllers which support re-tuning can
2025 * try tuning again at a later time, when the re-tuning timer expires.
2026 * So for these controllers, we return 0. Since there might be other
2027 * controllers who do not have this capability, we return error for
973905fe
AL		 2028 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2029 * a retuning timer to do the retuning for the card.
cf2b5eea 2030 */
973905fe 2031 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2032 err = 0;
2033
b513ea25
AN		 2034 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2035 spin_unlock(&host->lock);
2036 enable_irq(host->irq);
66fd8ad5 2037 sdhci_runtime_pm_put(host);
b513ea25
AN		 2038
2039 return err;
2040}
2041
52983382
KL		 2042
2043static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2044{
4d55c5a1 2045 u16 ctrl;
4d55c5a1 2046
4d55c5a1
AN		 2047 /* Host Controller v3.00 defines preset value registers */
2048 if (host->version < SDHCI_SPEC_300)
2049 return;
2050
4d55c5a1
AN		 2051 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2052
2053 /*
2054 * We only enable or disable Preset Value if they are not already
2055 * enabled or disabled respectively. Otherwise, we bail out.
2056 */
2057 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2058 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2059 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2060 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2061 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2062 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2063 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2064 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2065 }
66fd8ad5
AH		 2066}
2067
71e69211 2068static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2069{
71e69211 2070 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2071 unsigned long flags;
2072
722e1280
CD		 2073 /* First check if client has provided their own card event */
2074 if (host->ops->card_event)
2075 host->ops->card_event(host);
2076
d129bceb
PO		 2077 spin_lock_irqsave(&host->lock, flags);
2078
66fd8ad5 2079 /* Check host->mrq first in case we are runtime suspended */
9668d765 2080 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2081 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2082 mmc_hostname(host->mmc));
a3c76eb9 2083 pr_err("%s: Resetting controller.\n",
66fd8ad5 2084 mmc_hostname(host->mmc));
d129bceb 2085
66fd8ad5
AH		 2086 sdhci_reset(host, SDHCI_RESET_CMD);
2087 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 2088
66fd8ad5
AH		 2089 host->mrq->cmd->error = -ENOMEDIUM;
2090 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2091 }
2092
2093 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2094}
2095
2096static const struct mmc_host_ops sdhci_ops = {
2097 .request = sdhci_request,
2098 .set_ios = sdhci_set_ios,
94144a46 2099 .get_cd = sdhci_get_cd,
71e69211
GL		 2100 .get_ro = sdhci_get_ro,
2101 .hw_reset = sdhci_hw_reset,
2102 .enable_sdio_irq = sdhci_enable_sdio_irq,
2103 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2104 .execute_tuning = sdhci_execute_tuning,
71e69211 2105 .card_event = sdhci_card_event,
20b92a30 2106 .card_busy = sdhci_card_busy,
71e69211
GL		 2107};
2108
2109/*****************************************************************************\
2110 * *
2111 * Tasklets *
2112 * *
2113\*****************************************************************************/
2114
2115static void sdhci_tasklet_card(unsigned long param)
2116{
2117 struct sdhci_host *host = (struct sdhci_host*)param;
2118
2119 sdhci_card_event(host->mmc);
d129bceb 2120
04cf585d 2121 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 2122}
2123
2124static void sdhci_tasklet_finish(unsigned long param)
2125{
2126 struct sdhci_host *host;
2127 unsigned long flags;
2128 struct mmc_request *mrq;
2129
2130 host = (struct sdhci_host*)param;
2131
66fd8ad5
AH		 2132 spin_lock_irqsave(&host->lock, flags);
2133
0c9c99a7
CB		 2134 /*
2135 * If this tasklet gets rescheduled while running, it will
2136 * be run again afterwards but without any active request.
2137 */
66fd8ad5
AH		 2138 if (!host->mrq) {
2139 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2140 return;
66fd8ad5 2141 }
d129bceb
PO		 2142
2143 del_timer(&host->timer);
2144
2145 mrq = host->mrq;
2146
d129bceb
PO		 2147 /*
2148 * The controller needs a reset of internal state machines
2149 * upon error conditions.
2150 */
1e72859e 2151 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2152 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2153 (mrq->data && (mrq->data->error ||
2154 (mrq->data->stop && mrq->data->stop->error))) ||
2155 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2156
2157 /* Some controllers need this kick or reset won't work here */
8213af3b 2158 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2159 /* This is to force an update */
8213af3b 2160 sdhci_update_clock(host);
645289dc
PO		 2161
2162 /* Spec says we should do both at the same time, but Ricoh
2163 controllers do not like that. */
d129bceb
PO		 2164 sdhci_reset(host, SDHCI_RESET_CMD);
2165 sdhci_reset(host, SDHCI_RESET_DATA);
2166 }
2167
2168 host->mrq = NULL;
2169 host->cmd = NULL;
2170 host->data = NULL;
2171
f9134319 2172#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2173 sdhci_deactivate_led(host);
2f730fec 2174#endif
d129bceb 2175
5f25a66f 2176 mmiowb();
d129bceb
PO		 2177 spin_unlock_irqrestore(&host->lock, flags);
2178
2179 mmc_request_done(host->mmc, mrq);
66fd8ad5 2180 sdhci_runtime_pm_put(host);
d129bceb
PO		 2181}
2182
2183static void sdhci_timeout_timer(unsigned long data)
2184{
2185 struct sdhci_host *host;
2186 unsigned long flags;
2187
2188 host = (struct sdhci_host*)data;
2189
2190 spin_lock_irqsave(&host->lock, flags);
2191
2192 if (host->mrq) {
a3c76eb9 2193 pr_err("%s: Timeout waiting for hardware "
acf1da45 2194 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2195 sdhci_dumpregs(host);
2196
2197 if (host->data) {
17b0429d 2198 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2199 sdhci_finish_data(host);
2200 } else {
2201 if (host->cmd)
17b0429d 2202 host->cmd->error = -ETIMEDOUT;
d129bceb 2203 else
17b0429d 2204 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2205
2206 tasklet_schedule(&host->finish_tasklet);
2207 }
2208 }
2209
5f25a66f 2210 mmiowb();
d129bceb
PO		 2211 spin_unlock_irqrestore(&host->lock, flags);
2212}
2213
cf2b5eea
AN		 2214static void sdhci_tuning_timer(unsigned long data)
2215{
2216 struct sdhci_host *host;
2217 unsigned long flags;
2218
2219 host = (struct sdhci_host *)data;
2220
2221 spin_lock_irqsave(&host->lock, flags);
2222
2223 host->flags |= SDHCI_NEEDS_RETUNING;
2224
2225 spin_unlock_irqrestore(&host->lock, flags);
2226}
2227
d129bceb
PO		 2228/*****************************************************************************\
2229 * *
2230 * Interrupt handling *
2231 * *
2232\*****************************************************************************/
2233
2234static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2235{
2236 BUG_ON(intmask == 0);
2237
2238 if (!host->cmd) {
a3c76eb9 2239 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2240 "though no command operation was in progress.\n",
2241 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2242 sdhci_dumpregs(host);
2243 return;
2244 }
2245
43b58b36 2246 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2247 host->cmd->error = -ETIMEDOUT;
2248 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2249 SDHCI_INT_INDEX))
2250 host->cmd->error = -EILSEQ;
43b58b36 2251
e809517f 2252 if (host->cmd->error) {
d129bceb 2253 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2254 return;
2255 }
2256
2257 /*
2258 * The host can send and interrupt when the busy state has
2259 * ended, allowing us to wait without wasting CPU cycles.
2260 * Unfortunately this is overloaded on the "data complete"
2261 * interrupt, so we need to take some care when handling
2262 * it.
2263 *
2264 * Note: The 1.0 specification is a bit ambiguous about this
2265 * feature so there might be some problems with older
2266 * controllers.
2267 */
2268 if (host->cmd->flags & MMC_RSP_BUSY) {
2269 if (host->cmd->data)
2270 DBG("Cannot wait for busy signal when also "
2271 "doing a data transfer");
f945405c 2272 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2273 return;
f945405c
BD		 2274
2275 /* The controller does not support the end-of-busy IRQ,
2276 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2277 }
2278
2279 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2280 sdhci_finish_command(host);
d129bceb
PO		 2281}
2282
0957c333 2283#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2284static void sdhci_show_adma_error(struct sdhci_host *host)
2285{
2286 const char *name = mmc_hostname(host->mmc);
2287 u8 *desc = host->adma_desc;
2288 __le32 *dma;
2289 __le16 *len;
2290 u8 attr;
2291
2292 sdhci_dumpregs(host);
2293
2294 while (true) {
2295 dma = (__le32 *)(desc + 4);
2296 len = (__le16 *)(desc + 2);
2297 attr = *desc;
2298
2299 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2300 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2301
2302 desc += 8;
2303
2304 if (attr & 2)
2305 break;
2306 }
2307}
2308#else
2309static void sdhci_show_adma_error(struct sdhci_host *host) { }
2310#endif
2311
d129bceb
PO		 2312static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2313{
069c9f14 2314 u32 command;
d129bceb
PO		 2315 BUG_ON(intmask == 0);
2316
b513ea25
AN		 2317 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2318 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2319 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2320 if (command == MMC_SEND_TUNING_BLOCK ||
2321 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2322 host->tuning_done = 1;
2323 wake_up(&host->buf_ready_int);
2324 return;
2325 }
2326 }
2327
d129bceb
PO		 2328 if (!host->data) {
2329 /*
e809517f
PO		 2330 * The "data complete" interrupt is also used to
2331 * indicate that a busy state has ended. See comment
2332 * above in sdhci_cmd_irq().
d129bceb 2333 */
e809517f
PO		 2334 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2335 if (intmask & SDHCI_INT_DATA_END) {
2336 sdhci_finish_command(host);
2337 return;
2338 }
2339 }
d129bceb 2340
a3c76eb9 2341 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2342 "though no data operation was in progress.\n",
2343 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2344 sdhci_dumpregs(host);
2345
2346 return;
2347 }
2348
2349 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2350 host->data->error = -ETIMEDOUT;
22113efd
AL		 2351 else if (intmask & SDHCI_INT_DATA_END_BIT)
2352 host->data->error = -EILSEQ;
2353 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2354 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2355 != MMC_BUS_TEST_R)
17b0429d 2356 host->data->error = -EILSEQ;
6882a8c0 2357 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2358 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2359 sdhci_show_adma_error(host);
2134a922 2360 host->data->error = -EIO;
a4071fbb
HZ		 2361 if (host->ops->adma_workaround)
2362 host->ops->adma_workaround(host, intmask);
6882a8c0 2363 }
d129bceb 2364
17b0429d 2365 if (host->data->error)
d129bceb
PO		 2366 sdhci_finish_data(host);
2367 else {
a406f5a3 2368 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2369 sdhci_transfer_pio(host);
2370
6ba736a1
PO		 2371 /*
2372 * We currently don't do anything fancy with DMA
2373 * boundaries, but as we can't disable the feature
2374 * we need to at least restart the transfer.
f6a03cbf
MV		 2375 *
2376 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2377 * should return a valid address to continue from, but as
2378 * some controllers are faulty, don't trust them.
6ba736a1 2379 */
f6a03cbf
MV		 2380 if (intmask & SDHCI_INT_DMA_END) {
2381 u32 dmastart, dmanow;
2382 dmastart = sg_dma_address(host->data->sg);
2383 dmanow = dmastart + host->data->bytes_xfered;
2384 /*
2385 * Force update to the next DMA block boundary.
2386 */
2387 dmanow = (dmanow &
2388 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2389 SDHCI_DEFAULT_BOUNDARY_SIZE;
2390 host->data->bytes_xfered = dmanow - dmastart;
2391 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2392 " next 0x%08x\n",
2393 mmc_hostname(host->mmc), dmastart,
2394 host->data->bytes_xfered, dmanow);
2395 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2396 }
6ba736a1 2397
e538fbe8
PO		 2398 if (intmask & SDHCI_INT_DATA_END) {
2399 if (host->cmd) {
2400 /*
2401 * Data managed to finish before the
2402 * command completed. Make sure we do
2403 * things in the proper order.
2404 */
2405 host->data_early = 1;
2406 } else {
2407 sdhci_finish_data(host);
2408 }
2409 }
d129bceb
PO		 2410 }
2411}
2412
7d12e780 2413static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2414{
2415 irqreturn_t result;
66fd8ad5 2416 struct sdhci_host *host = dev_id;
6379b237
AS		 2417 u32 intmask, unexpected = 0;
2418 int cardint = 0, max_loops = 16;
d129bceb
PO		 2419
2420 spin_lock(&host->lock);
2421
66fd8ad5
AH		 2422 if (host->runtime_suspended) {
2423 spin_unlock(&host->lock);
a3c76eb9 2424 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2425 mmc_hostname(host->mmc));
2426 return IRQ_HANDLED;
2427 }
2428
4e4141a5 2429 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2430
62df67a5 2431 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2432 result = IRQ_NONE;
2433 goto out;
2434 }
2435
6379b237 2436again:
b69c9058
PO		 2437 DBG("*** %s got interrupt: 0x%08x\n",
2438 mmc_hostname(host->mmc), intmask);
d129bceb 2439
3192a28f 2440 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2441 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2442 SDHCI_CARD_PRESENT;
2443
2444 /*
2445 * There is a observation on i.mx esdhc. INSERT bit will be
2446 * immediately set again when it gets cleared, if a card is
2447 * inserted. We have to mask the irq to prevent interrupt
2448 * storm which will freeze the system. And the REMOVE gets
2449 * the same situation.
2450 *
2451 * More testing are needed here to ensure it works for other
2452 * platforms though.
2453 */
2454 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2455 SDHCI_INT_CARD_REMOVE);
2456 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2457 SDHCI_INT_CARD_INSERT);
2458
4e4141a5 2459 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2460 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2461 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2462 tasklet_schedule(&host->card_tasklet);
3192a28f 2463 }
d129bceb 2464
3192a28f 2465 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2466 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2467 SDHCI_INT_STATUS);
3192a28f 2468 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2469 }
2470
2471 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2472 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2473 SDHCI_INT_STATUS);
3192a28f 2474 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2475 }
2476
2477 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2478
964f9ce2
PO		 2479 intmask &= ~SDHCI_INT_ERROR;
2480
d129bceb 2481 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2482 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2483 mmc_hostname(host->mmc));
4e4141a5 2484 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2485 }
2486
9d26a5d3 2487 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2488
f75979b7
PO		 2489 if (intmask & SDHCI_INT_CARD_INT)
2490 cardint = 1;
2491
2492 intmask &= ~SDHCI_INT_CARD_INT;
2493
3192a28f 2494 if (intmask) {
6379b237 2495 unexpected |= intmask;
4e4141a5 2496 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2497 }
d129bceb
PO		 2498
2499 result = IRQ_HANDLED;
2500
6379b237
AS		 2501 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2502 if (intmask && --max_loops)
2503 goto again;
d129bceb
PO		 2504out:
2505 spin_unlock(&host->lock);
2506
6379b237
AS		 2507 if (unexpected) {
2508 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2509 mmc_hostname(host->mmc), unexpected);
2510 sdhci_dumpregs(host);
2511 }
f75979b7
PO		 2512 /*
2513 * We have to delay this as it calls back into the driver.
2514 */
2515 if (cardint)
2516 mmc_signal_sdio_irq(host->mmc);
2517
d129bceb
PO		 2518 return result;
2519}
2520
2521/*****************************************************************************\
2522 * *
2523 * Suspend/resume *
2524 * *
2525\*****************************************************************************/
2526
2527#ifdef CONFIG_PM
ad080d79
KL		 2528void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2529{
2530 u8 val;
2531 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2532 | SDHCI_WAKE_ON_INT;
2533
2534 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2535 val |= mask ;
2536 /* Avoid fake wake up */
2537 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2538 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2539 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2540}
2541EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2542
2543void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2544{
2545 u8 val;
2546 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2547 | SDHCI_WAKE_ON_INT;
2548
2549 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2550 val &= ~mask;
2551 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2552}
2553EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2554
29495aa0 2555int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2556{
b8c86fc5 2557 int ret;
a715dfc7 2558
a1b13b4e
CB		 2559 if (host->ops->platform_suspend)
2560 host->ops->platform_suspend(host);
2561
7260cf5e
AV		 2562 sdhci_disable_card_detection(host);
2563
cf2b5eea 2564 /* Disable tuning since we are suspending */
973905fe 2565 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2566 del_timer_sync(&host->tuning_timer);
cf2b5eea 2567 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2568 }
2569
1a13f8fa 2570 ret = mmc_suspend_host(host->mmc);
38a60ea2 2571 if (ret) {
973905fe 2572 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
38a60ea2
AL		 2573 host->flags |= SDHCI_NEEDS_RETUNING;
2574 mod_timer(&host->tuning_timer, jiffies +
2575 host->tuning_count * HZ);
2576 }
2577
2578 sdhci_enable_card_detection(host);
2579
b8c86fc5 2580 return ret;
38a60ea2 2581 }
a715dfc7 2582
ad080d79
KL		 2583 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2584 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2585 free_irq(host->irq, host);
2586 } else {
2587 sdhci_enable_irq_wakeups(host);
2588 enable_irq_wake(host->irq);
2589 }
9bea3c85 2590 return ret;
d129bceb
PO		 2591}
2592
b8c86fc5 2593EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2594
b8c86fc5
PO		 2595int sdhci_resume_host(struct sdhci_host *host)
2596{
2597 int ret;
d129bceb 2598
a13abc7b 2599 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2600 if (host->ops->enable_dma)
2601 host->ops->enable_dma(host);
2602 }
d129bceb 2603
ad080d79
KL		 2604 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2605 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2606 mmc_hostname(host->mmc), host);
2607 if (ret)
2608 return ret;
2609 } else {
2610 sdhci_disable_irq_wakeups(host);
2611 disable_irq_wake(host->irq);
2612 }
d129bceb 2613
6308d290
AH		 2614 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2615 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2616 /* Card keeps power but host controller does not */
2617 sdhci_init(host, 0);
2618 host->pwr = 0;
2619 host->clock = 0;
2620 sdhci_do_set_ios(host, &host->mmc->ios);
2621 } else {
2622 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2623 mmiowb();
2624 }
b8c86fc5
PO		 2625
2626 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2627 sdhci_enable_card_detection(host);
2628
a1b13b4e
CB		 2629 if (host->ops->platform_resume)
2630 host->ops->platform_resume(host);
2631
cf2b5eea 2632 /* Set the re-tuning expiration flag */
973905fe 2633 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2634 host->flags |= SDHCI_NEEDS_RETUNING;
2635
2f4cbb3d 2636 return ret;
d129bceb
PO		 2637}
2638
b8c86fc5 2639EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2640#endif /* CONFIG_PM */
2641
66fd8ad5
AH		 2642#ifdef CONFIG_PM_RUNTIME
2643
2644static int sdhci_runtime_pm_get(struct sdhci_host *host)
2645{
2646 return pm_runtime_get_sync(host->mmc->parent);
2647}
2648
2649static int sdhci_runtime_pm_put(struct sdhci_host *host)
2650{
2651 pm_runtime_mark_last_busy(host->mmc->parent);
2652 return pm_runtime_put_autosuspend(host->mmc->parent);
2653}
2654
f0710a55
AH		 2655static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2656{
2657 if (host->runtime_suspended || host->bus_on)
2658 return;
2659 host->bus_on = true;
2660 pm_runtime_get_noresume(host->mmc->parent);
2661}
2662
2663static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2664{
2665 if (host->runtime_suspended || !host->bus_on)
2666 return;
2667 host->bus_on = false;
2668 pm_runtime_put_noidle(host->mmc->parent);
2669}
2670
66fd8ad5
AH		 2671int sdhci_runtime_suspend_host(struct sdhci_host *host)
2672{
2673 unsigned long flags;
2674 int ret = 0;
2675
2676 /* Disable tuning since we are suspending */
973905fe 2677 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2678 del_timer_sync(&host->tuning_timer);
2679 host->flags &= ~SDHCI_NEEDS_RETUNING;
2680 }
2681
2682 spin_lock_irqsave(&host->lock, flags);
2683 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2684 spin_unlock_irqrestore(&host->lock, flags);
2685
2686 synchronize_irq(host->irq);
2687
2688 spin_lock_irqsave(&host->lock, flags);
2689 host->runtime_suspended = true;
2690 spin_unlock_irqrestore(&host->lock, flags);
2691
2692 return ret;
2693}
2694EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2695
2696int sdhci_runtime_resume_host(struct sdhci_host *host)
2697{
2698 unsigned long flags;
2699 int ret = 0, host_flags = host->flags;
2700
2701 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2702 if (host->ops->enable_dma)
2703 host->ops->enable_dma(host);
2704 }
2705
2706 sdhci_init(host, 0);
2707
2708 /* Force clock and power re-program */
2709 host->pwr = 0;
2710 host->clock = 0;
2711 sdhci_do_set_ios(host, &host->mmc->ios);
2712
2713 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2714 if ((host_flags & SDHCI_PV_ENABLED) &&
2715 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2716 spin_lock_irqsave(&host->lock, flags);
2717 sdhci_enable_preset_value(host, true);
2718 spin_unlock_irqrestore(&host->lock, flags);
2719 }
66fd8ad5
AH		 2720
2721 /* Set the re-tuning expiration flag */
973905fe 2722 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2723 host->flags |= SDHCI_NEEDS_RETUNING;
2724
2725 spin_lock_irqsave(&host->lock, flags);
2726
2727 host->runtime_suspended = false;
2728
2729 /* Enable SDIO IRQ */
2730 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2731 sdhci_enable_sdio_irq_nolock(host, true);
2732
2733 /* Enable Card Detection */
2734 sdhci_enable_card_detection(host);
2735
2736 spin_unlock_irqrestore(&host->lock, flags);
2737
2738 return ret;
2739}
2740EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2741
2742#endif
2743
d129bceb
PO		 2744/*****************************************************************************\
2745 * *
b8c86fc5 2746 * Device allocation/registration *
d129bceb
PO		 2747 * *
2748\*****************************************************************************/
2749
b8c86fc5
PO		 2750struct sdhci_host *sdhci_alloc_host(struct device *dev,
2751 size_t priv_size)
d129bceb 2752{
d129bceb
PO		 2753 struct mmc_host *mmc;
2754 struct sdhci_host *host;
2755
b8c86fc5 2756 WARN_ON(dev == NULL);
d129bceb 2757
b8c86fc5 2758 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2759 if (!mmc)
b8c86fc5 2760 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2761
2762 host = mmc_priv(mmc);
2763 host->mmc = mmc;
2764
b8c86fc5
PO		 2765 return host;
2766}
8a4da143 2767
b8c86fc5 2768EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2769
b8c86fc5
PO		 2770int sdhci_add_host(struct sdhci_host *host)
2771{
2772 struct mmc_host *mmc;
bd6a8c30 2773 u32 caps[2] = {0, 0};
f2119df6
AN		 2774 u32 max_current_caps;
2775 unsigned int ocr_avail;
b8c86fc5 2776 int ret;
d129bceb 2777
b8c86fc5
PO		 2778 WARN_ON(host == NULL);
2779 if (host == NULL)
2780 return -EINVAL;
d129bceb 2781
b8c86fc5 2782 mmc = host->mmc;
d129bceb 2783
b8c86fc5
PO		 2784 if (debug_quirks)
2785 host->quirks = debug_quirks;
66fd8ad5
AH		 2786 if (debug_quirks2)
2787 host->quirks2 = debug_quirks2;
d129bceb 2788
d96649ed
PO		 2789 sdhci_reset(host, SDHCI_RESET_ALL);
2790
4e4141a5 2791 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2792 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2793 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2794 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2795 pr_err("%s: Unknown controller version (%d). "
b69c9058 2796 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2797 host->version);
4a965505
PO		 2798 }
2799
f2119df6 2800 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2801 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2802
bd6a8c30
PR		 2803 if (host->version >= SDHCI_SPEC_300)
2804 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2805 host->caps1 :
2806 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2807
b8c86fc5 2808 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2809 host->flags |= SDHCI_USE_SDMA;
f2119df6 2810 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2811 DBG("Controller doesn't have SDMA capability\n");
67435274 2812 else
a13abc7b 2813 host->flags |= SDHCI_USE_SDMA;
d129bceb 2814
b8c86fc5 2815 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2816 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2817 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2818 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2819 }
2820
f2119df6
AN		 2821 if ((host->version >= SDHCI_SPEC_200) &&
2822 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2823 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2824
2825 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2826 (host->flags & SDHCI_USE_ADMA)) {
2827 DBG("Disabling ADMA as it is marked broken\n");
2828 host->flags &= ~SDHCI_USE_ADMA;
2829 }
2830
a13abc7b 2831 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2832 if (host->ops->enable_dma) {
2833 if (host->ops->enable_dma(host)) {
a3c76eb9 2834 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2835 "available. Falling back to PIO.\n",
2836 mmc_hostname(mmc));
a13abc7b
RR		 2837 host->flags &=
2838 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2839 }
d129bceb
PO		 2840 }
2841 }
2842
2134a922
PO		 2843 if (host->flags & SDHCI_USE_ADMA) {
2844 /*
2845 * We need to allocate descriptors for all sg entries
2846 * (128) and potentially one alignment transfer for
2847 * each of those entries.
2848 */
2849 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2850 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2851 if (!host->adma_desc || !host->align_buffer) {
2852 kfree(host->adma_desc);
2853 kfree(host->align_buffer);
a3c76eb9 2854 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2855 "buffers. Falling back to standard DMA.\n",
2856 mmc_hostname(mmc));
2857 host->flags &= ~SDHCI_USE_ADMA;
2858 }
2859 }
2860
7659150c
PO		 2861 /*
2862 * If we use DMA, then it's up to the caller to set the DMA
2863 * mask, but PIO does not need the hw shim so we set a new
2864 * mask here in that case.
2865 */
a13abc7b 2866 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2867 host->dma_mask = DMA_BIT_MASK(64);
2868 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2869 }
d129bceb 2870
c4687d5f 2871 if (host->version >= SDHCI_SPEC_300)
f2119df6 2872 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2873 >> SDHCI_CLOCK_BASE_SHIFT;
2874 else
f2119df6 2875 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2876 >> SDHCI_CLOCK_BASE_SHIFT;
2877
4240ff0a 2878 host->max_clk *= 1000000;
f27f47ef
AV		 2879 if (host->max_clk == 0 || host->quirks &
2880 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2881 if (!host->ops->get_max_clock) {
a3c76eb9 2882 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2883 "frequency.\n", mmc_hostname(mmc));
2884 return -ENODEV;
2885 }
2886 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2887 }
d129bceb 2888
c3ed3877
AN		 2889 /*
2890 * In case of Host Controller v3.00, find out whether clock
2891 * multiplier is supported.
2892 */
2893 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2894 SDHCI_CLOCK_MUL_SHIFT;
2895
2896 /*
2897 * In case the value in Clock Multiplier is 0, then programmable
2898 * clock mode is not supported, otherwise the actual clock
2899 * multiplier is one more than the value of Clock Multiplier
2900 * in the Capabilities Register.
2901 */
2902 if (host->clk_mul)
2903 host->clk_mul += 1;
2904
d129bceb
PO		 2905 /*
2906 * Set host parameters.
2907 */
2908 mmc->ops = &sdhci_ops;
c3ed3877 2909 mmc->f_max = host->max_clk;
ce5f036b 2910 if (host->ops->get_min_clock)
a9e58f25 2911 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2912 else if (host->version >= SDHCI_SPEC_300) {
2913 if (host->clk_mul) {
2914 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2915 mmc->f_max = host->max_clk * host->clk_mul;
2916 } else
2917 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2918 } else
0397526d 2919 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2920
272308ca
AS		 2921 host->timeout_clk =
2922 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2923 if (host->timeout_clk == 0) {
2924 if (host->ops->get_timeout_clock) {
2925 host->timeout_clk = host->ops->get_timeout_clock(host);
2926 } else if (!(host->quirks &
2927 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2928 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2929 "frequency.\n", mmc_hostname(mmc));
2930 return -ENODEV;
2931 }
2932 }
2933 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2934 host->timeout_clk *= 1000;
2935
2936 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2937 host->timeout_clk = mmc->f_max / 1000;
272308ca 2938
65be3fef 2939 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2940
e89d456f
AW		 2941 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2942
2943 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2944 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2945
8edf6371 2946 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2947 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2948 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2949 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2950 host->flags |= SDHCI_AUTO_CMD23;
2951 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2952 } else {
2953 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2954 }
2955
15ec4461
PR		 2956 /*
2957 * A controller may support 8-bit width, but the board itself
2958 * might not have the pins brought out. Boards that support
2959 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2960 * their platform code before calling sdhci_add_host(), and we
2961 * won't assume 8-bit width for hosts without that CAP.
2962 */
5fe23c7f 2963 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2964 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2965
63ef5d8c
JH		 2966 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2967 mmc->caps &= ~MMC_CAP_CMD23;
2968
f2119df6 2969 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2970 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2971
176d1ed4 2972 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2973 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2974 mmc->caps |= MMC_CAP_NEEDS_POLL;
2975
6231f3de 2976 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
462849aa 2977 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2978 if (IS_ERR_OR_NULL(host->vqmmc)) {
2979 if (PTR_ERR(host->vqmmc) < 0) {
2980 pr_info("%s: no vqmmc regulator found\n",
2981 mmc_hostname(mmc));
2982 host->vqmmc = NULL;
2983 }
8363c374 2984 } else {
a3361aba 2985 ret = regulator_enable(host->vqmmc);
cec2e216
KL		 2986 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2987 1950000))
8363c374
KL		 2988 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2989 SDHCI_SUPPORT_SDR50 |
2990 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 2991 if (ret) {
2992 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2993 mmc_hostname(mmc), ret);
2994 host->vqmmc = NULL;
2995 }
8363c374 2996 }
6231f3de 2997
6a66180a
DD		 2998 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2999 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3000 SDHCI_SUPPORT_DDR50);
3001
4188bba0
AC		 3002 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3003 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3004 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3005 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3006
3007 /* SDR104 supports also implies SDR50 support */
156e14b1 3008 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3009 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3010 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3011 * field can be promoted to support HS200.
3012 */
3013 mmc->caps2 |= MMC_CAP2_HS200;
3014 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3015 mmc->caps |= MMC_CAP_UHS_SDR50;
3016
3017 if (caps[1] & SDHCI_SUPPORT_DDR50)
3018 mmc->caps |= MMC_CAP_UHS_DDR50;
3019
069c9f14 3020 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3021 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3022 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3023
156e14b1 3024 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3025 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3026 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3027
d6d50a15
AN		 3028 /* Driver Type(s) (A, C, D) supported by the host */
3029 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3030 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3031 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3032 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3033 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3034 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3035
cf2b5eea
AN		 3036 /* Initial value for re-tuning timer count */
3037 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3038 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3039
3040 /*
3041 * In case Re-tuning Timer is not disabled, the actual value of
3042 * re-tuning timer will be 2 ^ (n - 1).
3043 */
3044 if (host->tuning_count)
3045 host->tuning_count = 1 << (host->tuning_count - 1);
3046
3047 /* Re-tuning mode supported by the Host Controller */
3048 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3049 SDHCI_RETUNING_MODE_SHIFT;
3050
8f230f45 3051 ocr_avail = 0;
bad37e1a 3052
462849aa 3053 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
657d5982
KL		 3054 if (IS_ERR_OR_NULL(host->vmmc)) {
3055 if (PTR_ERR(host->vmmc) < 0) {
3056 pr_info("%s: no vmmc regulator found\n",
3057 mmc_hostname(mmc));
3058 host->vmmc = NULL;
3059 }
8363c374 3060 }
bad37e1a 3061
68737043 3062#ifdef CONFIG_REGULATOR
a4f8f257
MS		 3063 /*
3064 * Voltage range check makes sense only if regulator reports
3065 * any voltage value.
3066 */
3067 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 3068 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3069 3600000);
68737043
PR		 3070 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3071 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 3072 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3073 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 3074 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3075 1950000);
68737043
PR		 3076 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3077 caps[0] &= ~SDHCI_CAN_VDD_180;
3078 }
3079#endif /* CONFIG_REGULATOR */
3080
f2119df6
AN		 3081 /*
3082 * According to SD Host Controller spec v3.00, if the Host System
3083 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3084 * the value is meaningful only if Voltage Support in the Capabilities
3085 * register is set. The actual current value is 4 times the register
3086 * value.
3087 */
3088 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3089 if (!max_current_caps && host->vmmc) {
3090 u32 curr = regulator_get_current_limit(host->vmmc);
3091 if (curr > 0) {
3092
3093 /* convert to SDHCI_MAX_CURRENT format */
3094 curr = curr/1000; /* convert to mA */
3095 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3096
3097 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3098 max_current_caps =
3099 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3100 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3101 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3102 }
3103 }
f2119df6
AN		 3104
3105 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3106 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3107
55c4665e 3108 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3109 SDHCI_MAX_CURRENT_330_MASK) >>
3110 SDHCI_MAX_CURRENT_330_SHIFT) *
3111 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3112 }
3113 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3114 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3115
55c4665e 3116 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3117 SDHCI_MAX_CURRENT_300_MASK) >>
3118 SDHCI_MAX_CURRENT_300_SHIFT) *
3119 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3120 }
3121 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3122 ocr_avail |= MMC_VDD_165_195;
3123
55c4665e 3124 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3125 SDHCI_MAX_CURRENT_180_MASK) >>
3126 SDHCI_MAX_CURRENT_180_SHIFT) *
3127 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3128 }
3129
c0b887b6
HZ		 3130 if (host->ocr_mask)
3131 ocr_avail = host->ocr_mask;
3132
8f230f45
TI		 3133 mmc->ocr_avail = ocr_avail;
3134 mmc->ocr_avail_sdio = ocr_avail;
3135 if (host->ocr_avail_sdio)
3136 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3137 mmc->ocr_avail_sd = ocr_avail;
3138 if (host->ocr_avail_sd)
3139 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3140 else /* normal SD controllers don't support 1.8V */
3141 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3142 mmc->ocr_avail_mmc = ocr_avail;
3143 if (host->ocr_avail_mmc)
3144 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3145
3146 if (mmc->ocr_avail == 0) {
a3c76eb9 3147 pr_err("%s: Hardware doesn't report any "
b69c9058 3148 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3149 return -ENODEV;
146ad66e
PO		 3150 }
3151
d129bceb
PO		 3152 spin_lock_init(&host->lock);
3153
3154 /*
2134a922
PO		 3155 * Maximum number of segments. Depends on if the hardware
3156 * can do scatter/gather or not.
d129bceb 3157 */
2134a922 3158 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3159 mmc->max_segs = 128;
a13abc7b 3160 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3161 mmc->max_segs = 1;
2134a922 3162 else /* PIO */
a36274e0 3163 mmc->max_segs = 128;
d129bceb
PO		 3164
3165 /*
bab76961 3166 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3167 * size (512KiB).
d129bceb 3168 */
55db890a 3169 mmc->max_req_size = 524288;
d129bceb
PO		 3170
3171 /*
3172 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3173 * of bytes. When doing hardware scatter/gather, each entry cannot
3174 * be larger than 64 KiB though.
d129bceb 3175 */
30652aa3
OJ		 3176 if (host->flags & SDHCI_USE_ADMA) {
3177 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3178 mmc->max_seg_size = 65535;
3179 else
3180 mmc->max_seg_size = 65536;
3181 } else {
2134a922 3182 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3183 }
d129bceb 3184
fe4a3c7a
PO		 3185 /*
3186 * Maximum block size. This varies from controller to controller and
3187 * is specified in the capabilities register.
3188 */
0633f654
AV		 3189 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3190 mmc->max_blk_size = 2;
3191 } else {
f2119df6 3192 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3193 SDHCI_MAX_BLOCK_SHIFT;
3194 if (mmc->max_blk_size >= 3) {
a3c76eb9 3195 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3196 "assuming 512 bytes\n", mmc_hostname(mmc));
3197 mmc->max_blk_size = 0;
3198 }
3199 }
3200
3201 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3202
55db890a
PO		 3203 /*
3204 * Maximum block count.
3205 */
1388eefd 3206 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3207
d129bceb
PO		 3208 /*
3209 * Init tasklets.
3210 */
3211 tasklet_init(&host->card_tasklet,
3212 sdhci_tasklet_card, (unsigned long)host);
3213 tasklet_init(&host->finish_tasklet,
3214 sdhci_tasklet_finish, (unsigned long)host);
3215
e4cad1b5 3216 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3217
cf2b5eea 3218 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3219 init_waitqueue_head(&host->buf_ready_int);
3220
cf2b5eea
AN		 3221 /* Initialize re-tuning timer */
3222 init_timer(&host->tuning_timer);
3223 host->tuning_timer.data = (unsigned long)host;
3224 host->tuning_timer.function = sdhci_tuning_timer;
3225 }
3226
2af502ca
SG		 3227 sdhci_init(host, 0);
3228
dace1453 3229 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 3230 mmc_hostname(mmc), host);
0fc81ee3
MB		 3231 if (ret) {
3232 pr_err("%s: Failed to request IRQ %d: %d\n",
3233 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3234 goto untasklet;
0fc81ee3 3235 }
d129bceb 3236
d129bceb
PO		 3237#ifdef CONFIG_MMC_DEBUG
3238 sdhci_dumpregs(host);
3239#endif
3240
f9134319 3241#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3242 snprintf(host->led_name, sizeof(host->led_name),
3243 "%s::", mmc_hostname(mmc));
3244 host->led.name = host->led_name;
2f730fec
PO		 3245 host->led.brightness = LED_OFF;
3246 host->led.default_trigger = mmc_hostname(mmc);
3247 host->led.brightness_set = sdhci_led_control;
3248
b8c86fc5 3249 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3250 if (ret) {
3251 pr_err("%s: Failed to register LED device: %d\n",
3252 mmc_hostname(mmc), ret);
2f730fec 3253 goto reset;
0fc81ee3 3254 }
2f730fec
PO		 3255#endif
3256
5f25a66f
PO		 3257 mmiowb();
3258
d129bceb
PO		 3259 mmc_add_host(mmc);
3260
a3c76eb9 3261 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3262 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3263 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3264 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3265
7260cf5e
AV		 3266 sdhci_enable_card_detection(host);
3267
d129bceb
PO		 3268 return 0;
3269
f9134319 3270#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3271reset:
3272 sdhci_reset(host, SDHCI_RESET_ALL);
b0a8dece 3273 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2f730fec
PO		 3274 free_irq(host->irq, host);
3275#endif
8ef1a143 3276untasklet:
d129bceb
PO		 3277 tasklet_kill(&host->card_tasklet);
3278 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3279
3280 return ret;
3281}
3282
b8c86fc5 3283EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3284
1e72859e 3285void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3286{
1e72859e
PO		 3287 unsigned long flags;
3288
3289 if (dead) {
3290 spin_lock_irqsave(&host->lock, flags);
3291
3292 host->flags |= SDHCI_DEVICE_DEAD;
3293
3294 if (host->mrq) {
a3c76eb9 3295 pr_err("%s: Controller removed during "
1e72859e
PO		 3296 " transfer!\n", mmc_hostname(host->mmc));
3297
3298 host->mrq->cmd->error = -ENOMEDIUM;
3299 tasklet_schedule(&host->finish_tasklet);
3300 }
3301
3302 spin_unlock_irqrestore(&host->lock, flags);
3303 }
3304
7260cf5e
AV		 3305 sdhci_disable_card_detection(host);
3306
b8c86fc5 3307 mmc_remove_host(host->mmc);
d129bceb 3308
f9134319 3309#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3310 led_classdev_unregister(&host->led);
3311#endif
3312
1e72859e
PO		 3313 if (!dead)
3314 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 3315
b0a8dece 3316 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
d129bceb
PO		 3317 free_irq(host->irq, host);
3318
3319 del_timer_sync(&host->timer);
3320
3321 tasklet_kill(&host->card_tasklet);
3322 tasklet_kill(&host->finish_tasklet);
2134a922 3323
77dcb3f4
PR		 3324 if (host->vmmc) {
3325 regulator_disable(host->vmmc);
9bea3c85 3326 regulator_put(host->vmmc);
77dcb3f4 3327 }
9bea3c85 3328
6231f3de
PR		 3329 if (host->vqmmc) {
3330 regulator_disable(host->vqmmc);
3331 regulator_put(host->vqmmc);
3332 }
3333
2134a922
PO		 3334 kfree(host->adma_desc);
3335 kfree(host->align_buffer);
3336
3337 host->adma_desc = NULL;
3338 host->align_buffer = NULL;
d129bceb
PO		 3339}
3340
b8c86fc5 3341EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3342
b8c86fc5 3343void sdhci_free_host(struct sdhci_host *host)
d129bceb 3344{
b8c86fc5 3345 mmc_free_host(host->mmc);
d129bceb
PO		 3346}
3347
b8c86fc5 3348EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3349
3350/*****************************************************************************\
3351 * *
3352 * Driver init/exit *
3353 * *
3354\*****************************************************************************/
3355
3356static int __init sdhci_drv_init(void)
3357{
a3c76eb9 3358 pr_info(DRIVER_NAME
52fbf9c9 3359 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3360 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3361
b8c86fc5 3362 return 0;
d129bceb
PO		 3363}
3364
3365static void __exit sdhci_drv_exit(void)
3366{
d129bceb
PO		 3367}
3368
3369module_init(sdhci_drv_init);
3370module_exit(sdhci_drv_exit);
3371
df673b22 3372module_param(debug_quirks, uint, 0444);
66fd8ad5 3373module_param(debug_quirks2, uint, 0444);
67435274 3374
32710e8f 3375MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3376MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3377MODULE_LICENSE("GPL");
67435274 3378
df673b22 3379MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3380MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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