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mmc: core: Do regular power cycle when lacking eMMC HW reset support
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
04e079cf 56static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 57
162d6f98 58#ifdef CONFIG_PM
66fd8ad5
AH		 59static int sdhci_runtime_pm_get(struct sdhci_host *host);
60static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 61static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
62static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 63#else
64static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
65{
66 return 0;
67}
68static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
69{
70 return 0;
71}
f0710a55
AH		 72static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
73{
74}
75static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
76{
77}
66fd8ad5
AH		 78#endif
79
d129bceb
PO		 80static void sdhci_dumpregs(struct sdhci_host *host)
81{
a3c76eb9 82 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 83 mmc_hostname(host->mmc));
d129bceb 84
a3c76eb9 85 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 86 sdhci_readl(host, SDHCI_DMA_ADDRESS),
87 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 88 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readw(host, SDHCI_BLOCK_SIZE),
90 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readl(host, SDHCI_ARGUMENT),
93 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readl(host, SDHCI_PRESENT_STATE),
96 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readb(host, SDHCI_POWER_CONTROL),
99 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 100 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
102 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 104 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
105 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 107 sdhci_readl(host, SDHCI_INT_ENABLE),
108 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 109 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 110 sdhci_readw(host, SDHCI_ACMD12_ERR),
111 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 112 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 113 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 114 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 115 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 116 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 117 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 118 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 119 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 120
e57a5f61
AH		 121 if (host->flags & SDHCI_USE_ADMA) {
122 if (host->flags & SDHCI_USE_64_BIT_DMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
126 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
127 else
128 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_ADMA_ERROR),
130 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
131 }
be3f4ae0 132
a3c76eb9 133 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 134}
135
136/*****************************************************************************\
137 * *
138 * Low level functions *
139 * *
140\*****************************************************************************/
141
7260cf5e
AV		 142static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
143{
5b4f1f6c 144 u32 present;
7260cf5e 145
c79396c1 146 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 147 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 148 return;
149
5b4f1f6c
RK		 150 if (enable) {
151 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
152 SDHCI_CARD_PRESENT;
d25928d1 153
5b4f1f6c
RK		 154 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
155 SDHCI_INT_CARD_INSERT;
156 } else {
157 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
158 }
b537f94c
RK		 159
160 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
161 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 162}
163
164static void sdhci_enable_card_detection(struct sdhci_host *host)
165{
166 sdhci_set_card_detection(host, true);
167}
168
169static void sdhci_disable_card_detection(struct sdhci_host *host)
170{
171 sdhci_set_card_detection(host, false);
172}
173
03231f9b 174void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 175{
e16514d8 176 unsigned long timeout;
393c1a34 177
4e4141a5 178 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 179
f0710a55 180 if (mask & SDHCI_RESET_ALL) {
d129bceb 181 host->clock = 0;
f0710a55
AH		 182 /* Reset-all turns off SD Bus Power */
183 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
184 sdhci_runtime_pm_bus_off(host);
185 }
d129bceb 186
e16514d8
PO		 187 /* Wait max 100 ms */
188 timeout = 100;
189
190 /* hw clears the bit when it's done */
4e4141a5 191 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 192 if (timeout == 0) {
a3c76eb9 193 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 194 mmc_hostname(host->mmc), (int)mask);
195 sdhci_dumpregs(host);
196 return;
197 }
198 timeout--;
199 mdelay(1);
d129bceb 200 }
03231f9b
RK		 201}
202EXPORT_SYMBOL_GPL(sdhci_reset);
203
204static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
205{
206 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
135b0a28 207 if (!sdhci_do_get_cd(host))
03231f9b
RK		 208 return;
209 }
063a9dbb 210
03231f9b 211 host->ops->reset(host, mask);
393c1a34 212
da91a8f9
RK		 213 if (mask & SDHCI_RESET_ALL) {
214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
215 if (host->ops->enable_dma)
216 host->ops->enable_dma(host);
217 }
218
219 /* Resetting the controller clears many */
220 host->preset_enabled = false;
3abc1e80 221 }
d129bceb
PO		 222}
223
2f4cbb3d
NP		 224static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 227{
2f4cbb3d 228 if (soft)
03231f9b 229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 230 else
03231f9b 231 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 232
b537f94c
RK		 233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
237 SDHCI_INT_RESPONSE;
238
239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 241
242 if (soft) {
243 /* force clock reconfiguration */
244 host->clock = 0;
245 sdhci_set_ios(host->mmc, &host->mmc->ios);
246 }
7260cf5e 247}
d129bceb 248
7260cf5e
AV		 249static void sdhci_reinit(struct sdhci_host *host)
250{
2f4cbb3d 251 sdhci_init(host, 0);
7260cf5e 252 sdhci_enable_card_detection(host);
d129bceb
PO		 253}
254
255static void sdhci_activate_led(struct sdhci_host *host)
256{
257 u8 ctrl;
258
4e4141a5 259 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 260 ctrl |= SDHCI_CTRL_LED;
4e4141a5 261 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 262}
263
264static void sdhci_deactivate_led(struct sdhci_host *host)
265{
266 u8 ctrl;
267
4e4141a5 268 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 269 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 270 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 271}
272
f9134319 273#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 274static void sdhci_led_control(struct led_classdev *led,
275 enum led_brightness brightness)
276{
277 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
278 unsigned long flags;
279
280 spin_lock_irqsave(&host->lock, flags);
281
66fd8ad5
AH		 282 if (host->runtime_suspended)
283 goto out;
284
2f730fec
PO		 285 if (brightness == LED_OFF)
286 sdhci_deactivate_led(host);
287 else
288 sdhci_activate_led(host);
66fd8ad5 289out:
2f730fec
PO		 290 spin_unlock_irqrestore(&host->lock, flags);
291}
292#endif
293
d129bceb
PO		 294/*****************************************************************************\
295 * *
296 * Core functions *
297 * *
298\*****************************************************************************/
299
a406f5a3 300static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 301{
7659150c
PO		 302 unsigned long flags;
303 size_t blksize, len, chunk;
7244b85b 304 u32 uninitialized_var(scratch);
7659150c 305 u8 *buf;
d129bceb 306
a406f5a3 307 DBG("PIO reading\n");
d129bceb 308
a406f5a3 309 blksize = host->data->blksz;
7659150c 310 chunk = 0;
d129bceb 311
7659150c 312 local_irq_save(flags);
d129bceb 313
a406f5a3 314 while (blksize) {
bf3a35ac 315 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 316
7659150c 317 len = min(host->sg_miter.length, blksize);
d129bceb 318
7659150c
PO		 319 blksize -= len;
320 host->sg_miter.consumed = len;
14d836e7 321
7659150c 322 buf = host->sg_miter.addr;
d129bceb 323
7659150c
PO		 324 while (len) {
325 if (chunk == 0) {
4e4141a5 326 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 327 chunk = 4;
a406f5a3 328 }
7659150c
PO		 329
330 *buf = scratch & 0xFF;
331
332 buf++;
333 scratch >>= 8;
334 chunk--;
335 len--;
d129bceb 336 }
a406f5a3 337 }
7659150c
PO		 338
339 sg_miter_stop(&host->sg_miter);
340
341 local_irq_restore(flags);
a406f5a3 342}
d129bceb 343
a406f5a3
PO		 344static void sdhci_write_block_pio(struct sdhci_host *host)
345{
7659150c
PO		 346 unsigned long flags;
347 size_t blksize, len, chunk;
348 u32 scratch;
349 u8 *buf;
d129bceb 350
a406f5a3
PO		 351 DBG("PIO writing\n");
352
353 blksize = host->data->blksz;
7659150c
PO		 354 chunk = 0;
355 scratch = 0;
d129bceb 356
7659150c 357 local_irq_save(flags);
d129bceb 358
a406f5a3 359 while (blksize) {
bf3a35ac 360 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 361
7659150c
PO		 362 len = min(host->sg_miter.length, blksize);
363
364 blksize -= len;
365 host->sg_miter.consumed = len;
366
367 buf = host->sg_miter.addr;
d129bceb 368
7659150c
PO		 369 while (len) {
370 scratch |= (u32)*buf << (chunk * 8);
371
372 buf++;
373 chunk++;
374 len--;
375
376 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 377 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 378 chunk = 0;
379 scratch = 0;
d129bceb 380 }
d129bceb
PO		 381 }
382 }
7659150c
PO		 383
384 sg_miter_stop(&host->sg_miter);
385
386 local_irq_restore(flags);
a406f5a3
PO		 387}
388
389static void sdhci_transfer_pio(struct sdhci_host *host)
390{
391 u32 mask;
392
393 BUG_ON(!host->data);
394
7659150c 395 if (host->blocks == 0)
a406f5a3
PO		 396 return;
397
398 if (host->data->flags & MMC_DATA_READ)
399 mask = SDHCI_DATA_AVAILABLE;
400 else
401 mask = SDHCI_SPACE_AVAILABLE;
402
4a3cba32
PO		 403 /*
404 * Some controllers (JMicron JMB38x) mess up the buffer bits
405 * for transfers < 4 bytes. As long as it is just one block,
406 * we can ignore the bits.
407 */
408 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
409 (host->data->blocks == 1))
410 mask = ~0;
411
4e4141a5 412 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 413 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
414 udelay(100);
415
a406f5a3
PO		 416 if (host->data->flags & MMC_DATA_READ)
417 sdhci_read_block_pio(host);
418 else
419 sdhci_write_block_pio(host);
d129bceb 420
7659150c
PO		 421 host->blocks--;
422 if (host->blocks == 0)
a406f5a3 423 break;
a406f5a3 424 }
d129bceb 425
a406f5a3 426 DBG("PIO transfer complete.\n");
d129bceb
PO		 427}
428
48857d9b 429static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 430 struct mmc_data *data, int cookie)
48857d9b
RK		 431{
432 int sg_count;
433
94538e51
RK		 434 /*
435 * If the data buffers are already mapped, return the previous
436 * dma_map_sg() result.
437 */
438 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 439 return data->sg_count;
48857d9b
RK		 440
441 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
442 data->flags & MMC_DATA_WRITE ?
443 DMA_TO_DEVICE : DMA_FROM_DEVICE);
444
445 if (sg_count == 0)
446 return -ENOSPC;
447
448 data->sg_count = sg_count;
c0999b72 449 data->host_cookie = cookie;
48857d9b
RK		 450
451 return sg_count;
452}
453
2134a922
PO		 454static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
455{
456 local_irq_save(*flags);
482fce99 457 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 458}
459
460static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
461{
482fce99 462 kunmap_atomic(buffer);
2134a922
PO		 463 local_irq_restore(*flags);
464}
465
e57a5f61
AH		 466static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
467 dma_addr_t addr, int len, unsigned cmd)
118cd17d 468{
e57a5f61 469 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 470
e57a5f61 471 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 472 dma_desc->cmd = cpu_to_le16(cmd);
473 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 474 dma_desc->addr_lo = cpu_to_le32((u32)addr);
475
476 if (host->flags & SDHCI_USE_64_BIT_DMA)
477 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 478}
479
b5ffa674
AH		 480static void sdhci_adma_mark_end(void *desc)
481{
e57a5f61 482 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 483
e57a5f61 484 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 485 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 486}
487
60c64762
RK		 488static void sdhci_adma_table_pre(struct sdhci_host *host,
489 struct mmc_data *data, int sg_count)
2134a922 490{
2134a922 491 struct scatterlist *sg;
2134a922 492 unsigned long flags;
acc3ad13
RK		 493 dma_addr_t addr, align_addr;
494 void *desc, *align;
495 char *buffer;
496 int len, offset, i;
2134a922
PO		 497
498 /*
499 * The spec does not specify endianness of descriptor table.
500 * We currently guess that it is LE.
501 */
502
60c64762 503 host->sg_count = sg_count;
2134a922 504
4efaa6fb 505 desc = host->adma_table;
2134a922
PO		 506 align = host->align_buffer;
507
508 align_addr = host->align_addr;
509
510 for_each_sg(data->sg, sg, host->sg_count, i) {
511 addr = sg_dma_address(sg);
512 len = sg_dma_len(sg);
513
514 /*
acc3ad13
RK		 515 * The SDHCI specification states that ADMA addresses must
516 * be 32-bit aligned. If they aren't, then we use a bounce
517 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 518 * alignment.
519 */
04a5ae6f
AH		 520 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
521 SDHCI_ADMA2_MASK;
2134a922
PO		 522 if (offset) {
523 if (data->flags & MMC_DATA_WRITE) {
524 buffer = sdhci_kmap_atomic(sg, &flags);
525 memcpy(align, buffer, offset);
526 sdhci_kunmap_atomic(buffer, &flags);
527 }
528
118cd17d 529 /* tran, valid */
e57a5f61 530 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 531 ADMA2_TRAN_VALID);
2134a922
PO		 532
533 BUG_ON(offset > 65536);
534
04a5ae6f
AH		 535 align += SDHCI_ADMA2_ALIGN;
536 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 537
76fe379a 538 desc += host->desc_sz;
2134a922
PO		 539
540 addr += offset;
541 len -= offset;
542 }
543
2134a922
PO		 544 BUG_ON(len > 65536);
545
347ea32d
AH		 546 if (len) {
547 /* tran, valid */
548 sdhci_adma_write_desc(host, desc, addr, len,
549 ADMA2_TRAN_VALID);
550 desc += host->desc_sz;
551 }
2134a922
PO		 552
553 /*
554 * If this triggers then we have a calculation bug
555 * somewhere. :/
556 */
76fe379a 557 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 558 }
559
70764a90 560 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 561 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 562 if (desc != host->adma_table) {
76fe379a 563 desc -= host->desc_sz;
b5ffa674 564 sdhci_adma_mark_end(desc);
70764a90
TA		 565 }
566 } else {
acc3ad13 567 /* Add a terminating entry - nop, end, valid */
e57a5f61 568 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 569 }
2134a922
PO		 570}
571
572static void sdhci_adma_table_post(struct sdhci_host *host,
573 struct mmc_data *data)
574{
2134a922
PO		 575 struct scatterlist *sg;
576 int i, size;
1c3d5f6d 577 void *align;
2134a922
PO		 578 char *buffer;
579 unsigned long flags;
580
47fa9613
RK		 581 if (data->flags & MMC_DATA_READ) {
582 bool has_unaligned = false;
de0b65a7 583
47fa9613
RK		 584 /* Do a quick scan of the SG list for any unaligned mappings */
585 for_each_sg(data->sg, sg, host->sg_count, i)
586 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
587 has_unaligned = true;
588 break;
589 }
2134a922 590
47fa9613
RK		 591 if (has_unaligned) {
592 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 593 data->sg_len, DMA_FROM_DEVICE);
2134a922 594
47fa9613 595 align = host->align_buffer;
2134a922 596
47fa9613
RK		 597 for_each_sg(data->sg, sg, host->sg_count, i) {
598 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
599 size = SDHCI_ADMA2_ALIGN -
600 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
601
602 buffer = sdhci_kmap_atomic(sg, &flags);
603 memcpy(buffer, align, size);
604 sdhci_kunmap_atomic(buffer, &flags);
2134a922 605
47fa9613
RK		 606 align += SDHCI_ADMA2_ALIGN;
607 }
2134a922
PO		 608 }
609 }
610 }
2134a922
PO		 611}
612
a3c7778f 613static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 614{
1c8cde92 615 u8 count;
a3c7778f 616 struct mmc_data *data = cmd->data;
1c8cde92 617 unsigned target_timeout, current_timeout;
d129bceb 618
ee53ab5d
PO		 619 /*
620 * If the host controller provides us with an incorrect timeout
621 * value, just skip the check and use 0xE. The hardware may take
622 * longer to time out, but that's much better than having a too-short
623 * timeout value.
624 */
11a2f1b7 625 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 626 return 0xE;
e538fbe8 627
a3c7778f 628 /* Unspecified timeout, assume max */
1d4d7744 629 if (!data && !cmd->busy_timeout)
a3c7778f 630 return 0xE;
d129bceb 631
a3c7778f
AW		 632 /* timeout in us */
633 if (!data)
1d4d7744 634 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 635 else {
fafcfda9 636 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 637 if (host->clock && data->timeout_clks) {
638 unsigned long long val;
639
640 /*
641 * data->timeout_clks is in units of clock cycles.
642 * host->clock is in Hz. target_timeout is in us.
643 * Hence, us = 1000000 * cycles / Hz. Round up.
644 */
645 val = 1000000 * data->timeout_clks;
646 if (do_div(val, host->clock))
647 target_timeout++;
648 target_timeout += val;
649 }
78a2ca27 650 }
81b39802 651
1c8cde92
PO		 652 /*
653 * Figure out needed cycles.
654 * We do this in steps in order to fit inside a 32 bit int.
655 * The first step is the minimum timeout, which will have a
656 * minimum resolution of 6 bits:
657 * (1) 2^13*1000 > 2^22,
658 * (2) host->timeout_clk < 2^16
659 * =>
660 * (1) / (2) > 2^6
661 */
662 count = 0;
663 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
664 while (current_timeout < target_timeout) {
665 count++;
666 current_timeout <<= 1;
667 if (count >= 0xF)
668 break;
669 }
670
671 if (count >= 0xF) {
09eeff52
CB		 672 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
673 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 674 count = 0xE;
675 }
676
ee53ab5d
PO		 677 return count;
678}
679
6aa943ab
AV		 680static void sdhci_set_transfer_irqs(struct sdhci_host *host)
681{
682 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
683 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
684
685 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 686 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 687 else
b537f94c
RK		 688 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
689
690 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
691 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 692}
693
b45e668a 694static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 695{
696 u8 count;
b45e668a
AD		 697
698 if (host->ops->set_timeout) {
699 host->ops->set_timeout(host, cmd);
700 } else {
701 count = sdhci_calc_timeout(host, cmd);
702 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
703 }
704}
705
706static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
707{
2134a922 708 u8 ctrl;
a3c7778f 709 struct mmc_data *data = cmd->data;
ee53ab5d
PO		 710
711 WARN_ON(host->data);
712
b45e668a
AD		 713 if (data || (cmd->flags & MMC_RSP_BUSY))
714 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 715
716 if (!data)
ee53ab5d
PO		 717 return;
718
719 /* Sanity checks */
720 BUG_ON(data->blksz * data->blocks > 524288);
721 BUG_ON(data->blksz > host->mmc->max_blk_size);
722 BUG_ON(data->blocks > 65535);
723
724 host->data = data;
725 host->data_early = 0;
f6a03cbf 726 host->data->bytes_xfered = 0;
ee53ab5d 727
fce14421 728 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 729 struct scatterlist *sg;
df953925 730 unsigned int length_mask, offset_mask;
a0eaf0f9 731 int i;
2134a922 732
fce14421
RK		 733 host->flags |= SDHCI_REQ_USE_DMA;
734
735 /*
736 * FIXME: This doesn't account for merging when mapping the
737 * scatterlist.
738 *
739 * The assumption here being that alignment and lengths are
740 * the same after DMA mapping to device address space.
741 */
a0eaf0f9 742 length_mask = 0;
df953925 743 offset_mask = 0;
2134a922 744 if (host->flags & SDHCI_USE_ADMA) {
df953925 745 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 746 length_mask = 3;
df953925
RK		 747 /*
748 * As we use up to 3 byte chunks to work
749 * around alignment problems, we need to
750 * check the offset as well.
751 */
752 offset_mask = 3;
753 }
2134a922
PO		 754 } else {
755 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 756 length_mask = 3;
df953925
RK		 757 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
758 offset_mask = 3;
2134a922
PO		 759 }
760
df953925 761 if (unlikely(length_mask | offset_mask)) {
2134a922 762 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 763 if (sg->length & length_mask) {
2e4456f0 764 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 765 sg->length);
2134a922
PO		 766 host->flags &= ~SDHCI_REQ_USE_DMA;
767 break;
768 }
a0eaf0f9 769 if (sg->offset & offset_mask) {
2e4456f0 770 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 771 host->flags &= ~SDHCI_REQ_USE_DMA;
772 break;
773 }
774 }
775 }
776 }
777
8f1934ce 778 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 779 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 780
781 if (sg_cnt <= 0) {
782 /*
783 * This only happens when someone fed
784 * us an invalid request.
785 */
786 WARN_ON(1);
787 host->flags &= ~SDHCI_REQ_USE_DMA;
788 } else if (host->flags & SDHCI_USE_ADMA) {
789 sdhci_adma_table_pre(host, data, sg_cnt);
790
791 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
792 if (host->flags & SDHCI_USE_64_BIT_DMA)
793 sdhci_writel(host,
794 (u64)host->adma_addr >> 32,
795 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 796 } else {
60c64762
RK		 797 WARN_ON(sg_cnt != 1);
798 sdhci_writel(host, sg_dma_address(data->sg),
799 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 800 }
801 }
802
2134a922
PO		 803 /*
804 * Always adjust the DMA selection as some controllers
805 * (e.g. JMicron) can't do PIO properly when the selection
806 * is ADMA.
807 */
808 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 809 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 810 ctrl &= ~SDHCI_CTRL_DMA_MASK;
811 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 812 (host->flags & SDHCI_USE_ADMA)) {
813 if (host->flags & SDHCI_USE_64_BIT_DMA)
814 ctrl |= SDHCI_CTRL_ADMA64;
815 else
816 ctrl |= SDHCI_CTRL_ADMA32;
817 } else {
2134a922 818 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 819 }
4e4141a5 820 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 821 }
822
8f1934ce 823 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 824 int flags;
825
826 flags = SG_MITER_ATOMIC;
827 if (host->data->flags & MMC_DATA_READ)
828 flags |= SG_MITER_TO_SG;
829 else
830 flags |= SG_MITER_FROM_SG;
831 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 832 host->blocks = data->blocks;
d129bceb 833 }
c7fa9963 834
6aa943ab
AV		 835 sdhci_set_transfer_irqs(host);
836
f6a03cbf
MV		 837 /* Set the DMA boundary value and block size */
838 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
839 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 840 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 841}
842
843static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 844 struct mmc_command *cmd)
c7fa9963 845{
d3fc5d71 846 u16 mode = 0;
e89d456f 847 struct mmc_data *data = cmd->data;
c7fa9963 848
2b558c13 849 if (data == NULL) {
9b8ffea6
VW		 850 if (host->quirks2 &
851 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
852 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
853 } else {
2b558c13 854 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 855 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
856 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 857 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 858 }
c7fa9963 859 return;
2b558c13 860 }
c7fa9963 861
e538fbe8
PO		 862 WARN_ON(!host->data);
863
d3fc5d71
VY		 864 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
865 mode = SDHCI_TRNS_BLK_CNT_EN;
866
e89d456f 867 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 868 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 869 /*
870 * If we are sending CMD23, CMD12 never gets sent
871 * on successful completion (so no Auto-CMD12).
872 */
85cc1c33
CD		 873 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
874 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 875 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 876 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
877 mode |= SDHCI_TRNS_AUTO_CMD23;
878 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
879 }
c4512f79 880 }
8edf6371 881
c7fa9963
PO		 882 if (data->flags & MMC_DATA_READ)
883 mode |= SDHCI_TRNS_READ;
c9fddbc4 884 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 885 mode |= SDHCI_TRNS_DMA;
886
4e4141a5 887 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 888}
889
890static void sdhci_finish_data(struct sdhci_host *host)
891{
892 struct mmc_data *data;
d129bceb
PO		 893
894 BUG_ON(!host->data);
895
896 data = host->data;
897 host->data = NULL;
898
add8913d
RK		 899 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
900 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
901 sdhci_adma_table_post(host, data);
d129bceb
PO		 902
903 /*
c9b74c5b
PO		 904 * The specification states that the block count register must
905 * be updated, but it does not specify at what point in the
906 * data flow. That makes the register entirely useless to read
907 * back so we have to assume that nothing made it to the card
908 * in the event of an error.
d129bceb 909 */
c9b74c5b
PO		 910 if (data->error)
911 data->bytes_xfered = 0;
d129bceb 912 else
c9b74c5b 913 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 914
e89d456f
AW		 915 /*
916 * Need to send CMD12 if -
917 * a) open-ended multiblock transfer (no CMD23)
918 * b) error in multiblock transfer
919 */
920 if (data->stop &&
921 (data->error ||
922 !host->mrq->sbc)) {
923
d129bceb
PO		 924 /*
925 * The controller needs a reset of internal state machines
926 * upon error conditions.
927 */
17b0429d 928 if (data->error) {
03231f9b
RK		 929 sdhci_do_reset(host, SDHCI_RESET_CMD);
930 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 931 }
932
933 sdhci_send_command(host, data->stop);
934 } else
935 tasklet_schedule(&host->finish_tasklet);
936}
937
c0e55129 938void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 939{
940 int flags;
fd2208d7 941 u32 mask;
7cb2c76f 942 unsigned long timeout;
d129bceb
PO		 943
944 WARN_ON(host->cmd);
945
96776200
RK		 946 /* Initially, a command has no error */
947 cmd->error = 0;
948
d129bceb 949 /* Wait max 10 ms */
7cb2c76f 950 timeout = 10;
fd2208d7
PO		 951
952 mask = SDHCI_CMD_INHIBIT;
953 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
954 mask |= SDHCI_DATA_INHIBIT;
955
956 /* We shouldn't wait for data inihibit for stop commands, even
957 though they might use busy signaling */
958 if (host->mrq->data && (cmd == host->mrq->data->stop))
959 mask &= ~SDHCI_DATA_INHIBIT;
960
4e4141a5 961 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 962 if (timeout == 0) {
2e4456f0
MV		 963 pr_err("%s: Controller never released inhibit bit(s).\n",
964 mmc_hostname(host->mmc));
d129bceb 965 sdhci_dumpregs(host);
17b0429d 966 cmd->error = -EIO;
d129bceb
PO		 967 tasklet_schedule(&host->finish_tasklet);
968 return;
969 }
7cb2c76f
PO		 970 timeout--;
971 mdelay(1);
972 }
d129bceb 973
3e1a6892 974 timeout = jiffies;
1d4d7744
UH		 975 if (!cmd->data && cmd->busy_timeout > 9000)
976 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 977 else
978 timeout += 10 * HZ;
979 mod_timer(&host->timer, timeout);
d129bceb
PO		 980
981 host->cmd = cmd;
e99783a4 982 host->busy_handle = 0;
d129bceb 983
a3c7778f 984 sdhci_prepare_data(host, cmd);
d129bceb 985
4e4141a5 986 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 987
e89d456f 988 sdhci_set_transfer_mode(host, cmd);
c7fa9963 989
d129bceb 990 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 991 pr_err("%s: Unsupported response type!\n",
d129bceb 992 mmc_hostname(host->mmc));
17b0429d 993 cmd->error = -EINVAL;
d129bceb
PO		 994 tasklet_schedule(&host->finish_tasklet);
995 return;
996 }
997
998 if (!(cmd->flags & MMC_RSP_PRESENT))
999 flags = SDHCI_CMD_RESP_NONE;
1000 else if (cmd->flags & MMC_RSP_136)
1001 flags = SDHCI_CMD_RESP_LONG;
1002 else if (cmd->flags & MMC_RSP_BUSY)
1003 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1004 else
1005 flags = SDHCI_CMD_RESP_SHORT;
1006
1007 if (cmd->flags & MMC_RSP_CRC)
1008 flags |= SDHCI_CMD_CRC;
1009 if (cmd->flags & MMC_RSP_OPCODE)
1010 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1011
1012 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1013 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1014 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1015 flags |= SDHCI_CMD_DATA;
1016
4e4141a5 1017 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1018}
c0e55129 1019EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1020
1021static void sdhci_finish_command(struct sdhci_host *host)
1022{
1023 int i;
1024
1025 BUG_ON(host->cmd == NULL);
1026
1027 if (host->cmd->flags & MMC_RSP_PRESENT) {
1028 if (host->cmd->flags & MMC_RSP_136) {
1029 /* CRC is stripped so we need to do some shifting. */
1030 for (i = 0;i < 4;i++) {
4e4141a5 1031 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1032 SDHCI_RESPONSE + (3-i)*4) << 8;
1033 if (i != 3)
1034 host->cmd->resp[i] |=
4e4141a5 1035 sdhci_readb(host,
d129bceb
PO		 1036 SDHCI_RESPONSE + (3-i)*4-1);
1037 }
1038 } else {
4e4141a5 1039 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1040 }
1041 }
1042
e89d456f
AW		 1043 /* Finished CMD23, now send actual command. */
1044 if (host->cmd == host->mrq->sbc) {
1045 host->cmd = NULL;
1046 sdhci_send_command(host, host->mrq->cmd);
1047 } else {
e538fbe8 1048
e89d456f
AW		 1049 /* Processed actual command. */
1050 if (host->data && host->data_early)
1051 sdhci_finish_data(host);
d129bceb 1052
e89d456f
AW		 1053 if (!host->cmd->data)
1054 tasklet_schedule(&host->finish_tasklet);
1055
1056 host->cmd = NULL;
1057 }
d129bceb
PO		 1058}
1059
52983382
KL		 1060static u16 sdhci_get_preset_value(struct sdhci_host *host)
1061{
d975f121 1062 u16 preset = 0;
52983382 1063
d975f121
RK		 1064 switch (host->timing) {
1065 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1066 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1067 break;
d975f121 1068 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1069 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1070 break;
d975f121 1071 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1072 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1073 break;
d975f121
RK		 1074 case MMC_TIMING_UHS_SDR104:
1075 case MMC_TIMING_MMC_HS200:
52983382
KL		 1076 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1077 break;
d975f121 1078 case MMC_TIMING_UHS_DDR50:
0dafa60e 1079 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1080 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1081 break;
e9fb05d5
AH		 1082 case MMC_TIMING_MMC_HS400:
1083 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1084 break;
52983382
KL		 1085 default:
1086 pr_warn("%s: Invalid UHS-I mode selected\n",
1087 mmc_hostname(host->mmc));
1088 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1089 break;
1090 }
1091 return preset;
1092}
1093
1771059c 1094void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1095{
c3ed3877 1096 int div = 0; /* Initialized for compiler warning */
df16219f 1097 int real_div = div, clk_mul = 1;
c3ed3877 1098 u16 clk = 0;
7cb2c76f 1099 unsigned long timeout;
5497159c 1100 bool switch_base_clk = false;
d129bceb 1101
1650d0c7
RK		 1102 host->mmc->actual_clock = 0;
1103
4e4141a5 1104 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
af951761 1105 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1106 mdelay(1);
d129bceb
PO		 1107
1108 if (clock == 0)
373073ef 1109 return;
d129bceb 1110
85105c53 1111 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1112 if (host->preset_enabled) {
52983382
KL		 1113 u16 pre_val;
1114
1115 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1116 pre_val = sdhci_get_preset_value(host);
1117 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1118 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1119 if (host->clk_mul &&
1120 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1121 clk = SDHCI_PROG_CLOCK_MODE;
1122 real_div = div + 1;
1123 clk_mul = host->clk_mul;
1124 } else {
1125 real_div = max_t(int, 1, div << 1);
1126 }
1127 goto clock_set;
1128 }
1129
c3ed3877
AN		 1130 /*
1131 * Check if the Host Controller supports Programmable Clock
1132 * Mode.
1133 */
1134 if (host->clk_mul) {
52983382
KL		 1135 for (div = 1; div <= 1024; div++) {
1136 if ((host->max_clk * host->clk_mul / div)
1137 <= clock)
1138 break;
1139 }
5497159c 1140 if ((host->max_clk * host->clk_mul / div) <= clock) {
1141 /*
1142 * Set Programmable Clock Mode in the Clock
1143 * Control register.
1144 */
1145 clk = SDHCI_PROG_CLOCK_MODE;
1146 real_div = div;
1147 clk_mul = host->clk_mul;
1148 div--;
1149 } else {
1150 /*
1151 * Divisor can be too small to reach clock
1152 * speed requirement. Then use the base clock.
1153 */
1154 switch_base_clk = true;
1155 }
1156 }
1157
1158 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1159 /* Version 3.00 divisors must be a multiple of 2. */
1160 if (host->max_clk <= clock)
1161 div = 1;
1162 else {
1163 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1164 div += 2) {
1165 if ((host->max_clk / div) <= clock)
1166 break;
1167 }
85105c53 1168 }
df16219f 1169 real_div = div;
c3ed3877 1170 div >>= 1;
d1955c3a
SG		 1171 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1172 && !div && host->max_clk <= 25000000)
1173 div = 1;
85105c53
ZG		 1174 }
1175 } else {
1176 /* Version 2.00 divisors must be a power of 2. */
0397526d 1177 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1178 if ((host->max_clk / div) <= clock)
1179 break;
1180 }
df16219f 1181 real_div = div;
c3ed3877 1182 div >>= 1;
d129bceb 1183 }
d129bceb 1184
52983382 1185clock_set:
03d6f5ff 1186 if (real_div)
df16219f 1187 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1188 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1189 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1190 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1191 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1192 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1193
27f6cb16
CB		 1194 /* Wait max 20 ms */
1195 timeout = 20;
4e4141a5 1196 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1197 & SDHCI_CLOCK_INT_STABLE)) {
1198 if (timeout == 0) {
2e4456f0
MV		 1199 pr_err("%s: Internal clock never stabilised.\n",
1200 mmc_hostname(host->mmc));
d129bceb
PO		 1201 sdhci_dumpregs(host);
1202 return;
1203 }
7cb2c76f
PO		 1204 timeout--;
1205 mdelay(1);
1206 }
d129bceb
PO		 1207
1208 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1209 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1210}
1771059c 1211EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1212
1dceb041
AH		 1213static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1214 unsigned short vdd)
146ad66e 1215{
3a48edc4 1216 struct mmc_host *mmc = host->mmc;
1dceb041
AH		 1217
1218 spin_unlock_irq(&host->lock);
1219 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1220 spin_lock_irq(&host->lock);
1221
1222 if (mode != MMC_POWER_OFF)
1223 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1224 else
1225 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1226}
1227
1228void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1229 unsigned short vdd)
1230{
8364248a 1231 u8 pwr = 0;
146ad66e 1232
24fbb3ca
RK		 1233 if (mode != MMC_POWER_OFF) {
1234 switch (1 << vdd) {
ae628903
PO		 1235 case MMC_VDD_165_195:
1236 pwr = SDHCI_POWER_180;
1237 break;
1238 case MMC_VDD_29_30:
1239 case MMC_VDD_30_31:
1240 pwr = SDHCI_POWER_300;
1241 break;
1242 case MMC_VDD_32_33:
1243 case MMC_VDD_33_34:
1244 pwr = SDHCI_POWER_330;
1245 break;
1246 default:
9d5de93f
AH		 1247 WARN(1, "%s: Invalid vdd %#x\n",
1248 mmc_hostname(host->mmc), vdd);
1249 break;
ae628903
PO		 1250 }
1251 }
1252
1253 if (host->pwr == pwr)
e921a8b6 1254 return;
146ad66e 1255
ae628903
PO		 1256 host->pwr = pwr;
1257
1258 if (pwr == 0) {
4e4141a5 1259 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1260 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1261 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 1262 } else {
1263 /*
1264 * Spec says that we should clear the power reg before setting
1265 * a new value. Some controllers don't seem to like this though.
1266 */
1267 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1268 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1269
e921a8b6
RK		 1270 /*
1271 * At least the Marvell CaFe chip gets confused if we set the
1272 * voltage and set turn on power at the same time, so set the
1273 * voltage first.
1274 */
1275 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1276 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1277
e921a8b6 1278 pwr |= SDHCI_POWER_ON;
146ad66e 1279
e921a8b6 1280 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1281
e921a8b6
RK		 1282 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1283 sdhci_runtime_pm_bus_on(host);
f0710a55 1284
e921a8b6
RK		 1285 /*
1286 * Some controllers need an extra 10ms delay of 10ms before
1287 * they can apply clock after applying power
1288 */
1289 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1290 mdelay(10);
1291 }
1dceb041
AH		 1292}
1293EXPORT_SYMBOL_GPL(sdhci_set_power);
918f4cbd 1294
1dceb041
AH		 1295static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1296 unsigned short vdd)
1297{
1298 struct mmc_host *mmc = host->mmc;
1299
1300 if (host->ops->set_power)
1301 host->ops->set_power(host, mode, vdd);
1302 else if (!IS_ERR(mmc->supply.vmmc))
1303 sdhci_set_power_reg(host, mode, vdd);
1304 else
1305 sdhci_set_power(host, mode, vdd);
146ad66e
PO		 1306}
1307
d129bceb
PO		 1308/*****************************************************************************\
1309 * *
1310 * MMC callbacks *
1311 * *
1312\*****************************************************************************/
1313
1314static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1315{
1316 struct sdhci_host *host;
505a8680 1317 int present;
d129bceb
PO		 1318 unsigned long flags;
1319
1320 host = mmc_priv(mmc);
1321
66fd8ad5
AH		 1322 sdhci_runtime_pm_get(host);
1323
04e079cf 1324 /* Firstly check card presence */
8d28b7a7 1325 present = mmc->ops->get_cd(mmc);
2836766a 1326
d129bceb
PO		 1327 spin_lock_irqsave(&host->lock, flags);
1328
1329 WARN_ON(host->mrq != NULL);
1330
f9134319 1331#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1332 sdhci_activate_led(host);
2f730fec 1333#endif
e89d456f
AW		 1334
1335 /*
1336 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1337 * requests if Auto-CMD12 is enabled.
1338 */
1339 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1340 if (mrq->stop) {
1341 mrq->data->stop = NULL;
1342 mrq->stop = NULL;
1343 }
1344 }
d129bceb
PO		 1345
1346 host->mrq = mrq;
1347
68d1fb7e 1348 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1349 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1350 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1351 } else {
8edf6371 1352 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1353 sdhci_send_command(host, mrq->sbc);
1354 else
1355 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1356 }
d129bceb 1357
5f25a66f 1358 mmiowb();
d129bceb
PO		 1359 spin_unlock_irqrestore(&host->lock, flags);
1360}
1361
2317f56c
RK		 1362void sdhci_set_bus_width(struct sdhci_host *host, int width)
1363{
1364 u8 ctrl;
1365
1366 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1367 if (width == MMC_BUS_WIDTH_8) {
1368 ctrl &= ~SDHCI_CTRL_4BITBUS;
1369 if (host->version >= SDHCI_SPEC_300)
1370 ctrl |= SDHCI_CTRL_8BITBUS;
1371 } else {
1372 if (host->version >= SDHCI_SPEC_300)
1373 ctrl &= ~SDHCI_CTRL_8BITBUS;
1374 if (width == MMC_BUS_WIDTH_4)
1375 ctrl |= SDHCI_CTRL_4BITBUS;
1376 else
1377 ctrl &= ~SDHCI_CTRL_4BITBUS;
1378 }
1379 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1380}
1381EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1382
96d7b78c
RK		 1383void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1384{
1385 u16 ctrl_2;
1386
1387 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1388 /* Select Bus Speed Mode for host */
1389 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1390 if ((timing == MMC_TIMING_MMC_HS200) ||
1391 (timing == MMC_TIMING_UHS_SDR104))
1392 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1393 else if (timing == MMC_TIMING_UHS_SDR12)
1394 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1395 else if (timing == MMC_TIMING_UHS_SDR25)
1396 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1397 else if (timing == MMC_TIMING_UHS_SDR50)
1398 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1399 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1400 (timing == MMC_TIMING_MMC_DDR52))
1401 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1402 else if (timing == MMC_TIMING_MMC_HS400)
1403 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1404 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1405}
1406EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1407
66fd8ad5 1408static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1409{
d129bceb
PO		 1410 unsigned long flags;
1411 u8 ctrl;
3a48edc4 1412 struct mmc_host *mmc = host->mmc;
d129bceb 1413
d129bceb
PO		 1414 spin_lock_irqsave(&host->lock, flags);
1415
ceb6143b
AH		 1416 if (host->flags & SDHCI_DEVICE_DEAD) {
1417 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1418 if (!IS_ERR(mmc->supply.vmmc) &&
1419 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1420 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1421 return;
1422 }
1e72859e 1423
d129bceb
PO		 1424 /*
1425 * Reset the chip on each power off.
1426 * Should clear out any weird states.
1427 */
1428 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1429 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1430 sdhci_reinit(host);
d129bceb
PO		 1431 }
1432
52983382 1433 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1434 (ios->power_mode == MMC_POWER_UP) &&
1435 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1436 sdhci_enable_preset_value(host, false);
1437
373073ef 1438 if (!ios->clock || ios->clock != host->clock) {
1771059c 1439 host->ops->set_clock(host, ios->clock);
373073ef 1440 host->clock = ios->clock;
03d6f5ff
AD		 1441
1442 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1443 host->clock) {
1444 host->timeout_clk = host->mmc->actual_clock ?
1445 host->mmc->actual_clock / 1000 :
1446 host->clock / 1000;
1447 host->mmc->max_busy_timeout =
1448 host->ops->get_max_timeout_count ?
1449 host->ops->get_max_timeout_count(host) :
1450 1 << 27;
1451 host->mmc->max_busy_timeout /= host->timeout_clk;
1452 }
373073ef 1453 }
d129bceb 1454
1dceb041 1455 __sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1456
643a81ff
PR		 1457 if (host->ops->platform_send_init_74_clocks)
1458 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1459
2317f56c 1460 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1461
15ec4461 1462 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1463
3ab9c8da
PR		 1464 if ((ios->timing == MMC_TIMING_SD_HS ||
1465 ios->timing == MMC_TIMING_MMC_HS)
1466 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1467 ctrl |= SDHCI_CTRL_HISPD;
1468 else
1469 ctrl &= ~SDHCI_CTRL_HISPD;
1470
d6d50a15 1471 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1472 u16 clk, ctrl_2;
49c468fc
AN		 1473
1474 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1475 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1476 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1477 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1478 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1479 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1480 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1481 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1482 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1483
da91a8f9 1484 if (!host->preset_enabled) {
758535c4 1485 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1486 /*
1487 * We only need to set Driver Strength if the
1488 * preset value enable is not set.
1489 */
da91a8f9 1490 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1491 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1492 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1493 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1494 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1495 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1496 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1497 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1498 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1499 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1500 else {
2e4456f0
MV		 1501 pr_warn("%s: invalid driver type, default to driver type B\n",
1502 mmc_hostname(mmc));
43e943a0
PG		 1503 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1504 }
d6d50a15
AN		 1505
1506 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1507 } else {
1508 /*
1509 * According to SDHC Spec v3.00, if the Preset Value
1510 * Enable in the Host Control 2 register is set, we
1511 * need to reset SD Clock Enable before changing High
1512 * Speed Enable to avoid generating clock gliches.
1513 */
758535c4
AN		 1514
1515 /* Reset SD Clock Enable */
1516 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1517 clk &= ~SDHCI_CLOCK_CARD_EN;
1518 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1519
1520 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1521
1522 /* Re-enable SD Clock */
1771059c 1523 host->ops->set_clock(host, host->clock);
d6d50a15 1524 }
49c468fc 1525
49c468fc
AN		 1526 /* Reset SD Clock Enable */
1527 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1528 clk &= ~SDHCI_CLOCK_CARD_EN;
1529 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1530
96d7b78c 1531 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1532 host->timing = ios->timing;
49c468fc 1533
52983382
KL		 1534 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1535 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1536 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1537 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1538 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1539 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1540 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1541 u16 preset;
1542
1543 sdhci_enable_preset_value(host, true);
1544 preset = sdhci_get_preset_value(host);
1545 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1546 >> SDHCI_PRESET_DRV_SHIFT;
1547 }
1548
49c468fc 1549 /* Re-enable SD Clock */
1771059c 1550 host->ops->set_clock(host, host->clock);
758535c4
AN		 1551 } else
1552 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1553
b8352260
LD		 1554 /*
1555 * Some (ENE) controllers go apeshit on some ios operation,
1556 * signalling timeout and CRC errors even on CMD0. Resetting
1557 * it on each ios seems to solve the problem.
1558 */
c63705e1 1559 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1560 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1561
5f25a66f 1562 mmiowb();
d129bceb
PO		 1563 spin_unlock_irqrestore(&host->lock, flags);
1564}
1565
66fd8ad5
AH		 1566static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1567{
1568 struct sdhci_host *host = mmc_priv(mmc);
1569
1570 sdhci_runtime_pm_get(host);
1571 sdhci_do_set_ios(host, ios);
1572 sdhci_runtime_pm_put(host);
1573}
1574
94144a46
KL		 1575static int sdhci_do_get_cd(struct sdhci_host *host)
1576{
1577 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1578
1579 if (host->flags & SDHCI_DEVICE_DEAD)
1580 return 0;
1581
88af5655
II		 1582 /* If nonremovable, assume that the card is always present. */
1583 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
94144a46
KL		 1584 return 1;
1585
88af5655
II		 1586 /*
1587 * Try slot gpio detect, if defined it take precedence
1588 * over build in controller functionality
1589 */
94144a46
KL		 1590 if (!IS_ERR_VALUE(gpio_cd))
1591 return !!gpio_cd;
1592
88af5655
II		 1593 /* If polling, assume that the card is always present. */
1594 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1595 return 1;
1596
94144a46
KL		 1597 /* Host native card detect */
1598 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1599}
1600
1601static int sdhci_get_cd(struct mmc_host *mmc)
1602{
1603 struct sdhci_host *host = mmc_priv(mmc);
1604 int ret;
1605
1606 sdhci_runtime_pm_get(host);
1607 ret = sdhci_do_get_cd(host);
1608 sdhci_runtime_pm_put(host);
1609 return ret;
1610}
1611
66fd8ad5 1612static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1613{
d129bceb 1614 unsigned long flags;
2dfb579c 1615 int is_readonly;
d129bceb 1616
d129bceb
PO		 1617 spin_lock_irqsave(&host->lock, flags);
1618
1e72859e 1619 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1620 is_readonly = 0;
1621 else if (host->ops->get_ro)
1622 is_readonly = host->ops->get_ro(host);
1e72859e 1623 else
2dfb579c
WS		 1624 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1625 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1626
1627 spin_unlock_irqrestore(&host->lock, flags);
1628
2dfb579c
WS		 1629 /* This quirk needs to be replaced by a callback-function later */
1630 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1631 !is_readonly : is_readonly;
d129bceb
PO		 1632}
1633
82b0e23a
TI		 1634#define SAMPLE_COUNT 5
1635
66fd8ad5 1636static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1637{
82b0e23a
TI		 1638 int i, ro_count;
1639
82b0e23a 1640 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1641 return sdhci_check_ro(host);
82b0e23a
TI		 1642
1643 ro_count = 0;
1644 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1645 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1646 if (++ro_count > SAMPLE_COUNT / 2)
1647 return 1;
1648 }
1649 msleep(30);
1650 }
1651 return 0;
1652}
1653
20758b66
AH		 1654static void sdhci_hw_reset(struct mmc_host *mmc)
1655{
1656 struct sdhci_host *host = mmc_priv(mmc);
1657
1658 if (host->ops && host->ops->hw_reset)
1659 host->ops->hw_reset(host);
1660}
1661
66fd8ad5 1662static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1663{
66fd8ad5
AH		 1664 struct sdhci_host *host = mmc_priv(mmc);
1665 int ret;
f75979b7 1666
66fd8ad5
AH		 1667 sdhci_runtime_pm_get(host);
1668 ret = sdhci_do_get_ro(host);
1669 sdhci_runtime_pm_put(host);
1670 return ret;
1671}
f75979b7 1672
66fd8ad5
AH		 1673static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1674{
be138554 1675 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1676 if (enable)
b537f94c 1677 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1678 else
b537f94c
RK		 1679 host->ier &= ~SDHCI_INT_CARD_INT;
1680
1681 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1682 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1683 mmiowb();
1684 }
66fd8ad5
AH		 1685}
1686
1687static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1688{
1689 struct sdhci_host *host = mmc_priv(mmc);
1690 unsigned long flags;
f75979b7 1691
ef104333
RK		 1692 sdhci_runtime_pm_get(host);
1693
66fd8ad5 1694 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1695 if (enable)
1696 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1697 else
1698 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1699
66fd8ad5 1700 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1701 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1702
1703 sdhci_runtime_pm_put(host);
f75979b7
PO		 1704}
1705
20b92a30 1706static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1707 struct mmc_ios *ios)
f2119df6 1708{
3a48edc4 1709 struct mmc_host *mmc = host->mmc;
20b92a30 1710 u16 ctrl;
6231f3de 1711 int ret;
f2119df6 1712
20b92a30
KL		 1713 /*
1714 * Signal Voltage Switching is only applicable for Host Controllers
1715 * v3.00 and above.
1716 */
1717 if (host->version < SDHCI_SPEC_300)
1718 return 0;
6231f3de 1719
f2119df6 1720 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1721
21f5998f 1722 switch (ios->signal_voltage) {
20b92a30
KL		 1723 case MMC_SIGNAL_VOLTAGE_330:
1724 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1725 ctrl &= ~SDHCI_CTRL_VDD_180;
1726 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1727
3a48edc4
TK		 1728 if (!IS_ERR(mmc->supply.vqmmc)) {
1729 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1730 3600000);
20b92a30 1731 if (ret) {
6606110d
JP		 1732 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1733 mmc_hostname(mmc));
20b92a30
KL		 1734 return -EIO;
1735 }
1736 }
1737 /* Wait for 5ms */
1738 usleep_range(5000, 5500);
f2119df6 1739
20b92a30
KL		 1740 /* 3.3V regulator output should be stable within 5 ms */
1741 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1742 if (!(ctrl & SDHCI_CTRL_VDD_180))
1743 return 0;
6231f3de 1744
6606110d
JP		 1745 pr_warn("%s: 3.3V regulator output did not became stable\n",
1746 mmc_hostname(mmc));
20b92a30
KL		 1747
1748 return -EAGAIN;
1749 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1750 if (!IS_ERR(mmc->supply.vqmmc)) {
1751 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1752 1700000, 1950000);
1753 if (ret) {
6606110d
JP		 1754 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1755 mmc_hostname(mmc));
20b92a30
KL		 1756 return -EIO;
1757 }
1758 }
6231f3de 1759
6231f3de
PR		 1760 /*
1761 * Enable 1.8V Signal Enable in the Host Control2
1762 * register
1763 */
20b92a30
KL		 1764 ctrl |= SDHCI_CTRL_VDD_180;
1765 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1766
9d967a61
VY		 1767 /* Some controller need to do more when switching */
1768 if (host->ops->voltage_switch)
1769 host->ops->voltage_switch(host);
1770
20b92a30
KL		 1771 /* 1.8V regulator output should be stable within 5 ms */
1772 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1773 if (ctrl & SDHCI_CTRL_VDD_180)
1774 return 0;
f2119df6 1775
6606110d
JP		 1776 pr_warn("%s: 1.8V regulator output did not became stable\n",
1777 mmc_hostname(mmc));
f2119df6 1778
20b92a30
KL		 1779 return -EAGAIN;
1780 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1781 if (!IS_ERR(mmc->supply.vqmmc)) {
1782 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1783 1300000);
20b92a30 1784 if (ret) {
6606110d
JP		 1785 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1786 mmc_hostname(mmc));
20b92a30 1787 return -EIO;
f2119df6
AN		 1788 }
1789 }
6231f3de 1790 return 0;
20b92a30 1791 default:
f2119df6
AN		 1792 /* No signal voltage switch required */
1793 return 0;
20b92a30 1794 }
f2119df6
AN		 1795}
1796
66fd8ad5 1797static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1798 struct mmc_ios *ios)
66fd8ad5
AH		 1799{
1800 struct sdhci_host *host = mmc_priv(mmc);
1801 int err;
1802
1803 if (host->version < SDHCI_SPEC_300)
1804 return 0;
1805 sdhci_runtime_pm_get(host);
21f5998f 1806 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1807 sdhci_runtime_pm_put(host);
1808 return err;
1809}
1810
20b92a30
KL		 1811static int sdhci_card_busy(struct mmc_host *mmc)
1812{
1813 struct sdhci_host *host = mmc_priv(mmc);
1814 u32 present_state;
1815
1816 sdhci_runtime_pm_get(host);
1817 /* Check whether DAT[3:0] is 0000 */
1818 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1819 sdhci_runtime_pm_put(host);
1820
1821 return !(present_state & SDHCI_DATA_LVL_MASK);
1822}
1823
b5540ce1
AH		 1824static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1825{
1826 struct sdhci_host *host = mmc_priv(mmc);
1827 unsigned long flags;
1828
1829 spin_lock_irqsave(&host->lock, flags);
1830 host->flags |= SDHCI_HS400_TUNING;
1831 spin_unlock_irqrestore(&host->lock, flags);
1832
1833 return 0;
1834}
1835
069c9f14 1836static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1837{
4b6f37d3 1838 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1839 u16 ctrl;
b513ea25 1840 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1841 int err = 0;
2b35bd83 1842 unsigned long flags;
38e40bf5 1843 unsigned int tuning_count = 0;
b5540ce1 1844 bool hs400_tuning;
b513ea25 1845
66fd8ad5 1846 sdhci_runtime_pm_get(host);
2b35bd83 1847 spin_lock_irqsave(&host->lock, flags);
b513ea25 1848
b5540ce1
AH		 1849 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1850 host->flags &= ~SDHCI_HS400_TUNING;
1851
38e40bf5
AH		 1852 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1853 tuning_count = host->tuning_count;
1854
b513ea25 1855 /*
9faac7b9
WY		 1856 * The Host Controller needs tuning in case of SDR104 and DDR50
1857 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1858 * the Capabilities register.
069c9f14
G		 1859 * If the Host Controller supports the HS200 mode then the
1860 * tuning function has to be executed.
b513ea25 1861 */
4b6f37d3 1862 switch (host->timing) {
b5540ce1 1863 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1864 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1865 err = -EINVAL;
1866 goto out_unlock;
1867
4b6f37d3 1868 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1869 /*
1870 * Periodic re-tuning for HS400 is not expected to be needed, so
1871 * disable it here.
1872 */
1873 if (hs400_tuning)
1874 tuning_count = 0;
1875 break;
1876
4b6f37d3 1877 case MMC_TIMING_UHS_SDR104:
9faac7b9 1878 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1879 break;
1880
1881 case MMC_TIMING_UHS_SDR50:
1882 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1883 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1884 break;
1885 /* FALLTHROUGH */
1886
1887 default:
d519c863 1888 goto out_unlock;
b513ea25
AN		 1889 }
1890
45251812 1891 if (host->ops->platform_execute_tuning) {
2b35bd83 1892 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1893 err = host->ops->platform_execute_tuning(host, opcode);
1894 sdhci_runtime_pm_put(host);
1895 return err;
1896 }
1897
4b6f37d3
RK		 1898 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1899 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1900 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1901 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1902 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1903
1904 /*
1905 * As per the Host Controller spec v3.00, tuning command
1906 * generates Buffer Read Ready interrupt, so enable that.
1907 *
1908 * Note: The spec clearly says that when tuning sequence
1909 * is being performed, the controller does not generate
1910 * interrupts other than Buffer Read Ready interrupt. But
1911 * to make sure we don't hit a controller bug, we _only_
1912 * enable Buffer Read Ready interrupt here.
1913 */
b537f94c
RK		 1914 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1915 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1916
1917 /*
1918 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1919 * of loops reaches 40 times or a timeout of 150ms occurs.
1920 */
b513ea25
AN		 1921 do {
1922 struct mmc_command cmd = {0};
66fd8ad5 1923 struct mmc_request mrq = {NULL};
b513ea25 1924
069c9f14 1925 cmd.opcode = opcode;
b513ea25
AN		 1926 cmd.arg = 0;
1927 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1928 cmd.retries = 0;
1929 cmd.data = NULL;
1930 cmd.error = 0;
1931
7ce45e95
AC		 1932 if (tuning_loop_counter-- == 0)
1933 break;
1934
b513ea25
AN		 1935 mrq.cmd = &cmd;
1936 host->mrq = &mrq;
1937
1938 /*
1939 * In response to CMD19, the card sends 64 bytes of tuning
1940 * block to the Host Controller. So we set the block size
1941 * to 64 here.
1942 */
069c9f14
G		 1943 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1944 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1945 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1946 SDHCI_BLOCK_SIZE);
1947 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1948 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1949 SDHCI_BLOCK_SIZE);
1950 } else {
1951 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1952 SDHCI_BLOCK_SIZE);
1953 }
b513ea25
AN		 1954
1955 /*
1956 * The tuning block is sent by the card to the host controller.
1957 * So we set the TRNS_READ bit in the Transfer Mode register.
1958 * This also takes care of setting DMA Enable and Multi Block
1959 * Select in the same register to 0.
1960 */
1961 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1962
1963 sdhci_send_command(host, &cmd);
1964
1965 host->cmd = NULL;
1966 host->mrq = NULL;
1967
2b35bd83 1968 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1969 /* Wait for Buffer Read Ready interrupt */
1970 wait_event_interruptible_timeout(host->buf_ready_int,
1971 (host->tuning_done == 1),
1972 msecs_to_jiffies(50));
2b35bd83 1973 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1974
1975 if (!host->tuning_done) {
2e4456f0 1976 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 1977 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1978 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1979 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1980 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1981
1982 err = -EIO;
1983 goto out;
1984 }
1985
1986 host->tuning_done = 0;
1987
1988 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 1989
1990 /* eMMC spec does not require a delay between tuning cycles */
1991 if (opcode == MMC_SEND_TUNING_BLOCK)
1992 mdelay(1);
b513ea25
AN		 1993 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1994
1995 /*
1996 * The Host Driver has exhausted the maximum number of loops allowed,
1997 * so use fixed sampling frequency.
1998 */
7ce45e95 1999 if (tuning_loop_counter < 0) {
b513ea25
AN		 2000 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2001 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2002 }
2003 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2004 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2005 err = -EIO;
b513ea25
AN		 2006 }
2007
2008out:
38e40bf5 2009 if (tuning_count) {
66c39dfc
AH		 2010 /*
2011 * In case tuning fails, host controllers which support
2012 * re-tuning can try tuning again at a later time, when the
2013 * re-tuning timer expires. So for these controllers, we
2014 * return 0. Since there might be other controllers who do not
2015 * have this capability, we return error for them.
2016 */
2017 err = 0;
cf2b5eea
AN		 2018 }
2019
66c39dfc 2020 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2021
b537f94c
RK		 2022 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2023 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2024out_unlock:
2b35bd83 2025 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2026 sdhci_runtime_pm_put(host);
b513ea25
AN		 2027
2028 return err;
2029}
2030
cb849648
AH		 2031static int sdhci_select_drive_strength(struct mmc_card *card,
2032 unsigned int max_dtr, int host_drv,
2033 int card_drv, int *drv_type)
2034{
2035 struct sdhci_host *host = mmc_priv(card->host);
2036
2037 if (!host->ops->select_drive_strength)
2038 return 0;
2039
2040 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2041 card_drv, drv_type);
2042}
52983382
KL		 2043
2044static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2045{
4d55c5a1
AN		 2046 /* Host Controller v3.00 defines preset value registers */
2047 if (host->version < SDHCI_SPEC_300)
2048 return;
2049
4d55c5a1
AN		 2050 /*
2051 * We only enable or disable Preset Value if they are not already
2052 * enabled or disabled respectively. Otherwise, we bail out.
2053 */
da91a8f9
RK		 2054 if (host->preset_enabled != enable) {
2055 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2056
2057 if (enable)
2058 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2059 else
2060 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2061
4d55c5a1 2062 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2063
2064 if (enable)
2065 host->flags |= SDHCI_PV_ENABLED;
2066 else
2067 host->flags &= ~SDHCI_PV_ENABLED;
2068
2069 host->preset_enabled = enable;
4d55c5a1 2070 }
66fd8ad5
AH		 2071}
2072
348487cb
HC		 2073static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2074 int err)
2075{
2076 struct sdhci_host *host = mmc_priv(mmc);
2077 struct mmc_data *data = mrq->data;
2078
f48f039c 2079 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2080 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2081 data->flags & MMC_DATA_WRITE ?
2082 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2083
2084 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2085}
2086
348487cb
HC		 2087static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2088 bool is_first_req)
2089{
2090 struct sdhci_host *host = mmc_priv(mmc);
2091
d31911b9 2092 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2093
2094 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2095 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2096}
2097
71e69211 2098static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2099{
71e69211 2100 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2101 unsigned long flags;
2836766a 2102 int present;
d129bceb 2103
722e1280
CD		 2104 /* First check if client has provided their own card event */
2105 if (host->ops->card_event)
2106 host->ops->card_event(host);
2107
2836766a
KK		 2108 present = sdhci_do_get_cd(host);
2109
d129bceb
PO		 2110 spin_lock_irqsave(&host->lock, flags);
2111
66fd8ad5 2112 /* Check host->mrq first in case we are runtime suspended */
2836766a 2113 if (host->mrq && !present) {
a3c76eb9 2114 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2115 mmc_hostname(host->mmc));
a3c76eb9 2116 pr_err("%s: Resetting controller.\n",
66fd8ad5 2117 mmc_hostname(host->mmc));
d129bceb 2118
03231f9b
RK		 2119 sdhci_do_reset(host, SDHCI_RESET_CMD);
2120 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2121
66fd8ad5
AH		 2122 host->mrq->cmd->error = -ENOMEDIUM;
2123 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2124 }
2125
2126 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2127}
2128
2129static const struct mmc_host_ops sdhci_ops = {
2130 .request = sdhci_request,
348487cb
HC		 2131 .post_req = sdhci_post_req,
2132 .pre_req = sdhci_pre_req,
71e69211 2133 .set_ios = sdhci_set_ios,
94144a46 2134 .get_cd = sdhci_get_cd,
71e69211
GL		 2135 .get_ro = sdhci_get_ro,
2136 .hw_reset = sdhci_hw_reset,
2137 .enable_sdio_irq = sdhci_enable_sdio_irq,
2138 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2139 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2140 .execute_tuning = sdhci_execute_tuning,
cb849648 2141 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2142 .card_event = sdhci_card_event,
20b92a30 2143 .card_busy = sdhci_card_busy,
71e69211
GL		 2144};
2145
2146/*****************************************************************************\
2147 * *
2148 * Tasklets *
2149 * *
2150\*****************************************************************************/
2151
d129bceb
PO		 2152static void sdhci_tasklet_finish(unsigned long param)
2153{
2154 struct sdhci_host *host;
2155 unsigned long flags;
2156 struct mmc_request *mrq;
2157
2158 host = (struct sdhci_host*)param;
2159
66fd8ad5
AH		 2160 spin_lock_irqsave(&host->lock, flags);
2161
0c9c99a7
CB		 2162 /*
2163 * If this tasklet gets rescheduled while running, it will
2164 * be run again afterwards but without any active request.
2165 */
66fd8ad5
AH		 2166 if (!host->mrq) {
2167 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2168 return;
66fd8ad5 2169 }
d129bceb
PO		 2170
2171 del_timer(&host->timer);
2172
2173 mrq = host->mrq;
2174
054cedff
RK		 2175 /*
2176 * Always unmap the data buffers if they were mapped by
2177 * sdhci_prepare_data() whenever we finish with a request.
2178 * This avoids leaking DMA mappings on error.
2179 */
2180 if (host->flags & SDHCI_REQ_USE_DMA) {
2181 struct mmc_data *data = mrq->data;
2182
2183 if (data && data->host_cookie == COOKIE_MAPPED) {
2184 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2185 (data->flags & MMC_DATA_READ) ?
2186 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2187 data->host_cookie = COOKIE_UNMAPPED;
2188 }
2189 }
2190
d129bceb
PO		 2191 /*
2192 * The controller needs a reset of internal state machines
2193 * upon error conditions.
2194 */
1e72859e 2195 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2196 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2197 (mrq->sbc && mrq->sbc->error) ||
2198 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2199 (mrq->data->stop && mrq->data->stop->error))) ||
2200 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2201
2202 /* Some controllers need this kick or reset won't work here */
8213af3b 2203 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2204 /* This is to force an update */
1771059c 2205 host->ops->set_clock(host, host->clock);
645289dc
PO		 2206
2207 /* Spec says we should do both at the same time, but Ricoh
2208 controllers do not like that. */
03231f9b
RK		 2209 sdhci_do_reset(host, SDHCI_RESET_CMD);
2210 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2211 }
2212
2213 host->mrq = NULL;
2214 host->cmd = NULL;
2215 host->data = NULL;
2216
f9134319 2217#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2218 sdhci_deactivate_led(host);
2f730fec 2219#endif
d129bceb 2220
5f25a66f 2221 mmiowb();
d129bceb
PO		 2222 spin_unlock_irqrestore(&host->lock, flags);
2223
2224 mmc_request_done(host->mmc, mrq);
66fd8ad5 2225 sdhci_runtime_pm_put(host);
d129bceb
PO		 2226}
2227
2228static void sdhci_timeout_timer(unsigned long data)
2229{
2230 struct sdhci_host *host;
2231 unsigned long flags;
2232
2233 host = (struct sdhci_host*)data;
2234
2235 spin_lock_irqsave(&host->lock, flags);
2236
2237 if (host->mrq) {
2e4456f0
MV		 2238 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2239 mmc_hostname(host->mmc));
d129bceb
PO		 2240 sdhci_dumpregs(host);
2241
2242 if (host->data) {
17b0429d 2243 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2244 sdhci_finish_data(host);
2245 } else {
2246 if (host->cmd)
17b0429d 2247 host->cmd->error = -ETIMEDOUT;
d129bceb 2248 else
17b0429d 2249 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2250
2251 tasklet_schedule(&host->finish_tasklet);
2252 }
2253 }
2254
5f25a66f 2255 mmiowb();
d129bceb
PO		 2256 spin_unlock_irqrestore(&host->lock, flags);
2257}
2258
2259/*****************************************************************************\
2260 * *
2261 * Interrupt handling *
2262 * *
2263\*****************************************************************************/
2264
61541397 2265static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2266{
2267 BUG_ON(intmask == 0);
2268
2269 if (!host->cmd) {
2e4456f0
MV		 2270 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2271 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2272 sdhci_dumpregs(host);
2273 return;
2274 }
2275
ec014cba
RK		 2276 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2277 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2278 if (intmask & SDHCI_INT_TIMEOUT)
2279 host->cmd->error = -ETIMEDOUT;
2280 else
2281 host->cmd->error = -EILSEQ;
43b58b36 2282
71fcbda0
RK		 2283 /*
2284 * If this command initiates a data phase and a response
2285 * CRC error is signalled, the card can start transferring
2286 * data - the card may have received the command without
2287 * error. We must not terminate the mmc_request early.
2288 *
2289 * If the card did not receive the command or returned an
2290 * error which prevented it sending data, the data phase
2291 * will time out.
2292 */
2293 if (host->cmd->data &&
2294 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2295 SDHCI_INT_CRC) {
2296 host->cmd = NULL;
2297 return;
2298 }
2299
d129bceb 2300 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2301 return;
2302 }
2303
2304 /*
2305 * The host can send and interrupt when the busy state has
2306 * ended, allowing us to wait without wasting CPU cycles.
2307 * Unfortunately this is overloaded on the "data complete"
2308 * interrupt, so we need to take some care when handling
2309 * it.
2310 *
2311 * Note: The 1.0 specification is a bit ambiguous about this
2312 * feature so there might be some problems with older
2313 * controllers.
2314 */
2315 if (host->cmd->flags & MMC_RSP_BUSY) {
2316 if (host->cmd->data)
2e4456f0 2317 DBG("Cannot wait for busy signal when also doing a data transfer");
e99783a4
CM		 2318 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2319 && !host->busy_handle) {
2320 /* Mark that command complete before busy is ended */
2321 host->busy_handle = 1;
e809517f 2322 return;
e99783a4 2323 }
f945405c
BD		 2324
2325 /* The controller does not support the end-of-busy IRQ,
2326 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2327 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2328 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2329 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2330 }
2331
2332 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2333 sdhci_finish_command(host);
d129bceb
PO		 2334}
2335
0957c333 2336#ifdef CONFIG_MMC_DEBUG
08621b18 2337static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2338{
2339 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2340 void *desc = host->adma_table;
6882a8c0
BD		 2341
2342 sdhci_dumpregs(host);
2343
2344 while (true) {
e57a5f61
AH		 2345 struct sdhci_adma2_64_desc *dma_desc = desc;
2346
2347 if (host->flags & SDHCI_USE_64_BIT_DMA)
2348 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2349 name, desc, le32_to_cpu(dma_desc->addr_hi),
2350 le32_to_cpu(dma_desc->addr_lo),
2351 le16_to_cpu(dma_desc->len),
2352 le16_to_cpu(dma_desc->cmd));
2353 else
2354 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2355 name, desc, le32_to_cpu(dma_desc->addr_lo),
2356 le16_to_cpu(dma_desc->len),
2357 le16_to_cpu(dma_desc->cmd));
6882a8c0 2358
76fe379a 2359 desc += host->desc_sz;
6882a8c0 2360
0545230f 2361 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2362 break;
2363 }
2364}
2365#else
08621b18 2366static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2367#endif
2368
d129bceb
PO		 2369static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2370{
069c9f14 2371 u32 command;
d129bceb
PO		 2372 BUG_ON(intmask == 0);
2373
b513ea25
AN		 2374 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2375 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2376 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2377 if (command == MMC_SEND_TUNING_BLOCK ||
2378 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2379 host->tuning_done = 1;
2380 wake_up(&host->buf_ready_int);
2381 return;
2382 }
2383 }
2384
d129bceb
PO		 2385 if (!host->data) {
2386 /*
e809517f
PO		 2387 * The "data complete" interrupt is also used to
2388 * indicate that a busy state has ended. See comment
2389 * above in sdhci_cmd_irq().
d129bceb 2390 */
e809517f 2391 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2392 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2393 host->cmd->error = -ETIMEDOUT;
2394 tasklet_schedule(&host->finish_tasklet);
2395 return;
2396 }
e809517f 2397 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2398 /*
2399 * Some cards handle busy-end interrupt
2400 * before the command completed, so make
2401 * sure we do things in the proper order.
2402 */
2403 if (host->busy_handle)
2404 sdhci_finish_command(host);
2405 else
2406 host->busy_handle = 1;
e809517f
PO		 2407 return;
2408 }
2409 }
d129bceb 2410
2e4456f0
MV		 2411 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2412 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2413 sdhci_dumpregs(host);
2414
2415 return;
2416 }
2417
2418 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2419 host->data->error = -ETIMEDOUT;
22113efd
AL		 2420 else if (intmask & SDHCI_INT_DATA_END_BIT)
2421 host->data->error = -EILSEQ;
2422 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2423 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2424 != MMC_BUS_TEST_R)
17b0429d 2425 host->data->error = -EILSEQ;
6882a8c0 2426 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2427 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2428 sdhci_adma_show_error(host);
2134a922 2429 host->data->error = -EIO;
a4071fbb
HZ		 2430 if (host->ops->adma_workaround)
2431 host->ops->adma_workaround(host, intmask);
6882a8c0 2432 }
d129bceb 2433
17b0429d 2434 if (host->data->error)
d129bceb
PO		 2435 sdhci_finish_data(host);
2436 else {
a406f5a3 2437 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2438 sdhci_transfer_pio(host);
2439
6ba736a1
PO		 2440 /*
2441 * We currently don't do anything fancy with DMA
2442 * boundaries, but as we can't disable the feature
2443 * we need to at least restart the transfer.
f6a03cbf
MV		 2444 *
2445 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2446 * should return a valid address to continue from, but as
2447 * some controllers are faulty, don't trust them.
6ba736a1 2448 */
f6a03cbf
MV		 2449 if (intmask & SDHCI_INT_DMA_END) {
2450 u32 dmastart, dmanow;
2451 dmastart = sg_dma_address(host->data->sg);
2452 dmanow = dmastart + host->data->bytes_xfered;
2453 /*
2454 * Force update to the next DMA block boundary.
2455 */
2456 dmanow = (dmanow &
2457 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2458 SDHCI_DEFAULT_BOUNDARY_SIZE;
2459 host->data->bytes_xfered = dmanow - dmastart;
2460 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2461 " next 0x%08x\n",
2462 mmc_hostname(host->mmc), dmastart,
2463 host->data->bytes_xfered, dmanow);
2464 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2465 }
6ba736a1 2466
e538fbe8
PO		 2467 if (intmask & SDHCI_INT_DATA_END) {
2468 if (host->cmd) {
2469 /*
2470 * Data managed to finish before the
2471 * command completed. Make sure we do
2472 * things in the proper order.
2473 */
2474 host->data_early = 1;
2475 } else {
2476 sdhci_finish_data(host);
2477 }
2478 }
d129bceb
PO		 2479 }
2480}
2481
7d12e780 2482static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2483{
781e989c 2484 irqreturn_t result = IRQ_NONE;
66fd8ad5 2485 struct sdhci_host *host = dev_id;
41005003 2486 u32 intmask, mask, unexpected = 0;
781e989c 2487 int max_loops = 16;
d129bceb
PO		 2488
2489 spin_lock(&host->lock);
2490
be138554 2491 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2492 spin_unlock(&host->lock);
655bca76 2493 return IRQ_NONE;
66fd8ad5
AH		 2494 }
2495
4e4141a5 2496 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2497 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2498 result = IRQ_NONE;
2499 goto out;
2500 }
2501
41005003
RK		 2502 do {
2503 /* Clear selected interrupts. */
2504 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2505 SDHCI_INT_BUS_POWER);
2506 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2507
41005003
RK		 2508 DBG("*** %s got interrupt: 0x%08x\n",
2509 mmc_hostname(host->mmc), intmask);
d129bceb 2510
41005003
RK		 2511 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2512 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2513 SDHCI_CARD_PRESENT;
d129bceb 2514
41005003
RK		 2515 /*
2516 * There is a observation on i.mx esdhc. INSERT
2517 * bit will be immediately set again when it gets
2518 * cleared, if a card is inserted. We have to mask
2519 * the irq to prevent interrupt storm which will
2520 * freeze the system. And the REMOVE gets the
2521 * same situation.
2522 *
2523 * More testing are needed here to ensure it works
2524 * for other platforms though.
2525 */
b537f94c
RK		 2526 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2527 SDHCI_INT_CARD_REMOVE);
2528 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2529 SDHCI_INT_CARD_INSERT;
2530 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2531 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2532
2533 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2534 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2535
2536 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2537 SDHCI_INT_CARD_REMOVE);
2538 result = IRQ_WAKE_THREAD;
41005003 2539 }
d129bceb 2540
41005003 2541 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2542 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2543 &intmask);
964f9ce2 2544
41005003
RK		 2545 if (intmask & SDHCI_INT_DATA_MASK)
2546 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2547
41005003
RK		 2548 if (intmask & SDHCI_INT_BUS_POWER)
2549 pr_err("%s: Card is consuming too much power!\n",
2550 mmc_hostname(host->mmc));
3192a28f 2551
781e989c
RK		 2552 if (intmask & SDHCI_INT_CARD_INT) {
2553 sdhci_enable_sdio_irq_nolock(host, false);
2554 host->thread_isr |= SDHCI_INT_CARD_INT;
2555 result = IRQ_WAKE_THREAD;
2556 }
f75979b7 2557
41005003
RK		 2558 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2559 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2560 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2561 SDHCI_INT_CARD_INT);
f75979b7 2562
41005003
RK		 2563 if (intmask) {
2564 unexpected |= intmask;
2565 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2566 }
d129bceb 2567
781e989c
RK		 2568 if (result == IRQ_NONE)
2569 result = IRQ_HANDLED;
d129bceb 2570
41005003 2571 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2572 } while (intmask && --max_loops);
d129bceb
PO		 2573out:
2574 spin_unlock(&host->lock);
2575
6379b237
AS		 2576 if (unexpected) {
2577 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2578 mmc_hostname(host->mmc), unexpected);
2579 sdhci_dumpregs(host);
2580 }
f75979b7 2581
d129bceb
PO		 2582 return result;
2583}
2584
781e989c
RK		 2585static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2586{
2587 struct sdhci_host *host = dev_id;
2588 unsigned long flags;
2589 u32 isr;
2590
2591 spin_lock_irqsave(&host->lock, flags);
2592 isr = host->thread_isr;
2593 host->thread_isr = 0;
2594 spin_unlock_irqrestore(&host->lock, flags);
2595
3560db8e
RK		 2596 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2597 sdhci_card_event(host->mmc);
2598 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2599 }
2600
781e989c
RK		 2601 if (isr & SDHCI_INT_CARD_INT) {
2602 sdio_run_irqs(host->mmc);
2603
2604 spin_lock_irqsave(&host->lock, flags);
2605 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2606 sdhci_enable_sdio_irq_nolock(host, true);
2607 spin_unlock_irqrestore(&host->lock, flags);
2608 }
2609
2610 return isr ? IRQ_HANDLED : IRQ_NONE;
2611}
2612
d129bceb
PO		 2613/*****************************************************************************\
2614 * *
2615 * Suspend/resume *
2616 * *
2617\*****************************************************************************/
2618
2619#ifdef CONFIG_PM
ad080d79
KL		 2620void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2621{
2622 u8 val;
2623 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2624 | SDHCI_WAKE_ON_INT;
2625
2626 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2627 val |= mask ;
2628 /* Avoid fake wake up */
2629 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2630 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2631 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2632}
2633EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2634
0b10f478 2635static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2636{
2637 u8 val;
2638 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2639 | SDHCI_WAKE_ON_INT;
2640
2641 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2642 val &= ~mask;
2643 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2644}
d129bceb 2645
29495aa0 2646int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2647{
7260cf5e
AV		 2648 sdhci_disable_card_detection(host);
2649
66c39dfc
AH		 2650 mmc_retune_timer_stop(host->mmc);
2651 mmc_retune_needed(host->mmc);
cf2b5eea 2652
ad080d79 2653 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2654 host->ier = 0;
2655 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2656 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2657 free_irq(host->irq, host);
2658 } else {
2659 sdhci_enable_irq_wakeups(host);
2660 enable_irq_wake(host->irq);
2661 }
4ee14ec6 2662 return 0;
d129bceb
PO		 2663}
2664
b8c86fc5 2665EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2666
b8c86fc5
PO		 2667int sdhci_resume_host(struct sdhci_host *host)
2668{
4ee14ec6 2669 int ret = 0;
d129bceb 2670
a13abc7b 2671 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2672 if (host->ops->enable_dma)
2673 host->ops->enable_dma(host);
2674 }
d129bceb 2675
6308d290
AH		 2676 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2677 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2678 /* Card keeps power but host controller does not */
2679 sdhci_init(host, 0);
2680 host->pwr = 0;
2681 host->clock = 0;
2682 sdhci_do_set_ios(host, &host->mmc->ios);
2683 } else {
2684 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2685 mmiowb();
2686 }
b8c86fc5 2687
14a7b416
HC		 2688 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2689 ret = request_threaded_irq(host->irq, sdhci_irq,
2690 sdhci_thread_irq, IRQF_SHARED,
2691 mmc_hostname(host->mmc), host);
2692 if (ret)
2693 return ret;
2694 } else {
2695 sdhci_disable_irq_wakeups(host);
2696 disable_irq_wake(host->irq);
2697 }
2698
7260cf5e
AV		 2699 sdhci_enable_card_detection(host);
2700
2f4cbb3d 2701 return ret;
d129bceb
PO		 2702}
2703
b8c86fc5 2704EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2705
2706static int sdhci_runtime_pm_get(struct sdhci_host *host)
2707{
2708 return pm_runtime_get_sync(host->mmc->parent);
2709}
2710
2711static int sdhci_runtime_pm_put(struct sdhci_host *host)
2712{
2713 pm_runtime_mark_last_busy(host->mmc->parent);
2714 return pm_runtime_put_autosuspend(host->mmc->parent);
2715}
2716
f0710a55
AH		 2717static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2718{
5c671c41 2719 if (host->bus_on)
f0710a55
AH		 2720 return;
2721 host->bus_on = true;
2722 pm_runtime_get_noresume(host->mmc->parent);
2723}
2724
2725static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2726{
5c671c41 2727 if (!host->bus_on)
f0710a55
AH		 2728 return;
2729 host->bus_on = false;
2730 pm_runtime_put_noidle(host->mmc->parent);
2731}
2732
66fd8ad5
AH		 2733int sdhci_runtime_suspend_host(struct sdhci_host *host)
2734{
2735 unsigned long flags;
66fd8ad5 2736
66c39dfc
AH		 2737 mmc_retune_timer_stop(host->mmc);
2738 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2739
2740 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2741 host->ier &= SDHCI_INT_CARD_INT;
2742 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2743 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2744 spin_unlock_irqrestore(&host->lock, flags);
2745
781e989c 2746 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2747
2748 spin_lock_irqsave(&host->lock, flags);
2749 host->runtime_suspended = true;
2750 spin_unlock_irqrestore(&host->lock, flags);
2751
8a125bad 2752 return 0;
66fd8ad5
AH		 2753}
2754EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2755
2756int sdhci_runtime_resume_host(struct sdhci_host *host)
2757{
2758 unsigned long flags;
8a125bad 2759 int host_flags = host->flags;
66fd8ad5
AH		 2760
2761 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2762 if (host->ops->enable_dma)
2763 host->ops->enable_dma(host);
2764 }
2765
2766 sdhci_init(host, 0);
2767
2768 /* Force clock and power re-program */
2769 host->pwr = 0;
2770 host->clock = 0;
3396e736 2771 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2772 sdhci_do_set_ios(host, &host->mmc->ios);
2773
52983382
KL		 2774 if ((host_flags & SDHCI_PV_ENABLED) &&
2775 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2776 spin_lock_irqsave(&host->lock, flags);
2777 sdhci_enable_preset_value(host, true);
2778 spin_unlock_irqrestore(&host->lock, flags);
2779 }
66fd8ad5 2780
66fd8ad5
AH		 2781 spin_lock_irqsave(&host->lock, flags);
2782
2783 host->runtime_suspended = false;
2784
2785 /* Enable SDIO IRQ */
ef104333 2786 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2787 sdhci_enable_sdio_irq_nolock(host, true);
2788
2789 /* Enable Card Detection */
2790 sdhci_enable_card_detection(host);
2791
2792 spin_unlock_irqrestore(&host->lock, flags);
2793
8a125bad 2794 return 0;
66fd8ad5
AH		 2795}
2796EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2797
162d6f98 2798#endif /* CONFIG_PM */
66fd8ad5 2799
d129bceb
PO		 2800/*****************************************************************************\
2801 * *
b8c86fc5 2802 * Device allocation/registration *
d129bceb
PO		 2803 * *
2804\*****************************************************************************/
2805
b8c86fc5
PO		 2806struct sdhci_host *sdhci_alloc_host(struct device *dev,
2807 size_t priv_size)
d129bceb 2808{
d129bceb
PO		 2809 struct mmc_host *mmc;
2810 struct sdhci_host *host;
2811
b8c86fc5 2812 WARN_ON(dev == NULL);
d129bceb 2813
b8c86fc5 2814 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2815 if (!mmc)
b8c86fc5 2816 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2817
2818 host = mmc_priv(mmc);
2819 host->mmc = mmc;
bf60e592
AH		 2820 host->mmc_host_ops = sdhci_ops;
2821 mmc->ops = &host->mmc_host_ops;
d129bceb 2822
b8c86fc5
PO		 2823 return host;
2824}
8a4da143 2825
b8c86fc5 2826EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2827
7b91369b
AC		 2828static int sdhci_set_dma_mask(struct sdhci_host *host)
2829{
2830 struct mmc_host *mmc = host->mmc;
2831 struct device *dev = mmc_dev(mmc);
2832 int ret = -EINVAL;
2833
2834 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2835 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2836
2837 /* Try 64-bit mask if hardware is capable of it */
2838 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2839 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2840 if (ret) {
2841 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2842 mmc_hostname(mmc));
2843 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2844 }
2845 }
2846
2847 /* 32-bit mask as default & fallback */
2848 if (ret) {
2849 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2850 if (ret)
2851 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2852 mmc_hostname(mmc));
2853 }
2854
2855 return ret;
2856}
2857
b8c86fc5
PO		 2858int sdhci_add_host(struct sdhci_host *host)
2859{
2860 struct mmc_host *mmc;
bd6a8c30 2861 u32 caps[2] = {0, 0};
f2119df6
AN		 2862 u32 max_current_caps;
2863 unsigned int ocr_avail;
f5fa92e5 2864 unsigned int override_timeout_clk;
59241757 2865 u32 max_clk;
b8c86fc5 2866 int ret;
d129bceb 2867
b8c86fc5
PO		 2868 WARN_ON(host == NULL);
2869 if (host == NULL)
2870 return -EINVAL;
d129bceb 2871
b8c86fc5 2872 mmc = host->mmc;
d129bceb 2873
b8c86fc5
PO		 2874 if (debug_quirks)
2875 host->quirks = debug_quirks;
66fd8ad5
AH		 2876 if (debug_quirks2)
2877 host->quirks2 = debug_quirks2;
d129bceb 2878
f5fa92e5
AH		 2879 override_timeout_clk = host->timeout_clk;
2880
03231f9b 2881 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2882
4e4141a5 2883 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2884 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2885 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2886 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2887 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2888 mmc_hostname(mmc), host->version);
4a965505
PO		 2889 }
2890
f2119df6 2891 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2892 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2893
bd6a8c30
PR		 2894 if (host->version >= SDHCI_SPEC_300)
2895 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2896 host->caps1 :
2897 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2898
b8c86fc5 2899 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2900 host->flags |= SDHCI_USE_SDMA;
f2119df6 2901 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2902 DBG("Controller doesn't have SDMA capability\n");
67435274 2903 else
a13abc7b 2904 host->flags |= SDHCI_USE_SDMA;
d129bceb 2905
b8c86fc5 2906 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2907 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2908 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2909 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2910 }
2911
f2119df6
AN		 2912 if ((host->version >= SDHCI_SPEC_200) &&
2913 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2914 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2915
2916 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2917 (host->flags & SDHCI_USE_ADMA)) {
2918 DBG("Disabling ADMA as it is marked broken\n");
2919 host->flags &= ~SDHCI_USE_ADMA;
2920 }
2921
e57a5f61
AH		 2922 /*
2923 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2924 * and *must* do 64-bit DMA. A driver has the opportunity to change
2925 * that during the first call to ->enable_dma(). Similarly
2926 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2927 * implement.
2928 */
5eaa7476 2929 if (caps[0] & SDHCI_CAN_64BIT)
e57a5f61
AH		 2930 host->flags |= SDHCI_USE_64_BIT_DMA;
2931
a13abc7b 2932 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
7b91369b
AC		 2933 ret = sdhci_set_dma_mask(host);
2934
2935 if (!ret && host->ops->enable_dma)
2936 ret = host->ops->enable_dma(host);
2937
2938 if (ret) {
2939 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2940 mmc_hostname(mmc));
2941 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2942
2943 ret = 0;
d129bceb
PO		 2944 }
2945 }
2946
e57a5f61
AH		 2947 /* SDMA does not support 64-bit DMA */
2948 if (host->flags & SDHCI_USE_64_BIT_DMA)
2949 host->flags &= ~SDHCI_USE_SDMA;
2950
2134a922 2951 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 2952 dma_addr_t dma;
2953 void *buf;
2954
2134a922 2955 /*
76fe379a
AH		 2956 * The DMA descriptor table size is calculated as the maximum
2957 * number of segments times 2, to allow for an alignment
2958 * descriptor for each segment, plus 1 for a nop end descriptor,
2959 * all multipled by the descriptor size.
2134a922 2960 */
e57a5f61
AH		 2961 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2962 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2963 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2964 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2965 } else {
2966 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2967 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2968 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2969 }
e66e61cb 2970
04a5ae6f 2971 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 2972 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2973 host->adma_table_sz, &dma, GFP_KERNEL);
2974 if (!buf) {
6606110d 2975 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2976 mmc_hostname(mmc));
2977 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2978 } else if ((dma + host->align_buffer_sz) &
2979 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 2980 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2981 mmc_hostname(mmc));
d1e49f77 2982 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2983 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2984 host->adma_table_sz, buf, dma);
2985 } else {
2986 host->align_buffer = buf;
2987 host->align_addr = dma;
edd63fcc 2988
e66e61cb
RK		 2989 host->adma_table = buf + host->align_buffer_sz;
2990 host->adma_addr = dma + host->align_buffer_sz;
2991 }
2134a922
PO		 2992 }
2993
7659150c
PO		 2994 /*
2995 * If we use DMA, then it's up to the caller to set the DMA
2996 * mask, but PIO does not need the hw shim so we set a new
2997 * mask here in that case.
2998 */
a13abc7b 2999 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3000 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3001 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3002 }
d129bceb 3003
c4687d5f 3004 if (host->version >= SDHCI_SPEC_300)
f2119df6 3005 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3006 >> SDHCI_CLOCK_BASE_SHIFT;
3007 else
f2119df6 3008 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3009 >> SDHCI_CLOCK_BASE_SHIFT;
3010
4240ff0a 3011 host->max_clk *= 1000000;
f27f47ef
AV		 3012 if (host->max_clk == 0 || host->quirks &
3013 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3014 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3015 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3016 mmc_hostname(mmc));
4240ff0a
BD		 3017 return -ENODEV;
3018 }
3019 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3020 }
d129bceb 3021
c3ed3877
AN		 3022 /*
3023 * In case of Host Controller v3.00, find out whether clock
3024 * multiplier is supported.
3025 */
3026 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3027 SDHCI_CLOCK_MUL_SHIFT;
3028
3029 /*
3030 * In case the value in Clock Multiplier is 0, then programmable
3031 * clock mode is not supported, otherwise the actual clock
3032 * multiplier is one more than the value of Clock Multiplier
3033 * in the Capabilities Register.
3034 */
3035 if (host->clk_mul)
3036 host->clk_mul += 1;
3037
d129bceb
PO		 3038 /*
3039 * Set host parameters.
3040 */
59241757
DA		 3041 max_clk = host->max_clk;
3042
ce5f036b 3043 if (host->ops->get_min_clock)
a9e58f25 3044 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3045 else if (host->version >= SDHCI_SPEC_300) {
3046 if (host->clk_mul) {
3047 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3048 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3049 } else
3050 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3051 } else
0397526d 3052 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3053
59241757
DA		 3054 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3055 mmc->f_max = max_clk;
3056
28aab053
AD		 3057 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3058 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3059 SDHCI_TIMEOUT_CLK_SHIFT;
3060 if (host->timeout_clk == 0) {
3061 if (host->ops->get_timeout_clock) {
3062 host->timeout_clk =
3063 host->ops->get_timeout_clock(host);
3064 } else {
3065 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3066 mmc_hostname(mmc));
3067 return -ENODEV;
3068 }
272308ca 3069 }
272308ca 3070
28aab053
AD		 3071 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3072 host->timeout_clk *= 1000;
272308ca 3073
99513624
AH		 3074 if (override_timeout_clk)
3075 host->timeout_clk = override_timeout_clk;
3076
28aab053 3077 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3078 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3079 mmc->max_busy_timeout /= host->timeout_clk;
3080 }
58d1246d 3081
e89d456f 3082 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3083 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3084
3085 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3086 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3087
8edf6371 3088 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3089 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3090 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3091 !(host->flags & SDHCI_USE_SDMA)) &&
3092 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3093 host->flags |= SDHCI_AUTO_CMD23;
3094 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3095 } else {
3096 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3097 }
3098
15ec4461
PR		 3099 /*
3100 * A controller may support 8-bit width, but the board itself
3101 * might not have the pins brought out. Boards that support
3102 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3103 * their platform code before calling sdhci_add_host(), and we
3104 * won't assume 8-bit width for hosts without that CAP.
3105 */
5fe23c7f 3106 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3107 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3108
63ef5d8c
JH		 3109 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3110 mmc->caps &= ~MMC_CAP_CMD23;
3111
f2119df6 3112 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3113 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3114
176d1ed4 3115 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
c31d22eb
II		 3116 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3117 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
68d1fb7e
AV		 3118 mmc->caps |= MMC_CAP_NEEDS_POLL;
3119
3a48edc4
TK		 3120 /* If there are external regulators, get them */
3121 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3122 return -EPROBE_DEFER;
3123
6231f3de 3124 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3125 if (!IS_ERR(mmc->supply.vqmmc)) {
3126 ret = regulator_enable(mmc->supply.vqmmc);
3127 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3128 1950000))
8363c374
KL		 3129 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3130 SDHCI_SUPPORT_SDR50 |
3131 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3132 if (ret) {
3133 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3134 mmc_hostname(mmc), ret);
4bb74313 3135 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3136 }
8363c374 3137 }
6231f3de 3138
6a66180a
DD		 3139 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3140 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3141 SDHCI_SUPPORT_DDR50);
3142
4188bba0
AC		 3143 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3144 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3145 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3146 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3147
3148 /* SDR104 supports also implies SDR50 support */
156e14b1 3149 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3150 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3151 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3152 * field can be promoted to support HS200.
3153 */
549c0b18 3154 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3155 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3156 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3157 mmc->caps |= MMC_CAP_UHS_SDR50;
3158
e9fb05d5
AH		 3159 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3160 (caps[1] & SDHCI_SUPPORT_HS400))
3161 mmc->caps2 |= MMC_CAP2_HS400;
3162
549c0b18
AH		 3163 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3164 (IS_ERR(mmc->supply.vqmmc) ||
3165 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3166 1300000)))
3167 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3168
9107ebbf
MC		 3169 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3170 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3171 mmc->caps |= MMC_CAP_UHS_DDR50;
3172
069c9f14 3173 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3174 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3175 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3176
156e14b1 3177 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3178 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3179 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3180
d6d50a15
AN		 3181 /* Driver Type(s) (A, C, D) supported by the host */
3182 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3183 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3184 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3185 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3186 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3187 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3188
cf2b5eea
AN		 3189 /* Initial value for re-tuning timer count */
3190 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3191 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3192
3193 /*
3194 * In case Re-tuning Timer is not disabled, the actual value of
3195 * re-tuning timer will be 2 ^ (n - 1).
3196 */
3197 if (host->tuning_count)
3198 host->tuning_count = 1 << (host->tuning_count - 1);
3199
3200 /* Re-tuning mode supported by the Host Controller */
3201 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3202 SDHCI_RETUNING_MODE_SHIFT;
3203
8f230f45 3204 ocr_avail = 0;
bad37e1a 3205
f2119df6
AN		 3206 /*
3207 * According to SD Host Controller spec v3.00, if the Host System
3208 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3209 * the value is meaningful only if Voltage Support in the Capabilities
3210 * register is set. The actual current value is 4 times the register
3211 * value.
3212 */
3213 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3214 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3215 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3216 if (curr > 0) {
3217
3218 /* convert to SDHCI_MAX_CURRENT format */
3219 curr = curr/1000; /* convert to mA */
3220 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3221
3222 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3223 max_current_caps =
3224 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3225 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3226 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3227 }
3228 }
f2119df6
AN		 3229
3230 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3231 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3232
55c4665e 3233 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3234 SDHCI_MAX_CURRENT_330_MASK) >>
3235 SDHCI_MAX_CURRENT_330_SHIFT) *
3236 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3237 }
3238 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3239 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3240
55c4665e 3241 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3242 SDHCI_MAX_CURRENT_300_MASK) >>
3243 SDHCI_MAX_CURRENT_300_SHIFT) *
3244 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3245 }
3246 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3247 ocr_avail |= MMC_VDD_165_195;
3248
55c4665e 3249 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3250 SDHCI_MAX_CURRENT_180_MASK) >>
3251 SDHCI_MAX_CURRENT_180_SHIFT) *
3252 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3253 }
3254
5fd26c7e
UH		 3255 /* If OCR set by host, use it instead. */
3256 if (host->ocr_mask)
3257 ocr_avail = host->ocr_mask;
3258
3259 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3260 if (mmc->ocr_avail)
52221610 3261 ocr_avail = mmc->ocr_avail;
3a48edc4 3262
8f230f45
TI		 3263 mmc->ocr_avail = ocr_avail;
3264 mmc->ocr_avail_sdio = ocr_avail;
3265 if (host->ocr_avail_sdio)
3266 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3267 mmc->ocr_avail_sd = ocr_avail;
3268 if (host->ocr_avail_sd)
3269 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3270 else /* normal SD controllers don't support 1.8V */
3271 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3272 mmc->ocr_avail_mmc = ocr_avail;
3273 if (host->ocr_avail_mmc)
3274 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3275
3276 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3277 pr_err("%s: Hardware doesn't report any support voltages.\n",
3278 mmc_hostname(mmc));
b8c86fc5 3279 return -ENODEV;
146ad66e
PO		 3280 }
3281
d129bceb
PO		 3282 spin_lock_init(&host->lock);
3283
3284 /*
2134a922
PO		 3285 * Maximum number of segments. Depends on if the hardware
3286 * can do scatter/gather or not.
d129bceb 3287 */
2134a922 3288 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3289 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3290 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3291 mmc->max_segs = 1;
2134a922 3292 else /* PIO */
4fb213f8 3293 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3294
3295 /*
ac00531d
AH		 3296 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3297 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3298 * is less anyway.
d129bceb 3299 */
55db890a 3300 mmc->max_req_size = 524288;
d129bceb
PO		 3301
3302 /*
3303 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3304 * of bytes. When doing hardware scatter/gather, each entry cannot
3305 * be larger than 64 KiB though.
d129bceb 3306 */
30652aa3
OJ		 3307 if (host->flags & SDHCI_USE_ADMA) {
3308 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3309 mmc->max_seg_size = 65535;
3310 else
3311 mmc->max_seg_size = 65536;
3312 } else {
2134a922 3313 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3314 }
d129bceb 3315
fe4a3c7a
PO		 3316 /*
3317 * Maximum block size. This varies from controller to controller and
3318 * is specified in the capabilities register.
3319 */
0633f654
AV		 3320 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3321 mmc->max_blk_size = 2;
3322 } else {
f2119df6 3323 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3324 SDHCI_MAX_BLOCK_SHIFT;
3325 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3326 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3327 mmc_hostname(mmc));
0633f654
AV		 3328 mmc->max_blk_size = 0;
3329 }
3330 }
3331
3332 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3333
55db890a
PO		 3334 /*
3335 * Maximum block count.
3336 */
1388eefd 3337 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3338
d129bceb
PO		 3339 /*
3340 * Init tasklets.
3341 */
d129bceb
PO		 3342 tasklet_init(&host->finish_tasklet,
3343 sdhci_tasklet_finish, (unsigned long)host);
3344
e4cad1b5 3345 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3346
250fb7b4 3347 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3348
2af502ca
SG		 3349 sdhci_init(host, 0);
3350
781e989c
RK		 3351 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3352 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3353 if (ret) {
3354 pr_err("%s: Failed to request IRQ %d: %d\n",
3355 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3356 goto untasklet;
0fc81ee3 3357 }
d129bceb 3358
d129bceb
PO		 3359#ifdef CONFIG_MMC_DEBUG
3360 sdhci_dumpregs(host);
3361#endif
3362
f9134319 3363#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3364 snprintf(host->led_name, sizeof(host->led_name),
3365 "%s::", mmc_hostname(mmc));
3366 host->led.name = host->led_name;
2f730fec
PO		 3367 host->led.brightness = LED_OFF;
3368 host->led.default_trigger = mmc_hostname(mmc);
3369 host->led.brightness_set = sdhci_led_control;
3370
b8c86fc5 3371 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3372 if (ret) {
3373 pr_err("%s: Failed to register LED device: %d\n",
3374 mmc_hostname(mmc), ret);
2f730fec 3375 goto reset;
0fc81ee3 3376 }
2f730fec
PO		 3377#endif
3378
5f25a66f
PO		 3379 mmiowb();
3380
d129bceb
PO		 3381 mmc_add_host(mmc);
3382
a3c76eb9 3383 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3384 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3385 (host->flags & SDHCI_USE_ADMA) ?
3386 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3387 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3388
7260cf5e
AV		 3389 sdhci_enable_card_detection(host);
3390
d129bceb
PO		 3391 return 0;
3392
f9134319 3393#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3394reset:
03231f9b 3395 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3396 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3397 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3398 free_irq(host->irq, host);
3399#endif
8ef1a143 3400untasklet:
d129bceb 3401 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3402
3403 return ret;
3404}
3405
b8c86fc5 3406EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3407
1e72859e 3408void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3409{
3a48edc4 3410 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3411 unsigned long flags;
3412
3413 if (dead) {
3414 spin_lock_irqsave(&host->lock, flags);
3415
3416 host->flags |= SDHCI_DEVICE_DEAD;
3417
3418 if (host->mrq) {
a3c76eb9 3419 pr_err("%s: Controller removed during "
4e743f1f 3420 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3421
3422 host->mrq->cmd->error = -ENOMEDIUM;
3423 tasklet_schedule(&host->finish_tasklet);
3424 }
3425
3426 spin_unlock_irqrestore(&host->lock, flags);
3427 }
3428
7260cf5e
AV		 3429 sdhci_disable_card_detection(host);
3430
4e743f1f 3431 mmc_remove_host(mmc);
d129bceb 3432
f9134319 3433#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3434 led_classdev_unregister(&host->led);
3435#endif
3436
1e72859e 3437 if (!dead)
03231f9b 3438 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3439
b537f94c
RK		 3440 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3441 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3442 free_irq(host->irq, host);
3443
3444 del_timer_sync(&host->timer);
3445
d129bceb 3446 tasklet_kill(&host->finish_tasklet);
2134a922 3447
3a48edc4
TK		 3448 if (!IS_ERR(mmc->supply.vqmmc))
3449 regulator_disable(mmc->supply.vqmmc);
6231f3de 3450
edd63fcc 3451 if (host->align_buffer)
e66e61cb
RK		 3452 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3453 host->adma_table_sz, host->align_buffer,
3454 host->align_addr);
2134a922 3455
4efaa6fb 3456 host->adma_table = NULL;
2134a922 3457 host->align_buffer = NULL;
d129bceb
PO		 3458}
3459
b8c86fc5 3460EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3461
b8c86fc5 3462void sdhci_free_host(struct sdhci_host *host)
d129bceb 3463{
b8c86fc5 3464 mmc_free_host(host->mmc);
d129bceb
PO		 3465}
3466
b8c86fc5 3467EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3468
3469/*****************************************************************************\
3470 * *
3471 * Driver init/exit *
3472 * *
3473\*****************************************************************************/
3474
3475static int __init sdhci_drv_init(void)
3476{
a3c76eb9 3477 pr_info(DRIVER_NAME
52fbf9c9 3478 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3479 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3480
b8c86fc5 3481 return 0;
d129bceb
PO		 3482}
3483
3484static void __exit sdhci_drv_exit(void)
3485{
d129bceb
PO		 3486}
3487
3488module_init(sdhci_drv_init);
3489module_exit(sdhci_drv_exit);
3490
df673b22 3491module_param(debug_quirks, uint, 0444);
66fd8ad5 3492module_param(debug_quirks2, uint, 0444);
67435274 3493
32710e8f 3494MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3495MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3496MODULE_LICENSE("GPL");
67435274 3497
df673b22 3498MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3499MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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