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mmc: sdhci: Clear also HS400 1.2V capability if 1.2V is not supported
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
d129bceb 52static void sdhci_finish_command(struct sdhci_host *);
069c9f14 53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 54static void sdhci_tuning_timer(unsigned long data);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 56
66fd8ad5
AH		 57#ifdef CONFIG_PM_RUNTIME
58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 60static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 62#else
63static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
64{
65 return 0;
66}
67static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
68{
69 return 0;
70}
f0710a55
AH		 71static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
72{
73}
74static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
75{
76}
66fd8ad5
AH		 77#endif
78
d129bceb
PO		 79static void sdhci_dumpregs(struct sdhci_host *host)
80{
a3c76eb9 81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 82 mmc_hostname(host->mmc));
d129bceb 83
a3c76eb9 84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 112 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 115 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 116 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 119
e57a5f61
AH		 120 if (host->flags & SDHCI_USE_ADMA) {
121 if (host->flags & SDHCI_USE_64_BIT_DMA)
122 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
123 readl(host->ioaddr + SDHCI_ADMA_ERROR),
124 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126 else
127 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
128 readl(host->ioaddr + SDHCI_ADMA_ERROR),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 }
be3f4ae0 131
a3c76eb9 132 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 133}
134
135/*****************************************************************************\
136 * *
137 * Low level functions *
138 * *
139\*****************************************************************************/
140
7260cf5e
AV		 141static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
142{
5b4f1f6c 143 u32 present;
7260cf5e 144
c79396c1 145 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 146 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 147 return;
148
5b4f1f6c
RK		 149 if (enable) {
150 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
151 SDHCI_CARD_PRESENT;
d25928d1 152
5b4f1f6c
RK		 153 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
154 SDHCI_INT_CARD_INSERT;
155 } else {
156 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
157 }
b537f94c
RK		 158
159 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
160 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 161}
162
163static void sdhci_enable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, true);
166}
167
168static void sdhci_disable_card_detection(struct sdhci_host *host)
169{
170 sdhci_set_card_detection(host, false);
171}
172
03231f9b 173void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 174{
e16514d8 175 unsigned long timeout;
393c1a34 176
4e4141a5 177 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 178
f0710a55 179 if (mask & SDHCI_RESET_ALL) {
d129bceb 180 host->clock = 0;
f0710a55
AH		 181 /* Reset-all turns off SD Bus Power */
182 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
183 sdhci_runtime_pm_bus_off(host);
184 }
d129bceb 185
e16514d8
PO		 186 /* Wait max 100 ms */
187 timeout = 100;
188
189 /* hw clears the bit when it's done */
4e4141a5 190 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 191 if (timeout == 0) {
a3c76eb9 192 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 193 mmc_hostname(host->mmc), (int)mask);
194 sdhci_dumpregs(host);
195 return;
196 }
197 timeout--;
198 mdelay(1);
d129bceb 199 }
03231f9b
RK		 200}
201EXPORT_SYMBOL_GPL(sdhci_reset);
202
203static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
204{
205 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
206 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
207 SDHCI_CARD_PRESENT))
208 return;
209 }
063a9dbb 210
03231f9b 211 host->ops->reset(host, mask);
393c1a34 212
da91a8f9
RK		 213 if (mask & SDHCI_RESET_ALL) {
214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
215 if (host->ops->enable_dma)
216 host->ops->enable_dma(host);
217 }
218
219 /* Resetting the controller clears many */
220 host->preset_enabled = false;
3abc1e80 221 }
d129bceb
PO		 222}
223
2f4cbb3d
NP		 224static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 227{
2f4cbb3d 228 if (soft)
03231f9b 229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 230 else
03231f9b 231 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 232
b537f94c
RK		 233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
237 SDHCI_INT_RESPONSE;
238
239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 241
242 if (soft) {
243 /* force clock reconfiguration */
244 host->clock = 0;
245 sdhci_set_ios(host->mmc, &host->mmc->ios);
246 }
7260cf5e 247}
d129bceb 248
7260cf5e
AV		 249static void sdhci_reinit(struct sdhci_host *host)
250{
2f4cbb3d 251 sdhci_init(host, 0);
b67c6b41
AL		 252 /*
253 * Retuning stuffs are affected by different cards inserted and only
254 * applicable to UHS-I cards. So reset these fields to their initial
255 * value when card is removed.
256 */
973905fe
AL		 257 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
258 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
259
b67c6b41
AL		 260 del_timer_sync(&host->tuning_timer);
261 host->flags &= ~SDHCI_NEEDS_RETUNING;
262 host->mmc->max_blk_count =
263 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
264 }
7260cf5e 265 sdhci_enable_card_detection(host);
d129bceb
PO		 266}
267
268static void sdhci_activate_led(struct sdhci_host *host)
269{
270 u8 ctrl;
271
4e4141a5 272 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 273 ctrl |= SDHCI_CTRL_LED;
4e4141a5 274 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 275}
276
277static void sdhci_deactivate_led(struct sdhci_host *host)
278{
279 u8 ctrl;
280
4e4141a5 281 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 282 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 283 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 284}
285
f9134319 286#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 287static void sdhci_led_control(struct led_classdev *led,
288 enum led_brightness brightness)
289{
290 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
291 unsigned long flags;
292
293 spin_lock_irqsave(&host->lock, flags);
294
66fd8ad5
AH		 295 if (host->runtime_suspended)
296 goto out;
297
2f730fec
PO		 298 if (brightness == LED_OFF)
299 sdhci_deactivate_led(host);
300 else
301 sdhci_activate_led(host);
66fd8ad5 302out:
2f730fec
PO		 303 spin_unlock_irqrestore(&host->lock, flags);
304}
305#endif
306
d129bceb
PO		 307/*****************************************************************************\
308 * *
309 * Core functions *
310 * *
311\*****************************************************************************/
312
a406f5a3 313static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 314{
7659150c
PO		 315 unsigned long flags;
316 size_t blksize, len, chunk;
7244b85b 317 u32 uninitialized_var(scratch);
7659150c 318 u8 *buf;
d129bceb 319
a406f5a3 320 DBG("PIO reading\n");
d129bceb 321
a406f5a3 322 blksize = host->data->blksz;
7659150c 323 chunk = 0;
d129bceb 324
7659150c 325 local_irq_save(flags);
d129bceb 326
a406f5a3 327 while (blksize) {
7659150c
PO		 328 if (!sg_miter_next(&host->sg_miter))
329 BUG();
d129bceb 330
7659150c 331 len = min(host->sg_miter.length, blksize);
d129bceb 332
7659150c
PO		 333 blksize -= len;
334 host->sg_miter.consumed = len;
14d836e7 335
7659150c 336 buf = host->sg_miter.addr;
d129bceb 337
7659150c
PO		 338 while (len) {
339 if (chunk == 0) {
4e4141a5 340 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 341 chunk = 4;
a406f5a3 342 }
7659150c
PO		 343
344 *buf = scratch & 0xFF;
345
346 buf++;
347 scratch >>= 8;
348 chunk--;
349 len--;
d129bceb 350 }
a406f5a3 351 }
7659150c
PO		 352
353 sg_miter_stop(&host->sg_miter);
354
355 local_irq_restore(flags);
a406f5a3 356}
d129bceb 357
a406f5a3
PO		 358static void sdhci_write_block_pio(struct sdhci_host *host)
359{
7659150c
PO		 360 unsigned long flags;
361 size_t blksize, len, chunk;
362 u32 scratch;
363 u8 *buf;
d129bceb 364
a406f5a3
PO		 365 DBG("PIO writing\n");
366
367 blksize = host->data->blksz;
7659150c
PO		 368 chunk = 0;
369 scratch = 0;
d129bceb 370
7659150c 371 local_irq_save(flags);
d129bceb 372
a406f5a3 373 while (blksize) {
7659150c
PO		 374 if (!sg_miter_next(&host->sg_miter))
375 BUG();
a406f5a3 376
7659150c
PO		 377 len = min(host->sg_miter.length, blksize);
378
379 blksize -= len;
380 host->sg_miter.consumed = len;
381
382 buf = host->sg_miter.addr;
d129bceb 383
7659150c
PO		 384 while (len) {
385 scratch |= (u32)*buf << (chunk * 8);
386
387 buf++;
388 chunk++;
389 len--;
390
391 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 392 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 393 chunk = 0;
394 scratch = 0;
d129bceb 395 }
d129bceb
PO		 396 }
397 }
7659150c
PO		 398
399 sg_miter_stop(&host->sg_miter);
400
401 local_irq_restore(flags);
a406f5a3
PO		 402}
403
404static void sdhci_transfer_pio(struct sdhci_host *host)
405{
406 u32 mask;
407
408 BUG_ON(!host->data);
409
7659150c 410 if (host->blocks == 0)
a406f5a3
PO		 411 return;
412
413 if (host->data->flags & MMC_DATA_READ)
414 mask = SDHCI_DATA_AVAILABLE;
415 else
416 mask = SDHCI_SPACE_AVAILABLE;
417
4a3cba32
PO		 418 /*
419 * Some controllers (JMicron JMB38x) mess up the buffer bits
420 * for transfers < 4 bytes. As long as it is just one block,
421 * we can ignore the bits.
422 */
423 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
424 (host->data->blocks == 1))
425 mask = ~0;
426
4e4141a5 427 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 428 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
429 udelay(100);
430
a406f5a3
PO		 431 if (host->data->flags & MMC_DATA_READ)
432 sdhci_read_block_pio(host);
433 else
434 sdhci_write_block_pio(host);
d129bceb 435
7659150c
PO		 436 host->blocks--;
437 if (host->blocks == 0)
a406f5a3 438 break;
a406f5a3 439 }
d129bceb 440
a406f5a3 441 DBG("PIO transfer complete.\n");
d129bceb
PO		 442}
443
2134a922
PO		 444static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
445{
446 local_irq_save(*flags);
482fce99 447 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 448}
449
450static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
451{
482fce99 452 kunmap_atomic(buffer);
2134a922
PO		 453 local_irq_restore(*flags);
454}
455
e57a5f61
AH		 456static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
457 dma_addr_t addr, int len, unsigned cmd)
118cd17d 458{
e57a5f61 459 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 460
e57a5f61 461 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 462 dma_desc->cmd = cpu_to_le16(cmd);
463 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 464 dma_desc->addr_lo = cpu_to_le32((u32)addr);
465
466 if (host->flags & SDHCI_USE_64_BIT_DMA)
467 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 468}
469
b5ffa674
AH		 470static void sdhci_adma_mark_end(void *desc)
471{
e57a5f61 472 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 473
e57a5f61 474 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 475 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 476}
477
8f1934ce 478static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 479 struct mmc_data *data)
480{
481 int direction;
482
1c3d5f6d
AH		 483 void *desc;
484 void *align;
2134a922
PO		 485 dma_addr_t addr;
486 dma_addr_t align_addr;
487 int len, offset;
488
489 struct scatterlist *sg;
490 int i;
491 char *buffer;
492 unsigned long flags;
493
494 /*
495 * The spec does not specify endianness of descriptor table.
496 * We currently guess that it is LE.
497 */
498
499 if (data->flags & MMC_DATA_READ)
500 direction = DMA_FROM_DEVICE;
501 else
502 direction = DMA_TO_DEVICE;
503
2134a922 504 host->align_addr = dma_map_single(mmc_dev(host->mmc),
76fe379a 505 host->align_buffer, host->align_buffer_sz, direction);
8d8bb39b 506 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 507 goto fail;
76fe379a 508 BUG_ON(host->align_addr & host->align_mask);
2134a922
PO		 509
510 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
511 data->sg, data->sg_len, direction);
8f1934ce
PO		 512 if (host->sg_count == 0)
513 goto unmap_align;
2134a922 514
4efaa6fb 515 desc = host->adma_table;
2134a922
PO		 516 align = host->align_buffer;
517
518 align_addr = host->align_addr;
519
520 for_each_sg(data->sg, sg, host->sg_count, i) {
521 addr = sg_dma_address(sg);
522 len = sg_dma_len(sg);
523
524 /*
525 * The SDHCI specification states that ADMA
526 * addresses must be 32-bit aligned. If they
527 * aren't, then we use a bounce buffer for
528 * the (up to three) bytes that screw up the
529 * alignment.
530 */
76fe379a
AH		 531 offset = (host->align_sz - (addr & host->align_mask)) &
532 host->align_mask;
2134a922
PO		 533 if (offset) {
534 if (data->flags & MMC_DATA_WRITE) {
535 buffer = sdhci_kmap_atomic(sg, &flags);
8be78c6a
AH		 536 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
537 (PAGE_SIZE - offset));
2134a922
PO		 538 memcpy(align, buffer, offset);
539 sdhci_kunmap_atomic(buffer, &flags);
540 }
541
118cd17d 542 /* tran, valid */
e57a5f61 543 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 544 ADMA2_TRAN_VALID);
2134a922
PO		 545
546 BUG_ON(offset > 65536);
547
76fe379a
AH		 548 align += host->align_sz;
549 align_addr += host->align_sz;
2134a922 550
76fe379a 551 desc += host->desc_sz;
2134a922
PO		 552
553 addr += offset;
554 len -= offset;
555 }
556
2134a922
PO		 557 BUG_ON(len > 65536);
558
118cd17d 559 /* tran, valid */
e57a5f61 560 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
76fe379a 561 desc += host->desc_sz;
2134a922
PO		 562
563 /*
564 * If this triggers then we have a calculation bug
565 * somewhere. :/
566 */
76fe379a 567 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 568 }
569
70764a90
TA		 570 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
571 /*
572 * Mark the last descriptor as the terminating descriptor
573 */
4efaa6fb 574 if (desc != host->adma_table) {
76fe379a 575 desc -= host->desc_sz;
b5ffa674 576 sdhci_adma_mark_end(desc);
70764a90
TA		 577 }
578 } else {
579 /*
580 * Add a terminating entry.
581 */
2134a922 582
70764a90 583 /* nop, end, valid */
e57a5f61 584 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 585 }
2134a922
PO		 586
587 /*
588 * Resync align buffer as we might have changed it.
589 */
590 if (data->flags & MMC_DATA_WRITE) {
591 dma_sync_single_for_device(mmc_dev(host->mmc),
76fe379a 592 host->align_addr, host->align_buffer_sz, direction);
2134a922
PO		 593 }
594
8f1934ce
PO		 595 return 0;
596
8f1934ce
PO		 597unmap_align:
598 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 599 host->align_buffer_sz, direction);
8f1934ce
PO		 600fail:
601 return -EINVAL;
2134a922
PO		 602}
603
604static void sdhci_adma_table_post(struct sdhci_host *host,
605 struct mmc_data *data)
606{
607 int direction;
608
609 struct scatterlist *sg;
610 int i, size;
1c3d5f6d 611 void *align;
2134a922
PO		 612 char *buffer;
613 unsigned long flags;
de0b65a7 614 bool has_unaligned;
2134a922
PO		 615
616 if (data->flags & MMC_DATA_READ)
617 direction = DMA_FROM_DEVICE;
618 else
619 direction = DMA_TO_DEVICE;
620
2134a922 621 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 622 host->align_buffer_sz, direction);
2134a922 623
de0b65a7
RK		 624 /* Do a quick scan of the SG list for any unaligned mappings */
625 has_unaligned = false;
626 for_each_sg(data->sg, sg, host->sg_count, i)
76fe379a 627 if (sg_dma_address(sg) & host->align_mask) {
de0b65a7
RK		 628 has_unaligned = true;
629 break;
630 }
631
632 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 633 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
634 data->sg_len, direction);
635
636 align = host->align_buffer;
637
638 for_each_sg(data->sg, sg, host->sg_count, i) {
76fe379a
AH		 639 if (sg_dma_address(sg) & host->align_mask) {
640 size = host->align_sz -
641 (sg_dma_address(sg) & host->align_mask);
2134a922
PO		 642
643 buffer = sdhci_kmap_atomic(sg, &flags);
8be78c6a
AH		 644 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
645 (PAGE_SIZE - size));
2134a922
PO		 646 memcpy(buffer, align, size);
647 sdhci_kunmap_atomic(buffer, &flags);
648
76fe379a 649 align += host->align_sz;
2134a922
PO		 650 }
651 }
652 }
653
654 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
655 data->sg_len, direction);
656}
657
a3c7778f 658static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 659{
1c8cde92 660 u8 count;
a3c7778f 661 struct mmc_data *data = cmd->data;
1c8cde92 662 unsigned target_timeout, current_timeout;
d129bceb 663
ee53ab5d
PO		 664 /*
665 * If the host controller provides us with an incorrect timeout
666 * value, just skip the check and use 0xE. The hardware may take
667 * longer to time out, but that's much better than having a too-short
668 * timeout value.
669 */
11a2f1b7 670 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 671 return 0xE;
e538fbe8 672
a3c7778f 673 /* Unspecified timeout, assume max */
1d4d7744 674 if (!data && !cmd->busy_timeout)
a3c7778f 675 return 0xE;
d129bceb 676
a3c7778f
AW		 677 /* timeout in us */
678 if (!data)
1d4d7744 679 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 680 else {
681 target_timeout = data->timeout_ns / 1000;
682 if (host->clock)
683 target_timeout += data->timeout_clks / host->clock;
684 }
81b39802 685
1c8cde92
PO		 686 /*
687 * Figure out needed cycles.
688 * We do this in steps in order to fit inside a 32 bit int.
689 * The first step is the minimum timeout, which will have a
690 * minimum resolution of 6 bits:
691 * (1) 2^13*1000 > 2^22,
692 * (2) host->timeout_clk < 2^16
693 * =>
694 * (1) / (2) > 2^6
695 */
696 count = 0;
697 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
698 while (current_timeout < target_timeout) {
699 count++;
700 current_timeout <<= 1;
701 if (count >= 0xF)
702 break;
703 }
704
705 if (count >= 0xF) {
09eeff52
CB		 706 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
707 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 708 count = 0xE;
709 }
710
ee53ab5d
PO		 711 return count;
712}
713
6aa943ab
AV		 714static void sdhci_set_transfer_irqs(struct sdhci_host *host)
715{
716 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
717 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
718
719 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 720 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 721 else
b537f94c
RK		 722 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
723
724 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
725 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 726}
727
b45e668a 728static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 729{
730 u8 count;
b45e668a
AD		 731
732 if (host->ops->set_timeout) {
733 host->ops->set_timeout(host, cmd);
734 } else {
735 count = sdhci_calc_timeout(host, cmd);
736 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
737 }
738}
739
740static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
741{
2134a922 742 u8 ctrl;
a3c7778f 743 struct mmc_data *data = cmd->data;
8f1934ce 744 int ret;
ee53ab5d
PO		 745
746 WARN_ON(host->data);
747
b45e668a
AD		 748 if (data || (cmd->flags & MMC_RSP_BUSY))
749 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 750
751 if (!data)
ee53ab5d
PO		 752 return;
753
754 /* Sanity checks */
755 BUG_ON(data->blksz * data->blocks > 524288);
756 BUG_ON(data->blksz > host->mmc->max_blk_size);
757 BUG_ON(data->blocks > 65535);
758
759 host->data = data;
760 host->data_early = 0;
f6a03cbf 761 host->data->bytes_xfered = 0;
ee53ab5d 762
a13abc7b 763 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 764 host->flags |= SDHCI_REQ_USE_DMA;
765
2134a922
PO		 766 /*
767 * FIXME: This doesn't account for merging when mapping the
768 * scatterlist.
769 */
770 if (host->flags & SDHCI_REQ_USE_DMA) {
771 int broken, i;
772 struct scatterlist *sg;
773
774 broken = 0;
775 if (host->flags & SDHCI_USE_ADMA) {
776 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
777 broken = 1;
778 } else {
779 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
780 broken = 1;
781 }
782
783 if (unlikely(broken)) {
784 for_each_sg(data->sg, sg, data->sg_len, i) {
785 if (sg->length & 0x3) {
786 DBG("Reverting to PIO because of "
787 "transfer size (%d)\n",
788 sg->length);
789 host->flags &= ~SDHCI_REQ_USE_DMA;
790 break;
791 }
792 }
793 }
c9fddbc4
PO		 794 }
795
796 /*
797 * The assumption here being that alignment is the same after
798 * translation to device address space.
799 */
2134a922
PO		 800 if (host->flags & SDHCI_REQ_USE_DMA) {
801 int broken, i;
802 struct scatterlist *sg;
803
804 broken = 0;
805 if (host->flags & SDHCI_USE_ADMA) {
806 /*
807 * As we use 3 byte chunks to work around
808 * alignment problems, we need to check this
809 * quirk.
810 */
811 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
812 broken = 1;
813 } else {
814 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
815 broken = 1;
816 }
817
818 if (unlikely(broken)) {
819 for_each_sg(data->sg, sg, data->sg_len, i) {
820 if (sg->offset & 0x3) {
821 DBG("Reverting to PIO because of "
822 "bad alignment\n");
823 host->flags &= ~SDHCI_REQ_USE_DMA;
824 break;
825 }
826 }
827 }
828 }
829
8f1934ce
PO		 830 if (host->flags & SDHCI_REQ_USE_DMA) {
831 if (host->flags & SDHCI_USE_ADMA) {
832 ret = sdhci_adma_table_pre(host, data);
833 if (ret) {
834 /*
835 * This only happens when someone fed
836 * us an invalid request.
837 */
838 WARN_ON(1);
ebd6d357 839 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 840 } else {
4e4141a5
AV		 841 sdhci_writel(host, host->adma_addr,
842 SDHCI_ADMA_ADDRESS);
e57a5f61
AH		 843 if (host->flags & SDHCI_USE_64_BIT_DMA)
844 sdhci_writel(host,
845 (u64)host->adma_addr >> 32,
846 SDHCI_ADMA_ADDRESS_HI);
8f1934ce
PO		 847 }
848 } else {
c8b3e02e 849 int sg_cnt;
8f1934ce 850
c8b3e02e 851 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 852 data->sg, data->sg_len,
853 (data->flags & MMC_DATA_READ) ?
854 DMA_FROM_DEVICE :
855 DMA_TO_DEVICE);
c8b3e02e 856 if (sg_cnt == 0) {
8f1934ce
PO		 857 /*
858 * This only happens when someone fed
859 * us an invalid request.
860 */
861 WARN_ON(1);
ebd6d357 862 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 863 } else {
719a61b4 864 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 865 sdhci_writel(host, sg_dma_address(data->sg),
866 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 867 }
868 }
869 }
870
2134a922
PO		 871 /*
872 * Always adjust the DMA selection as some controllers
873 * (e.g. JMicron) can't do PIO properly when the selection
874 * is ADMA.
875 */
876 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 877 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 878 ctrl &= ~SDHCI_CTRL_DMA_MASK;
879 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 880 (host->flags & SDHCI_USE_ADMA)) {
881 if (host->flags & SDHCI_USE_64_BIT_DMA)
882 ctrl |= SDHCI_CTRL_ADMA64;
883 else
884 ctrl |= SDHCI_CTRL_ADMA32;
885 } else {
2134a922 886 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 887 }
4e4141a5 888 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 889 }
890
8f1934ce 891 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 892 int flags;
893
894 flags = SG_MITER_ATOMIC;
895 if (host->data->flags & MMC_DATA_READ)
896 flags |= SG_MITER_TO_SG;
897 else
898 flags |= SG_MITER_FROM_SG;
899 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 900 host->blocks = data->blocks;
d129bceb 901 }
c7fa9963 902
6aa943ab
AV		 903 sdhci_set_transfer_irqs(host);
904
f6a03cbf
MV		 905 /* Set the DMA boundary value and block size */
906 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
907 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 908 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 909}
910
911static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 912 struct mmc_command *cmd)
c7fa9963
PO		 913{
914 u16 mode;
e89d456f 915 struct mmc_data *data = cmd->data;
c7fa9963 916
2b558c13 917 if (data == NULL) {
9b8ffea6
VW		 918 if (host->quirks2 &
919 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
920 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
921 } else {
2b558c13 922 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 923 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
924 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 925 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 926 }
c7fa9963 927 return;
2b558c13 928 }
c7fa9963 929
e538fbe8
PO		 930 WARN_ON(!host->data);
931
c7fa9963 932 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 933 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
934 mode |= SDHCI_TRNS_MULTI;
935 /*
936 * If we are sending CMD23, CMD12 never gets sent
937 * on successful completion (so no Auto-CMD12).
938 */
939 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
940 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 941 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
942 mode |= SDHCI_TRNS_AUTO_CMD23;
943 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
944 }
c4512f79 945 }
8edf6371 946
c7fa9963
PO		 947 if (data->flags & MMC_DATA_READ)
948 mode |= SDHCI_TRNS_READ;
c9fddbc4 949 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 950 mode |= SDHCI_TRNS_DMA;
951
4e4141a5 952 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 953}
954
955static void sdhci_finish_data(struct sdhci_host *host)
956{
957 struct mmc_data *data;
d129bceb
PO		 958
959 BUG_ON(!host->data);
960
961 data = host->data;
962 host->data = NULL;
963
c9fddbc4 964 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 965 if (host->flags & SDHCI_USE_ADMA)
966 sdhci_adma_table_post(host, data);
967 else {
968 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
969 data->sg_len, (data->flags & MMC_DATA_READ) ?
970 DMA_FROM_DEVICE : DMA_TO_DEVICE);
971 }
d129bceb
PO		 972 }
973
974 /*
c9b74c5b
PO		 975 * The specification states that the block count register must
976 * be updated, but it does not specify at what point in the
977 * data flow. That makes the register entirely useless to read
978 * back so we have to assume that nothing made it to the card
979 * in the event of an error.
d129bceb 980 */
c9b74c5b
PO		 981 if (data->error)
982 data->bytes_xfered = 0;
d129bceb 983 else
c9b74c5b 984 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 985
e89d456f
AW		 986 /*
987 * Need to send CMD12 if -
988 * a) open-ended multiblock transfer (no CMD23)
989 * b) error in multiblock transfer
990 */
991 if (data->stop &&
992 (data->error ||
993 !host->mrq->sbc)) {
994
d129bceb
PO		 995 /*
996 * The controller needs a reset of internal state machines
997 * upon error conditions.
998 */
17b0429d 999 if (data->error) {
03231f9b
RK		 1000 sdhci_do_reset(host, SDHCI_RESET_CMD);
1001 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 1002 }
1003
1004 sdhci_send_command(host, data->stop);
1005 } else
1006 tasklet_schedule(&host->finish_tasklet);
1007}
1008
c0e55129 1009void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1010{
1011 int flags;
fd2208d7 1012 u32 mask;
7cb2c76f 1013 unsigned long timeout;
d129bceb
PO		 1014
1015 WARN_ON(host->cmd);
1016
d129bceb 1017 /* Wait max 10 ms */
7cb2c76f 1018 timeout = 10;
fd2208d7
PO		 1019
1020 mask = SDHCI_CMD_INHIBIT;
1021 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1022 mask |= SDHCI_DATA_INHIBIT;
1023
1024 /* We shouldn't wait for data inihibit for stop commands, even
1025 though they might use busy signaling */
1026 if (host->mrq->data && (cmd == host->mrq->data->stop))
1027 mask &= ~SDHCI_DATA_INHIBIT;
1028
4e4141a5 1029 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1030 if (timeout == 0) {
a3c76eb9 1031 pr_err("%s: Controller never released "
acf1da45 1032 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1033 sdhci_dumpregs(host);
17b0429d 1034 cmd->error = -EIO;
d129bceb
PO		 1035 tasklet_schedule(&host->finish_tasklet);
1036 return;
1037 }
7cb2c76f
PO		 1038 timeout--;
1039 mdelay(1);
1040 }
d129bceb 1041
3e1a6892 1042 timeout = jiffies;
1d4d7744
UH		 1043 if (!cmd->data && cmd->busy_timeout > 9000)
1044 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1045 else
1046 timeout += 10 * HZ;
1047 mod_timer(&host->timer, timeout);
d129bceb
PO		 1048
1049 host->cmd = cmd;
e99783a4 1050 host->busy_handle = 0;
d129bceb 1051
a3c7778f 1052 sdhci_prepare_data(host, cmd);
d129bceb 1053
4e4141a5 1054 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1055
e89d456f 1056 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1057
d129bceb 1058 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1059 pr_err("%s: Unsupported response type!\n",
d129bceb 1060 mmc_hostname(host->mmc));
17b0429d 1061 cmd->error = -EINVAL;
d129bceb
PO		 1062 tasklet_schedule(&host->finish_tasklet);
1063 return;
1064 }
1065
1066 if (!(cmd->flags & MMC_RSP_PRESENT))
1067 flags = SDHCI_CMD_RESP_NONE;
1068 else if (cmd->flags & MMC_RSP_136)
1069 flags = SDHCI_CMD_RESP_LONG;
1070 else if (cmd->flags & MMC_RSP_BUSY)
1071 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1072 else
1073 flags = SDHCI_CMD_RESP_SHORT;
1074
1075 if (cmd->flags & MMC_RSP_CRC)
1076 flags |= SDHCI_CMD_CRC;
1077 if (cmd->flags & MMC_RSP_OPCODE)
1078 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1079
1080 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1081 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1082 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1083 flags |= SDHCI_CMD_DATA;
1084
4e4141a5 1085 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1086}
c0e55129 1087EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1088
1089static void sdhci_finish_command(struct sdhci_host *host)
1090{
1091 int i;
1092
1093 BUG_ON(host->cmd == NULL);
1094
1095 if (host->cmd->flags & MMC_RSP_PRESENT) {
1096 if (host->cmd->flags & MMC_RSP_136) {
1097 /* CRC is stripped so we need to do some shifting. */
1098 for (i = 0;i < 4;i++) {
4e4141a5 1099 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1100 SDHCI_RESPONSE + (3-i)*4) << 8;
1101 if (i != 3)
1102 host->cmd->resp[i] |=
4e4141a5 1103 sdhci_readb(host,
d129bceb
PO		 1104 SDHCI_RESPONSE + (3-i)*4-1);
1105 }
1106 } else {
4e4141a5 1107 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1108 }
1109 }
1110
17b0429d 1111 host->cmd->error = 0;
d129bceb 1112
e89d456f
AW		 1113 /* Finished CMD23, now send actual command. */
1114 if (host->cmd == host->mrq->sbc) {
1115 host->cmd = NULL;
1116 sdhci_send_command(host, host->mrq->cmd);
1117 } else {
e538fbe8 1118
e89d456f
AW		 1119 /* Processed actual command. */
1120 if (host->data && host->data_early)
1121 sdhci_finish_data(host);
d129bceb 1122
e89d456f
AW		 1123 if (!host->cmd->data)
1124 tasklet_schedule(&host->finish_tasklet);
1125
1126 host->cmd = NULL;
1127 }
d129bceb
PO		 1128}
1129
52983382
KL		 1130static u16 sdhci_get_preset_value(struct sdhci_host *host)
1131{
d975f121 1132 u16 preset = 0;
52983382 1133
d975f121
RK		 1134 switch (host->timing) {
1135 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1136 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1137 break;
d975f121 1138 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1139 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1140 break;
d975f121 1141 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1142 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1143 break;
d975f121
RK		 1144 case MMC_TIMING_UHS_SDR104:
1145 case MMC_TIMING_MMC_HS200:
52983382
KL		 1146 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1147 break;
d975f121 1148 case MMC_TIMING_UHS_DDR50:
52983382
KL		 1149 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1150 break;
1151 default:
1152 pr_warn("%s: Invalid UHS-I mode selected\n",
1153 mmc_hostname(host->mmc));
1154 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1155 break;
1156 }
1157 return preset;
1158}
1159
1771059c 1160void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1161{
c3ed3877 1162 int div = 0; /* Initialized for compiler warning */
df16219f 1163 int real_div = div, clk_mul = 1;
c3ed3877 1164 u16 clk = 0;
7cb2c76f 1165 unsigned long timeout;
d129bceb 1166
1650d0c7
RK		 1167 host->mmc->actual_clock = 0;
1168
4e4141a5 1169 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1170
1171 if (clock == 0)
373073ef 1172 return;
d129bceb 1173
85105c53 1174 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1175 if (host->preset_enabled) {
52983382
KL		 1176 u16 pre_val;
1177
1178 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1179 pre_val = sdhci_get_preset_value(host);
1180 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1181 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1182 if (host->clk_mul &&
1183 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1184 clk = SDHCI_PROG_CLOCK_MODE;
1185 real_div = div + 1;
1186 clk_mul = host->clk_mul;
1187 } else {
1188 real_div = max_t(int, 1, div << 1);
1189 }
1190 goto clock_set;
1191 }
1192
c3ed3877
AN		 1193 /*
1194 * Check if the Host Controller supports Programmable Clock
1195 * Mode.
1196 */
1197 if (host->clk_mul) {
52983382
KL		 1198 for (div = 1; div <= 1024; div++) {
1199 if ((host->max_clk * host->clk_mul / div)
1200 <= clock)
1201 break;
1202 }
c3ed3877 1203 /*
52983382
KL		 1204 * Set Programmable Clock Mode in the Clock
1205 * Control register.
c3ed3877 1206 */
52983382
KL		 1207 clk = SDHCI_PROG_CLOCK_MODE;
1208 real_div = div;
1209 clk_mul = host->clk_mul;
1210 div--;
c3ed3877
AN		 1211 } else {
1212 /* Version 3.00 divisors must be a multiple of 2. */
1213 if (host->max_clk <= clock)
1214 div = 1;
1215 else {
1216 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1217 div += 2) {
1218 if ((host->max_clk / div) <= clock)
1219 break;
1220 }
85105c53 1221 }
df16219f 1222 real_div = div;
c3ed3877 1223 div >>= 1;
85105c53
ZG		 1224 }
1225 } else {
1226 /* Version 2.00 divisors must be a power of 2. */
0397526d 1227 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1228 if ((host->max_clk / div) <= clock)
1229 break;
1230 }
df16219f 1231 real_div = div;
c3ed3877 1232 div >>= 1;
d129bceb 1233 }
d129bceb 1234
52983382 1235clock_set:
03d6f5ff 1236 if (real_div)
df16219f 1237 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1238 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1239 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1240 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1241 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1242 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1243
27f6cb16
CB		 1244 /* Wait max 20 ms */
1245 timeout = 20;
4e4141a5 1246 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1247 & SDHCI_CLOCK_INT_STABLE)) {
1248 if (timeout == 0) {
a3c76eb9 1249 pr_err("%s: Internal clock never "
acf1da45 1250 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1251 sdhci_dumpregs(host);
1252 return;
1253 }
7cb2c76f
PO		 1254 timeout--;
1255 mdelay(1);
1256 }
d129bceb
PO		 1257
1258 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1259 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1260}
1771059c 1261EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1262
24fbb3ca
RK		 1263static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1264 unsigned short vdd)
146ad66e 1265{
3a48edc4 1266 struct mmc_host *mmc = host->mmc;
8364248a 1267 u8 pwr = 0;
146ad66e 1268
52221610
TK		 1269 if (!IS_ERR(mmc->supply.vmmc)) {
1270 spin_unlock_irq(&host->lock);
4e743f1f 1271 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
52221610
TK		 1272 spin_lock_irq(&host->lock);
1273 return;
1274 }
1275
24fbb3ca
RK		 1276 if (mode != MMC_POWER_OFF) {
1277 switch (1 << vdd) {
ae628903
PO		 1278 case MMC_VDD_165_195:
1279 pwr = SDHCI_POWER_180;
1280 break;
1281 case MMC_VDD_29_30:
1282 case MMC_VDD_30_31:
1283 pwr = SDHCI_POWER_300;
1284 break;
1285 case MMC_VDD_32_33:
1286 case MMC_VDD_33_34:
1287 pwr = SDHCI_POWER_330;
1288 break;
1289 default:
1290 BUG();
1291 }
1292 }
1293
1294 if (host->pwr == pwr)
e921a8b6 1295 return;
146ad66e 1296
ae628903
PO		 1297 host->pwr = pwr;
1298
1299 if (pwr == 0) {
4e4141a5 1300 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1301 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1302 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1303 vdd = 0;
e921a8b6
RK		 1304 } else {
1305 /*
1306 * Spec says that we should clear the power reg before setting
1307 * a new value. Some controllers don't seem to like this though.
1308 */
1309 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1310 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1311
e921a8b6
RK		 1312 /*
1313 * At least the Marvell CaFe chip gets confused if we set the
1314 * voltage and set turn on power at the same time, so set the
1315 * voltage first.
1316 */
1317 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1318 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1319
e921a8b6 1320 pwr |= SDHCI_POWER_ON;
146ad66e 1321
e921a8b6 1322 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1323
e921a8b6
RK		 1324 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1325 sdhci_runtime_pm_bus_on(host);
f0710a55 1326
e921a8b6
RK		 1327 /*
1328 * Some controllers need an extra 10ms delay of 10ms before
1329 * they can apply clock after applying power
1330 */
1331 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1332 mdelay(10);
1333 }
146ad66e
PO		 1334}
1335
d129bceb
PO		 1336/*****************************************************************************\
1337 * *
1338 * MMC callbacks *
1339 * *
1340\*****************************************************************************/
1341
1342static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1343{
1344 struct sdhci_host *host;
505a8680 1345 int present;
d129bceb 1346 unsigned long flags;
473b095a 1347 u32 tuning_opcode;
d129bceb
PO		 1348
1349 host = mmc_priv(mmc);
1350
66fd8ad5
AH		 1351 sdhci_runtime_pm_get(host);
1352
d129bceb
PO		 1353 spin_lock_irqsave(&host->lock, flags);
1354
1355 WARN_ON(host->mrq != NULL);
1356
f9134319 1357#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1358 sdhci_activate_led(host);
2f730fec 1359#endif
e89d456f
AW		 1360
1361 /*
1362 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1363 * requests if Auto-CMD12 is enabled.
1364 */
1365 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1366 if (mrq->stop) {
1367 mrq->data->stop = NULL;
1368 mrq->stop = NULL;
1369 }
1370 }
d129bceb
PO		 1371
1372 host->mrq = mrq;
1373
505a8680
SG		 1374 /*
1375 * Firstly check card presence from cd-gpio. The return could
1376 * be one of the following possibilities:
1377 * negative: cd-gpio is not available
1378 * zero: cd-gpio is used, and card is removed
1379 * one: cd-gpio is used, and card is present
1380 */
1381 present = mmc_gpio_get_cd(host->mmc);
1382 if (present < 0) {
1383 /* If polling, assume that the card is always present. */
1384 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1385 present = 1;
1386 else
1387 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1388 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1389 }
1390
68d1fb7e 1391 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1392 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1393 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1394 } else {
1395 u32 present_state;
1396
1397 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1398 /*
1399 * Check if the re-tuning timer has already expired and there
7756a96d
YS		 1400 * is no on-going data transfer and DAT0 is not busy. If so,
1401 * we need to execute tuning procedure before sending command.
cf2b5eea
AN		 1402 */
1403 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
7756a96d
YS		 1404 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1405 (present_state & SDHCI_DATA_0_LVL_MASK)) {
14efd957
CB		 1406 if (mmc->card) {
1407 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1408 tuning_opcode =
1409 mmc->card->type == MMC_TYPE_MMC ?
1410 MMC_SEND_TUNING_BLOCK_HS200 :
1411 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1412
1413 /* Here we need to set the host->mrq to NULL,
1414 * in case the pending finish_tasklet
1415 * finishes it incorrectly.
1416 */
1417 host->mrq = NULL;
1418
14efd957
CB		 1419 spin_unlock_irqrestore(&host->lock, flags);
1420 sdhci_execute_tuning(mmc, tuning_opcode);
1421 spin_lock_irqsave(&host->lock, flags);
1422
1423 /* Restore original mmc_request structure */
1424 host->mrq = mrq;
1425 }
cf2b5eea
AN		 1426 }
1427
8edf6371 1428 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1429 sdhci_send_command(host, mrq->sbc);
1430 else
1431 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1432 }
d129bceb 1433
5f25a66f 1434 mmiowb();
d129bceb
PO		 1435 spin_unlock_irqrestore(&host->lock, flags);
1436}
1437
2317f56c
RK		 1438void sdhci_set_bus_width(struct sdhci_host *host, int width)
1439{
1440 u8 ctrl;
1441
1442 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1443 if (width == MMC_BUS_WIDTH_8) {
1444 ctrl &= ~SDHCI_CTRL_4BITBUS;
1445 if (host->version >= SDHCI_SPEC_300)
1446 ctrl |= SDHCI_CTRL_8BITBUS;
1447 } else {
1448 if (host->version >= SDHCI_SPEC_300)
1449 ctrl &= ~SDHCI_CTRL_8BITBUS;
1450 if (width == MMC_BUS_WIDTH_4)
1451 ctrl |= SDHCI_CTRL_4BITBUS;
1452 else
1453 ctrl &= ~SDHCI_CTRL_4BITBUS;
1454 }
1455 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1456}
1457EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1458
96d7b78c
RK		 1459void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1460{
1461 u16 ctrl_2;
1462
1463 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1464 /* Select Bus Speed Mode for host */
1465 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1466 if ((timing == MMC_TIMING_MMC_HS200) ||
1467 (timing == MMC_TIMING_UHS_SDR104))
1468 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1469 else if (timing == MMC_TIMING_UHS_SDR12)
1470 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1471 else if (timing == MMC_TIMING_UHS_SDR25)
1472 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1473 else if (timing == MMC_TIMING_UHS_SDR50)
1474 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1475 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1476 (timing == MMC_TIMING_MMC_DDR52))
1477 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1478 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1479}
1480EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1481
66fd8ad5 1482static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1483{
d129bceb
PO		 1484 unsigned long flags;
1485 u8 ctrl;
3a48edc4 1486 struct mmc_host *mmc = host->mmc;
d129bceb 1487
d129bceb
PO		 1488 spin_lock_irqsave(&host->lock, flags);
1489
ceb6143b
AH		 1490 if (host->flags & SDHCI_DEVICE_DEAD) {
1491 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1492 if (!IS_ERR(mmc->supply.vmmc) &&
1493 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1494 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1495 return;
1496 }
1e72859e 1497
d129bceb
PO		 1498 /*
1499 * Reset the chip on each power off.
1500 * Should clear out any weird states.
1501 */
1502 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1503 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1504 sdhci_reinit(host);
d129bceb
PO		 1505 }
1506
52983382 1507 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1508 (ios->power_mode == MMC_POWER_UP) &&
1509 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1510 sdhci_enable_preset_value(host, false);
1511
373073ef 1512 if (!ios->clock || ios->clock != host->clock) {
1771059c 1513 host->ops->set_clock(host, ios->clock);
373073ef 1514 host->clock = ios->clock;
03d6f5ff
AD		 1515
1516 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1517 host->clock) {
1518 host->timeout_clk = host->mmc->actual_clock ?
1519 host->mmc->actual_clock / 1000 :
1520 host->clock / 1000;
1521 host->mmc->max_busy_timeout =
1522 host->ops->get_max_timeout_count ?
1523 host->ops->get_max_timeout_count(host) :
1524 1 << 27;
1525 host->mmc->max_busy_timeout /= host->timeout_clk;
1526 }
373073ef 1527 }
d129bceb 1528
24fbb3ca 1529 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1530
643a81ff
PR		 1531 if (host->ops->platform_send_init_74_clocks)
1532 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1533
2317f56c 1534 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1535
15ec4461 1536 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1537
3ab9c8da
PR		 1538 if ((ios->timing == MMC_TIMING_SD_HS ||
1539 ios->timing == MMC_TIMING_MMC_HS)
1540 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1541 ctrl |= SDHCI_CTRL_HISPD;
1542 else
1543 ctrl &= ~SDHCI_CTRL_HISPD;
1544
d6d50a15 1545 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1546 u16 clk, ctrl_2;
49c468fc
AN		 1547
1548 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1549 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1550 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1551 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1552 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1553 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1554 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1555 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1556
da91a8f9 1557 if (!host->preset_enabled) {
758535c4 1558 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1559 /*
1560 * We only need to set Driver Strength if the
1561 * preset value enable is not set.
1562 */
da91a8f9 1563 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1564 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1565 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1566 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1567 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1568 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1569
1570 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1571 } else {
1572 /*
1573 * According to SDHC Spec v3.00, if the Preset Value
1574 * Enable in the Host Control 2 register is set, we
1575 * need to reset SD Clock Enable before changing High
1576 * Speed Enable to avoid generating clock gliches.
1577 */
758535c4
AN		 1578
1579 /* Reset SD Clock Enable */
1580 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1581 clk &= ~SDHCI_CLOCK_CARD_EN;
1582 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1583
1584 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1585
1586 /* Re-enable SD Clock */
1771059c 1587 host->ops->set_clock(host, host->clock);
d6d50a15 1588 }
49c468fc 1589
49c468fc
AN		 1590 /* Reset SD Clock Enable */
1591 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1592 clk &= ~SDHCI_CLOCK_CARD_EN;
1593 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1594
96d7b78c 1595 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1596 host->timing = ios->timing;
49c468fc 1597
52983382
KL		 1598 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1599 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1600 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1601 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1602 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1603 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1604 u16 preset;
1605
1606 sdhci_enable_preset_value(host, true);
1607 preset = sdhci_get_preset_value(host);
1608 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1609 >> SDHCI_PRESET_DRV_SHIFT;
1610 }
1611
49c468fc 1612 /* Re-enable SD Clock */
1771059c 1613 host->ops->set_clock(host, host->clock);
758535c4
AN		 1614 } else
1615 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1616
b8352260
LD		 1617 /*
1618 * Some (ENE) controllers go apeshit on some ios operation,
1619 * signalling timeout and CRC errors even on CMD0. Resetting
1620 * it on each ios seems to solve the problem.
1621 */
b8c86fc5 1622 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1623 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1624
5f25a66f 1625 mmiowb();
d129bceb
PO		 1626 spin_unlock_irqrestore(&host->lock, flags);
1627}
1628
66fd8ad5
AH		 1629static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1630{
1631 struct sdhci_host *host = mmc_priv(mmc);
1632
1633 sdhci_runtime_pm_get(host);
1634 sdhci_do_set_ios(host, ios);
1635 sdhci_runtime_pm_put(host);
1636}
1637
94144a46
KL		 1638static int sdhci_do_get_cd(struct sdhci_host *host)
1639{
1640 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1641
1642 if (host->flags & SDHCI_DEVICE_DEAD)
1643 return 0;
1644
1645 /* If polling/nonremovable, assume that the card is always present. */
1646 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1647 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1648 return 1;
1649
1650 /* Try slot gpio detect */
1651 if (!IS_ERR_VALUE(gpio_cd))
1652 return !!gpio_cd;
1653
1654 /* Host native card detect */
1655 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1656}
1657
1658static int sdhci_get_cd(struct mmc_host *mmc)
1659{
1660 struct sdhci_host *host = mmc_priv(mmc);
1661 int ret;
1662
1663 sdhci_runtime_pm_get(host);
1664 ret = sdhci_do_get_cd(host);
1665 sdhci_runtime_pm_put(host);
1666 return ret;
1667}
1668
66fd8ad5 1669static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1670{
d129bceb 1671 unsigned long flags;
2dfb579c 1672 int is_readonly;
d129bceb 1673
d129bceb
PO		 1674 spin_lock_irqsave(&host->lock, flags);
1675
1e72859e 1676 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1677 is_readonly = 0;
1678 else if (host->ops->get_ro)
1679 is_readonly = host->ops->get_ro(host);
1e72859e 1680 else
2dfb579c
WS		 1681 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1682 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1683
1684 spin_unlock_irqrestore(&host->lock, flags);
1685
2dfb579c
WS		 1686 /* This quirk needs to be replaced by a callback-function later */
1687 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1688 !is_readonly : is_readonly;
d129bceb
PO		 1689}
1690
82b0e23a
TI		 1691#define SAMPLE_COUNT 5
1692
66fd8ad5 1693static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1694{
82b0e23a
TI		 1695 int i, ro_count;
1696
82b0e23a 1697 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1698 return sdhci_check_ro(host);
82b0e23a
TI		 1699
1700 ro_count = 0;
1701 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1702 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1703 if (++ro_count > SAMPLE_COUNT / 2)
1704 return 1;
1705 }
1706 msleep(30);
1707 }
1708 return 0;
1709}
1710
20758b66
AH		 1711static void sdhci_hw_reset(struct mmc_host *mmc)
1712{
1713 struct sdhci_host *host = mmc_priv(mmc);
1714
1715 if (host->ops && host->ops->hw_reset)
1716 host->ops->hw_reset(host);
1717}
1718
66fd8ad5 1719static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1720{
66fd8ad5
AH		 1721 struct sdhci_host *host = mmc_priv(mmc);
1722 int ret;
f75979b7 1723
66fd8ad5
AH		 1724 sdhci_runtime_pm_get(host);
1725 ret = sdhci_do_get_ro(host);
1726 sdhci_runtime_pm_put(host);
1727 return ret;
1728}
f75979b7 1729
66fd8ad5
AH		 1730static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1731{
be138554 1732 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1733 if (enable)
b537f94c 1734 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1735 else
b537f94c
RK		 1736 host->ier &= ~SDHCI_INT_CARD_INT;
1737
1738 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1739 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1740 mmiowb();
1741 }
66fd8ad5
AH		 1742}
1743
1744static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1745{
1746 struct sdhci_host *host = mmc_priv(mmc);
1747 unsigned long flags;
f75979b7 1748
ef104333
RK		 1749 sdhci_runtime_pm_get(host);
1750
66fd8ad5 1751 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1752 if (enable)
1753 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1754 else
1755 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1756
66fd8ad5 1757 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1758 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1759
1760 sdhci_runtime_pm_put(host);
f75979b7
PO		 1761}
1762
20b92a30 1763static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1764 struct mmc_ios *ios)
f2119df6 1765{
3a48edc4 1766 struct mmc_host *mmc = host->mmc;
20b92a30 1767 u16 ctrl;
6231f3de 1768 int ret;
f2119df6 1769
20b92a30
KL		 1770 /*
1771 * Signal Voltage Switching is only applicable for Host Controllers
1772 * v3.00 and above.
1773 */
1774 if (host->version < SDHCI_SPEC_300)
1775 return 0;
6231f3de 1776
f2119df6 1777 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1778
21f5998f 1779 switch (ios->signal_voltage) {
20b92a30
KL		 1780 case MMC_SIGNAL_VOLTAGE_330:
1781 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1782 ctrl &= ~SDHCI_CTRL_VDD_180;
1783 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1784
3a48edc4
TK		 1785 if (!IS_ERR(mmc->supply.vqmmc)) {
1786 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1787 3600000);
20b92a30 1788 if (ret) {
6606110d
JP		 1789 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1790 mmc_hostname(mmc));
20b92a30
KL		 1791 return -EIO;
1792 }
1793 }
1794 /* Wait for 5ms */
1795 usleep_range(5000, 5500);
f2119df6 1796
20b92a30
KL		 1797 /* 3.3V regulator output should be stable within 5 ms */
1798 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1799 if (!(ctrl & SDHCI_CTRL_VDD_180))
1800 return 0;
6231f3de 1801
6606110d
JP		 1802 pr_warn("%s: 3.3V regulator output did not became stable\n",
1803 mmc_hostname(mmc));
20b92a30
KL		 1804
1805 return -EAGAIN;
1806 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1807 if (!IS_ERR(mmc->supply.vqmmc)) {
1808 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1809 1700000, 1950000);
1810 if (ret) {
6606110d
JP		 1811 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1812 mmc_hostname(mmc));
20b92a30
KL		 1813 return -EIO;
1814 }
1815 }
6231f3de 1816
6231f3de
PR		 1817 /*
1818 * Enable 1.8V Signal Enable in the Host Control2
1819 * register
1820 */
20b92a30
KL		 1821 ctrl |= SDHCI_CTRL_VDD_180;
1822 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1823
20b92a30
KL		 1824 /* 1.8V regulator output should be stable within 5 ms */
1825 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1826 if (ctrl & SDHCI_CTRL_VDD_180)
1827 return 0;
f2119df6 1828
6606110d
JP		 1829 pr_warn("%s: 1.8V regulator output did not became stable\n",
1830 mmc_hostname(mmc));
f2119df6 1831
20b92a30
KL		 1832 return -EAGAIN;
1833 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1834 if (!IS_ERR(mmc->supply.vqmmc)) {
1835 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1836 1300000);
20b92a30 1837 if (ret) {
6606110d
JP		 1838 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1839 mmc_hostname(mmc));
20b92a30 1840 return -EIO;
f2119df6
AN		 1841 }
1842 }
6231f3de 1843 return 0;
20b92a30 1844 default:
f2119df6
AN		 1845 /* No signal voltage switch required */
1846 return 0;
20b92a30 1847 }
f2119df6
AN		 1848}
1849
66fd8ad5 1850static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1851 struct mmc_ios *ios)
66fd8ad5
AH		 1852{
1853 struct sdhci_host *host = mmc_priv(mmc);
1854 int err;
1855
1856 if (host->version < SDHCI_SPEC_300)
1857 return 0;
1858 sdhci_runtime_pm_get(host);
21f5998f 1859 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1860 sdhci_runtime_pm_put(host);
1861 return err;
1862}
1863
20b92a30
KL		 1864static int sdhci_card_busy(struct mmc_host *mmc)
1865{
1866 struct sdhci_host *host = mmc_priv(mmc);
1867 u32 present_state;
1868
1869 sdhci_runtime_pm_get(host);
1870 /* Check whether DAT[3:0] is 0000 */
1871 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1872 sdhci_runtime_pm_put(host);
1873
1874 return !(present_state & SDHCI_DATA_LVL_MASK);
1875}
1876
069c9f14 1877static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1878{
4b6f37d3 1879 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1880 u16 ctrl;
b513ea25 1881 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1882 int err = 0;
2b35bd83 1883 unsigned long flags;
b513ea25 1884
66fd8ad5 1885 sdhci_runtime_pm_get(host);
2b35bd83 1886 spin_lock_irqsave(&host->lock, flags);
b513ea25 1887
b513ea25 1888 /*
069c9f14
G		 1889 * The Host Controller needs tuning only in case of SDR104 mode
1890 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1891 * Capabilities register.
069c9f14
G		 1892 * If the Host Controller supports the HS200 mode then the
1893 * tuning function has to be executed.
b513ea25 1894 */
4b6f37d3
RK		 1895 switch (host->timing) {
1896 case MMC_TIMING_MMC_HS200:
1897 case MMC_TIMING_UHS_SDR104:
1898 break;
1899
1900 case MMC_TIMING_UHS_SDR50:
1901 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1902 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1903 break;
1904 /* FALLTHROUGH */
1905
1906 default:
2b35bd83 1907 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1908 sdhci_runtime_pm_put(host);
b513ea25
AN		 1909 return 0;
1910 }
1911
45251812 1912 if (host->ops->platform_execute_tuning) {
2b35bd83 1913 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1914 err = host->ops->platform_execute_tuning(host, opcode);
1915 sdhci_runtime_pm_put(host);
1916 return err;
1917 }
1918
4b6f37d3
RK		 1919 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1920 ctrl |= SDHCI_CTRL_EXEC_TUNING;
b513ea25
AN		 1921 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1922
1923 /*
1924 * As per the Host Controller spec v3.00, tuning command
1925 * generates Buffer Read Ready interrupt, so enable that.
1926 *
1927 * Note: The spec clearly says that when tuning sequence
1928 * is being performed, the controller does not generate
1929 * interrupts other than Buffer Read Ready interrupt. But
1930 * to make sure we don't hit a controller bug, we _only_
1931 * enable Buffer Read Ready interrupt here.
1932 */
b537f94c
RK		 1933 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1934 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1935
1936 /*
1937 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1938 * of loops reaches 40 times or a timeout of 150ms occurs.
1939 */
b513ea25
AN		 1940 do {
1941 struct mmc_command cmd = {0};
66fd8ad5 1942 struct mmc_request mrq = {NULL};
b513ea25 1943
069c9f14 1944 cmd.opcode = opcode;
b513ea25
AN		 1945 cmd.arg = 0;
1946 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1947 cmd.retries = 0;
1948 cmd.data = NULL;
1949 cmd.error = 0;
1950
7ce45e95
AC		 1951 if (tuning_loop_counter-- == 0)
1952 break;
1953
b513ea25
AN		 1954 mrq.cmd = &cmd;
1955 host->mrq = &mrq;
1956
1957 /*
1958 * In response to CMD19, the card sends 64 bytes of tuning
1959 * block to the Host Controller. So we set the block size
1960 * to 64 here.
1961 */
069c9f14
G		 1962 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1963 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1964 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1965 SDHCI_BLOCK_SIZE);
1966 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1967 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1968 SDHCI_BLOCK_SIZE);
1969 } else {
1970 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1971 SDHCI_BLOCK_SIZE);
1972 }
b513ea25
AN		 1973
1974 /*
1975 * The tuning block is sent by the card to the host controller.
1976 * So we set the TRNS_READ bit in the Transfer Mode register.
1977 * This also takes care of setting DMA Enable and Multi Block
1978 * Select in the same register to 0.
1979 */
1980 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1981
1982 sdhci_send_command(host, &cmd);
1983
1984 host->cmd = NULL;
1985 host->mrq = NULL;
1986
2b35bd83 1987 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1988 /* Wait for Buffer Read Ready interrupt */
1989 wait_event_interruptible_timeout(host->buf_ready_int,
1990 (host->tuning_done == 1),
1991 msecs_to_jiffies(50));
2b35bd83 1992 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1993
1994 if (!host->tuning_done) {
a3c76eb9 1995 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1996 "Buffer Read Ready interrupt during tuning "
1997 "procedure, falling back to fixed sampling "
1998 "clock\n");
1999 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2000 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2001 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2002 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2003
2004 err = -EIO;
2005 goto out;
2006 }
2007
2008 host->tuning_done = 0;
2009
2010 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2011
2012 /* eMMC spec does not require a delay between tuning cycles */
2013 if (opcode == MMC_SEND_TUNING_BLOCK)
2014 mdelay(1);
b513ea25
AN		 2015 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2016
2017 /*
2018 * The Host Driver has exhausted the maximum number of loops allowed,
2019 * so use fixed sampling frequency.
2020 */
7ce45e95 2021 if (tuning_loop_counter < 0) {
b513ea25
AN		 2022 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2023 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2024 }
2025 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2026 pr_info(DRIVER_NAME ": Tuning procedure"
2027 " failed, falling back to fixed sampling"
2028 " clock\n");
114f2bf6 2029 err = -EIO;
b513ea25
AN		 2030 }
2031
2032out:
cf2b5eea
AN		 2033 /*
2034 * If this is the very first time we are here, we start the retuning
2035 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2036 * flag won't be set, we check this condition before actually starting
2037 * the timer.
2038 */
2039 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2040 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 2041 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 2042 mod_timer(&host->tuning_timer, jiffies +
2043 host->tuning_count * HZ);
2044 /* Tuning mode 1 limits the maximum data length to 4MB */
2045 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 2046 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 2047 host->flags &= ~SDHCI_NEEDS_RETUNING;
2048 /* Reload the new initial value for timer */
2bc02485
AS		 2049 mod_timer(&host->tuning_timer, jiffies +
2050 host->tuning_count * HZ);
cf2b5eea
AN		 2051 }
2052
2053 /*
2054 * In case tuning fails, host controllers which support re-tuning can
2055 * try tuning again at a later time, when the re-tuning timer expires.
2056 * So for these controllers, we return 0. Since there might be other
2057 * controllers who do not have this capability, we return error for
973905fe
AL		 2058 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2059 * a retuning timer to do the retuning for the card.
cf2b5eea 2060 */
973905fe 2061 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2062 err = 0;
2063
b537f94c
RK		 2064 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2065 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2b35bd83 2066 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2067 sdhci_runtime_pm_put(host);
b513ea25
AN		 2068
2069 return err;
2070}
2071
52983382
KL		 2072
2073static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2074{
4d55c5a1
AN		 2075 /* Host Controller v3.00 defines preset value registers */
2076 if (host->version < SDHCI_SPEC_300)
2077 return;
2078
4d55c5a1
AN		 2079 /*
2080 * We only enable or disable Preset Value if they are not already
2081 * enabled or disabled respectively. Otherwise, we bail out.
2082 */
da91a8f9
RK		 2083 if (host->preset_enabled != enable) {
2084 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2085
2086 if (enable)
2087 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2088 else
2089 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2090
4d55c5a1 2091 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2092
2093 if (enable)
2094 host->flags |= SDHCI_PV_ENABLED;
2095 else
2096 host->flags &= ~SDHCI_PV_ENABLED;
2097
2098 host->preset_enabled = enable;
4d55c5a1 2099 }
66fd8ad5
AH		 2100}
2101
71e69211 2102static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2103{
71e69211 2104 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2105 unsigned long flags;
2106
722e1280
CD		 2107 /* First check if client has provided their own card event */
2108 if (host->ops->card_event)
2109 host->ops->card_event(host);
2110
d129bceb
PO		 2111 spin_lock_irqsave(&host->lock, flags);
2112
66fd8ad5 2113 /* Check host->mrq first in case we are runtime suspended */
9668d765 2114 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2115 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2116 mmc_hostname(host->mmc));
a3c76eb9 2117 pr_err("%s: Resetting controller.\n",
66fd8ad5 2118 mmc_hostname(host->mmc));
d129bceb 2119
03231f9b
RK		 2120 sdhci_do_reset(host, SDHCI_RESET_CMD);
2121 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2122
66fd8ad5
AH		 2123 host->mrq->cmd->error = -ENOMEDIUM;
2124 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2125 }
2126
2127 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2128}
2129
2130static const struct mmc_host_ops sdhci_ops = {
2131 .request = sdhci_request,
2132 .set_ios = sdhci_set_ios,
94144a46 2133 .get_cd = sdhci_get_cd,
71e69211
GL		 2134 .get_ro = sdhci_get_ro,
2135 .hw_reset = sdhci_hw_reset,
2136 .enable_sdio_irq = sdhci_enable_sdio_irq,
2137 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2138 .execute_tuning = sdhci_execute_tuning,
71e69211 2139 .card_event = sdhci_card_event,
20b92a30 2140 .card_busy = sdhci_card_busy,
71e69211
GL		 2141};
2142
2143/*****************************************************************************\
2144 * *
2145 * Tasklets *
2146 * *
2147\*****************************************************************************/
2148
d129bceb
PO		 2149static void sdhci_tasklet_finish(unsigned long param)
2150{
2151 struct sdhci_host *host;
2152 unsigned long flags;
2153 struct mmc_request *mrq;
2154
2155 host = (struct sdhci_host*)param;
2156
66fd8ad5
AH		 2157 spin_lock_irqsave(&host->lock, flags);
2158
0c9c99a7
CB		 2159 /*
2160 * If this tasklet gets rescheduled while running, it will
2161 * be run again afterwards but without any active request.
2162 */
66fd8ad5
AH		 2163 if (!host->mrq) {
2164 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2165 return;
66fd8ad5 2166 }
d129bceb
PO		 2167
2168 del_timer(&host->timer);
2169
2170 mrq = host->mrq;
2171
d129bceb
PO		 2172 /*
2173 * The controller needs a reset of internal state machines
2174 * upon error conditions.
2175 */
1e72859e 2176 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2177 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2178 (mrq->sbc && mrq->sbc->error) ||
2179 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2180 (mrq->data->stop && mrq->data->stop->error))) ||
2181 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2182
2183 /* Some controllers need this kick or reset won't work here */
8213af3b 2184 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2185 /* This is to force an update */
1771059c 2186 host->ops->set_clock(host, host->clock);
645289dc
PO		 2187
2188 /* Spec says we should do both at the same time, but Ricoh
2189 controllers do not like that. */
03231f9b
RK		 2190 sdhci_do_reset(host, SDHCI_RESET_CMD);
2191 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2192 }
2193
2194 host->mrq = NULL;
2195 host->cmd = NULL;
2196 host->data = NULL;
2197
f9134319 2198#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2199 sdhci_deactivate_led(host);
2f730fec 2200#endif
d129bceb 2201
5f25a66f 2202 mmiowb();
d129bceb
PO		 2203 spin_unlock_irqrestore(&host->lock, flags);
2204
2205 mmc_request_done(host->mmc, mrq);
66fd8ad5 2206 sdhci_runtime_pm_put(host);
d129bceb
PO		 2207}
2208
2209static void sdhci_timeout_timer(unsigned long data)
2210{
2211 struct sdhci_host *host;
2212 unsigned long flags;
2213
2214 host = (struct sdhci_host*)data;
2215
2216 spin_lock_irqsave(&host->lock, flags);
2217
2218 if (host->mrq) {
a3c76eb9 2219 pr_err("%s: Timeout waiting for hardware "
acf1da45 2220 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2221 sdhci_dumpregs(host);
2222
2223 if (host->data) {
17b0429d 2224 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2225 sdhci_finish_data(host);
2226 } else {
2227 if (host->cmd)
17b0429d 2228 host->cmd->error = -ETIMEDOUT;
d129bceb 2229 else
17b0429d 2230 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2231
2232 tasklet_schedule(&host->finish_tasklet);
2233 }
2234 }
2235
5f25a66f 2236 mmiowb();
d129bceb
PO		 2237 spin_unlock_irqrestore(&host->lock, flags);
2238}
2239
cf2b5eea
AN		 2240static void sdhci_tuning_timer(unsigned long data)
2241{
2242 struct sdhci_host *host;
2243 unsigned long flags;
2244
2245 host = (struct sdhci_host *)data;
2246
2247 spin_lock_irqsave(&host->lock, flags);
2248
2249 host->flags |= SDHCI_NEEDS_RETUNING;
2250
2251 spin_unlock_irqrestore(&host->lock, flags);
2252}
2253
d129bceb
PO		 2254/*****************************************************************************\
2255 * *
2256 * Interrupt handling *
2257 * *
2258\*****************************************************************************/
2259
61541397 2260static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2261{
2262 BUG_ON(intmask == 0);
2263
2264 if (!host->cmd) {
a3c76eb9 2265 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2266 "though no command operation was in progress.\n",
2267 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2268 sdhci_dumpregs(host);
2269 return;
2270 }
2271
43b58b36 2272 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2273 host->cmd->error = -ETIMEDOUT;
2274 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2275 SDHCI_INT_INDEX))
2276 host->cmd->error = -EILSEQ;
43b58b36 2277
e809517f 2278 if (host->cmd->error) {
d129bceb 2279 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2280 return;
2281 }
2282
2283 /*
2284 * The host can send and interrupt when the busy state has
2285 * ended, allowing us to wait without wasting CPU cycles.
2286 * Unfortunately this is overloaded on the "data complete"
2287 * interrupt, so we need to take some care when handling
2288 * it.
2289 *
2290 * Note: The 1.0 specification is a bit ambiguous about this
2291 * feature so there might be some problems with older
2292 * controllers.
2293 */
2294 if (host->cmd->flags & MMC_RSP_BUSY) {
2295 if (host->cmd->data)
2296 DBG("Cannot wait for busy signal when also "
2297 "doing a data transfer");
e99783a4
CM		 2298 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2299 && !host->busy_handle) {
2300 /* Mark that command complete before busy is ended */
2301 host->busy_handle = 1;
e809517f 2302 return;
e99783a4 2303 }
f945405c
BD		 2304
2305 /* The controller does not support the end-of-busy IRQ,
2306 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2307 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2308 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2309 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2310 }
2311
2312 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2313 sdhci_finish_command(host);
d129bceb
PO		 2314}
2315
0957c333 2316#ifdef CONFIG_MMC_DEBUG
08621b18 2317static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2318{
2319 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2320 void *desc = host->adma_table;
6882a8c0
BD		 2321
2322 sdhci_dumpregs(host);
2323
2324 while (true) {
e57a5f61
AH		 2325 struct sdhci_adma2_64_desc *dma_desc = desc;
2326
2327 if (host->flags & SDHCI_USE_64_BIT_DMA)
2328 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2329 name, desc, le32_to_cpu(dma_desc->addr_hi),
2330 le32_to_cpu(dma_desc->addr_lo),
2331 le16_to_cpu(dma_desc->len),
2332 le16_to_cpu(dma_desc->cmd));
2333 else
2334 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2335 name, desc, le32_to_cpu(dma_desc->addr_lo),
2336 le16_to_cpu(dma_desc->len),
2337 le16_to_cpu(dma_desc->cmd));
6882a8c0 2338
76fe379a 2339 desc += host->desc_sz;
6882a8c0 2340
0545230f 2341 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2342 break;
2343 }
2344}
2345#else
08621b18 2346static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2347#endif
2348
d129bceb
PO		 2349static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2350{
069c9f14 2351 u32 command;
d129bceb
PO		 2352 BUG_ON(intmask == 0);
2353
b513ea25
AN		 2354 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2355 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2356 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2357 if (command == MMC_SEND_TUNING_BLOCK ||
2358 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2359 host->tuning_done = 1;
2360 wake_up(&host->buf_ready_int);
2361 return;
2362 }
2363 }
2364
d129bceb
PO		 2365 if (!host->data) {
2366 /*
e809517f
PO		 2367 * The "data complete" interrupt is also used to
2368 * indicate that a busy state has ended. See comment
2369 * above in sdhci_cmd_irq().
d129bceb 2370 */
e809517f 2371 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2372 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2373 host->cmd->error = -ETIMEDOUT;
2374 tasklet_schedule(&host->finish_tasklet);
2375 return;
2376 }
e809517f 2377 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2378 /*
2379 * Some cards handle busy-end interrupt
2380 * before the command completed, so make
2381 * sure we do things in the proper order.
2382 */
2383 if (host->busy_handle)
2384 sdhci_finish_command(host);
2385 else
2386 host->busy_handle = 1;
e809517f
PO		 2387 return;
2388 }
2389 }
d129bceb 2390
a3c76eb9 2391 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2392 "though no data operation was in progress.\n",
2393 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2394 sdhci_dumpregs(host);
2395
2396 return;
2397 }
2398
2399 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2400 host->data->error = -ETIMEDOUT;
22113efd
AL		 2401 else if (intmask & SDHCI_INT_DATA_END_BIT)
2402 host->data->error = -EILSEQ;
2403 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2404 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2405 != MMC_BUS_TEST_R)
17b0429d 2406 host->data->error = -EILSEQ;
6882a8c0 2407 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2408 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2409 sdhci_adma_show_error(host);
2134a922 2410 host->data->error = -EIO;
a4071fbb
HZ		 2411 if (host->ops->adma_workaround)
2412 host->ops->adma_workaround(host, intmask);
6882a8c0 2413 }
d129bceb 2414
17b0429d 2415 if (host->data->error)
d129bceb
PO		 2416 sdhci_finish_data(host);
2417 else {
a406f5a3 2418 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2419 sdhci_transfer_pio(host);
2420
6ba736a1
PO		 2421 /*
2422 * We currently don't do anything fancy with DMA
2423 * boundaries, but as we can't disable the feature
2424 * we need to at least restart the transfer.
f6a03cbf
MV		 2425 *
2426 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2427 * should return a valid address to continue from, but as
2428 * some controllers are faulty, don't trust them.
6ba736a1 2429 */
f6a03cbf
MV		 2430 if (intmask & SDHCI_INT_DMA_END) {
2431 u32 dmastart, dmanow;
2432 dmastart = sg_dma_address(host->data->sg);
2433 dmanow = dmastart + host->data->bytes_xfered;
2434 /*
2435 * Force update to the next DMA block boundary.
2436 */
2437 dmanow = (dmanow &
2438 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2439 SDHCI_DEFAULT_BOUNDARY_SIZE;
2440 host->data->bytes_xfered = dmanow - dmastart;
2441 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2442 " next 0x%08x\n",
2443 mmc_hostname(host->mmc), dmastart,
2444 host->data->bytes_xfered, dmanow);
2445 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2446 }
6ba736a1 2447
e538fbe8
PO		 2448 if (intmask & SDHCI_INT_DATA_END) {
2449 if (host->cmd) {
2450 /*
2451 * Data managed to finish before the
2452 * command completed. Make sure we do
2453 * things in the proper order.
2454 */
2455 host->data_early = 1;
2456 } else {
2457 sdhci_finish_data(host);
2458 }
2459 }
d129bceb
PO		 2460 }
2461}
2462
7d12e780 2463static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2464{
781e989c 2465 irqreturn_t result = IRQ_NONE;
66fd8ad5 2466 struct sdhci_host *host = dev_id;
41005003 2467 u32 intmask, mask, unexpected = 0;
781e989c 2468 int max_loops = 16;
d129bceb
PO		 2469
2470 spin_lock(&host->lock);
2471
be138554 2472 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2473 spin_unlock(&host->lock);
655bca76 2474 return IRQ_NONE;
66fd8ad5
AH		 2475 }
2476
4e4141a5 2477 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2478 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2479 result = IRQ_NONE;
2480 goto out;
2481 }
2482
41005003
RK		 2483 do {
2484 /* Clear selected interrupts. */
2485 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2486 SDHCI_INT_BUS_POWER);
2487 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2488
41005003
RK		 2489 DBG("*** %s got interrupt: 0x%08x\n",
2490 mmc_hostname(host->mmc), intmask);
d129bceb 2491
41005003
RK		 2492 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2493 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2494 SDHCI_CARD_PRESENT;
d129bceb 2495
41005003
RK		 2496 /*
2497 * There is a observation on i.mx esdhc. INSERT
2498 * bit will be immediately set again when it gets
2499 * cleared, if a card is inserted. We have to mask
2500 * the irq to prevent interrupt storm which will
2501 * freeze the system. And the REMOVE gets the
2502 * same situation.
2503 *
2504 * More testing are needed here to ensure it works
2505 * for other platforms though.
2506 */
b537f94c
RK		 2507 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2508 SDHCI_INT_CARD_REMOVE);
2509 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2510 SDHCI_INT_CARD_INSERT;
2511 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2512 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2513
2514 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2515 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2516
2517 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2518 SDHCI_INT_CARD_REMOVE);
2519 result = IRQ_WAKE_THREAD;
41005003 2520 }
d129bceb 2521
41005003 2522 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2523 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2524 &intmask);
964f9ce2 2525
41005003
RK		 2526 if (intmask & SDHCI_INT_DATA_MASK)
2527 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2528
41005003
RK		 2529 if (intmask & SDHCI_INT_BUS_POWER)
2530 pr_err("%s: Card is consuming too much power!\n",
2531 mmc_hostname(host->mmc));
3192a28f 2532
781e989c
RK		 2533 if (intmask & SDHCI_INT_CARD_INT) {
2534 sdhci_enable_sdio_irq_nolock(host, false);
2535 host->thread_isr |= SDHCI_INT_CARD_INT;
2536 result = IRQ_WAKE_THREAD;
2537 }
f75979b7 2538
41005003
RK		 2539 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2540 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2541 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2542 SDHCI_INT_CARD_INT);
f75979b7 2543
41005003
RK		 2544 if (intmask) {
2545 unexpected |= intmask;
2546 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2547 }
d129bceb 2548
781e989c
RK		 2549 if (result == IRQ_NONE)
2550 result = IRQ_HANDLED;
d129bceb 2551
41005003 2552 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2553 } while (intmask && --max_loops);
d129bceb
PO		 2554out:
2555 spin_unlock(&host->lock);
2556
6379b237
AS		 2557 if (unexpected) {
2558 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2559 mmc_hostname(host->mmc), unexpected);
2560 sdhci_dumpregs(host);
2561 }
f75979b7 2562
d129bceb
PO		 2563 return result;
2564}
2565
781e989c
RK		 2566static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2567{
2568 struct sdhci_host *host = dev_id;
2569 unsigned long flags;
2570 u32 isr;
2571
2572 spin_lock_irqsave(&host->lock, flags);
2573 isr = host->thread_isr;
2574 host->thread_isr = 0;
2575 spin_unlock_irqrestore(&host->lock, flags);
2576
3560db8e
RK		 2577 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2578 sdhci_card_event(host->mmc);
2579 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2580 }
2581
781e989c
RK		 2582 if (isr & SDHCI_INT_CARD_INT) {
2583 sdio_run_irqs(host->mmc);
2584
2585 spin_lock_irqsave(&host->lock, flags);
2586 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2587 sdhci_enable_sdio_irq_nolock(host, true);
2588 spin_unlock_irqrestore(&host->lock, flags);
2589 }
2590
2591 return isr ? IRQ_HANDLED : IRQ_NONE;
2592}
2593
d129bceb
PO		 2594/*****************************************************************************\
2595 * *
2596 * Suspend/resume *
2597 * *
2598\*****************************************************************************/
2599
2600#ifdef CONFIG_PM
ad080d79
KL		 2601void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2602{
2603 u8 val;
2604 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2605 | SDHCI_WAKE_ON_INT;
2606
2607 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2608 val |= mask ;
2609 /* Avoid fake wake up */
2610 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2611 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2612 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2613}
2614EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2615
0b10f478 2616static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2617{
2618 u8 val;
2619 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2620 | SDHCI_WAKE_ON_INT;
2621
2622 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2623 val &= ~mask;
2624 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2625}
d129bceb 2626
29495aa0 2627int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2628{
7260cf5e
AV		 2629 sdhci_disable_card_detection(host);
2630
cf2b5eea 2631 /* Disable tuning since we are suspending */
973905fe 2632 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2633 del_timer_sync(&host->tuning_timer);
cf2b5eea 2634 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2635 }
2636
ad080d79 2637 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2638 host->ier = 0;
2639 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2640 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2641 free_irq(host->irq, host);
2642 } else {
2643 sdhci_enable_irq_wakeups(host);
2644 enable_irq_wake(host->irq);
2645 }
4ee14ec6 2646 return 0;
d129bceb
PO		 2647}
2648
b8c86fc5 2649EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2650
b8c86fc5
PO		 2651int sdhci_resume_host(struct sdhci_host *host)
2652{
4ee14ec6 2653 int ret = 0;
d129bceb 2654
a13abc7b 2655 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2656 if (host->ops->enable_dma)
2657 host->ops->enable_dma(host);
2658 }
d129bceb 2659
ad080d79 2660 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2661 ret = request_threaded_irq(host->irq, sdhci_irq,
2662 sdhci_thread_irq, IRQF_SHARED,
2663 mmc_hostname(host->mmc), host);
ad080d79
KL		 2664 if (ret)
2665 return ret;
2666 } else {
2667 sdhci_disable_irq_wakeups(host);
2668 disable_irq_wake(host->irq);
2669 }
d129bceb 2670
6308d290
AH		 2671 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2672 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2673 /* Card keeps power but host controller does not */
2674 sdhci_init(host, 0);
2675 host->pwr = 0;
2676 host->clock = 0;
2677 sdhci_do_set_ios(host, &host->mmc->ios);
2678 } else {
2679 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2680 mmiowb();
2681 }
b8c86fc5 2682
7260cf5e
AV		 2683 sdhci_enable_card_detection(host);
2684
cf2b5eea 2685 /* Set the re-tuning expiration flag */
973905fe 2686 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2687 host->flags |= SDHCI_NEEDS_RETUNING;
2688
2f4cbb3d 2689 return ret;
d129bceb
PO		 2690}
2691
b8c86fc5 2692EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2693#endif /* CONFIG_PM */
2694
66fd8ad5
AH		 2695#ifdef CONFIG_PM_RUNTIME
2696
2697static int sdhci_runtime_pm_get(struct sdhci_host *host)
2698{
2699 return pm_runtime_get_sync(host->mmc->parent);
2700}
2701
2702static int sdhci_runtime_pm_put(struct sdhci_host *host)
2703{
2704 pm_runtime_mark_last_busy(host->mmc->parent);
2705 return pm_runtime_put_autosuspend(host->mmc->parent);
2706}
2707
f0710a55
AH		 2708static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2709{
2710 if (host->runtime_suspended || host->bus_on)
2711 return;
2712 host->bus_on = true;
2713 pm_runtime_get_noresume(host->mmc->parent);
2714}
2715
2716static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2717{
2718 if (host->runtime_suspended || !host->bus_on)
2719 return;
2720 host->bus_on = false;
2721 pm_runtime_put_noidle(host->mmc->parent);
2722}
2723
66fd8ad5
AH		 2724int sdhci_runtime_suspend_host(struct sdhci_host *host)
2725{
2726 unsigned long flags;
66fd8ad5
AH		 2727
2728 /* Disable tuning since we are suspending */
973905fe 2729 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2730 del_timer_sync(&host->tuning_timer);
2731 host->flags &= ~SDHCI_NEEDS_RETUNING;
2732 }
2733
2734 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2735 host->ier &= SDHCI_INT_CARD_INT;
2736 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2737 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2738 spin_unlock_irqrestore(&host->lock, flags);
2739
781e989c 2740 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2741
2742 spin_lock_irqsave(&host->lock, flags);
2743 host->runtime_suspended = true;
2744 spin_unlock_irqrestore(&host->lock, flags);
2745
8a125bad 2746 return 0;
66fd8ad5
AH		 2747}
2748EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2749
2750int sdhci_runtime_resume_host(struct sdhci_host *host)
2751{
2752 unsigned long flags;
8a125bad 2753 int host_flags = host->flags;
66fd8ad5
AH		 2754
2755 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2756 if (host->ops->enable_dma)
2757 host->ops->enable_dma(host);
2758 }
2759
2760 sdhci_init(host, 0);
2761
2762 /* Force clock and power re-program */
2763 host->pwr = 0;
2764 host->clock = 0;
2765 sdhci_do_set_ios(host, &host->mmc->ios);
2766
2767 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2768 if ((host_flags & SDHCI_PV_ENABLED) &&
2769 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2770 spin_lock_irqsave(&host->lock, flags);
2771 sdhci_enable_preset_value(host, true);
2772 spin_unlock_irqrestore(&host->lock, flags);
2773 }
66fd8ad5
AH		 2774
2775 /* Set the re-tuning expiration flag */
973905fe 2776 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2777 host->flags |= SDHCI_NEEDS_RETUNING;
2778
2779 spin_lock_irqsave(&host->lock, flags);
2780
2781 host->runtime_suspended = false;
2782
2783 /* Enable SDIO IRQ */
ef104333 2784 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2785 sdhci_enable_sdio_irq_nolock(host, true);
2786
2787 /* Enable Card Detection */
2788 sdhci_enable_card_detection(host);
2789
2790 spin_unlock_irqrestore(&host->lock, flags);
2791
8a125bad 2792 return 0;
66fd8ad5
AH		 2793}
2794EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2795
2796#endif
2797
d129bceb
PO		 2798/*****************************************************************************\
2799 * *
b8c86fc5 2800 * Device allocation/registration *
d129bceb
PO		 2801 * *
2802\*****************************************************************************/
2803
b8c86fc5
PO		 2804struct sdhci_host *sdhci_alloc_host(struct device *dev,
2805 size_t priv_size)
d129bceb 2806{
d129bceb
PO		 2807 struct mmc_host *mmc;
2808 struct sdhci_host *host;
2809
b8c86fc5 2810 WARN_ON(dev == NULL);
d129bceb 2811
b8c86fc5 2812 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2813 if (!mmc)
b8c86fc5 2814 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2815
2816 host = mmc_priv(mmc);
2817 host->mmc = mmc;
2818
b8c86fc5
PO		 2819 return host;
2820}
8a4da143 2821
b8c86fc5 2822EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2823
b8c86fc5
PO		 2824int sdhci_add_host(struct sdhci_host *host)
2825{
2826 struct mmc_host *mmc;
bd6a8c30 2827 u32 caps[2] = {0, 0};
f2119df6
AN		 2828 u32 max_current_caps;
2829 unsigned int ocr_avail;
f5fa92e5 2830 unsigned int override_timeout_clk;
b8c86fc5 2831 int ret;
d129bceb 2832
b8c86fc5
PO		 2833 WARN_ON(host == NULL);
2834 if (host == NULL)
2835 return -EINVAL;
d129bceb 2836
b8c86fc5 2837 mmc = host->mmc;
d129bceb 2838
b8c86fc5
PO		 2839 if (debug_quirks)
2840 host->quirks = debug_quirks;
66fd8ad5
AH		 2841 if (debug_quirks2)
2842 host->quirks2 = debug_quirks2;
d129bceb 2843
f5fa92e5
AH		 2844 override_timeout_clk = host->timeout_clk;
2845
03231f9b 2846 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2847
4e4141a5 2848 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2849 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2850 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2851 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2852 pr_err("%s: Unknown controller version (%d). "
b69c9058 2853 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2854 host->version);
4a965505
PO		 2855 }
2856
f2119df6 2857 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2858 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2859
bd6a8c30
PR		 2860 if (host->version >= SDHCI_SPEC_300)
2861 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2862 host->caps1 :
2863 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2864
b8c86fc5 2865 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2866 host->flags |= SDHCI_USE_SDMA;
f2119df6 2867 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2868 DBG("Controller doesn't have SDMA capability\n");
67435274 2869 else
a13abc7b 2870 host->flags |= SDHCI_USE_SDMA;
d129bceb 2871
b8c86fc5 2872 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2873 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2874 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2875 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2876 }
2877
f2119df6
AN		 2878 if ((host->version >= SDHCI_SPEC_200) &&
2879 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2880 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2881
2882 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2883 (host->flags & SDHCI_USE_ADMA)) {
2884 DBG("Disabling ADMA as it is marked broken\n");
2885 host->flags &= ~SDHCI_USE_ADMA;
2886 }
2887
e57a5f61
AH		 2888 /*
2889 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2890 * and *must* do 64-bit DMA. A driver has the opportunity to change
2891 * that during the first call to ->enable_dma(). Similarly
2892 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2893 * implement.
2894 */
2895 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2896 host->flags |= SDHCI_USE_64_BIT_DMA;
2897
a13abc7b 2898 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2899 if (host->ops->enable_dma) {
2900 if (host->ops->enable_dma(host)) {
6606110d 2901 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2902 mmc_hostname(mmc));
a13abc7b
RR		 2903 host->flags &=
2904 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2905 }
d129bceb
PO		 2906 }
2907 }
2908
e57a5f61
AH		 2909 /* SDMA does not support 64-bit DMA */
2910 if (host->flags & SDHCI_USE_64_BIT_DMA)
2911 host->flags &= ~SDHCI_USE_SDMA;
2912
2134a922
PO		 2913 if (host->flags & SDHCI_USE_ADMA) {
2914 /*
76fe379a
AH		 2915 * The DMA descriptor table size is calculated as the maximum
2916 * number of segments times 2, to allow for an alignment
2917 * descriptor for each segment, plus 1 for a nop end descriptor,
2918 * all multipled by the descriptor size.
2134a922 2919 */
e57a5f61
AH		 2920 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2921 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2922 SDHCI_ADMA2_64_DESC_SZ;
2923 host->align_buffer_sz = SDHCI_MAX_SEGS *
2924 SDHCI_ADMA2_64_ALIGN;
2925 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2926 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2927 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2928 } else {
2929 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2930 SDHCI_ADMA2_32_DESC_SZ;
2931 host->align_buffer_sz = SDHCI_MAX_SEGS *
2932 SDHCI_ADMA2_32_ALIGN;
2933 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2934 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2935 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2936 }
4efaa6fb 2937 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
76fe379a 2938 host->adma_table_sz,
4efaa6fb
AH		 2939 &host->adma_addr,
2940 GFP_KERNEL);
76fe379a 2941 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
4efaa6fb 2942 if (!host->adma_table || !host->align_buffer) {
76fe379a 2943 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 2944 host->adma_table, host->adma_addr);
2134a922 2945 kfree(host->align_buffer);
6606110d 2946 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2947 mmc_hostname(mmc));
2948 host->flags &= ~SDHCI_USE_ADMA;
4efaa6fb 2949 host->adma_table = NULL;
d1e49f77 2950 host->align_buffer = NULL;
76fe379a 2951 } else if (host->adma_addr & host->align_mask) {
6606110d
JP		 2952 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2953 mmc_hostname(mmc));
d1e49f77 2954 host->flags &= ~SDHCI_USE_ADMA;
76fe379a 2955 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 2956 host->adma_table, host->adma_addr);
d1e49f77 2957 kfree(host->align_buffer);
4efaa6fb 2958 host->adma_table = NULL;
d1e49f77 2959 host->align_buffer = NULL;
2134a922
PO		 2960 }
2961 }
2962
7659150c
PO		 2963 /*
2964 * If we use DMA, then it's up to the caller to set the DMA
2965 * mask, but PIO does not need the hw shim so we set a new
2966 * mask here in that case.
2967 */
a13abc7b 2968 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2969 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2970 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2971 }
d129bceb 2972
c4687d5f 2973 if (host->version >= SDHCI_SPEC_300)
f2119df6 2974 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2975 >> SDHCI_CLOCK_BASE_SHIFT;
2976 else
f2119df6 2977 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2978 >> SDHCI_CLOCK_BASE_SHIFT;
2979
4240ff0a 2980 host->max_clk *= 1000000;
f27f47ef
AV		 2981 if (host->max_clk == 0 || host->quirks &
2982 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2983 if (!host->ops->get_max_clock) {
a3c76eb9 2984 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2985 "frequency.\n", mmc_hostname(mmc));
2986 return -ENODEV;
2987 }
2988 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2989 }
d129bceb 2990
c3ed3877
AN		 2991 /*
2992 * In case of Host Controller v3.00, find out whether clock
2993 * multiplier is supported.
2994 */
2995 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2996 SDHCI_CLOCK_MUL_SHIFT;
2997
2998 /*
2999 * In case the value in Clock Multiplier is 0, then programmable
3000 * clock mode is not supported, otherwise the actual clock
3001 * multiplier is one more than the value of Clock Multiplier
3002 * in the Capabilities Register.
3003 */
3004 if (host->clk_mul)
3005 host->clk_mul += 1;
3006
d129bceb
PO		 3007 /*
3008 * Set host parameters.
3009 */
3010 mmc->ops = &sdhci_ops;
c3ed3877 3011 mmc->f_max = host->max_clk;
ce5f036b 3012 if (host->ops->get_min_clock)
a9e58f25 3013 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3014 else if (host->version >= SDHCI_SPEC_300) {
3015 if (host->clk_mul) {
3016 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3017 mmc->f_max = host->max_clk * host->clk_mul;
3018 } else
3019 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3020 } else
0397526d 3021 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3022
28aab053
AD		 3023 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3024 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3025 SDHCI_TIMEOUT_CLK_SHIFT;
3026 if (host->timeout_clk == 0) {
3027 if (host->ops->get_timeout_clock) {
3028 host->timeout_clk =
3029 host->ops->get_timeout_clock(host);
3030 } else {
3031 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3032 mmc_hostname(mmc));
3033 return -ENODEV;
3034 }
272308ca 3035 }
272308ca 3036
28aab053
AD		 3037 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3038 host->timeout_clk *= 1000;
272308ca 3039
28aab053 3040 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3041 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3042 mmc->max_busy_timeout /= host->timeout_clk;
3043 }
58d1246d 3044
f5fa92e5
AH		 3045 if (override_timeout_clk)
3046 host->timeout_clk = override_timeout_clk;
3047
e89d456f 3048 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3049 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3050
3051 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3052 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3053
8edf6371 3054 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3055 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3056 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 3057 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 3058 host->flags |= SDHCI_AUTO_CMD23;
3059 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3060 } else {
3061 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3062 }
3063
15ec4461
PR		 3064 /*
3065 * A controller may support 8-bit width, but the board itself
3066 * might not have the pins brought out. Boards that support
3067 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3068 * their platform code before calling sdhci_add_host(), and we
3069 * won't assume 8-bit width for hosts without that CAP.
3070 */
5fe23c7f 3071 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3072 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3073
63ef5d8c
JH		 3074 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3075 mmc->caps &= ~MMC_CAP_CMD23;
3076
f2119df6 3077 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3078 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3079
176d1ed4 3080 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4e743f1f 3081 !(mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 3082 mmc->caps |= MMC_CAP_NEEDS_POLL;
3083
3a48edc4
TK		 3084 /* If there are external regulators, get them */
3085 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3086 return -EPROBE_DEFER;
3087
6231f3de 3088 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3089 if (!IS_ERR(mmc->supply.vqmmc)) {
3090 ret = regulator_enable(mmc->supply.vqmmc);
3091 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3092 1950000))
8363c374
KL		 3093 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3094 SDHCI_SUPPORT_SDR50 |
3095 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3096 if (ret) {
3097 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3098 mmc_hostname(mmc), ret);
4bb74313 3099 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3100 }
8363c374 3101 }
6231f3de 3102
6a66180a
DD		 3103 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3104 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3105 SDHCI_SUPPORT_DDR50);
3106
4188bba0
AC		 3107 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3108 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3109 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3110 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3111
3112 /* SDR104 supports also implies SDR50 support */
156e14b1 3113 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3114 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3115 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3116 * field can be promoted to support HS200.
3117 */
549c0b18 3118 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3119 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3120 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3121 mmc->caps |= MMC_CAP_UHS_SDR50;
3122
549c0b18
AH		 3123 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3124 (IS_ERR(mmc->supply.vqmmc) ||
3125 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3126 1300000)))
3127 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3128
9107ebbf
MC		 3129 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3130 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3131 mmc->caps |= MMC_CAP_UHS_DDR50;
3132
069c9f14 3133 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3134 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3135 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3136
156e14b1 3137 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3138 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3139 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3140
d6d50a15
AN		 3141 /* Driver Type(s) (A, C, D) supported by the host */
3142 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3143 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3144 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3145 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3146 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3147 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3148
cf2b5eea
AN		 3149 /* Initial value for re-tuning timer count */
3150 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3151 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3152
3153 /*
3154 * In case Re-tuning Timer is not disabled, the actual value of
3155 * re-tuning timer will be 2 ^ (n - 1).
3156 */
3157 if (host->tuning_count)
3158 host->tuning_count = 1 << (host->tuning_count - 1);
3159
3160 /* Re-tuning mode supported by the Host Controller */
3161 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3162 SDHCI_RETUNING_MODE_SHIFT;
3163
8f230f45 3164 ocr_avail = 0;
bad37e1a 3165
f2119df6
AN		 3166 /*
3167 * According to SD Host Controller spec v3.00, if the Host System
3168 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3169 * the value is meaningful only if Voltage Support in the Capabilities
3170 * register is set. The actual current value is 4 times the register
3171 * value.
3172 */
3173 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3174 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3175 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3176 if (curr > 0) {
3177
3178 /* convert to SDHCI_MAX_CURRENT format */
3179 curr = curr/1000; /* convert to mA */
3180 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3181
3182 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3183 max_current_caps =
3184 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3185 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3186 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3187 }
3188 }
f2119df6
AN		 3189
3190 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3191 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3192
55c4665e 3193 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3194 SDHCI_MAX_CURRENT_330_MASK) >>
3195 SDHCI_MAX_CURRENT_330_SHIFT) *
3196 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3197 }
3198 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3199 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3200
55c4665e 3201 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3202 SDHCI_MAX_CURRENT_300_MASK) >>
3203 SDHCI_MAX_CURRENT_300_SHIFT) *
3204 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3205 }
3206 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3207 ocr_avail |= MMC_VDD_165_195;
3208
55c4665e 3209 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3210 SDHCI_MAX_CURRENT_180_MASK) >>
3211 SDHCI_MAX_CURRENT_180_SHIFT) *
3212 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3213 }
3214
52221610 3215 /* If OCR set by external regulators, use it instead */
3a48edc4 3216 if (mmc->ocr_avail)
52221610 3217 ocr_avail = mmc->ocr_avail;
3a48edc4 3218
c0b887b6 3219 if (host->ocr_mask)
3a48edc4 3220 ocr_avail &= host->ocr_mask;
c0b887b6 3221
8f230f45
TI		 3222 mmc->ocr_avail = ocr_avail;
3223 mmc->ocr_avail_sdio = ocr_avail;
3224 if (host->ocr_avail_sdio)
3225 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3226 mmc->ocr_avail_sd = ocr_avail;
3227 if (host->ocr_avail_sd)
3228 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3229 else /* normal SD controllers don't support 1.8V */
3230 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3231 mmc->ocr_avail_mmc = ocr_avail;
3232 if (host->ocr_avail_mmc)
3233 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3234
3235 if (mmc->ocr_avail == 0) {
a3c76eb9 3236 pr_err("%s: Hardware doesn't report any "
b69c9058 3237 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3238 return -ENODEV;
146ad66e
PO		 3239 }
3240
d129bceb
PO		 3241 spin_lock_init(&host->lock);
3242
3243 /*
2134a922
PO		 3244 * Maximum number of segments. Depends on if the hardware
3245 * can do scatter/gather or not.
d129bceb 3246 */
2134a922 3247 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3248 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3249 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3250 mmc->max_segs = 1;
2134a922 3251 else /* PIO */
4fb213f8 3252 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3253
3254 /*
bab76961 3255 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3256 * size (512KiB).
d129bceb 3257 */
55db890a 3258 mmc->max_req_size = 524288;
d129bceb
PO		 3259
3260 /*
3261 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3262 * of bytes. When doing hardware scatter/gather, each entry cannot
3263 * be larger than 64 KiB though.
d129bceb 3264 */
30652aa3
OJ		 3265 if (host->flags & SDHCI_USE_ADMA) {
3266 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3267 mmc->max_seg_size = 65535;
3268 else
3269 mmc->max_seg_size = 65536;
3270 } else {
2134a922 3271 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3272 }
d129bceb 3273
fe4a3c7a
PO		 3274 /*
3275 * Maximum block size. This varies from controller to controller and
3276 * is specified in the capabilities register.
3277 */
0633f654
AV		 3278 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3279 mmc->max_blk_size = 2;
3280 } else {
f2119df6 3281 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3282 SDHCI_MAX_BLOCK_SHIFT;
3283 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3284 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3285 mmc_hostname(mmc));
0633f654
AV		 3286 mmc->max_blk_size = 0;
3287 }
3288 }
3289
3290 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3291
55db890a
PO		 3292 /*
3293 * Maximum block count.
3294 */
1388eefd 3295 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3296
d129bceb
PO		 3297 /*
3298 * Init tasklets.
3299 */
d129bceb
PO		 3300 tasklet_init(&host->finish_tasklet,
3301 sdhci_tasklet_finish, (unsigned long)host);
3302
e4cad1b5 3303 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3304
cf2b5eea 3305 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3306 init_waitqueue_head(&host->buf_ready_int);
3307
cf2b5eea
AN		 3308 /* Initialize re-tuning timer */
3309 init_timer(&host->tuning_timer);
3310 host->tuning_timer.data = (unsigned long)host;
3311 host->tuning_timer.function = sdhci_tuning_timer;
3312 }
3313
2af502ca
SG		 3314 sdhci_init(host, 0);
3315
781e989c
RK		 3316 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3317 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3318 if (ret) {
3319 pr_err("%s: Failed to request IRQ %d: %d\n",
3320 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3321 goto untasklet;
0fc81ee3 3322 }
d129bceb 3323
d129bceb
PO		 3324#ifdef CONFIG_MMC_DEBUG
3325 sdhci_dumpregs(host);
3326#endif
3327
f9134319 3328#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3329 snprintf(host->led_name, sizeof(host->led_name),
3330 "%s::", mmc_hostname(mmc));
3331 host->led.name = host->led_name;
2f730fec
PO		 3332 host->led.brightness = LED_OFF;
3333 host->led.default_trigger = mmc_hostname(mmc);
3334 host->led.brightness_set = sdhci_led_control;
3335
b8c86fc5 3336 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3337 if (ret) {
3338 pr_err("%s: Failed to register LED device: %d\n",
3339 mmc_hostname(mmc), ret);
2f730fec 3340 goto reset;
0fc81ee3 3341 }
2f730fec
PO		 3342#endif
3343
5f25a66f
PO		 3344 mmiowb();
3345
d129bceb
PO		 3346 mmc_add_host(mmc);
3347
a3c76eb9 3348 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3349 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3350 (host->flags & SDHCI_USE_ADMA) ?
3351 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3352 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3353
7260cf5e
AV		 3354 sdhci_enable_card_detection(host);
3355
d129bceb
PO		 3356 return 0;
3357
f9134319 3358#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3359reset:
03231f9b 3360 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3361 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3362 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3363 free_irq(host->irq, host);
3364#endif
8ef1a143 3365untasklet:
d129bceb 3366 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3367
3368 return ret;
3369}
3370
b8c86fc5 3371EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3372
1e72859e 3373void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3374{
3a48edc4 3375 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3376 unsigned long flags;
3377
3378 if (dead) {
3379 spin_lock_irqsave(&host->lock, flags);
3380
3381 host->flags |= SDHCI_DEVICE_DEAD;
3382
3383 if (host->mrq) {
a3c76eb9 3384 pr_err("%s: Controller removed during "
4e743f1f 3385 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3386
3387 host->mrq->cmd->error = -ENOMEDIUM;
3388 tasklet_schedule(&host->finish_tasklet);
3389 }
3390
3391 spin_unlock_irqrestore(&host->lock, flags);
3392 }
3393
7260cf5e
AV		 3394 sdhci_disable_card_detection(host);
3395
4e743f1f 3396 mmc_remove_host(mmc);
d129bceb 3397
f9134319 3398#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3399 led_classdev_unregister(&host->led);
3400#endif
3401
1e72859e 3402 if (!dead)
03231f9b 3403 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3404
b537f94c
RK		 3405 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3406 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3407 free_irq(host->irq, host);
3408
3409 del_timer_sync(&host->timer);
3410
d129bceb 3411 tasklet_kill(&host->finish_tasklet);
2134a922 3412
3a48edc4
TK		 3413 if (!IS_ERR(mmc->supply.vqmmc))
3414 regulator_disable(mmc->supply.vqmmc);
6231f3de 3415
4efaa6fb 3416 if (host->adma_table)
76fe379a 3417 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3418 host->adma_table, host->adma_addr);
2134a922
PO		 3419 kfree(host->align_buffer);
3420
4efaa6fb 3421 host->adma_table = NULL;
2134a922 3422 host->align_buffer = NULL;
d129bceb
PO		 3423}
3424
b8c86fc5 3425EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3426
b8c86fc5 3427void sdhci_free_host(struct sdhci_host *host)
d129bceb 3428{
b8c86fc5 3429 mmc_free_host(host->mmc);
d129bceb
PO		 3430}
3431
b8c86fc5 3432EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3433
3434/*****************************************************************************\
3435 * *
3436 * Driver init/exit *
3437 * *
3438\*****************************************************************************/
3439
3440static int __init sdhci_drv_init(void)
3441{
a3c76eb9 3442 pr_info(DRIVER_NAME
52fbf9c9 3443 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3444 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3445
b8c86fc5 3446 return 0;
d129bceb
PO		 3447}
3448
3449static void __exit sdhci_drv_exit(void)
3450{
d129bceb
PO		 3451}
3452
3453module_init(sdhci_drv_init);
3454module_exit(sdhci_drv_exit);
3455
df673b22 3456module_param(debug_quirks, uint, 0444);
66fd8ad5 3457module_param(debug_quirks2, uint, 0444);
67435274 3458
32710e8f 3459MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3460MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3461MODULE_LICENSE("GPL");
67435274 3462
df673b22 3463MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3464MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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