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mmc: add bus handler
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb
PO		 1/*
2 * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
3 *
14d836e7 4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
d129bceb
PO		 10 */
11
d129bceb
PO		 12#include <linux/delay.h>
13#include <linux/highmem.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16
17#include <linux/mmc/host.h>
d129bceb
PO		 18
19#include <asm/scatterlist.h>
20
21#include "sdhci.h"
22
23#define DRIVER_NAME "sdhci"
d129bceb 24
d129bceb 25#define DBG(f, x...) \
c6563178 26 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 27
67435274
PO		 28static unsigned int debug_nodma = 0;
29static unsigned int debug_forcedma = 0;
df673b22 30static unsigned int debug_quirks = 0;
67435274 31
645289dc 32#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
98608076 33#define SDHCI_QUIRK_FORCE_DMA (1<<1)
8a4da143
PO		 34/* Controller doesn't like some resets when there is no card inserted. */
35#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
9e9dc5f2 36#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
645289dc 37
d129bceb 38static const struct pci_device_id pci_ids[] __devinitdata = {
645289dc
PO		 39 {
40 .vendor = PCI_VENDOR_ID_RICOH,
41 .device = PCI_DEVICE_ID_RICOH_R5C822,
42 .subvendor = PCI_VENDOR_ID_IBM,
43 .subdevice = PCI_ANY_ID,
98608076
PO		 44 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
45 SDHCI_QUIRK_FORCE_DMA,
46 },
47
48 {
49 .vendor = PCI_VENDOR_ID_RICOH,
50 .device = PCI_DEVICE_ID_RICOH_R5C822,
51 .subvendor = PCI_ANY_ID,
52 .subdevice = PCI_ANY_ID,
8a4da143
PO		 53 .driver_data = SDHCI_QUIRK_FORCE_DMA |
54 SDHCI_QUIRK_NO_CARD_NO_RESET,
98608076
PO		 55 },
56
57 {
58 .vendor = PCI_VENDOR_ID_TI,
59 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
60 .subvendor = PCI_ANY_ID,
61 .subdevice = PCI_ANY_ID,
62 .driver_data = SDHCI_QUIRK_FORCE_DMA,
645289dc
PO		 63 },
64
9e9dc5f2
DS		 65 {
66 .vendor = PCI_VENDOR_ID_ENE,
67 .device = PCI_DEVICE_ID_ENE_CB712_SD,
68 .subvendor = PCI_ANY_ID,
69 .subdevice = PCI_ANY_ID,
70 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
71 },
72
645289dc
PO		 73 { /* Generic SD host controller */
74 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
75 },
76
d129bceb
PO		 77 { /* end: all zeroes */ },
78};
79
80MODULE_DEVICE_TABLE(pci, pci_ids);
81
82static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
83static void sdhci_finish_data(struct sdhci_host *);
84
85static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
86static void sdhci_finish_command(struct sdhci_host *);
87
88static void sdhci_dumpregs(struct sdhci_host *host)
89{
90 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
91
92 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
93 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
94 readw(host->ioaddr + SDHCI_HOST_VERSION));
95 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
96 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
97 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
98 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
99 readl(host->ioaddr + SDHCI_ARGUMENT),
100 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
101 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
102 readl(host->ioaddr + SDHCI_PRESENT_STATE),
103 readb(host->ioaddr + SDHCI_HOST_CONTROL));
104 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
105 readb(host->ioaddr + SDHCI_POWER_CONTROL),
106 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
107 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
108 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
109 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
110 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
111 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
112 readl(host->ioaddr + SDHCI_INT_STATUS));
113 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
114 readl(host->ioaddr + SDHCI_INT_ENABLE),
115 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
116 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
117 readw(host->ioaddr + SDHCI_ACMD12_ERR),
118 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
119 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
120 readl(host->ioaddr + SDHCI_CAPABILITIES),
121 readl(host->ioaddr + SDHCI_MAX_CURRENT));
122
123 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
124}
125
126/*****************************************************************************\
127 * *
128 * Low level functions *
129 * *
130\*****************************************************************************/
131
132static void sdhci_reset(struct sdhci_host *host, u8 mask)
133{
e16514d8
PO		 134 unsigned long timeout;
135
8a4da143
PO		 136 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
137 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
138 SDHCI_CARD_PRESENT))
139 return;
140 }
141
d129bceb
PO		 142 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
143
e16514d8 144 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 145 host->clock = 0;
146
e16514d8
PO		 147 /* Wait max 100 ms */
148 timeout = 100;
149
150 /* hw clears the bit when it's done */
151 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
152 if (timeout == 0) {
acf1da45 153 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 154 mmc_hostname(host->mmc), (int)mask);
155 sdhci_dumpregs(host);
156 return;
157 }
158 timeout--;
159 mdelay(1);
d129bceb
PO		 160 }
161}
162
163static void sdhci_init(struct sdhci_host *host)
164{
165 u32 intmask;
166
167 sdhci_reset(host, SDHCI_RESET_ALL);
168
3192a28f
PO		 169 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
170 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
171 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
172 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 173 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
3192a28f 174 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
d129bceb
PO		 175
176 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
177 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 178}
179
180static void sdhci_activate_led(struct sdhci_host *host)
181{
182 u8 ctrl;
183
184 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
185 ctrl |= SDHCI_CTRL_LED;
186 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
187}
188
189static void sdhci_deactivate_led(struct sdhci_host *host)
190{
191 u8 ctrl;
192
193 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
194 ctrl &= ~SDHCI_CTRL_LED;
195 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
196}
197
198/*****************************************************************************\
199 * *
200 * Core functions *
201 * *
202\*****************************************************************************/
203
2a22b14e 204static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
d129bceb 205{
2a22b14e 206 return page_address(host->cur_sg->page) + host->cur_sg->offset;
d129bceb
PO		 207}
208
209static inline int sdhci_next_sg(struct sdhci_host* host)
210{
211 /*
212 * Skip to next SG entry.
213 */
214 host->cur_sg++;
215 host->num_sg--;
216
217 /*
218 * Any entries left?
219 */
220 if (host->num_sg > 0) {
221 host->offset = 0;
222 host->remain = host->cur_sg->length;
223 }
224
225 return host->num_sg;
226}
227
a406f5a3 228static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 229{
a406f5a3
PO		 230 int blksize, chunk_remain;
231 u32 data;
d129bceb 232 char *buffer;
a406f5a3 233 int size;
d129bceb 234
a406f5a3 235 DBG("PIO reading\n");
d129bceb 236
a406f5a3
PO		 237 blksize = host->data->blksz;
238 chunk_remain = 0;
239 data = 0;
d129bceb 240
2a22b14e 241 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 242
a406f5a3
PO		 243 while (blksize) {
244 if (chunk_remain == 0) {
245 data = readl(host->ioaddr + SDHCI_BUFFER);
246 chunk_remain = min(blksize, 4);
247 }
d129bceb 248
14d836e7 249 size = min(host->remain, chunk_remain);
d129bceb 250
a406f5a3
PO		 251 chunk_remain -= size;
252 blksize -= size;
253 host->offset += size;
254 host->remain -= size;
14d836e7 255
a406f5a3
PO		 256 while (size) {
257 *buffer = data & 0xFF;
258 buffer++;
259 data >>= 8;
260 size--;
261 }
d129bceb 262
a406f5a3 263 if (host->remain == 0) {
a406f5a3
PO		 264 if (sdhci_next_sg(host) == 0) {
265 BUG_ON(blksize != 0);
266 return;
267 }
2a22b14e 268 buffer = sdhci_sg_to_buffer(host);
d129bceb 269 }
a406f5a3 270 }
a406f5a3 271}
d129bceb 272
a406f5a3
PO		 273static void sdhci_write_block_pio(struct sdhci_host *host)
274{
275 int blksize, chunk_remain;
276 u32 data;
277 char *buffer;
278 int bytes, size;
d129bceb 279
a406f5a3
PO		 280 DBG("PIO writing\n");
281
282 blksize = host->data->blksz;
283 chunk_remain = 4;
284 data = 0;
d129bceb 285
a406f5a3 286 bytes = 0;
2a22b14e 287 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 288
a406f5a3 289 while (blksize) {
14d836e7 290 size = min(host->remain, chunk_remain);
a406f5a3
PO		 291
292 chunk_remain -= size;
293 blksize -= size;
d129bceb
PO		 294 host->offset += size;
295 host->remain -= size;
14d836e7 296
a406f5a3
PO		 297 while (size) {
298 data >>= 8;
299 data |= (u32)*buffer << 24;
300 buffer++;
301 size--;
302 }
303
304 if (chunk_remain == 0) {
305 writel(data, host->ioaddr + SDHCI_BUFFER);
306 chunk_remain = min(blksize, 4);
307 }
d129bceb
PO		 308
309 if (host->remain == 0) {
d129bceb 310 if (sdhci_next_sg(host) == 0) {
a406f5a3 311 BUG_ON(blksize != 0);
d129bceb
PO		 312 return;
313 }
2a22b14e 314 buffer = sdhci_sg_to_buffer(host);
d129bceb
PO		 315 }
316 }
a406f5a3
PO		 317}
318
319static void sdhci_transfer_pio(struct sdhci_host *host)
320{
321 u32 mask;
322
323 BUG_ON(!host->data);
324
14d836e7 325 if (host->num_sg == 0)
a406f5a3
PO		 326 return;
327
328 if (host->data->flags & MMC_DATA_READ)
329 mask = SDHCI_DATA_AVAILABLE;
330 else
331 mask = SDHCI_SPACE_AVAILABLE;
332
333 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
334 if (host->data->flags & MMC_DATA_READ)
335 sdhci_read_block_pio(host);
336 else
337 sdhci_write_block_pio(host);
d129bceb 338
14d836e7 339 if (host->num_sg == 0)
a406f5a3 340 break;
a406f5a3 341 }
d129bceb 342
a406f5a3 343 DBG("PIO transfer complete.\n");
d129bceb
PO		 344}
345
346static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
347{
1c8cde92
PO		 348 u8 count;
349 unsigned target_timeout, current_timeout;
d129bceb
PO		 350
351 WARN_ON(host->data);
352
c7fa9963 353 if (data == NULL)
d129bceb 354 return;
d129bceb
PO		 355
356 DBG("blksz %04x blks %04x flags %08x\n",
a3fd4a1b 357 data->blksz, data->blocks, data->flags);
d129bceb
PO		 358 DBG("tsac %d ms nsac %d clk\n",
359 data->timeout_ns / 1000000, data->timeout_clks);
360
bab76961
PO		 361 /* Sanity checks */
362 BUG_ON(data->blksz * data->blocks > 524288);
fe4a3c7a 363 BUG_ON(data->blksz > host->mmc->max_blk_size);
1d676e02 364 BUG_ON(data->blocks > 65535);
d129bceb 365
1c8cde92
PO		 366 /* timeout in us */
367 target_timeout = data->timeout_ns / 1000 +
368 data->timeout_clks / host->clock;
d129bceb 369
1c8cde92
PO		 370 /*
371 * Figure out needed cycles.
372 * We do this in steps in order to fit inside a 32 bit int.
373 * The first step is the minimum timeout, which will have a
374 * minimum resolution of 6 bits:
375 * (1) 2^13*1000 > 2^22,
376 * (2) host->timeout_clk < 2^16
377 * =>
378 * (1) / (2) > 2^6
379 */
380 count = 0;
381 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
382 while (current_timeout < target_timeout) {
383 count++;
384 current_timeout <<= 1;
385 if (count >= 0xF)
386 break;
387 }
388
389 if (count >= 0xF) {
390 printk(KERN_WARNING "%s: Too large timeout requested!\n",
391 mmc_hostname(host->mmc));
392 count = 0xE;
393 }
394
395 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb
PO		 396
397 if (host->flags & SDHCI_USE_DMA) {
398 int count;
399
400 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
401 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
402 BUG_ON(count != 1);
403
404 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
405 } else {
d129bceb
PO		 406 host->cur_sg = data->sg;
407 host->num_sg = data->sg_len;
408
409 host->offset = 0;
410 host->remain = host->cur_sg->length;
411 }
c7fa9963 412
bab76961
PO		 413 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
414 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
415 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 416 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
417}
418
419static void sdhci_set_transfer_mode(struct sdhci_host *host,
420 struct mmc_data *data)
421{
422 u16 mode;
423
424 WARN_ON(host->data);
425
426 if (data == NULL)
427 return;
428
429 mode = SDHCI_TRNS_BLK_CNT_EN;
430 if (data->blocks > 1)
431 mode |= SDHCI_TRNS_MULTI;
432 if (data->flags & MMC_DATA_READ)
433 mode |= SDHCI_TRNS_READ;
434 if (host->flags & SDHCI_USE_DMA)
435 mode |= SDHCI_TRNS_DMA;
436
437 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 438}
439
440static void sdhci_finish_data(struct sdhci_host *host)
441{
442 struct mmc_data *data;
d129bceb
PO		 443 u16 blocks;
444
445 BUG_ON(!host->data);
446
447 data = host->data;
448 host->data = NULL;
449
450 if (host->flags & SDHCI_USE_DMA) {
451 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
452 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
d129bceb
PO		 453 }
454
455 /*
456 * Controller doesn't count down when in single block mode.
457 */
458 if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
459 blocks = 0;
460 else
461 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
a3fd4a1b 462 data->bytes_xfered = data->blksz * (data->blocks - blocks);
d129bceb
PO		 463
464 if ((data->error == MMC_ERR_NONE) && blocks) {
465 printk(KERN_ERR "%s: Controller signalled completion even "
acf1da45
PO		 466 "though there were blocks left.\n",
467 mmc_hostname(host->mmc));
d129bceb 468 data->error = MMC_ERR_FAILED;
d129bceb
PO		 469 }
470
471 DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
472
473 if (data->stop) {
474 /*
475 * The controller needs a reset of internal state machines
476 * upon error conditions.
477 */
478 if (data->error != MMC_ERR_NONE) {
479 sdhci_reset(host, SDHCI_RESET_CMD);
480 sdhci_reset(host, SDHCI_RESET_DATA);
481 }
482
483 sdhci_send_command(host, data->stop);
484 } else
485 tasklet_schedule(&host->finish_tasklet);
486}
487
488static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
489{
490 int flags;
fd2208d7 491 u32 mask;
7cb2c76f 492 unsigned long timeout;
d129bceb
PO		 493
494 WARN_ON(host->cmd);
495
496 DBG("Sending cmd (%x)\n", cmd->opcode);
497
498 /* Wait max 10 ms */
7cb2c76f 499 timeout = 10;
fd2208d7
PO		 500
501 mask = SDHCI_CMD_INHIBIT;
502 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
503 mask |= SDHCI_DATA_INHIBIT;
504
505 /* We shouldn't wait for data inihibit for stop commands, even
506 though they might use busy signaling */
507 if (host->mrq->data && (cmd == host->mrq->data->stop))
508 mask &= ~SDHCI_DATA_INHIBIT;
509
510 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 511 if (timeout == 0) {
d129bceb 512 printk(KERN_ERR "%s: Controller never released "
acf1da45 513 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb
PO		 514 sdhci_dumpregs(host);
515 cmd->error = MMC_ERR_FAILED;
516 tasklet_schedule(&host->finish_tasklet);
517 return;
518 }
7cb2c76f
PO		 519 timeout--;
520 mdelay(1);
521 }
d129bceb
PO		 522
523 mod_timer(&host->timer, jiffies + 10 * HZ);
524
525 host->cmd = cmd;
526
527 sdhci_prepare_data(host, cmd->data);
528
529 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
530
c7fa9963
PO		 531 sdhci_set_transfer_mode(host, cmd->data);
532
d129bceb 533 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 534 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb
PO		 535 mmc_hostname(host->mmc));
536 cmd->error = MMC_ERR_INVALID;
537 tasklet_schedule(&host->finish_tasklet);
538 return;
539 }
540
541 if (!(cmd->flags & MMC_RSP_PRESENT))
542 flags = SDHCI_CMD_RESP_NONE;
543 else if (cmd->flags & MMC_RSP_136)
544 flags = SDHCI_CMD_RESP_LONG;
545 else if (cmd->flags & MMC_RSP_BUSY)
546 flags = SDHCI_CMD_RESP_SHORT_BUSY;
547 else
548 flags = SDHCI_CMD_RESP_SHORT;
549
550 if (cmd->flags & MMC_RSP_CRC)
551 flags |= SDHCI_CMD_CRC;
552 if (cmd->flags & MMC_RSP_OPCODE)
553 flags |= SDHCI_CMD_INDEX;
554 if (cmd->data)
555 flags |= SDHCI_CMD_DATA;
556
fb61e289 557 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 558 host->ioaddr + SDHCI_COMMAND);
559}
560
561static void sdhci_finish_command(struct sdhci_host *host)
562{
563 int i;
564
565 BUG_ON(host->cmd == NULL);
566
567 if (host->cmd->flags & MMC_RSP_PRESENT) {
568 if (host->cmd->flags & MMC_RSP_136) {
569 /* CRC is stripped so we need to do some shifting. */
570 for (i = 0;i < 4;i++) {
571 host->cmd->resp[i] = readl(host->ioaddr +
572 SDHCI_RESPONSE + (3-i)*4) << 8;
573 if (i != 3)
574 host->cmd->resp[i] |=
575 readb(host->ioaddr +
576 SDHCI_RESPONSE + (3-i)*4-1);
577 }
578 } else {
579 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
580 }
581 }
582
583 host->cmd->error = MMC_ERR_NONE;
584
585 DBG("Ending cmd (%x)\n", host->cmd->opcode);
586
3192a28f 587 if (host->cmd->data)
d129bceb 588 host->data = host->cmd->data;
3192a28f 589 else
d129bceb
PO		 590 tasklet_schedule(&host->finish_tasklet);
591
592 host->cmd = NULL;
593}
594
595static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
596{
597 int div;
598 u16 clk;
7cb2c76f 599 unsigned long timeout;
d129bceb
PO		 600
601 if (clock == host->clock)
602 return;
603
604 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
605
606 if (clock == 0)
607 goto out;
608
609 for (div = 1;div < 256;div *= 2) {
610 if ((host->max_clk / div) <= clock)
611 break;
612 }
613 div >>= 1;
614
615 clk = div << SDHCI_DIVIDER_SHIFT;
616 clk |= SDHCI_CLOCK_INT_EN;
617 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
618
619 /* Wait max 10 ms */
7cb2c76f
PO		 620 timeout = 10;
621 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
622 & SDHCI_CLOCK_INT_STABLE)) {
623 if (timeout == 0) {
acf1da45
PO		 624 printk(KERN_ERR "%s: Internal clock never "
625 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 626 sdhci_dumpregs(host);
627 return;
628 }
7cb2c76f
PO		 629 timeout--;
630 mdelay(1);
631 }
d129bceb
PO		 632
633 clk |= SDHCI_CLOCK_CARD_EN;
634 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
635
636out:
637 host->clock = clock;
638}
639
146ad66e
PO		 640static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
641{
642 u8 pwr;
643
644 if (host->power == power)
645 return;
646
9e9dc5f2
DS		 647 if (power == (unsigned short)-1) {
648 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e 649 goto out;
9e9dc5f2
DS		 650 }
651
652 /*
653 * Spec says that we should clear the power reg before setting
654 * a new value. Some controllers don't seem to like this though.
655 */
656 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
657 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e
PO		 658
659 pwr = SDHCI_POWER_ON;
660
661 switch (power) {
662 case MMC_VDD_170:
663 case MMC_VDD_180:
664 case MMC_VDD_190:
665 pwr |= SDHCI_POWER_180;
666 break;
667 case MMC_VDD_290:
668 case MMC_VDD_300:
669 case MMC_VDD_310:
670 pwr |= SDHCI_POWER_300;
671 break;
672 case MMC_VDD_320:
673 case MMC_VDD_330:
674 case MMC_VDD_340:
675 pwr |= SDHCI_POWER_330;
676 break;
677 default:
678 BUG();
679 }
680
681 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
682
683out:
684 host->power = power;
685}
686
d129bceb
PO		 687/*****************************************************************************\
688 * *
689 * MMC callbacks *
690 * *
691\*****************************************************************************/
692
693static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
694{
695 struct sdhci_host *host;
696 unsigned long flags;
697
698 host = mmc_priv(mmc);
699
700 spin_lock_irqsave(&host->lock, flags);
701
702 WARN_ON(host->mrq != NULL);
703
704 sdhci_activate_led(host);
705
706 host->mrq = mrq;
707
708 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
709 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
710 tasklet_schedule(&host->finish_tasklet);
711 } else
712 sdhci_send_command(host, mrq->cmd);
713
5f25a66f 714 mmiowb();
d129bceb
PO		 715 spin_unlock_irqrestore(&host->lock, flags);
716}
717
718static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
719{
720 struct sdhci_host *host;
721 unsigned long flags;
722 u8 ctrl;
723
724 host = mmc_priv(mmc);
725
726 spin_lock_irqsave(&host->lock, flags);
727
d129bceb
PO		 728 /*
729 * Reset the chip on each power off.
730 * Should clear out any weird states.
731 */
732 if (ios->power_mode == MMC_POWER_OFF) {
733 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 734 sdhci_init(host);
d129bceb
PO		 735 }
736
737 sdhci_set_clock(host, ios->clock);
738
739 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 740 sdhci_set_power(host, -1);
d129bceb 741 else
146ad66e 742 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 743
744 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
cd9277c0 745
d129bceb
PO		 746 if (ios->bus_width == MMC_BUS_WIDTH_4)
747 ctrl |= SDHCI_CTRL_4BITBUS;
748 else
749 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 750
751 if (ios->timing == MMC_TIMING_SD_HS)
752 ctrl |= SDHCI_CTRL_HISPD;
753 else
754 ctrl &= ~SDHCI_CTRL_HISPD;
755
d129bceb
PO		 756 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
757
5f25a66f 758 mmiowb();
d129bceb
PO		 759 spin_unlock_irqrestore(&host->lock, flags);
760}
761
762static int sdhci_get_ro(struct mmc_host *mmc)
763{
764 struct sdhci_host *host;
765 unsigned long flags;
766 int present;
767
768 host = mmc_priv(mmc);
769
770 spin_lock_irqsave(&host->lock, flags);
771
772 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
773
774 spin_unlock_irqrestore(&host->lock, flags);
775
776 return !(present & SDHCI_WRITE_PROTECT);
777}
778
ab7aefd0 779static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 780 .request = sdhci_request,
781 .set_ios = sdhci_set_ios,
782 .get_ro = sdhci_get_ro,
783};
784
785/*****************************************************************************\
786 * *
787 * Tasklets *
788 * *
789\*****************************************************************************/
790
791static void sdhci_tasklet_card(unsigned long param)
792{
793 struct sdhci_host *host;
794 unsigned long flags;
795
796 host = (struct sdhci_host*)param;
797
798 spin_lock_irqsave(&host->lock, flags);
799
800 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
801 if (host->mrq) {
802 printk(KERN_ERR "%s: Card removed during transfer!\n",
803 mmc_hostname(host->mmc));
804 printk(KERN_ERR "%s: Resetting controller.\n",
805 mmc_hostname(host->mmc));
806
807 sdhci_reset(host, SDHCI_RESET_CMD);
808 sdhci_reset(host, SDHCI_RESET_DATA);
809
810 host->mrq->cmd->error = MMC_ERR_FAILED;
811 tasklet_schedule(&host->finish_tasklet);
812 }
813 }
814
815 spin_unlock_irqrestore(&host->lock, flags);
816
817 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
818}
819
820static void sdhci_tasklet_finish(unsigned long param)
821{
822 struct sdhci_host *host;
823 unsigned long flags;
824 struct mmc_request *mrq;
825
826 host = (struct sdhci_host*)param;
827
828 spin_lock_irqsave(&host->lock, flags);
829
830 del_timer(&host->timer);
831
832 mrq = host->mrq;
833
834 DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
835
836 /*
837 * The controller needs a reset of internal state machines
838 * upon error conditions.
839 */
840 if ((mrq->cmd->error != MMC_ERR_NONE) ||
841 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
842 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
645289dc
PO		 843
844 /* Some controllers need this kick or reset won't work here */
845 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
846 unsigned int clock;
847
848 /* This is to force an update */
849 clock = host->clock;
850 host->clock = 0;
851 sdhci_set_clock(host, clock);
852 }
853
854 /* Spec says we should do both at the same time, but Ricoh
855 controllers do not like that. */
d129bceb
PO		 856 sdhci_reset(host, SDHCI_RESET_CMD);
857 sdhci_reset(host, SDHCI_RESET_DATA);
858 }
859
860 host->mrq = NULL;
861 host->cmd = NULL;
862 host->data = NULL;
863
864 sdhci_deactivate_led(host);
865
5f25a66f 866 mmiowb();
d129bceb
PO		 867 spin_unlock_irqrestore(&host->lock, flags);
868
869 mmc_request_done(host->mmc, mrq);
870}
871
872static void sdhci_timeout_timer(unsigned long data)
873{
874 struct sdhci_host *host;
875 unsigned long flags;
876
877 host = (struct sdhci_host*)data;
878
879 spin_lock_irqsave(&host->lock, flags);
880
881 if (host->mrq) {
acf1da45
PO		 882 printk(KERN_ERR "%s: Timeout waiting for hardware "
883 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 884 sdhci_dumpregs(host);
885
886 if (host->data) {
887 host->data->error = MMC_ERR_TIMEOUT;
888 sdhci_finish_data(host);
889 } else {
890 if (host->cmd)
891 host->cmd->error = MMC_ERR_TIMEOUT;
892 else
893 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
894
895 tasklet_schedule(&host->finish_tasklet);
896 }
897 }
898
5f25a66f 899 mmiowb();
d129bceb
PO		 900 spin_unlock_irqrestore(&host->lock, flags);
901}
902
903/*****************************************************************************\
904 * *
905 * Interrupt handling *
906 * *
907\*****************************************************************************/
908
909static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
910{
911 BUG_ON(intmask == 0);
912
913 if (!host->cmd) {
914 printk(KERN_ERR "%s: Got command interrupt even though no "
915 "command operation was in progress.\n",
916 mmc_hostname(host->mmc));
d129bceb
PO		 917 sdhci_dumpregs(host);
918 return;
919 }
920
921 if (intmask & SDHCI_INT_RESPONSE)
922 sdhci_finish_command(host);
923 else {
924 if (intmask & SDHCI_INT_TIMEOUT)
925 host->cmd->error = MMC_ERR_TIMEOUT;
926 else if (intmask & SDHCI_INT_CRC)
927 host->cmd->error = MMC_ERR_BADCRC;
928 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
929 host->cmd->error = MMC_ERR_FAILED;
930 else
931 host->cmd->error = MMC_ERR_INVALID;
932
933 tasklet_schedule(&host->finish_tasklet);
934 }
935}
936
937static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
938{
939 BUG_ON(intmask == 0);
940
941 if (!host->data) {
942 /*
943 * A data end interrupt is sent together with the response
944 * for the stop command.
945 */
946 if (intmask & SDHCI_INT_DATA_END)
947 return;
948
949 printk(KERN_ERR "%s: Got data interrupt even though no "
950 "data operation was in progress.\n",
951 mmc_hostname(host->mmc));
d129bceb
PO		 952 sdhci_dumpregs(host);
953
954 return;
955 }
956
957 if (intmask & SDHCI_INT_DATA_TIMEOUT)
958 host->data->error = MMC_ERR_TIMEOUT;
959 else if (intmask & SDHCI_INT_DATA_CRC)
960 host->data->error = MMC_ERR_BADCRC;
961 else if (intmask & SDHCI_INT_DATA_END_BIT)
962 host->data->error = MMC_ERR_FAILED;
963
964 if (host->data->error != MMC_ERR_NONE)
965 sdhci_finish_data(host);
966 else {
a406f5a3 967 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 968 sdhci_transfer_pio(host);
969
970 if (intmask & SDHCI_INT_DATA_END)
971 sdhci_finish_data(host);
972 }
973}
974
7d12e780 975static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 976{
977 irqreturn_t result;
978 struct sdhci_host* host = dev_id;
979 u32 intmask;
980
981 spin_lock(&host->lock);
982
983 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
984
62df67a5 985 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 986 result = IRQ_NONE;
987 goto out;
988 }
989
990 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
991
3192a28f
PO		 992 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
993 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
994 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 995 tasklet_schedule(&host->card_tasklet);
3192a28f 996 }
d129bceb 997
3192a28f 998 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 999
3192a28f 1000 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1001 writel(intmask & SDHCI_INT_CMD_MASK,
1002 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1003 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1004 }
1005
1006 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1007 writel(intmask & SDHCI_INT_DATA_MASK,
1008 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1009 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1010 }
1011
1012 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1013
d129bceb 1014 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1015 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1016 mmc_hostname(host->mmc));
3192a28f 1017 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1018 }
1019
3192a28f
PO		 1020 intmask &= SDHCI_INT_BUS_POWER;
1021
1022 if (intmask) {
acf1da45 1023 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1024 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1025 sdhci_dumpregs(host);
1026
d129bceb 1027 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1028 }
d129bceb
PO		 1029
1030 result = IRQ_HANDLED;
1031
5f25a66f 1032 mmiowb();
d129bceb
PO		 1033out:
1034 spin_unlock(&host->lock);
1035
1036 return result;
1037}
1038
1039/*****************************************************************************\
1040 * *
1041 * Suspend/resume *
1042 * *
1043\*****************************************************************************/
1044
1045#ifdef CONFIG_PM
1046
1047static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1048{
1049 struct sdhci_chip *chip;
1050 int i, ret;
1051
1052 chip = pci_get_drvdata(pdev);
1053 if (!chip)
1054 return 0;
1055
1056 DBG("Suspending...\n");
1057
1058 for (i = 0;i < chip->num_slots;i++) {
1059 if (!chip->hosts[i])
1060 continue;
1061 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1062 if (ret) {
1063 for (i--;i >= 0;i--)
1064 mmc_resume_host(chip->hosts[i]->mmc);
1065 return ret;
1066 }
1067 }
1068
1069 pci_save_state(pdev);
1070 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
a715dfc7
PO		 1071
1072 for (i = 0;i < chip->num_slots;i++) {
1073 if (!chip->hosts[i])
1074 continue;
1075 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1076 }
1077
d129bceb
PO		 1078 pci_disable_device(pdev);
1079 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1080
1081 return 0;
1082}
1083
1084static int sdhci_resume (struct pci_dev *pdev)
1085{
1086 struct sdhci_chip *chip;
1087 int i, ret;
1088
1089 chip = pci_get_drvdata(pdev);
1090 if (!chip)
1091 return 0;
1092
1093 DBG("Resuming...\n");
1094
1095 pci_set_power_state(pdev, PCI_D0);
1096 pci_restore_state(pdev);
df1c4b7b
PO		 1097 ret = pci_enable_device(pdev);
1098 if (ret)
1099 return ret;
d129bceb
PO		 1100
1101 for (i = 0;i < chip->num_slots;i++) {
1102 if (!chip->hosts[i])
1103 continue;
1104 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1105 pci_set_master(pdev);
a715dfc7
PO		 1106 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1107 IRQF_SHARED, chip->hosts[i]->slot_descr,
1108 chip->hosts[i]);
1109 if (ret)
1110 return ret;
d129bceb 1111 sdhci_init(chip->hosts[i]);
5f25a66f 1112 mmiowb();
d129bceb
PO		 1113 ret = mmc_resume_host(chip->hosts[i]->mmc);
1114 if (ret)
1115 return ret;
1116 }
1117
1118 return 0;
1119}
1120
1121#else /* CONFIG_PM */
1122
1123#define sdhci_suspend NULL
1124#define sdhci_resume NULL
1125
1126#endif /* CONFIG_PM */
1127
1128/*****************************************************************************\
1129 * *
1130 * Device probing/removal *
1131 * *
1132\*****************************************************************************/
1133
1134static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1135{
1136 int ret;
4a965505 1137 unsigned int version;
d129bceb
PO		 1138 struct sdhci_chip *chip;
1139 struct mmc_host *mmc;
1140 struct sdhci_host *host;
1141
1142 u8 first_bar;
1143 unsigned int caps;
1144
1145 chip = pci_get_drvdata(pdev);
1146 BUG_ON(!chip);
1147
1148 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1149 if (ret)
1150 return ret;
1151
1152 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1153
1154 if (first_bar > 5) {
1155 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1156 return -ENODEV;
1157 }
1158
1159 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1160 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1161 return -ENODEV;
1162 }
1163
1164 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
a98087cf
PO		 1165 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1166 "You may experience problems.\n");
d129bceb
PO		 1167 }
1168
67435274
PO		 1169 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1170 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1171 return -ENODEV;
1172 }
1173
1174 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1175 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1176 return -ENODEV;
1177 }
1178
d129bceb
PO		 1179 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1180 if (!mmc)
1181 return -ENOMEM;
1182
1183 host = mmc_priv(mmc);
1184 host->mmc = mmc;
1185
8a4da143
PO		 1186 host->chip = chip;
1187 chip->hosts[slot] = host;
1188
d129bceb
PO		 1189 host->bar = first_bar + slot;
1190
1191 host->addr = pci_resource_start(pdev, host->bar);
1192 host->irq = pdev->irq;
1193
1194 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1195
1196 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1197
1198 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1199 if (ret)
1200 goto free;
1201
1202 host->ioaddr = ioremap_nocache(host->addr,
1203 pci_resource_len(pdev, host->bar));
1204 if (!host->ioaddr) {
1205 ret = -ENOMEM;
1206 goto release;
1207 }
1208
d96649ed
PO		 1209 sdhci_reset(host, SDHCI_RESET_ALL);
1210
4a965505
PO		 1211 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1212 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1213 if (version != 0) {
1214 printk(KERN_ERR "%s: Unknown controller version (%d). "
8b1b2185 1215 "You may experience problems.\n", host->slot_descr,
4a965505 1216 version);
4a965505
PO		 1217 }
1218
d129bceb
PO		 1219 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1220
67435274
PO		 1221 if (debug_nodma)
1222 DBG("DMA forced off\n");
1223 else if (debug_forcedma) {
1224 DBG("DMA forced on\n");
1225 host->flags |= SDHCI_USE_DMA;
98608076
PO		 1226 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1227 host->flags |= SDHCI_USE_DMA;
1228 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
67435274
PO		 1229 DBG("Controller doesn't have DMA interface\n");
1230 else if (!(caps & SDHCI_CAN_DO_DMA))
1231 DBG("Controller doesn't have DMA capability\n");
1232 else
d129bceb
PO		 1233 host->flags |= SDHCI_USE_DMA;
1234
1235 if (host->flags & SDHCI_USE_DMA) {
1236 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1237 printk(KERN_WARNING "%s: No suitable DMA available. "
1238 "Falling back to PIO.\n", host->slot_descr);
1239 host->flags &= ~SDHCI_USE_DMA;
1240 }
1241 }
1242
1243 if (host->flags & SDHCI_USE_DMA)
1244 pci_set_master(pdev);
1245 else /* XXX: Hack to get MMC layer to avoid highmem */
1246 pdev->dma_mask = 0;
1247
8ef1a143
PO		 1248 host->max_clk =
1249 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1250 if (host->max_clk == 0) {
1251 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1252 "frequency.\n", host->slot_descr);
1253 ret = -ENODEV;
1254 goto unmap;
1255 }
d129bceb
PO		 1256 host->max_clk *= 1000000;
1257
1c8cde92
PO		 1258 host->timeout_clk =
1259 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1260 if (host->timeout_clk == 0) {
1261 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1262 "frequency.\n", host->slot_descr);
1263 ret = -ENODEV;
1264 goto unmap;
1265 }
1266 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1267 host->timeout_clk *= 1000;
d129bceb
PO		 1268
1269 /*
1270 * Set host parameters.
1271 */
1272 mmc->ops = &sdhci_ops;
1273 mmc->f_min = host->max_clk / 256;
1274 mmc->f_max = host->max_clk;
42431acb 1275 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
d129bceb 1276
cd9277c0
PO		 1277 if (caps & SDHCI_CAN_DO_HISPD)
1278 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1279
146ad66e
PO		 1280 mmc->ocr_avail = 0;
1281 if (caps & SDHCI_CAN_VDD_330)
1282 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1283 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1284 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1285 if (caps & SDHCI_CAN_VDD_180)
146ad66e
PO		 1286 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
1287
1288 if (mmc->ocr_avail == 0) {
1289 printk(KERN_ERR "%s: Hardware doesn't report any "
1290 "support voltages.\n", host->slot_descr);
1291 ret = -ENODEV;
1292 goto unmap;
1293 }
1294
d129bceb
PO		 1295 spin_lock_init(&host->lock);
1296
1297 /*
1298 * Maximum number of segments. Hardware cannot do scatter lists.
1299 */
1300 if (host->flags & SDHCI_USE_DMA)
1301 mmc->max_hw_segs = 1;
1302 else
1303 mmc->max_hw_segs = 16;
1304 mmc->max_phys_segs = 16;
1305
1306 /*
bab76961 1307 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1308 * size (512KiB).
d129bceb 1309 */
55db890a 1310 mmc->max_req_size = 524288;
d129bceb
PO		 1311
1312 /*
1313 * Maximum segment size. Could be one segment with the maximum number
55db890a 1314 * of bytes.
d129bceb 1315 */
55db890a 1316 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1317
fe4a3c7a
PO		 1318 /*
1319 * Maximum block size. This varies from controller to controller and
1320 * is specified in the capabilities register.
1321 */
1322 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1323 if (mmc->max_blk_size >= 3) {
1324 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1325 host->slot_descr);
1326 ret = -ENODEV;
1327 goto unmap;
1328 }
1329 mmc->max_blk_size = 512 << mmc->max_blk_size;
1330
55db890a
PO		 1331 /*
1332 * Maximum block count.
1333 */
1334 mmc->max_blk_count = 65535;
1335
d129bceb
PO		 1336 /*
1337 * Init tasklets.
1338 */
1339 tasklet_init(&host->card_tasklet,
1340 sdhci_tasklet_card, (unsigned long)host);
1341 tasklet_init(&host->finish_tasklet,
1342 sdhci_tasklet_finish, (unsigned long)host);
1343
e4cad1b5 1344 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1345
dace1453 1346 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
d129bceb
PO		 1347 host->slot_descr, host);
1348 if (ret)
8ef1a143 1349 goto untasklet;
d129bceb
PO		 1350
1351 sdhci_init(host);
1352
1353#ifdef CONFIG_MMC_DEBUG
1354 sdhci_dumpregs(host);
1355#endif
1356
5f25a66f
PO		 1357 mmiowb();
1358
d129bceb
PO		 1359 mmc_add_host(mmc);
1360
1361 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1362 host->addr, host->irq,
1363 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1364
1365 return 0;
1366
8ef1a143 1367untasklet:
d129bceb
PO		 1368 tasklet_kill(&host->card_tasklet);
1369 tasklet_kill(&host->finish_tasklet);
8ef1a143 1370unmap:
d129bceb
PO		 1371 iounmap(host->ioaddr);
1372release:
1373 pci_release_region(pdev, host->bar);
1374free:
1375 mmc_free_host(mmc);
1376
1377 return ret;
1378}
1379
1380static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1381{
1382 struct sdhci_chip *chip;
1383 struct mmc_host *mmc;
1384 struct sdhci_host *host;
1385
1386 chip = pci_get_drvdata(pdev);
1387 host = chip->hosts[slot];
1388 mmc = host->mmc;
1389
1390 chip->hosts[slot] = NULL;
1391
1392 mmc_remove_host(mmc);
1393
1394 sdhci_reset(host, SDHCI_RESET_ALL);
1395
1396 free_irq(host->irq, host);
1397
1398 del_timer_sync(&host->timer);
1399
1400 tasklet_kill(&host->card_tasklet);
1401 tasklet_kill(&host->finish_tasklet);
1402
1403 iounmap(host->ioaddr);
1404
1405 pci_release_region(pdev, host->bar);
1406
1407 mmc_free_host(mmc);
1408}
1409
1410static int __devinit sdhci_probe(struct pci_dev *pdev,
1411 const struct pci_device_id *ent)
1412{
1413 int ret, i;
51f82bc0 1414 u8 slots, rev;
d129bceb
PO		 1415 struct sdhci_chip *chip;
1416
1417 BUG_ON(pdev == NULL);
1418 BUG_ON(ent == NULL);
1419
51f82bc0
PO		 1420 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1421
1422 printk(KERN_INFO DRIVER_NAME
1423 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1424 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1425 (int)rev);
d129bceb
PO		 1426
1427 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1428 if (ret)
1429 return ret;
1430
1431 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1432 DBG("found %d slot(s)\n", slots);
1433 if (slots == 0)
1434 return -ENODEV;
1435
1436 ret = pci_enable_device(pdev);
1437 if (ret)
1438 return ret;
1439
1440 chip = kzalloc(sizeof(struct sdhci_chip) +
1441 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1442 if (!chip) {
1443 ret = -ENOMEM;
1444 goto err;
1445 }
1446
1447 chip->pdev = pdev;
df673b22
PO		 1448 chip->quirks = ent->driver_data;
1449
1450 if (debug_quirks)
1451 chip->quirks = debug_quirks;
d129bceb
PO		 1452
1453 chip->num_slots = slots;
1454 pci_set_drvdata(pdev, chip);
1455
1456 for (i = 0;i < slots;i++) {
1457 ret = sdhci_probe_slot(pdev, i);
1458 if (ret) {
1459 for (i--;i >= 0;i--)
1460 sdhci_remove_slot(pdev, i);
1461 goto free;
1462 }
1463 }
1464
1465 return 0;
1466
1467free:
1468 pci_set_drvdata(pdev, NULL);
1469 kfree(chip);
1470
1471err:
1472 pci_disable_device(pdev);
1473 return ret;
1474}
1475
1476static void __devexit sdhci_remove(struct pci_dev *pdev)
1477{
1478 int i;
1479 struct sdhci_chip *chip;
1480
1481 chip = pci_get_drvdata(pdev);
1482
1483 if (chip) {
1484 for (i = 0;i < chip->num_slots;i++)
1485 sdhci_remove_slot(pdev, i);
1486
1487 pci_set_drvdata(pdev, NULL);
1488
1489 kfree(chip);
1490 }
1491
1492 pci_disable_device(pdev);
1493}
1494
1495static struct pci_driver sdhci_driver = {
1496 .name = DRIVER_NAME,
1497 .id_table = pci_ids,
1498 .probe = sdhci_probe,
1499 .remove = __devexit_p(sdhci_remove),
1500 .suspend = sdhci_suspend,
1501 .resume = sdhci_resume,
1502};
1503
1504/*****************************************************************************\
1505 * *
1506 * Driver init/exit *
1507 * *
1508\*****************************************************************************/
1509
1510static int __init sdhci_drv_init(void)
1511{
1512 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1513 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1514 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1515
1516 return pci_register_driver(&sdhci_driver);
1517}
1518
1519static void __exit sdhci_drv_exit(void)
1520{
1521 DBG("Exiting\n");
1522
1523 pci_unregister_driver(&sdhci_driver);
1524}
1525
1526module_init(sdhci_drv_init);
1527module_exit(sdhci_drv_exit);
1528
67435274
PO		 1529module_param(debug_nodma, uint, 0444);
1530module_param(debug_forcedma, uint, 0444);
df673b22 1531module_param(debug_quirks, uint, 0444);
67435274 1532
d129bceb
PO		 1533MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1534MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
d129bceb 1535MODULE_LICENSE("GPL");
67435274
PO		 1536
1537MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1538MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
df673b22 1539MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux kernel - Deliverables
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