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mmc: sdhci: fix data timeout (part 2)
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
348487cb 56static int sdhci_pre_dma_transfer(struct sdhci_host *host,
d31911b9 57 struct mmc_data *data);
04e079cf 58static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 59
162d6f98 60#ifdef CONFIG_PM
66fd8ad5
AH		 61static int sdhci_runtime_pm_get(struct sdhci_host *host);
62static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 63static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
64static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 65#else
66static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
67{
68 return 0;
69}
70static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
71{
72 return 0;
73}
f0710a55
AH		 74static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
75{
76}
77static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
78{
79}
66fd8ad5
AH		 80#endif
81
d129bceb
PO		 82static void sdhci_dumpregs(struct sdhci_host *host)
83{
a3c76eb9 84 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 85 mmc_hostname(host->mmc));
d129bceb 86
a3c76eb9 87 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readl(host, SDHCI_DMA_ADDRESS),
89 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readw(host, SDHCI_BLOCK_SIZE),
92 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_ARGUMENT),
95 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readl(host, SDHCI_PRESENT_STATE),
98 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_POWER_CONTROL),
101 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
104 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
107 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 108 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readl(host, SDHCI_INT_ENABLE),
110 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 111 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 112 sdhci_readw(host, SDHCI_ACMD12_ERR),
113 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 115 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 116 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 118 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 119 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 120 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 121 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 122
e57a5f61
AH		 123 if (host->flags & SDHCI_USE_ADMA) {
124 if (host->flags & SDHCI_USE_64_BIT_DMA)
125 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
126 readl(host->ioaddr + SDHCI_ADMA_ERROR),
127 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
129 else
130 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
131 readl(host->ioaddr + SDHCI_ADMA_ERROR),
132 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
133 }
be3f4ae0 134
a3c76eb9 135 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 136}
137
138/*****************************************************************************\
139 * *
140 * Low level functions *
141 * *
142\*****************************************************************************/
143
7260cf5e
AV		 144static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
145{
5b4f1f6c 146 u32 present;
7260cf5e 147
c79396c1 148 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 149 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 150 return;
151
5b4f1f6c
RK		 152 if (enable) {
153 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
154 SDHCI_CARD_PRESENT;
d25928d1 155
5b4f1f6c
RK		 156 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
157 SDHCI_INT_CARD_INSERT;
158 } else {
159 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
160 }
b537f94c
RK		 161
162 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
163 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 164}
165
166static void sdhci_enable_card_detection(struct sdhci_host *host)
167{
168 sdhci_set_card_detection(host, true);
169}
170
171static void sdhci_disable_card_detection(struct sdhci_host *host)
172{
173 sdhci_set_card_detection(host, false);
174}
175
03231f9b 176void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 177{
e16514d8 178 unsigned long timeout;
393c1a34 179
4e4141a5 180 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 181
f0710a55 182 if (mask & SDHCI_RESET_ALL) {
d129bceb 183 host->clock = 0;
f0710a55
AH		 184 /* Reset-all turns off SD Bus Power */
185 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
186 sdhci_runtime_pm_bus_off(host);
187 }
d129bceb 188
e16514d8
PO		 189 /* Wait max 100 ms */
190 timeout = 100;
191
192 /* hw clears the bit when it's done */
4e4141a5 193 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 194 if (timeout == 0) {
a3c76eb9 195 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 196 mmc_hostname(host->mmc), (int)mask);
197 sdhci_dumpregs(host);
198 return;
199 }
200 timeout--;
201 mdelay(1);
d129bceb 202 }
03231f9b
RK		 203}
204EXPORT_SYMBOL_GPL(sdhci_reset);
205
206static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
207{
208 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
135b0a28 209 if (!sdhci_do_get_cd(host))
03231f9b
RK		 210 return;
211 }
063a9dbb 212
03231f9b 213 host->ops->reset(host, mask);
393c1a34 214
da91a8f9
RK		 215 if (mask & SDHCI_RESET_ALL) {
216 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
217 if (host->ops->enable_dma)
218 host->ops->enable_dma(host);
219 }
220
221 /* Resetting the controller clears many */
222 host->preset_enabled = false;
3abc1e80 223 }
d129bceb
PO		 224}
225
2f4cbb3d
NP		 226static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
227
228static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 229{
2f4cbb3d 230 if (soft)
03231f9b 231 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 232 else
03231f9b 233 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 234
b537f94c
RK		 235 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
237 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
238 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
239 SDHCI_INT_RESPONSE;
240
241 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
242 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 243
244 if (soft) {
245 /* force clock reconfiguration */
246 host->clock = 0;
247 sdhci_set_ios(host->mmc, &host->mmc->ios);
248 }
7260cf5e 249}
d129bceb 250
7260cf5e
AV		 251static void sdhci_reinit(struct sdhci_host *host)
252{
2f4cbb3d 253 sdhci_init(host, 0);
7260cf5e 254 sdhci_enable_card_detection(host);
d129bceb
PO		 255}
256
257static void sdhci_activate_led(struct sdhci_host *host)
258{
259 u8 ctrl;
260
4e4141a5 261 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 262 ctrl |= SDHCI_CTRL_LED;
4e4141a5 263 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 264}
265
266static void sdhci_deactivate_led(struct sdhci_host *host)
267{
268 u8 ctrl;
269
4e4141a5 270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 271 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 273}
274
f9134319 275#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 276static void sdhci_led_control(struct led_classdev *led,
277 enum led_brightness brightness)
278{
279 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
280 unsigned long flags;
281
282 spin_lock_irqsave(&host->lock, flags);
283
66fd8ad5
AH		 284 if (host->runtime_suspended)
285 goto out;
286
2f730fec
PO		 287 if (brightness == LED_OFF)
288 sdhci_deactivate_led(host);
289 else
290 sdhci_activate_led(host);
66fd8ad5 291out:
2f730fec
PO		 292 spin_unlock_irqrestore(&host->lock, flags);
293}
294#endif
295
d129bceb
PO		 296/*****************************************************************************\
297 * *
298 * Core functions *
299 * *
300\*****************************************************************************/
301
a406f5a3 302static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 303{
7659150c
PO		 304 unsigned long flags;
305 size_t blksize, len, chunk;
7244b85b 306 u32 uninitialized_var(scratch);
7659150c 307 u8 *buf;
d129bceb 308
a406f5a3 309 DBG("PIO reading\n");
d129bceb 310
a406f5a3 311 blksize = host->data->blksz;
7659150c 312 chunk = 0;
d129bceb 313
7659150c 314 local_irq_save(flags);
d129bceb 315
a406f5a3 316 while (blksize) {
bf3a35ac 317 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 318
7659150c 319 len = min(host->sg_miter.length, blksize);
d129bceb 320
7659150c
PO		 321 blksize -= len;
322 host->sg_miter.consumed = len;
14d836e7 323
7659150c 324 buf = host->sg_miter.addr;
d129bceb 325
7659150c
PO		 326 while (len) {
327 if (chunk == 0) {
4e4141a5 328 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 329 chunk = 4;
a406f5a3 330 }
7659150c
PO		 331
332 *buf = scratch & 0xFF;
333
334 buf++;
335 scratch >>= 8;
336 chunk--;
337 len--;
d129bceb 338 }
a406f5a3 339 }
7659150c
PO		 340
341 sg_miter_stop(&host->sg_miter);
342
343 local_irq_restore(flags);
a406f5a3 344}
d129bceb 345
a406f5a3
PO		 346static void sdhci_write_block_pio(struct sdhci_host *host)
347{
7659150c
PO		 348 unsigned long flags;
349 size_t blksize, len, chunk;
350 u32 scratch;
351 u8 *buf;
d129bceb 352
a406f5a3
PO		 353 DBG("PIO writing\n");
354
355 blksize = host->data->blksz;
7659150c
PO		 356 chunk = 0;
357 scratch = 0;
d129bceb 358
7659150c 359 local_irq_save(flags);
d129bceb 360
a406f5a3 361 while (blksize) {
bf3a35ac 362 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 363
7659150c
PO		 364 len = min(host->sg_miter.length, blksize);
365
366 blksize -= len;
367 host->sg_miter.consumed = len;
368
369 buf = host->sg_miter.addr;
d129bceb 370
7659150c
PO		 371 while (len) {
372 scratch |= (u32)*buf << (chunk * 8);
373
374 buf++;
375 chunk++;
376 len--;
377
378 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 379 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 380 chunk = 0;
381 scratch = 0;
d129bceb 382 }
d129bceb
PO		 383 }
384 }
7659150c
PO		 385
386 sg_miter_stop(&host->sg_miter);
387
388 local_irq_restore(flags);
a406f5a3
PO		 389}
390
391static void sdhci_transfer_pio(struct sdhci_host *host)
392{
393 u32 mask;
394
395 BUG_ON(!host->data);
396
7659150c 397 if (host->blocks == 0)
a406f5a3
PO		 398 return;
399
400 if (host->data->flags & MMC_DATA_READ)
401 mask = SDHCI_DATA_AVAILABLE;
402 else
403 mask = SDHCI_SPACE_AVAILABLE;
404
4a3cba32
PO		 405 /*
406 * Some controllers (JMicron JMB38x) mess up the buffer bits
407 * for transfers < 4 bytes. As long as it is just one block,
408 * we can ignore the bits.
409 */
410 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
411 (host->data->blocks == 1))
412 mask = ~0;
413
4e4141a5 414 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 415 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
416 udelay(100);
417
a406f5a3
PO		 418 if (host->data->flags & MMC_DATA_READ)
419 sdhci_read_block_pio(host);
420 else
421 sdhci_write_block_pio(host);
d129bceb 422
7659150c
PO		 423 host->blocks--;
424 if (host->blocks == 0)
a406f5a3 425 break;
a406f5a3 426 }
d129bceb 427
a406f5a3 428 DBG("PIO transfer complete.\n");
d129bceb
PO		 429}
430
2134a922
PO		 431static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
432{
433 local_irq_save(*flags);
482fce99 434 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 435}
436
437static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
438{
482fce99 439 kunmap_atomic(buffer);
2134a922
PO		 440 local_irq_restore(*flags);
441}
442
e57a5f61
AH		 443static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
444 dma_addr_t addr, int len, unsigned cmd)
118cd17d 445{
e57a5f61 446 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 447
e57a5f61 448 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 449 dma_desc->cmd = cpu_to_le16(cmd);
450 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 451 dma_desc->addr_lo = cpu_to_le32((u32)addr);
452
453 if (host->flags & SDHCI_USE_64_BIT_DMA)
454 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 455}
456
b5ffa674
AH		 457static void sdhci_adma_mark_end(void *desc)
458{
e57a5f61 459 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 460
e57a5f61 461 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 462 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 463}
464
8f1934ce 465static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 466 struct mmc_data *data)
467{
1c3d5f6d
AH		 468 void *desc;
469 void *align;
2134a922
PO		 470 dma_addr_t addr;
471 dma_addr_t align_addr;
472 int len, offset;
473
474 struct scatterlist *sg;
475 int i;
476 char *buffer;
477 unsigned long flags;
478
479 /*
480 * The spec does not specify endianness of descriptor table.
481 * We currently guess that it is LE.
482 */
483
d31911b9 484 host->sg_count = sdhci_pre_dma_transfer(host, data);
348487cb 485 if (host->sg_count < 0)
edd63fcc 486 return -EINVAL;
2134a922 487
4efaa6fb 488 desc = host->adma_table;
2134a922
PO		 489 align = host->align_buffer;
490
491 align_addr = host->align_addr;
492
493 for_each_sg(data->sg, sg, host->sg_count, i) {
494 addr = sg_dma_address(sg);
495 len = sg_dma_len(sg);
496
497 /*
498 * The SDHCI specification states that ADMA
499 * addresses must be 32-bit aligned. If they
500 * aren't, then we use a bounce buffer for
501 * the (up to three) bytes that screw up the
502 * alignment.
503 */
04a5ae6f
AH		 504 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
505 SDHCI_ADMA2_MASK;
2134a922
PO		 506 if (offset) {
507 if (data->flags & MMC_DATA_WRITE) {
508 buffer = sdhci_kmap_atomic(sg, &flags);
509 memcpy(align, buffer, offset);
510 sdhci_kunmap_atomic(buffer, &flags);
511 }
512
118cd17d 513 /* tran, valid */
e57a5f61 514 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 515 ADMA2_TRAN_VALID);
2134a922
PO		 516
517 BUG_ON(offset > 65536);
518
04a5ae6f
AH		 519 align += SDHCI_ADMA2_ALIGN;
520 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 521
76fe379a 522 desc += host->desc_sz;
2134a922
PO		 523
524 addr += offset;
525 len -= offset;
526 }
527
2134a922
PO		 528 BUG_ON(len > 65536);
529
347ea32d
AH		 530 if (len) {
531 /* tran, valid */
532 sdhci_adma_write_desc(host, desc, addr, len,
533 ADMA2_TRAN_VALID);
534 desc += host->desc_sz;
535 }
2134a922
PO		 536
537 /*
538 * If this triggers then we have a calculation bug
539 * somewhere. :/
540 */
76fe379a 541 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 542 }
543
70764a90
TA		 544 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
545 /*
546 * Mark the last descriptor as the terminating descriptor
547 */
4efaa6fb 548 if (desc != host->adma_table) {
76fe379a 549 desc -= host->desc_sz;
b5ffa674 550 sdhci_adma_mark_end(desc);
70764a90
TA		 551 }
552 } else {
553 /*
554 * Add a terminating entry.
555 */
2134a922 556
70764a90 557 /* nop, end, valid */
e57a5f61 558 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 559 }
8f1934ce 560 return 0;
2134a922
PO		 561}
562
563static void sdhci_adma_table_post(struct sdhci_host *host,
564 struct mmc_data *data)
565{
566 int direction;
567
568 struct scatterlist *sg;
569 int i, size;
1c3d5f6d 570 void *align;
2134a922
PO		 571 char *buffer;
572 unsigned long flags;
de0b65a7 573 bool has_unaligned;
2134a922
PO		 574
575 if (data->flags & MMC_DATA_READ)
576 direction = DMA_FROM_DEVICE;
577 else
578 direction = DMA_TO_DEVICE;
579
de0b65a7
RK		 580 /* Do a quick scan of the SG list for any unaligned mappings */
581 has_unaligned = false;
582 for_each_sg(data->sg, sg, host->sg_count, i)
04a5ae6f 583 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
de0b65a7
RK		 584 has_unaligned = true;
585 break;
586 }
587
588 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 589 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
590 data->sg_len, direction);
591
592 align = host->align_buffer;
593
594 for_each_sg(data->sg, sg, host->sg_count, i) {
04a5ae6f
AH		 595 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
596 size = SDHCI_ADMA2_ALIGN -
597 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
2134a922
PO		 598
599 buffer = sdhci_kmap_atomic(sg, &flags);
600 memcpy(buffer, align, size);
601 sdhci_kunmap_atomic(buffer, &flags);
602
04a5ae6f 603 align += SDHCI_ADMA2_ALIGN;
2134a922
PO		 604 }
605 }
606 }
607
d31911b9 608 if (data->host_cookie == COOKIE_MAPPED) {
348487cb
HC		 609 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
610 data->sg_len, direction);
d31911b9
HC		 611 data->host_cookie = COOKIE_UNMAPPED;
612 }
2134a922
PO		 613}
614
a3c7778f 615static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 616{
1c8cde92 617 u8 count;
a3c7778f 618 struct mmc_data *data = cmd->data;
1c8cde92 619 unsigned target_timeout, current_timeout;
d129bceb 620
ee53ab5d
PO		 621 /*
622 * If the host controller provides us with an incorrect timeout
623 * value, just skip the check and use 0xE. The hardware may take
624 * longer to time out, but that's much better than having a too-short
625 * timeout value.
626 */
11a2f1b7 627 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 628 return 0xE;
e538fbe8 629
a3c7778f 630 /* Unspecified timeout, assume max */
1d4d7744 631 if (!data && !cmd->busy_timeout)
a3c7778f 632 return 0xE;
d129bceb 633
a3c7778f
AW		 634 /* timeout in us */
635 if (!data)
1d4d7744 636 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 637 else {
fafcfda9 638 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 639 if (host->clock && data->timeout_clks) {
640 unsigned long long val;
641
642 /*
643 * data->timeout_clks is in units of clock cycles.
644 * host->clock is in Hz. target_timeout is in us.
645 * Hence, us = 1000000 * cycles / Hz. Round up.
646 */
647 val = 1000000 * data->timeout_clks;
648 if (do_div(val, host->clock))
649 target_timeout++;
650 target_timeout += val;
651 }
78a2ca27 652 }
81b39802 653
1c8cde92
PO		 654 /*
655 * Figure out needed cycles.
656 * We do this in steps in order to fit inside a 32 bit int.
657 * The first step is the minimum timeout, which will have a
658 * minimum resolution of 6 bits:
659 * (1) 2^13*1000 > 2^22,
660 * (2) host->timeout_clk < 2^16
661 * =>
662 * (1) / (2) > 2^6
663 */
664 count = 0;
665 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
666 while (current_timeout < target_timeout) {
667 count++;
668 current_timeout <<= 1;
669 if (count >= 0xF)
670 break;
671 }
672
673 if (count >= 0xF) {
09eeff52
CB		 674 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
675 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 676 count = 0xE;
677 }
678
ee53ab5d
PO		 679 return count;
680}
681
6aa943ab
AV		 682static void sdhci_set_transfer_irqs(struct sdhci_host *host)
683{
684 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
685 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
686
687 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 688 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 689 else
b537f94c
RK		 690 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
691
692 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
693 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 694}
695
b45e668a 696static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 697{
698 u8 count;
b45e668a
AD		 699
700 if (host->ops->set_timeout) {
701 host->ops->set_timeout(host, cmd);
702 } else {
703 count = sdhci_calc_timeout(host, cmd);
704 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
705 }
706}
707
708static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
709{
2134a922 710 u8 ctrl;
a3c7778f 711 struct mmc_data *data = cmd->data;
8f1934ce 712 int ret;
ee53ab5d
PO		 713
714 WARN_ON(host->data);
715
b45e668a
AD		 716 if (data || (cmd->flags & MMC_RSP_BUSY))
717 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 718
719 if (!data)
ee53ab5d
PO		 720 return;
721
722 /* Sanity checks */
723 BUG_ON(data->blksz * data->blocks > 524288);
724 BUG_ON(data->blksz > host->mmc->max_blk_size);
725 BUG_ON(data->blocks > 65535);
726
727 host->data = data;
728 host->data_early = 0;
f6a03cbf 729 host->data->bytes_xfered = 0;
ee53ab5d 730
a13abc7b 731 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 732 host->flags |= SDHCI_REQ_USE_DMA;
733
2134a922
PO		 734 /*
735 * FIXME: This doesn't account for merging when mapping the
736 * scatterlist.
737 */
738 if (host->flags & SDHCI_REQ_USE_DMA) {
739 int broken, i;
740 struct scatterlist *sg;
741
742 broken = 0;
743 if (host->flags & SDHCI_USE_ADMA) {
744 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
745 broken = 1;
746 } else {
747 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
748 broken = 1;
749 }
750
751 if (unlikely(broken)) {
752 for_each_sg(data->sg, sg, data->sg_len, i) {
753 if (sg->length & 0x3) {
2e4456f0 754 DBG("Reverting to PIO because of transfer size (%d)\n",
2134a922
PO		 755 sg->length);
756 host->flags &= ~SDHCI_REQ_USE_DMA;
757 break;
758 }
759 }
760 }
c9fddbc4
PO		 761 }
762
763 /*
764 * The assumption here being that alignment is the same after
765 * translation to device address space.
766 */
2134a922
PO		 767 if (host->flags & SDHCI_REQ_USE_DMA) {
768 int broken, i;
769 struct scatterlist *sg;
770
771 broken = 0;
772 if (host->flags & SDHCI_USE_ADMA) {
773 /*
774 * As we use 3 byte chunks to work around
775 * alignment problems, we need to check this
776 * quirk.
777 */
778 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
779 broken = 1;
780 } else {
781 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
782 broken = 1;
783 }
784
785 if (unlikely(broken)) {
786 for_each_sg(data->sg, sg, data->sg_len, i) {
787 if (sg->offset & 0x3) {
2e4456f0 788 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 789 host->flags &= ~SDHCI_REQ_USE_DMA;
790 break;
791 }
792 }
793 }
794 }
795
8f1934ce
PO		 796 if (host->flags & SDHCI_REQ_USE_DMA) {
797 if (host->flags & SDHCI_USE_ADMA) {
798 ret = sdhci_adma_table_pre(host, data);
799 if (ret) {
800 /*
801 * This only happens when someone fed
802 * us an invalid request.
803 */
804 WARN_ON(1);
ebd6d357 805 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 806 } else {
4e4141a5
AV		 807 sdhci_writel(host, host->adma_addr,
808 SDHCI_ADMA_ADDRESS);
e57a5f61
AH		 809 if (host->flags & SDHCI_USE_64_BIT_DMA)
810 sdhci_writel(host,
811 (u64)host->adma_addr >> 32,
812 SDHCI_ADMA_ADDRESS_HI);
8f1934ce
PO		 813 }
814 } else {
c8b3e02e 815 int sg_cnt;
8f1934ce 816
d31911b9 817 sg_cnt = sdhci_pre_dma_transfer(host, data);
62a7f368 818 if (sg_cnt <= 0) {
8f1934ce
PO		 819 /*
820 * This only happens when someone fed
821 * us an invalid request.
822 */
823 WARN_ON(1);
ebd6d357 824 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 825 } else {
719a61b4 826 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 827 sdhci_writel(host, sg_dma_address(data->sg),
828 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 829 }
830 }
831 }
832
2134a922
PO		 833 /*
834 * Always adjust the DMA selection as some controllers
835 * (e.g. JMicron) can't do PIO properly when the selection
836 * is ADMA.
837 */
838 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 839 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 840 ctrl &= ~SDHCI_CTRL_DMA_MASK;
841 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 842 (host->flags & SDHCI_USE_ADMA)) {
843 if (host->flags & SDHCI_USE_64_BIT_DMA)
844 ctrl |= SDHCI_CTRL_ADMA64;
845 else
846 ctrl |= SDHCI_CTRL_ADMA32;
847 } else {
2134a922 848 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 849 }
4e4141a5 850 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 851 }
852
8f1934ce 853 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 854 int flags;
855
856 flags = SG_MITER_ATOMIC;
857 if (host->data->flags & MMC_DATA_READ)
858 flags |= SG_MITER_TO_SG;
859 else
860 flags |= SG_MITER_FROM_SG;
861 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 862 host->blocks = data->blocks;
d129bceb 863 }
c7fa9963 864
6aa943ab
AV		 865 sdhci_set_transfer_irqs(host);
866
f6a03cbf
MV		 867 /* Set the DMA boundary value and block size */
868 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
869 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 870 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 871}
872
873static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 874 struct mmc_command *cmd)
c7fa9963 875{
d3fc5d71 876 u16 mode = 0;
e89d456f 877 struct mmc_data *data = cmd->data;
c7fa9963 878
2b558c13 879 if (data == NULL) {
9b8ffea6
VW		 880 if (host->quirks2 &
881 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
882 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
883 } else {
2b558c13 884 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 885 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
886 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 887 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 888 }
c7fa9963 889 return;
2b558c13 890 }
c7fa9963 891
e538fbe8
PO		 892 WARN_ON(!host->data);
893
d3fc5d71
VY		 894 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
895 mode = SDHCI_TRNS_BLK_CNT_EN;
896
e89d456f 897 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 898 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 899 /*
900 * If we are sending CMD23, CMD12 never gets sent
901 * on successful completion (so no Auto-CMD12).
902 */
85cc1c33
CD		 903 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
904 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 905 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 906 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
907 mode |= SDHCI_TRNS_AUTO_CMD23;
908 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
909 }
c4512f79 910 }
8edf6371 911
c7fa9963
PO		 912 if (data->flags & MMC_DATA_READ)
913 mode |= SDHCI_TRNS_READ;
c9fddbc4 914 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 915 mode |= SDHCI_TRNS_DMA;
916
4e4141a5 917 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 918}
919
920static void sdhci_finish_data(struct sdhci_host *host)
921{
922 struct mmc_data *data;
d129bceb
PO		 923
924 BUG_ON(!host->data);
925
926 data = host->data;
927 host->data = NULL;
928
c9fddbc4 929 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 930 if (host->flags & SDHCI_USE_ADMA)
931 sdhci_adma_table_post(host, data);
932 else {
d31911b9 933 if (data->host_cookie == COOKIE_MAPPED) {
348487cb
HC		 934 dma_unmap_sg(mmc_dev(host->mmc),
935 data->sg, data->sg_len,
936 (data->flags & MMC_DATA_READ) ?
2134a922 937 DMA_FROM_DEVICE : DMA_TO_DEVICE);
d31911b9
HC		 938 data->host_cookie = COOKIE_UNMAPPED;
939 }
2134a922 940 }
d129bceb
PO		 941 }
942
943 /*
c9b74c5b
PO		 944 * The specification states that the block count register must
945 * be updated, but it does not specify at what point in the
946 * data flow. That makes the register entirely useless to read
947 * back so we have to assume that nothing made it to the card
948 * in the event of an error.
d129bceb 949 */
c9b74c5b
PO		 950 if (data->error)
951 data->bytes_xfered = 0;
d129bceb 952 else
c9b74c5b 953 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 954
e89d456f
AW		 955 /*
956 * Need to send CMD12 if -
957 * a) open-ended multiblock transfer (no CMD23)
958 * b) error in multiblock transfer
959 */
960 if (data->stop &&
961 (data->error ||
962 !host->mrq->sbc)) {
963
d129bceb
PO		 964 /*
965 * The controller needs a reset of internal state machines
966 * upon error conditions.
967 */
17b0429d 968 if (data->error) {
03231f9b
RK		 969 sdhci_do_reset(host, SDHCI_RESET_CMD);
970 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 971 }
972
973 sdhci_send_command(host, data->stop);
974 } else
975 tasklet_schedule(&host->finish_tasklet);
976}
977
c0e55129 978void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 979{
980 int flags;
fd2208d7 981 u32 mask;
7cb2c76f 982 unsigned long timeout;
d129bceb
PO		 983
984 WARN_ON(host->cmd);
985
96776200
RK		 986 /* Initially, a command has no error */
987 cmd->error = 0;
988
d129bceb 989 /* Wait max 10 ms */
7cb2c76f 990 timeout = 10;
fd2208d7
PO		 991
992 mask = SDHCI_CMD_INHIBIT;
993 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
994 mask |= SDHCI_DATA_INHIBIT;
995
996 /* We shouldn't wait for data inihibit for stop commands, even
997 though they might use busy signaling */
998 if (host->mrq->data && (cmd == host->mrq->data->stop))
999 mask &= ~SDHCI_DATA_INHIBIT;
1000
4e4141a5 1001 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1002 if (timeout == 0) {
2e4456f0
MV		 1003 pr_err("%s: Controller never released inhibit bit(s).\n",
1004 mmc_hostname(host->mmc));
d129bceb 1005 sdhci_dumpregs(host);
17b0429d 1006 cmd->error = -EIO;
d129bceb
PO		 1007 tasklet_schedule(&host->finish_tasklet);
1008 return;
1009 }
7cb2c76f
PO		 1010 timeout--;
1011 mdelay(1);
1012 }
d129bceb 1013
3e1a6892 1014 timeout = jiffies;
1d4d7744
UH		 1015 if (!cmd->data && cmd->busy_timeout > 9000)
1016 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1017 else
1018 timeout += 10 * HZ;
1019 mod_timer(&host->timer, timeout);
d129bceb
PO		 1020
1021 host->cmd = cmd;
e99783a4 1022 host->busy_handle = 0;
d129bceb 1023
a3c7778f 1024 sdhci_prepare_data(host, cmd);
d129bceb 1025
4e4141a5 1026 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1027
e89d456f 1028 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1029
d129bceb 1030 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1031 pr_err("%s: Unsupported response type!\n",
d129bceb 1032 mmc_hostname(host->mmc));
17b0429d 1033 cmd->error = -EINVAL;
d129bceb
PO		 1034 tasklet_schedule(&host->finish_tasklet);
1035 return;
1036 }
1037
1038 if (!(cmd->flags & MMC_RSP_PRESENT))
1039 flags = SDHCI_CMD_RESP_NONE;
1040 else if (cmd->flags & MMC_RSP_136)
1041 flags = SDHCI_CMD_RESP_LONG;
1042 else if (cmd->flags & MMC_RSP_BUSY)
1043 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1044 else
1045 flags = SDHCI_CMD_RESP_SHORT;
1046
1047 if (cmd->flags & MMC_RSP_CRC)
1048 flags |= SDHCI_CMD_CRC;
1049 if (cmd->flags & MMC_RSP_OPCODE)
1050 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1051
1052 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1053 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1054 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1055 flags |= SDHCI_CMD_DATA;
1056
4e4141a5 1057 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1058}
c0e55129 1059EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1060
1061static void sdhci_finish_command(struct sdhci_host *host)
1062{
1063 int i;
1064
1065 BUG_ON(host->cmd == NULL);
1066
1067 if (host->cmd->flags & MMC_RSP_PRESENT) {
1068 if (host->cmd->flags & MMC_RSP_136) {
1069 /* CRC is stripped so we need to do some shifting. */
1070 for (i = 0;i < 4;i++) {
4e4141a5 1071 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1072 SDHCI_RESPONSE + (3-i)*4) << 8;
1073 if (i != 3)
1074 host->cmd->resp[i] |=
4e4141a5 1075 sdhci_readb(host,
d129bceb
PO		 1076 SDHCI_RESPONSE + (3-i)*4-1);
1077 }
1078 } else {
4e4141a5 1079 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1080 }
1081 }
1082
e89d456f
AW		 1083 /* Finished CMD23, now send actual command. */
1084 if (host->cmd == host->mrq->sbc) {
1085 host->cmd = NULL;
1086 sdhci_send_command(host, host->mrq->cmd);
1087 } else {
e538fbe8 1088
e89d456f
AW		 1089 /* Processed actual command. */
1090 if (host->data && host->data_early)
1091 sdhci_finish_data(host);
d129bceb 1092
e89d456f
AW		 1093 if (!host->cmd->data)
1094 tasklet_schedule(&host->finish_tasklet);
1095
1096 host->cmd = NULL;
1097 }
d129bceb
PO		 1098}
1099
52983382
KL		 1100static u16 sdhci_get_preset_value(struct sdhci_host *host)
1101{
d975f121 1102 u16 preset = 0;
52983382 1103
d975f121
RK		 1104 switch (host->timing) {
1105 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1107 break;
d975f121 1108 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1110 break;
d975f121 1111 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1112 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1113 break;
d975f121
RK		 1114 case MMC_TIMING_UHS_SDR104:
1115 case MMC_TIMING_MMC_HS200:
52983382
KL		 1116 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1117 break;
d975f121 1118 case MMC_TIMING_UHS_DDR50:
0dafa60e 1119 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1120 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1121 break;
e9fb05d5
AH		 1122 case MMC_TIMING_MMC_HS400:
1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1124 break;
52983382
KL		 1125 default:
1126 pr_warn("%s: Invalid UHS-I mode selected\n",
1127 mmc_hostname(host->mmc));
1128 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1129 break;
1130 }
1131 return preset;
1132}
1133
1771059c 1134void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1135{
c3ed3877 1136 int div = 0; /* Initialized for compiler warning */
df16219f 1137 int real_div = div, clk_mul = 1;
c3ed3877 1138 u16 clk = 0;
7cb2c76f 1139 unsigned long timeout;
5497159c 1140 bool switch_base_clk = false;
d129bceb 1141
1650d0c7
RK		 1142 host->mmc->actual_clock = 0;
1143
4e4141a5 1144 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
af951761 1145 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1146 mdelay(1);
d129bceb
PO		 1147
1148 if (clock == 0)
373073ef 1149 return;
d129bceb 1150
85105c53 1151 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1152 if (host->preset_enabled) {
52983382
KL		 1153 u16 pre_val;
1154
1155 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1156 pre_val = sdhci_get_preset_value(host);
1157 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1158 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1159 if (host->clk_mul &&
1160 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1161 clk = SDHCI_PROG_CLOCK_MODE;
1162 real_div = div + 1;
1163 clk_mul = host->clk_mul;
1164 } else {
1165 real_div = max_t(int, 1, div << 1);
1166 }
1167 goto clock_set;
1168 }
1169
c3ed3877
AN		 1170 /*
1171 * Check if the Host Controller supports Programmable Clock
1172 * Mode.
1173 */
1174 if (host->clk_mul) {
52983382
KL		 1175 for (div = 1; div <= 1024; div++) {
1176 if ((host->max_clk * host->clk_mul / div)
1177 <= clock)
1178 break;
1179 }
5497159c 1180 if ((host->max_clk * host->clk_mul / div) <= clock) {
1181 /*
1182 * Set Programmable Clock Mode in the Clock
1183 * Control register.
1184 */
1185 clk = SDHCI_PROG_CLOCK_MODE;
1186 real_div = div;
1187 clk_mul = host->clk_mul;
1188 div--;
1189 } else {
1190 /*
1191 * Divisor can be too small to reach clock
1192 * speed requirement. Then use the base clock.
1193 */
1194 switch_base_clk = true;
1195 }
1196 }
1197
1198 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1199 /* Version 3.00 divisors must be a multiple of 2. */
1200 if (host->max_clk <= clock)
1201 div = 1;
1202 else {
1203 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1204 div += 2) {
1205 if ((host->max_clk / div) <= clock)
1206 break;
1207 }
85105c53 1208 }
df16219f 1209 real_div = div;
c3ed3877 1210 div >>= 1;
d1955c3a
SG		 1211 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1212 && !div && host->max_clk <= 25000000)
1213 div = 1;
85105c53
ZG		 1214 }
1215 } else {
1216 /* Version 2.00 divisors must be a power of 2. */
0397526d 1217 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1218 if ((host->max_clk / div) <= clock)
1219 break;
1220 }
df16219f 1221 real_div = div;
c3ed3877 1222 div >>= 1;
d129bceb 1223 }
d129bceb 1224
52983382 1225clock_set:
03d6f5ff 1226 if (real_div)
df16219f 1227 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1228 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1229 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1230 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1231 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1232 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1233
27f6cb16
CB		 1234 /* Wait max 20 ms */
1235 timeout = 20;
4e4141a5 1236 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1237 & SDHCI_CLOCK_INT_STABLE)) {
1238 if (timeout == 0) {
2e4456f0
MV		 1239 pr_err("%s: Internal clock never stabilised.\n",
1240 mmc_hostname(host->mmc));
d129bceb
PO		 1241 sdhci_dumpregs(host);
1242 return;
1243 }
7cb2c76f
PO		 1244 timeout--;
1245 mdelay(1);
1246 }
d129bceb
PO		 1247
1248 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1249 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1250}
1771059c 1251EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1252
24fbb3ca
RK		 1253static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1254 unsigned short vdd)
146ad66e 1255{
3a48edc4 1256 struct mmc_host *mmc = host->mmc;
8364248a 1257 u8 pwr = 0;
146ad66e 1258
24fbb3ca
RK		 1259 if (mode != MMC_POWER_OFF) {
1260 switch (1 << vdd) {
ae628903
PO		 1261 case MMC_VDD_165_195:
1262 pwr = SDHCI_POWER_180;
1263 break;
1264 case MMC_VDD_29_30:
1265 case MMC_VDD_30_31:
1266 pwr = SDHCI_POWER_300;
1267 break;
1268 case MMC_VDD_32_33:
1269 case MMC_VDD_33_34:
1270 pwr = SDHCI_POWER_330;
1271 break;
1272 default:
9d5de93f
AH		 1273 WARN(1, "%s: Invalid vdd %#x\n",
1274 mmc_hostname(host->mmc), vdd);
1275 break;
ae628903
PO		 1276 }
1277 }
1278
1279 if (host->pwr == pwr)
e921a8b6 1280 return;
146ad66e 1281
ae628903
PO		 1282 host->pwr = pwr;
1283
1284 if (pwr == 0) {
4e4141a5 1285 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1286 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1287 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1288 vdd = 0;
e921a8b6
RK		 1289 } else {
1290 /*
1291 * Spec says that we should clear the power reg before setting
1292 * a new value. Some controllers don't seem to like this though.
1293 */
1294 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1295 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1296
e921a8b6
RK		 1297 /*
1298 * At least the Marvell CaFe chip gets confused if we set the
1299 * voltage and set turn on power at the same time, so set the
1300 * voltage first.
1301 */
1302 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1303 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1304
e921a8b6 1305 pwr |= SDHCI_POWER_ON;
146ad66e 1306
e921a8b6 1307 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1308
e921a8b6
RK		 1309 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1310 sdhci_runtime_pm_bus_on(host);
f0710a55 1311
e921a8b6
RK		 1312 /*
1313 * Some controllers need an extra 10ms delay of 10ms before
1314 * they can apply clock after applying power
1315 */
1316 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1317 mdelay(10);
1318 }
918f4cbd
JZ		 1319
1320 if (!IS_ERR(mmc->supply.vmmc)) {
1321 spin_unlock_irq(&host->lock);
1322 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1323 spin_lock_irq(&host->lock);
1324 }
146ad66e
PO		 1325}
1326
d129bceb
PO		 1327/*****************************************************************************\
1328 * *
1329 * MMC callbacks *
1330 * *
1331\*****************************************************************************/
1332
1333static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1334{
1335 struct sdhci_host *host;
505a8680 1336 int present;
d129bceb
PO		 1337 unsigned long flags;
1338
1339 host = mmc_priv(mmc);
1340
66fd8ad5
AH		 1341 sdhci_runtime_pm_get(host);
1342
04e079cf 1343 /* Firstly check card presence */
8d28b7a7 1344 present = mmc->ops->get_cd(mmc);
2836766a 1345
d129bceb
PO		 1346 spin_lock_irqsave(&host->lock, flags);
1347
1348 WARN_ON(host->mrq != NULL);
1349
f9134319 1350#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1351 sdhci_activate_led(host);
2f730fec 1352#endif
e89d456f
AW		 1353
1354 /*
1355 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1356 * requests if Auto-CMD12 is enabled.
1357 */
1358 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1359 if (mrq->stop) {
1360 mrq->data->stop = NULL;
1361 mrq->stop = NULL;
1362 }
1363 }
d129bceb
PO		 1364
1365 host->mrq = mrq;
1366
68d1fb7e 1367 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1368 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1369 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1370 } else {
8edf6371 1371 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1372 sdhci_send_command(host, mrq->sbc);
1373 else
1374 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1375 }
d129bceb 1376
5f25a66f 1377 mmiowb();
d129bceb
PO		 1378 spin_unlock_irqrestore(&host->lock, flags);
1379}
1380
2317f56c
RK		 1381void sdhci_set_bus_width(struct sdhci_host *host, int width)
1382{
1383 u8 ctrl;
1384
1385 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1386 if (width == MMC_BUS_WIDTH_8) {
1387 ctrl &= ~SDHCI_CTRL_4BITBUS;
1388 if (host->version >= SDHCI_SPEC_300)
1389 ctrl |= SDHCI_CTRL_8BITBUS;
1390 } else {
1391 if (host->version >= SDHCI_SPEC_300)
1392 ctrl &= ~SDHCI_CTRL_8BITBUS;
1393 if (width == MMC_BUS_WIDTH_4)
1394 ctrl |= SDHCI_CTRL_4BITBUS;
1395 else
1396 ctrl &= ~SDHCI_CTRL_4BITBUS;
1397 }
1398 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1399}
1400EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1401
96d7b78c
RK		 1402void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1403{
1404 u16 ctrl_2;
1405
1406 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1407 /* Select Bus Speed Mode for host */
1408 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1409 if ((timing == MMC_TIMING_MMC_HS200) ||
1410 (timing == MMC_TIMING_UHS_SDR104))
1411 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1412 else if (timing == MMC_TIMING_UHS_SDR12)
1413 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1414 else if (timing == MMC_TIMING_UHS_SDR25)
1415 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1416 else if (timing == MMC_TIMING_UHS_SDR50)
1417 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1418 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1419 (timing == MMC_TIMING_MMC_DDR52))
1420 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1421 else if (timing == MMC_TIMING_MMC_HS400)
1422 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1423 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1424}
1425EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1426
66fd8ad5 1427static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1428{
d129bceb
PO		 1429 unsigned long flags;
1430 u8 ctrl;
3a48edc4 1431 struct mmc_host *mmc = host->mmc;
d129bceb 1432
d129bceb
PO		 1433 spin_lock_irqsave(&host->lock, flags);
1434
ceb6143b
AH		 1435 if (host->flags & SDHCI_DEVICE_DEAD) {
1436 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1437 if (!IS_ERR(mmc->supply.vmmc) &&
1438 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1439 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1440 return;
1441 }
1e72859e 1442
d129bceb
PO		 1443 /*
1444 * Reset the chip on each power off.
1445 * Should clear out any weird states.
1446 */
1447 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1448 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1449 sdhci_reinit(host);
d129bceb
PO		 1450 }
1451
52983382 1452 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1453 (ios->power_mode == MMC_POWER_UP) &&
1454 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1455 sdhci_enable_preset_value(host, false);
1456
373073ef 1457 if (!ios->clock || ios->clock != host->clock) {
1771059c 1458 host->ops->set_clock(host, ios->clock);
373073ef 1459 host->clock = ios->clock;
03d6f5ff
AD		 1460
1461 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1462 host->clock) {
1463 host->timeout_clk = host->mmc->actual_clock ?
1464 host->mmc->actual_clock / 1000 :
1465 host->clock / 1000;
1466 host->mmc->max_busy_timeout =
1467 host->ops->get_max_timeout_count ?
1468 host->ops->get_max_timeout_count(host) :
1469 1 << 27;
1470 host->mmc->max_busy_timeout /= host->timeout_clk;
1471 }
373073ef 1472 }
d129bceb 1473
24fbb3ca 1474 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1475
643a81ff
PR		 1476 if (host->ops->platform_send_init_74_clocks)
1477 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1478
2317f56c 1479 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1480
15ec4461 1481 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1482
3ab9c8da
PR		 1483 if ((ios->timing == MMC_TIMING_SD_HS ||
1484 ios->timing == MMC_TIMING_MMC_HS)
1485 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1486 ctrl |= SDHCI_CTRL_HISPD;
1487 else
1488 ctrl &= ~SDHCI_CTRL_HISPD;
1489
d6d50a15 1490 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1491 u16 clk, ctrl_2;
49c468fc
AN		 1492
1493 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1494 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1495 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1496 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1497 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1498 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1499 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1500 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1501 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1502
da91a8f9 1503 if (!host->preset_enabled) {
758535c4 1504 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1505 /*
1506 * We only need to set Driver Strength if the
1507 * preset value enable is not set.
1508 */
da91a8f9 1509 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1510 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1511 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1512 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1513 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1514 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1515 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1516 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1517 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1518 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1519 else {
2e4456f0
MV		 1520 pr_warn("%s: invalid driver type, default to driver type B\n",
1521 mmc_hostname(mmc));
43e943a0
PG		 1522 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1523 }
d6d50a15
AN		 1524
1525 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1526 } else {
1527 /*
1528 * According to SDHC Spec v3.00, if the Preset Value
1529 * Enable in the Host Control 2 register is set, we
1530 * need to reset SD Clock Enable before changing High
1531 * Speed Enable to avoid generating clock gliches.
1532 */
758535c4
AN		 1533
1534 /* Reset SD Clock Enable */
1535 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1536 clk &= ~SDHCI_CLOCK_CARD_EN;
1537 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1538
1539 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1540
1541 /* Re-enable SD Clock */
1771059c 1542 host->ops->set_clock(host, host->clock);
d6d50a15 1543 }
49c468fc 1544
49c468fc
AN		 1545 /* Reset SD Clock Enable */
1546 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1547 clk &= ~SDHCI_CLOCK_CARD_EN;
1548 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1549
96d7b78c 1550 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1551 host->timing = ios->timing;
49c468fc 1552
52983382
KL		 1553 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1554 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1555 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1556 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1557 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1558 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1559 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1560 u16 preset;
1561
1562 sdhci_enable_preset_value(host, true);
1563 preset = sdhci_get_preset_value(host);
1564 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1565 >> SDHCI_PRESET_DRV_SHIFT;
1566 }
1567
49c468fc 1568 /* Re-enable SD Clock */
1771059c 1569 host->ops->set_clock(host, host->clock);
758535c4
AN		 1570 } else
1571 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1572
b8352260
LD		 1573 /*
1574 * Some (ENE) controllers go apeshit on some ios operation,
1575 * signalling timeout and CRC errors even on CMD0. Resetting
1576 * it on each ios seems to solve the problem.
1577 */
c63705e1 1578 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1579 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1580
5f25a66f 1581 mmiowb();
d129bceb
PO		 1582 spin_unlock_irqrestore(&host->lock, flags);
1583}
1584
66fd8ad5
AH		 1585static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1586{
1587 struct sdhci_host *host = mmc_priv(mmc);
1588
1589 sdhci_runtime_pm_get(host);
1590 sdhci_do_set_ios(host, ios);
1591 sdhci_runtime_pm_put(host);
1592}
1593
94144a46
KL		 1594static int sdhci_do_get_cd(struct sdhci_host *host)
1595{
1596 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1597
1598 if (host->flags & SDHCI_DEVICE_DEAD)
1599 return 0;
1600
88af5655
II		 1601 /* If nonremovable, assume that the card is always present. */
1602 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
94144a46
KL		 1603 return 1;
1604
88af5655
II		 1605 /*
1606 * Try slot gpio detect, if defined it take precedence
1607 * over build in controller functionality
1608 */
94144a46
KL		 1609 if (!IS_ERR_VALUE(gpio_cd))
1610 return !!gpio_cd;
1611
88af5655
II		 1612 /* If polling, assume that the card is always present. */
1613 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1614 return 1;
1615
94144a46
KL		 1616 /* Host native card detect */
1617 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1618}
1619
1620static int sdhci_get_cd(struct mmc_host *mmc)
1621{
1622 struct sdhci_host *host = mmc_priv(mmc);
1623 int ret;
1624
1625 sdhci_runtime_pm_get(host);
1626 ret = sdhci_do_get_cd(host);
1627 sdhci_runtime_pm_put(host);
1628 return ret;
1629}
1630
66fd8ad5 1631static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1632{
d129bceb 1633 unsigned long flags;
2dfb579c 1634 int is_readonly;
d129bceb 1635
d129bceb
PO		 1636 spin_lock_irqsave(&host->lock, flags);
1637
1e72859e 1638 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1639 is_readonly = 0;
1640 else if (host->ops->get_ro)
1641 is_readonly = host->ops->get_ro(host);
1e72859e 1642 else
2dfb579c
WS		 1643 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1644 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1645
1646 spin_unlock_irqrestore(&host->lock, flags);
1647
2dfb579c
WS		 1648 /* This quirk needs to be replaced by a callback-function later */
1649 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1650 !is_readonly : is_readonly;
d129bceb
PO		 1651}
1652
82b0e23a
TI		 1653#define SAMPLE_COUNT 5
1654
66fd8ad5 1655static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1656{
82b0e23a
TI		 1657 int i, ro_count;
1658
82b0e23a 1659 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1660 return sdhci_check_ro(host);
82b0e23a
TI		 1661
1662 ro_count = 0;
1663 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1664 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1665 if (++ro_count > SAMPLE_COUNT / 2)
1666 return 1;
1667 }
1668 msleep(30);
1669 }
1670 return 0;
1671}
1672
20758b66
AH		 1673static void sdhci_hw_reset(struct mmc_host *mmc)
1674{
1675 struct sdhci_host *host = mmc_priv(mmc);
1676
1677 if (host->ops && host->ops->hw_reset)
1678 host->ops->hw_reset(host);
1679}
1680
66fd8ad5 1681static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1682{
66fd8ad5
AH		 1683 struct sdhci_host *host = mmc_priv(mmc);
1684 int ret;
f75979b7 1685
66fd8ad5
AH		 1686 sdhci_runtime_pm_get(host);
1687 ret = sdhci_do_get_ro(host);
1688 sdhci_runtime_pm_put(host);
1689 return ret;
1690}
f75979b7 1691
66fd8ad5
AH		 1692static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1693{
be138554 1694 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1695 if (enable)
b537f94c 1696 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1697 else
b537f94c
RK		 1698 host->ier &= ~SDHCI_INT_CARD_INT;
1699
1700 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1701 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1702 mmiowb();
1703 }
66fd8ad5
AH		 1704}
1705
1706static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1707{
1708 struct sdhci_host *host = mmc_priv(mmc);
1709 unsigned long flags;
f75979b7 1710
ef104333
RK		 1711 sdhci_runtime_pm_get(host);
1712
66fd8ad5 1713 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1714 if (enable)
1715 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1716 else
1717 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1718
66fd8ad5 1719 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1720 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1721
1722 sdhci_runtime_pm_put(host);
f75979b7
PO		 1723}
1724
20b92a30 1725static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1726 struct mmc_ios *ios)
f2119df6 1727{
3a48edc4 1728 struct mmc_host *mmc = host->mmc;
20b92a30 1729 u16 ctrl;
6231f3de 1730 int ret;
f2119df6 1731
20b92a30
KL		 1732 /*
1733 * Signal Voltage Switching is only applicable for Host Controllers
1734 * v3.00 and above.
1735 */
1736 if (host->version < SDHCI_SPEC_300)
1737 return 0;
6231f3de 1738
f2119df6 1739 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1740
21f5998f 1741 switch (ios->signal_voltage) {
20b92a30
KL		 1742 case MMC_SIGNAL_VOLTAGE_330:
1743 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1744 ctrl &= ~SDHCI_CTRL_VDD_180;
1745 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1746
3a48edc4
TK		 1747 if (!IS_ERR(mmc->supply.vqmmc)) {
1748 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1749 3600000);
20b92a30 1750 if (ret) {
6606110d
JP		 1751 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1752 mmc_hostname(mmc));
20b92a30
KL		 1753 return -EIO;
1754 }
1755 }
1756 /* Wait for 5ms */
1757 usleep_range(5000, 5500);
f2119df6 1758
20b92a30
KL		 1759 /* 3.3V regulator output should be stable within 5 ms */
1760 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1761 if (!(ctrl & SDHCI_CTRL_VDD_180))
1762 return 0;
6231f3de 1763
6606110d
JP		 1764 pr_warn("%s: 3.3V regulator output did not became stable\n",
1765 mmc_hostname(mmc));
20b92a30
KL		 1766
1767 return -EAGAIN;
1768 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1769 if (!IS_ERR(mmc->supply.vqmmc)) {
1770 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1771 1700000, 1950000);
1772 if (ret) {
6606110d
JP		 1773 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1774 mmc_hostname(mmc));
20b92a30
KL		 1775 return -EIO;
1776 }
1777 }
6231f3de 1778
6231f3de
PR		 1779 /*
1780 * Enable 1.8V Signal Enable in the Host Control2
1781 * register
1782 */
20b92a30
KL		 1783 ctrl |= SDHCI_CTRL_VDD_180;
1784 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1785
9d967a61
VY		 1786 /* Some controller need to do more when switching */
1787 if (host->ops->voltage_switch)
1788 host->ops->voltage_switch(host);
1789
20b92a30
KL		 1790 /* 1.8V regulator output should be stable within 5 ms */
1791 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1792 if (ctrl & SDHCI_CTRL_VDD_180)
1793 return 0;
f2119df6 1794
6606110d
JP		 1795 pr_warn("%s: 1.8V regulator output did not became stable\n",
1796 mmc_hostname(mmc));
f2119df6 1797
20b92a30
KL		 1798 return -EAGAIN;
1799 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1800 if (!IS_ERR(mmc->supply.vqmmc)) {
1801 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1802 1300000);
20b92a30 1803 if (ret) {
6606110d
JP		 1804 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1805 mmc_hostname(mmc));
20b92a30 1806 return -EIO;
f2119df6
AN		 1807 }
1808 }
6231f3de 1809 return 0;
20b92a30 1810 default:
f2119df6
AN		 1811 /* No signal voltage switch required */
1812 return 0;
20b92a30 1813 }
f2119df6
AN		 1814}
1815
66fd8ad5 1816static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1817 struct mmc_ios *ios)
66fd8ad5
AH		 1818{
1819 struct sdhci_host *host = mmc_priv(mmc);
1820 int err;
1821
1822 if (host->version < SDHCI_SPEC_300)
1823 return 0;
1824 sdhci_runtime_pm_get(host);
21f5998f 1825 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1826 sdhci_runtime_pm_put(host);
1827 return err;
1828}
1829
20b92a30
KL		 1830static int sdhci_card_busy(struct mmc_host *mmc)
1831{
1832 struct sdhci_host *host = mmc_priv(mmc);
1833 u32 present_state;
1834
1835 sdhci_runtime_pm_get(host);
1836 /* Check whether DAT[3:0] is 0000 */
1837 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1838 sdhci_runtime_pm_put(host);
1839
1840 return !(present_state & SDHCI_DATA_LVL_MASK);
1841}
1842
b5540ce1
AH		 1843static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1844{
1845 struct sdhci_host *host = mmc_priv(mmc);
1846 unsigned long flags;
1847
1848 spin_lock_irqsave(&host->lock, flags);
1849 host->flags |= SDHCI_HS400_TUNING;
1850 spin_unlock_irqrestore(&host->lock, flags);
1851
1852 return 0;
1853}
1854
069c9f14 1855static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1856{
4b6f37d3 1857 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1858 u16 ctrl;
b513ea25 1859 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1860 int err = 0;
2b35bd83 1861 unsigned long flags;
38e40bf5 1862 unsigned int tuning_count = 0;
b5540ce1 1863 bool hs400_tuning;
b513ea25 1864
66fd8ad5 1865 sdhci_runtime_pm_get(host);
2b35bd83 1866 spin_lock_irqsave(&host->lock, flags);
b513ea25 1867
b5540ce1
AH		 1868 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1869 host->flags &= ~SDHCI_HS400_TUNING;
1870
38e40bf5
AH		 1871 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1872 tuning_count = host->tuning_count;
1873
b513ea25 1874 /*
9faac7b9
WY		 1875 * The Host Controller needs tuning in case of SDR104 and DDR50
1876 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1877 * the Capabilities register.
069c9f14
G		 1878 * If the Host Controller supports the HS200 mode then the
1879 * tuning function has to be executed.
b513ea25 1880 */
4b6f37d3 1881 switch (host->timing) {
b5540ce1 1882 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1883 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1884 err = -EINVAL;
1885 goto out_unlock;
1886
4b6f37d3 1887 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1888 /*
1889 * Periodic re-tuning for HS400 is not expected to be needed, so
1890 * disable it here.
1891 */
1892 if (hs400_tuning)
1893 tuning_count = 0;
1894 break;
1895
4b6f37d3 1896 case MMC_TIMING_UHS_SDR104:
9faac7b9 1897 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1898 break;
1899
1900 case MMC_TIMING_UHS_SDR50:
1901 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1902 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1903 break;
1904 /* FALLTHROUGH */
1905
1906 default:
d519c863 1907 goto out_unlock;
b513ea25
AN		 1908 }
1909
45251812 1910 if (host->ops->platform_execute_tuning) {
2b35bd83 1911 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1912 err = host->ops->platform_execute_tuning(host, opcode);
1913 sdhci_runtime_pm_put(host);
1914 return err;
1915 }
1916
4b6f37d3
RK		 1917 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1918 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1919 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1920 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1921 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1922
1923 /*
1924 * As per the Host Controller spec v3.00, tuning command
1925 * generates Buffer Read Ready interrupt, so enable that.
1926 *
1927 * Note: The spec clearly says that when tuning sequence
1928 * is being performed, the controller does not generate
1929 * interrupts other than Buffer Read Ready interrupt. But
1930 * to make sure we don't hit a controller bug, we _only_
1931 * enable Buffer Read Ready interrupt here.
1932 */
b537f94c
RK		 1933 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1934 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1935
1936 /*
1937 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1938 * of loops reaches 40 times or a timeout of 150ms occurs.
1939 */
b513ea25
AN		 1940 do {
1941 struct mmc_command cmd = {0};
66fd8ad5 1942 struct mmc_request mrq = {NULL};
b513ea25 1943
069c9f14 1944 cmd.opcode = opcode;
b513ea25
AN		 1945 cmd.arg = 0;
1946 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1947 cmd.retries = 0;
1948 cmd.data = NULL;
1949 cmd.error = 0;
1950
7ce45e95
AC		 1951 if (tuning_loop_counter-- == 0)
1952 break;
1953
b513ea25
AN		 1954 mrq.cmd = &cmd;
1955 host->mrq = &mrq;
1956
1957 /*
1958 * In response to CMD19, the card sends 64 bytes of tuning
1959 * block to the Host Controller. So we set the block size
1960 * to 64 here.
1961 */
069c9f14
G		 1962 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1963 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1964 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1965 SDHCI_BLOCK_SIZE);
1966 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1967 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1968 SDHCI_BLOCK_SIZE);
1969 } else {
1970 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1971 SDHCI_BLOCK_SIZE);
1972 }
b513ea25
AN		 1973
1974 /*
1975 * The tuning block is sent by the card to the host controller.
1976 * So we set the TRNS_READ bit in the Transfer Mode register.
1977 * This also takes care of setting DMA Enable and Multi Block
1978 * Select in the same register to 0.
1979 */
1980 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1981
1982 sdhci_send_command(host, &cmd);
1983
1984 host->cmd = NULL;
1985 host->mrq = NULL;
1986
2b35bd83 1987 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1988 /* Wait for Buffer Read Ready interrupt */
1989 wait_event_interruptible_timeout(host->buf_ready_int,
1990 (host->tuning_done == 1),
1991 msecs_to_jiffies(50));
2b35bd83 1992 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1993
1994 if (!host->tuning_done) {
2e4456f0 1995 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 1996 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1997 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1998 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1999 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2000
2001 err = -EIO;
2002 goto out;
2003 }
2004
2005 host->tuning_done = 0;
2006
2007 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2008
2009 /* eMMC spec does not require a delay between tuning cycles */
2010 if (opcode == MMC_SEND_TUNING_BLOCK)
2011 mdelay(1);
b513ea25
AN		 2012 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2013
2014 /*
2015 * The Host Driver has exhausted the maximum number of loops allowed,
2016 * so use fixed sampling frequency.
2017 */
7ce45e95 2018 if (tuning_loop_counter < 0) {
b513ea25
AN		 2019 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2020 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2021 }
2022 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2023 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2024 err = -EIO;
b513ea25
AN		 2025 }
2026
2027out:
38e40bf5 2028 if (tuning_count) {
66c39dfc
AH		 2029 /*
2030 * In case tuning fails, host controllers which support
2031 * re-tuning can try tuning again at a later time, when the
2032 * re-tuning timer expires. So for these controllers, we
2033 * return 0. Since there might be other controllers who do not
2034 * have this capability, we return error for them.
2035 */
2036 err = 0;
cf2b5eea
AN		 2037 }
2038
66c39dfc 2039 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2040
b537f94c
RK		 2041 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2042 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2043out_unlock:
2b35bd83 2044 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2045 sdhci_runtime_pm_put(host);
b513ea25
AN		 2046
2047 return err;
2048}
2049
cb849648
AH		 2050static int sdhci_select_drive_strength(struct mmc_card *card,
2051 unsigned int max_dtr, int host_drv,
2052 int card_drv, int *drv_type)
2053{
2054 struct sdhci_host *host = mmc_priv(card->host);
2055
2056 if (!host->ops->select_drive_strength)
2057 return 0;
2058
2059 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2060 card_drv, drv_type);
2061}
52983382
KL		 2062
2063static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2064{
4d55c5a1
AN		 2065 /* Host Controller v3.00 defines preset value registers */
2066 if (host->version < SDHCI_SPEC_300)
2067 return;
2068
4d55c5a1
AN		 2069 /*
2070 * We only enable or disable Preset Value if they are not already
2071 * enabled or disabled respectively. Otherwise, we bail out.
2072 */
da91a8f9
RK		 2073 if (host->preset_enabled != enable) {
2074 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2075
2076 if (enable)
2077 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2078 else
2079 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2080
4d55c5a1 2081 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2082
2083 if (enable)
2084 host->flags |= SDHCI_PV_ENABLED;
2085 else
2086 host->flags &= ~SDHCI_PV_ENABLED;
2087
2088 host->preset_enabled = enable;
4d55c5a1 2089 }
66fd8ad5
AH		 2090}
2091
348487cb
HC		 2092static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2093 int err)
2094{
2095 struct sdhci_host *host = mmc_priv(mmc);
2096 struct mmc_data *data = mrq->data;
2097
771a3dc2
RK		 2098 if (data->host_cookie == COOKIE_GIVEN ||
2099 data->host_cookie == COOKIE_MAPPED)
2100 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2101 data->flags & MMC_DATA_WRITE ?
2102 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2103
2104 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2105}
2106
2107static int sdhci_pre_dma_transfer(struct sdhci_host *host,
d31911b9 2108 struct mmc_data *data)
348487cb
HC		 2109{
2110 int sg_count;
2111
d31911b9
HC		 2112 if (data->host_cookie == COOKIE_MAPPED) {
2113 data->host_cookie = COOKIE_GIVEN;
2114 return data->sg_count;
348487cb
HC		 2115 }
2116
d31911b9 2117 WARN_ON(data->host_cookie == COOKIE_GIVEN);
348487cb 2118
d31911b9
HC		 2119 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2120 data->flags & MMC_DATA_WRITE ?
2121 DMA_TO_DEVICE : DMA_FROM_DEVICE);
348487cb
HC		 2122
2123 if (sg_count == 0)
d31911b9 2124 return -ENOSPC;
348487cb 2125
d31911b9
HC		 2126 data->sg_count = sg_count;
2127 data->host_cookie = COOKIE_MAPPED;
348487cb
HC		 2128
2129 return sg_count;
2130}
2131
2132static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2133 bool is_first_req)
2134{
2135 struct sdhci_host *host = mmc_priv(mmc);
2136
d31911b9 2137 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2138
2139 if (host->flags & SDHCI_REQ_USE_DMA)
d31911b9 2140 sdhci_pre_dma_transfer(host, mrq->data);
348487cb
HC		 2141}
2142
71e69211 2143static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2144{
71e69211 2145 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2146 unsigned long flags;
2836766a 2147 int present;
d129bceb 2148
722e1280
CD		 2149 /* First check if client has provided their own card event */
2150 if (host->ops->card_event)
2151 host->ops->card_event(host);
2152
2836766a
KK		 2153 present = sdhci_do_get_cd(host);
2154
d129bceb
PO		 2155 spin_lock_irqsave(&host->lock, flags);
2156
66fd8ad5 2157 /* Check host->mrq first in case we are runtime suspended */
2836766a 2158 if (host->mrq && !present) {
a3c76eb9 2159 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2160 mmc_hostname(host->mmc));
a3c76eb9 2161 pr_err("%s: Resetting controller.\n",
66fd8ad5 2162 mmc_hostname(host->mmc));
d129bceb 2163
03231f9b
RK		 2164 sdhci_do_reset(host, SDHCI_RESET_CMD);
2165 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2166
66fd8ad5
AH		 2167 host->mrq->cmd->error = -ENOMEDIUM;
2168 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2169 }
2170
2171 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2172}
2173
2174static const struct mmc_host_ops sdhci_ops = {
2175 .request = sdhci_request,
348487cb
HC		 2176 .post_req = sdhci_post_req,
2177 .pre_req = sdhci_pre_req,
71e69211 2178 .set_ios = sdhci_set_ios,
94144a46 2179 .get_cd = sdhci_get_cd,
71e69211
GL		 2180 .get_ro = sdhci_get_ro,
2181 .hw_reset = sdhci_hw_reset,
2182 .enable_sdio_irq = sdhci_enable_sdio_irq,
2183 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2184 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2185 .execute_tuning = sdhci_execute_tuning,
cb849648 2186 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2187 .card_event = sdhci_card_event,
20b92a30 2188 .card_busy = sdhci_card_busy,
71e69211
GL		 2189};
2190
2191/*****************************************************************************\
2192 * *
2193 * Tasklets *
2194 * *
2195\*****************************************************************************/
2196
d129bceb
PO		 2197static void sdhci_tasklet_finish(unsigned long param)
2198{
2199 struct sdhci_host *host;
2200 unsigned long flags;
2201 struct mmc_request *mrq;
2202
2203 host = (struct sdhci_host*)param;
2204
66fd8ad5
AH		 2205 spin_lock_irqsave(&host->lock, flags);
2206
0c9c99a7
CB		 2207 /*
2208 * If this tasklet gets rescheduled while running, it will
2209 * be run again afterwards but without any active request.
2210 */
66fd8ad5
AH		 2211 if (!host->mrq) {
2212 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2213 return;
66fd8ad5 2214 }
d129bceb
PO		 2215
2216 del_timer(&host->timer);
2217
2218 mrq = host->mrq;
2219
054cedff
RK		 2220 /*
2221 * Always unmap the data buffers if they were mapped by
2222 * sdhci_prepare_data() whenever we finish with a request.
2223 * This avoids leaking DMA mappings on error.
2224 */
2225 if (host->flags & SDHCI_REQ_USE_DMA) {
2226 struct mmc_data *data = mrq->data;
2227
2228 if (data && data->host_cookie == COOKIE_MAPPED) {
2229 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2230 (data->flags & MMC_DATA_READ) ?
2231 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2232 data->host_cookie = COOKIE_UNMAPPED;
2233 }
2234 }
2235
d129bceb
PO		 2236 /*
2237 * The controller needs a reset of internal state machines
2238 * upon error conditions.
2239 */
1e72859e 2240 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2241 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2242 (mrq->sbc && mrq->sbc->error) ||
2243 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2244 (mrq->data->stop && mrq->data->stop->error))) ||
2245 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2246
2247 /* Some controllers need this kick or reset won't work here */
8213af3b 2248 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2249 /* This is to force an update */
1771059c 2250 host->ops->set_clock(host, host->clock);
645289dc
PO		 2251
2252 /* Spec says we should do both at the same time, but Ricoh
2253 controllers do not like that. */
03231f9b
RK		 2254 sdhci_do_reset(host, SDHCI_RESET_CMD);
2255 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2256 }
2257
2258 host->mrq = NULL;
2259 host->cmd = NULL;
2260 host->data = NULL;
2261
f9134319 2262#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2263 sdhci_deactivate_led(host);
2f730fec 2264#endif
d129bceb 2265
5f25a66f 2266 mmiowb();
d129bceb
PO		 2267 spin_unlock_irqrestore(&host->lock, flags);
2268
2269 mmc_request_done(host->mmc, mrq);
66fd8ad5 2270 sdhci_runtime_pm_put(host);
d129bceb
PO		 2271}
2272
2273static void sdhci_timeout_timer(unsigned long data)
2274{
2275 struct sdhci_host *host;
2276 unsigned long flags;
2277
2278 host = (struct sdhci_host*)data;
2279
2280 spin_lock_irqsave(&host->lock, flags);
2281
2282 if (host->mrq) {
2e4456f0
MV		 2283 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2284 mmc_hostname(host->mmc));
d129bceb
PO		 2285 sdhci_dumpregs(host);
2286
2287 if (host->data) {
17b0429d 2288 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2289 sdhci_finish_data(host);
2290 } else {
2291 if (host->cmd)
17b0429d 2292 host->cmd->error = -ETIMEDOUT;
d129bceb 2293 else
17b0429d 2294 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2295
2296 tasklet_schedule(&host->finish_tasklet);
2297 }
2298 }
2299
5f25a66f 2300 mmiowb();
d129bceb
PO		 2301 spin_unlock_irqrestore(&host->lock, flags);
2302}
2303
2304/*****************************************************************************\
2305 * *
2306 * Interrupt handling *
2307 * *
2308\*****************************************************************************/
2309
61541397 2310static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2311{
2312 BUG_ON(intmask == 0);
2313
2314 if (!host->cmd) {
2e4456f0
MV		 2315 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2316 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2317 sdhci_dumpregs(host);
2318 return;
2319 }
2320
ec014cba
RK		 2321 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2322 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2323 if (intmask & SDHCI_INT_TIMEOUT)
2324 host->cmd->error = -ETIMEDOUT;
2325 else
2326 host->cmd->error = -EILSEQ;
43b58b36 2327
71fcbda0
RK		 2328 /*
2329 * If this command initiates a data phase and a response
2330 * CRC error is signalled, the card can start transferring
2331 * data - the card may have received the command without
2332 * error. We must not terminate the mmc_request early.
2333 *
2334 * If the card did not receive the command or returned an
2335 * error which prevented it sending data, the data phase
2336 * will time out.
2337 */
2338 if (host->cmd->data &&
2339 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2340 SDHCI_INT_CRC) {
2341 host->cmd = NULL;
2342 return;
2343 }
2344
d129bceb 2345 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2346 return;
2347 }
2348
2349 /*
2350 * The host can send and interrupt when the busy state has
2351 * ended, allowing us to wait without wasting CPU cycles.
2352 * Unfortunately this is overloaded on the "data complete"
2353 * interrupt, so we need to take some care when handling
2354 * it.
2355 *
2356 * Note: The 1.0 specification is a bit ambiguous about this
2357 * feature so there might be some problems with older
2358 * controllers.
2359 */
2360 if (host->cmd->flags & MMC_RSP_BUSY) {
2361 if (host->cmd->data)
2e4456f0 2362 DBG("Cannot wait for busy signal when also doing a data transfer");
e99783a4
CM		 2363 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2364 && !host->busy_handle) {
2365 /* Mark that command complete before busy is ended */
2366 host->busy_handle = 1;
e809517f 2367 return;
e99783a4 2368 }
f945405c
BD		 2369
2370 /* The controller does not support the end-of-busy IRQ,
2371 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2372 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2373 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2374 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2375 }
2376
2377 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2378 sdhci_finish_command(host);
d129bceb
PO		 2379}
2380
0957c333 2381#ifdef CONFIG_MMC_DEBUG
08621b18 2382static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2383{
2384 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2385 void *desc = host->adma_table;
6882a8c0
BD		 2386
2387 sdhci_dumpregs(host);
2388
2389 while (true) {
e57a5f61
AH		 2390 struct sdhci_adma2_64_desc *dma_desc = desc;
2391
2392 if (host->flags & SDHCI_USE_64_BIT_DMA)
2393 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2394 name, desc, le32_to_cpu(dma_desc->addr_hi),
2395 le32_to_cpu(dma_desc->addr_lo),
2396 le16_to_cpu(dma_desc->len),
2397 le16_to_cpu(dma_desc->cmd));
2398 else
2399 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2400 name, desc, le32_to_cpu(dma_desc->addr_lo),
2401 le16_to_cpu(dma_desc->len),
2402 le16_to_cpu(dma_desc->cmd));
6882a8c0 2403
76fe379a 2404 desc += host->desc_sz;
6882a8c0 2405
0545230f 2406 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2407 break;
2408 }
2409}
2410#else
08621b18 2411static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2412#endif
2413
d129bceb
PO		 2414static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2415{
069c9f14 2416 u32 command;
d129bceb
PO		 2417 BUG_ON(intmask == 0);
2418
b513ea25
AN		 2419 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2420 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2421 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2422 if (command == MMC_SEND_TUNING_BLOCK ||
2423 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2424 host->tuning_done = 1;
2425 wake_up(&host->buf_ready_int);
2426 return;
2427 }
2428 }
2429
d129bceb
PO		 2430 if (!host->data) {
2431 /*
e809517f
PO		 2432 * The "data complete" interrupt is also used to
2433 * indicate that a busy state has ended. See comment
2434 * above in sdhci_cmd_irq().
d129bceb 2435 */
e809517f 2436 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2437 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2438 host->cmd->error = -ETIMEDOUT;
2439 tasklet_schedule(&host->finish_tasklet);
2440 return;
2441 }
e809517f 2442 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2443 /*
2444 * Some cards handle busy-end interrupt
2445 * before the command completed, so make
2446 * sure we do things in the proper order.
2447 */
2448 if (host->busy_handle)
2449 sdhci_finish_command(host);
2450 else
2451 host->busy_handle = 1;
e809517f
PO		 2452 return;
2453 }
2454 }
d129bceb 2455
2e4456f0
MV		 2456 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2457 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2458 sdhci_dumpregs(host);
2459
2460 return;
2461 }
2462
2463 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2464 host->data->error = -ETIMEDOUT;
22113efd
AL		 2465 else if (intmask & SDHCI_INT_DATA_END_BIT)
2466 host->data->error = -EILSEQ;
2467 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2468 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2469 != MMC_BUS_TEST_R)
17b0429d 2470 host->data->error = -EILSEQ;
6882a8c0 2471 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2472 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2473 sdhci_adma_show_error(host);
2134a922 2474 host->data->error = -EIO;
a4071fbb
HZ		 2475 if (host->ops->adma_workaround)
2476 host->ops->adma_workaround(host, intmask);
6882a8c0 2477 }
d129bceb 2478
17b0429d 2479 if (host->data->error)
d129bceb
PO		 2480 sdhci_finish_data(host);
2481 else {
a406f5a3 2482 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2483 sdhci_transfer_pio(host);
2484
6ba736a1
PO		 2485 /*
2486 * We currently don't do anything fancy with DMA
2487 * boundaries, but as we can't disable the feature
2488 * we need to at least restart the transfer.
f6a03cbf
MV		 2489 *
2490 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2491 * should return a valid address to continue from, but as
2492 * some controllers are faulty, don't trust them.
6ba736a1 2493 */
f6a03cbf
MV		 2494 if (intmask & SDHCI_INT_DMA_END) {
2495 u32 dmastart, dmanow;
2496 dmastart = sg_dma_address(host->data->sg);
2497 dmanow = dmastart + host->data->bytes_xfered;
2498 /*
2499 * Force update to the next DMA block boundary.
2500 */
2501 dmanow = (dmanow &
2502 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2503 SDHCI_DEFAULT_BOUNDARY_SIZE;
2504 host->data->bytes_xfered = dmanow - dmastart;
2505 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2506 " next 0x%08x\n",
2507 mmc_hostname(host->mmc), dmastart,
2508 host->data->bytes_xfered, dmanow);
2509 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2510 }
6ba736a1 2511
e538fbe8
PO		 2512 if (intmask & SDHCI_INT_DATA_END) {
2513 if (host->cmd) {
2514 /*
2515 * Data managed to finish before the
2516 * command completed. Make sure we do
2517 * things in the proper order.
2518 */
2519 host->data_early = 1;
2520 } else {
2521 sdhci_finish_data(host);
2522 }
2523 }
d129bceb
PO		 2524 }
2525}
2526
7d12e780 2527static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2528{
781e989c 2529 irqreturn_t result = IRQ_NONE;
66fd8ad5 2530 struct sdhci_host *host = dev_id;
41005003 2531 u32 intmask, mask, unexpected = 0;
781e989c 2532 int max_loops = 16;
d129bceb
PO		 2533
2534 spin_lock(&host->lock);
2535
be138554 2536 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2537 spin_unlock(&host->lock);
655bca76 2538 return IRQ_NONE;
66fd8ad5
AH		 2539 }
2540
4e4141a5 2541 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2542 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2543 result = IRQ_NONE;
2544 goto out;
2545 }
2546
41005003
RK		 2547 do {
2548 /* Clear selected interrupts. */
2549 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2550 SDHCI_INT_BUS_POWER);
2551 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2552
41005003
RK		 2553 DBG("*** %s got interrupt: 0x%08x\n",
2554 mmc_hostname(host->mmc), intmask);
d129bceb 2555
41005003
RK		 2556 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2557 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2558 SDHCI_CARD_PRESENT;
d129bceb 2559
41005003
RK		 2560 /*
2561 * There is a observation on i.mx esdhc. INSERT
2562 * bit will be immediately set again when it gets
2563 * cleared, if a card is inserted. We have to mask
2564 * the irq to prevent interrupt storm which will
2565 * freeze the system. And the REMOVE gets the
2566 * same situation.
2567 *
2568 * More testing are needed here to ensure it works
2569 * for other platforms though.
2570 */
b537f94c
RK		 2571 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2572 SDHCI_INT_CARD_REMOVE);
2573 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2574 SDHCI_INT_CARD_INSERT;
2575 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2576 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2577
2578 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2579 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2580
2581 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2582 SDHCI_INT_CARD_REMOVE);
2583 result = IRQ_WAKE_THREAD;
41005003 2584 }
d129bceb 2585
41005003 2586 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2587 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2588 &intmask);
964f9ce2 2589
41005003
RK		 2590 if (intmask & SDHCI_INT_DATA_MASK)
2591 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2592
41005003
RK		 2593 if (intmask & SDHCI_INT_BUS_POWER)
2594 pr_err("%s: Card is consuming too much power!\n",
2595 mmc_hostname(host->mmc));
3192a28f 2596
781e989c
RK		 2597 if (intmask & SDHCI_INT_CARD_INT) {
2598 sdhci_enable_sdio_irq_nolock(host, false);
2599 host->thread_isr |= SDHCI_INT_CARD_INT;
2600 result = IRQ_WAKE_THREAD;
2601 }
f75979b7 2602
41005003
RK		 2603 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2604 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2605 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2606 SDHCI_INT_CARD_INT);
f75979b7 2607
41005003
RK		 2608 if (intmask) {
2609 unexpected |= intmask;
2610 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2611 }
d129bceb 2612
781e989c
RK		 2613 if (result == IRQ_NONE)
2614 result = IRQ_HANDLED;
d129bceb 2615
41005003 2616 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2617 } while (intmask && --max_loops);
d129bceb
PO		 2618out:
2619 spin_unlock(&host->lock);
2620
6379b237
AS		 2621 if (unexpected) {
2622 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2623 mmc_hostname(host->mmc), unexpected);
2624 sdhci_dumpregs(host);
2625 }
f75979b7 2626
d129bceb
PO		 2627 return result;
2628}
2629
781e989c
RK		 2630static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2631{
2632 struct sdhci_host *host = dev_id;
2633 unsigned long flags;
2634 u32 isr;
2635
2636 spin_lock_irqsave(&host->lock, flags);
2637 isr = host->thread_isr;
2638 host->thread_isr = 0;
2639 spin_unlock_irqrestore(&host->lock, flags);
2640
3560db8e
RK		 2641 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2642 sdhci_card_event(host->mmc);
2643 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2644 }
2645
781e989c
RK		 2646 if (isr & SDHCI_INT_CARD_INT) {
2647 sdio_run_irqs(host->mmc);
2648
2649 spin_lock_irqsave(&host->lock, flags);
2650 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2651 sdhci_enable_sdio_irq_nolock(host, true);
2652 spin_unlock_irqrestore(&host->lock, flags);
2653 }
2654
2655 return isr ? IRQ_HANDLED : IRQ_NONE;
2656}
2657
d129bceb
PO		 2658/*****************************************************************************\
2659 * *
2660 * Suspend/resume *
2661 * *
2662\*****************************************************************************/
2663
2664#ifdef CONFIG_PM
ad080d79
KL		 2665void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2666{
2667 u8 val;
2668 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2669 | SDHCI_WAKE_ON_INT;
2670
2671 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2672 val |= mask ;
2673 /* Avoid fake wake up */
2674 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2675 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2676 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2677}
2678EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2679
0b10f478 2680static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2681{
2682 u8 val;
2683 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2684 | SDHCI_WAKE_ON_INT;
2685
2686 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2687 val &= ~mask;
2688 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2689}
d129bceb 2690
29495aa0 2691int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2692{
7260cf5e
AV		 2693 sdhci_disable_card_detection(host);
2694
66c39dfc
AH		 2695 mmc_retune_timer_stop(host->mmc);
2696 mmc_retune_needed(host->mmc);
cf2b5eea 2697
ad080d79 2698 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2699 host->ier = 0;
2700 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2701 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2702 free_irq(host->irq, host);
2703 } else {
2704 sdhci_enable_irq_wakeups(host);
2705 enable_irq_wake(host->irq);
2706 }
4ee14ec6 2707 return 0;
d129bceb
PO		 2708}
2709
b8c86fc5 2710EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2711
b8c86fc5
PO		 2712int sdhci_resume_host(struct sdhci_host *host)
2713{
4ee14ec6 2714 int ret = 0;
d129bceb 2715
a13abc7b 2716 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2717 if (host->ops->enable_dma)
2718 host->ops->enable_dma(host);
2719 }
d129bceb 2720
6308d290
AH		 2721 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2722 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2723 /* Card keeps power but host controller does not */
2724 sdhci_init(host, 0);
2725 host->pwr = 0;
2726 host->clock = 0;
2727 sdhci_do_set_ios(host, &host->mmc->ios);
2728 } else {
2729 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2730 mmiowb();
2731 }
b8c86fc5 2732
14a7b416
HC		 2733 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2734 ret = request_threaded_irq(host->irq, sdhci_irq,
2735 sdhci_thread_irq, IRQF_SHARED,
2736 mmc_hostname(host->mmc), host);
2737 if (ret)
2738 return ret;
2739 } else {
2740 sdhci_disable_irq_wakeups(host);
2741 disable_irq_wake(host->irq);
2742 }
2743
7260cf5e
AV		 2744 sdhci_enable_card_detection(host);
2745
2f4cbb3d 2746 return ret;
d129bceb
PO		 2747}
2748
b8c86fc5 2749EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2750
2751static int sdhci_runtime_pm_get(struct sdhci_host *host)
2752{
2753 return pm_runtime_get_sync(host->mmc->parent);
2754}
2755
2756static int sdhci_runtime_pm_put(struct sdhci_host *host)
2757{
2758 pm_runtime_mark_last_busy(host->mmc->parent);
2759 return pm_runtime_put_autosuspend(host->mmc->parent);
2760}
2761
f0710a55
AH		 2762static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2763{
5c671c41 2764 if (host->bus_on)
f0710a55
AH		 2765 return;
2766 host->bus_on = true;
2767 pm_runtime_get_noresume(host->mmc->parent);
2768}
2769
2770static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2771{
5c671c41 2772 if (!host->bus_on)
f0710a55
AH		 2773 return;
2774 host->bus_on = false;
2775 pm_runtime_put_noidle(host->mmc->parent);
2776}
2777
66fd8ad5
AH		 2778int sdhci_runtime_suspend_host(struct sdhci_host *host)
2779{
2780 unsigned long flags;
66fd8ad5 2781
66c39dfc
AH		 2782 mmc_retune_timer_stop(host->mmc);
2783 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2784
2785 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2786 host->ier &= SDHCI_INT_CARD_INT;
2787 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2788 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2789 spin_unlock_irqrestore(&host->lock, flags);
2790
781e989c 2791 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2792
2793 spin_lock_irqsave(&host->lock, flags);
2794 host->runtime_suspended = true;
2795 spin_unlock_irqrestore(&host->lock, flags);
2796
8a125bad 2797 return 0;
66fd8ad5
AH		 2798}
2799EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2800
2801int sdhci_runtime_resume_host(struct sdhci_host *host)
2802{
2803 unsigned long flags;
8a125bad 2804 int host_flags = host->flags;
66fd8ad5
AH		 2805
2806 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2807 if (host->ops->enable_dma)
2808 host->ops->enable_dma(host);
2809 }
2810
2811 sdhci_init(host, 0);
2812
2813 /* Force clock and power re-program */
2814 host->pwr = 0;
2815 host->clock = 0;
3396e736 2816 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2817 sdhci_do_set_ios(host, &host->mmc->ios);
2818
52983382
KL		 2819 if ((host_flags & SDHCI_PV_ENABLED) &&
2820 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2821 spin_lock_irqsave(&host->lock, flags);
2822 sdhci_enable_preset_value(host, true);
2823 spin_unlock_irqrestore(&host->lock, flags);
2824 }
66fd8ad5 2825
66fd8ad5
AH		 2826 spin_lock_irqsave(&host->lock, flags);
2827
2828 host->runtime_suspended = false;
2829
2830 /* Enable SDIO IRQ */
ef104333 2831 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2832 sdhci_enable_sdio_irq_nolock(host, true);
2833
2834 /* Enable Card Detection */
2835 sdhci_enable_card_detection(host);
2836
2837 spin_unlock_irqrestore(&host->lock, flags);
2838
8a125bad 2839 return 0;
66fd8ad5
AH		 2840}
2841EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2842
162d6f98 2843#endif /* CONFIG_PM */
66fd8ad5 2844
d129bceb
PO		 2845/*****************************************************************************\
2846 * *
b8c86fc5 2847 * Device allocation/registration *
d129bceb
PO		 2848 * *
2849\*****************************************************************************/
2850
b8c86fc5
PO		 2851struct sdhci_host *sdhci_alloc_host(struct device *dev,
2852 size_t priv_size)
d129bceb 2853{
d129bceb
PO		 2854 struct mmc_host *mmc;
2855 struct sdhci_host *host;
2856
b8c86fc5 2857 WARN_ON(dev == NULL);
d129bceb 2858
b8c86fc5 2859 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2860 if (!mmc)
b8c86fc5 2861 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2862
2863 host = mmc_priv(mmc);
2864 host->mmc = mmc;
bf60e592
AH		 2865 host->mmc_host_ops = sdhci_ops;
2866 mmc->ops = &host->mmc_host_ops;
d129bceb 2867
b8c86fc5
PO		 2868 return host;
2869}
8a4da143 2870
b8c86fc5 2871EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2872
b8c86fc5
PO		 2873int sdhci_add_host(struct sdhci_host *host)
2874{
2875 struct mmc_host *mmc;
bd6a8c30 2876 u32 caps[2] = {0, 0};
f2119df6
AN		 2877 u32 max_current_caps;
2878 unsigned int ocr_avail;
f5fa92e5 2879 unsigned int override_timeout_clk;
59241757 2880 u32 max_clk;
b8c86fc5 2881 int ret;
d129bceb 2882
b8c86fc5
PO		 2883 WARN_ON(host == NULL);
2884 if (host == NULL)
2885 return -EINVAL;
d129bceb 2886
b8c86fc5 2887 mmc = host->mmc;
d129bceb 2888
b8c86fc5
PO		 2889 if (debug_quirks)
2890 host->quirks = debug_quirks;
66fd8ad5
AH		 2891 if (debug_quirks2)
2892 host->quirks2 = debug_quirks2;
d129bceb 2893
f5fa92e5
AH		 2894 override_timeout_clk = host->timeout_clk;
2895
03231f9b 2896 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2897
4e4141a5 2898 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2899 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2900 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2901 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2902 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2903 mmc_hostname(mmc), host->version);
4a965505
PO		 2904 }
2905
f2119df6 2906 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2907 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2908
bd6a8c30
PR		 2909 if (host->version >= SDHCI_SPEC_300)
2910 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2911 host->caps1 :
2912 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2913
b8c86fc5 2914 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2915 host->flags |= SDHCI_USE_SDMA;
f2119df6 2916 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2917 DBG("Controller doesn't have SDMA capability\n");
67435274 2918 else
a13abc7b 2919 host->flags |= SDHCI_USE_SDMA;
d129bceb 2920
b8c86fc5 2921 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2922 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2923 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2924 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2925 }
2926
f2119df6
AN		 2927 if ((host->version >= SDHCI_SPEC_200) &&
2928 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2929 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2930
2931 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2932 (host->flags & SDHCI_USE_ADMA)) {
2933 DBG("Disabling ADMA as it is marked broken\n");
2934 host->flags &= ~SDHCI_USE_ADMA;
2935 }
2936
e57a5f61
AH		 2937 /*
2938 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2939 * and *must* do 64-bit DMA. A driver has the opportunity to change
2940 * that during the first call to ->enable_dma(). Similarly
2941 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2942 * implement.
2943 */
5eaa7476 2944 if (caps[0] & SDHCI_CAN_64BIT)
e57a5f61
AH		 2945 host->flags |= SDHCI_USE_64_BIT_DMA;
2946
a13abc7b 2947 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2948 if (host->ops->enable_dma) {
2949 if (host->ops->enable_dma(host)) {
6606110d 2950 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2951 mmc_hostname(mmc));
a13abc7b
RR		 2952 host->flags &=
2953 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2954 }
d129bceb
PO		 2955 }
2956 }
2957
e57a5f61
AH		 2958 /* SDMA does not support 64-bit DMA */
2959 if (host->flags & SDHCI_USE_64_BIT_DMA)
2960 host->flags &= ~SDHCI_USE_SDMA;
2961
2134a922
PO		 2962 if (host->flags & SDHCI_USE_ADMA) {
2963 /*
76fe379a
AH		 2964 * The DMA descriptor table size is calculated as the maximum
2965 * number of segments times 2, to allow for an alignment
2966 * descriptor for each segment, plus 1 for a nop end descriptor,
2967 * all multipled by the descriptor size.
2134a922 2968 */
e57a5f61
AH		 2969 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2970 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2971 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2972 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2973 } else {
2974 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2975 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2976 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2977 }
4efaa6fb 2978 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
76fe379a 2979 host->adma_table_sz,
4efaa6fb
AH		 2980 &host->adma_addr,
2981 GFP_KERNEL);
04a5ae6f 2982 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
edd63fcc
RK		 2983 host->align_buffer = dma_alloc_coherent(mmc_dev(mmc),
2984 host->align_buffer_sz,
2985 &host->align_addr,
2986 GFP_KERNEL);
4efaa6fb 2987 if (!host->adma_table || !host->align_buffer) {
7ac02036
PF		 2988 if (host->adma_table)
2989 dma_free_coherent(mmc_dev(mmc),
2990 host->adma_table_sz,
2991 host->adma_table,
2992 host->adma_addr);
edd63fcc
RK		 2993 if (host->align_buffer)
2994 dma_free_coherent(mmc_dev(mmc),
2995 host->align_buffer_sz,
2996 host->align_buffer,
2997 host->align_addr);
6606110d 2998 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2999 mmc_hostname(mmc));
3000 host->flags &= ~SDHCI_USE_ADMA;
4efaa6fb 3001 host->adma_table = NULL;
d1e49f77 3002 host->align_buffer = NULL;
04a5ae6f 3003 } else if (host->adma_addr & (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 3004 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3005 mmc_hostname(mmc));
d1e49f77 3006 host->flags &= ~SDHCI_USE_ADMA;
76fe379a 3007 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3008 host->adma_table, host->adma_addr);
edd63fcc
RK		 3009 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz,
3010 host->align_buffer, host->align_addr);
4efaa6fb 3011 host->adma_table = NULL;
d1e49f77 3012 host->align_buffer = NULL;
2134a922 3013 }
edd63fcc
RK		 3014
3015 /* dma_alloc_coherent returns page aligned and sized buffers */
3016 BUG_ON(host->align_addr & SDHCI_ADMA2_MASK);
2134a922
PO		 3017 }
3018
7659150c
PO		 3019 /*
3020 * If we use DMA, then it's up to the caller to set the DMA
3021 * mask, but PIO does not need the hw shim so we set a new
3022 * mask here in that case.
3023 */
a13abc7b 3024 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3025 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3026 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3027 }
d129bceb 3028
c4687d5f 3029 if (host->version >= SDHCI_SPEC_300)
f2119df6 3030 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3031 >> SDHCI_CLOCK_BASE_SHIFT;
3032 else
f2119df6 3033 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3034 >> SDHCI_CLOCK_BASE_SHIFT;
3035
4240ff0a 3036 host->max_clk *= 1000000;
f27f47ef
AV		 3037 if (host->max_clk == 0 || host->quirks &
3038 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3039 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3040 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3041 mmc_hostname(mmc));
4240ff0a
BD		 3042 return -ENODEV;
3043 }
3044 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3045 }
d129bceb 3046
c3ed3877
AN		 3047 /*
3048 * In case of Host Controller v3.00, find out whether clock
3049 * multiplier is supported.
3050 */
3051 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3052 SDHCI_CLOCK_MUL_SHIFT;
3053
3054 /*
3055 * In case the value in Clock Multiplier is 0, then programmable
3056 * clock mode is not supported, otherwise the actual clock
3057 * multiplier is one more than the value of Clock Multiplier
3058 * in the Capabilities Register.
3059 */
3060 if (host->clk_mul)
3061 host->clk_mul += 1;
3062
d129bceb
PO		 3063 /*
3064 * Set host parameters.
3065 */
59241757
DA		 3066 max_clk = host->max_clk;
3067
ce5f036b 3068 if (host->ops->get_min_clock)
a9e58f25 3069 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3070 else if (host->version >= SDHCI_SPEC_300) {
3071 if (host->clk_mul) {
3072 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3073 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3074 } else
3075 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3076 } else
0397526d 3077 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3078
59241757
DA		 3079 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3080 mmc->f_max = max_clk;
3081
28aab053
AD		 3082 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3083 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3084 SDHCI_TIMEOUT_CLK_SHIFT;
3085 if (host->timeout_clk == 0) {
3086 if (host->ops->get_timeout_clock) {
3087 host->timeout_clk =
3088 host->ops->get_timeout_clock(host);
3089 } else {
3090 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3091 mmc_hostname(mmc));
3092 return -ENODEV;
3093 }
272308ca 3094 }
272308ca 3095
28aab053
AD		 3096 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3097 host->timeout_clk *= 1000;
272308ca 3098
28aab053 3099 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3100 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3101 mmc->max_busy_timeout /= host->timeout_clk;
3102 }
58d1246d 3103
f5fa92e5
AH		 3104 if (override_timeout_clk)
3105 host->timeout_clk = override_timeout_clk;
3106
e89d456f 3107 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3108 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3109
3110 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3111 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3112
8edf6371 3113 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3114 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3115 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3116 !(host->flags & SDHCI_USE_SDMA)) &&
3117 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3118 host->flags |= SDHCI_AUTO_CMD23;
3119 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3120 } else {
3121 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3122 }
3123
15ec4461
PR		 3124 /*
3125 * A controller may support 8-bit width, but the board itself
3126 * might not have the pins brought out. Boards that support
3127 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3128 * their platform code before calling sdhci_add_host(), and we
3129 * won't assume 8-bit width for hosts without that CAP.
3130 */
5fe23c7f 3131 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3132 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3133
63ef5d8c
JH		 3134 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3135 mmc->caps &= ~MMC_CAP_CMD23;
3136
f2119df6 3137 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3138 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3139
176d1ed4 3140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
c31d22eb
II		 3141 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3142 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
68d1fb7e
AV		 3143 mmc->caps |= MMC_CAP_NEEDS_POLL;
3144
3a48edc4
TK		 3145 /* If there are external regulators, get them */
3146 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3147 return -EPROBE_DEFER;
3148
6231f3de 3149 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3150 if (!IS_ERR(mmc->supply.vqmmc)) {
3151 ret = regulator_enable(mmc->supply.vqmmc);
3152 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3153 1950000))
8363c374
KL		 3154 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3155 SDHCI_SUPPORT_SDR50 |
3156 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3157 if (ret) {
3158 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3159 mmc_hostname(mmc), ret);
4bb74313 3160 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3161 }
8363c374 3162 }
6231f3de 3163
6a66180a
DD		 3164 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3165 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3166 SDHCI_SUPPORT_DDR50);
3167
4188bba0
AC		 3168 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3169 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3170 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3171 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3172
3173 /* SDR104 supports also implies SDR50 support */
156e14b1 3174 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3175 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3176 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3177 * field can be promoted to support HS200.
3178 */
549c0b18 3179 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3180 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3181 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3182 mmc->caps |= MMC_CAP_UHS_SDR50;
3183
e9fb05d5
AH		 3184 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3185 (caps[1] & SDHCI_SUPPORT_HS400))
3186 mmc->caps2 |= MMC_CAP2_HS400;
3187
549c0b18
AH		 3188 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3189 (IS_ERR(mmc->supply.vqmmc) ||
3190 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3191 1300000)))
3192 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3193
9107ebbf
MC		 3194 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3195 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3196 mmc->caps |= MMC_CAP_UHS_DDR50;
3197
069c9f14 3198 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3199 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3200 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3201
156e14b1 3202 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3203 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3204 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3205
d6d50a15
AN		 3206 /* Driver Type(s) (A, C, D) supported by the host */
3207 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3208 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3209 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3210 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3211 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3212 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3213
cf2b5eea
AN		 3214 /* Initial value for re-tuning timer count */
3215 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3216 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3217
3218 /*
3219 * In case Re-tuning Timer is not disabled, the actual value of
3220 * re-tuning timer will be 2 ^ (n - 1).
3221 */
3222 if (host->tuning_count)
3223 host->tuning_count = 1 << (host->tuning_count - 1);
3224
3225 /* Re-tuning mode supported by the Host Controller */
3226 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3227 SDHCI_RETUNING_MODE_SHIFT;
3228
8f230f45 3229 ocr_avail = 0;
bad37e1a 3230
f2119df6
AN		 3231 /*
3232 * According to SD Host Controller spec v3.00, if the Host System
3233 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3234 * the value is meaningful only if Voltage Support in the Capabilities
3235 * register is set. The actual current value is 4 times the register
3236 * value.
3237 */
3238 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3239 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3240 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3241 if (curr > 0) {
3242
3243 /* convert to SDHCI_MAX_CURRENT format */
3244 curr = curr/1000; /* convert to mA */
3245 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3246
3247 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3248 max_current_caps =
3249 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3250 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3251 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3252 }
3253 }
f2119df6
AN		 3254
3255 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3256 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3257
55c4665e 3258 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3259 SDHCI_MAX_CURRENT_330_MASK) >>
3260 SDHCI_MAX_CURRENT_330_SHIFT) *
3261 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3262 }
3263 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3264 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3265
55c4665e 3266 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3267 SDHCI_MAX_CURRENT_300_MASK) >>
3268 SDHCI_MAX_CURRENT_300_SHIFT) *
3269 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3270 }
3271 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3272 ocr_avail |= MMC_VDD_165_195;
3273
55c4665e 3274 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3275 SDHCI_MAX_CURRENT_180_MASK) >>
3276 SDHCI_MAX_CURRENT_180_SHIFT) *
3277 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3278 }
3279
5fd26c7e
UH		 3280 /* If OCR set by host, use it instead. */
3281 if (host->ocr_mask)
3282 ocr_avail = host->ocr_mask;
3283
3284 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3285 if (mmc->ocr_avail)
52221610 3286 ocr_avail = mmc->ocr_avail;
3a48edc4 3287
8f230f45
TI		 3288 mmc->ocr_avail = ocr_avail;
3289 mmc->ocr_avail_sdio = ocr_avail;
3290 if (host->ocr_avail_sdio)
3291 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3292 mmc->ocr_avail_sd = ocr_avail;
3293 if (host->ocr_avail_sd)
3294 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3295 else /* normal SD controllers don't support 1.8V */
3296 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3297 mmc->ocr_avail_mmc = ocr_avail;
3298 if (host->ocr_avail_mmc)
3299 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3300
3301 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3302 pr_err("%s: Hardware doesn't report any support voltages.\n",
3303 mmc_hostname(mmc));
b8c86fc5 3304 return -ENODEV;
146ad66e
PO		 3305 }
3306
d129bceb
PO		 3307 spin_lock_init(&host->lock);
3308
3309 /*
2134a922
PO		 3310 * Maximum number of segments. Depends on if the hardware
3311 * can do scatter/gather or not.
d129bceb 3312 */
2134a922 3313 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3314 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3315 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3316 mmc->max_segs = 1;
2134a922 3317 else /* PIO */
4fb213f8 3318 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3319
3320 /*
ac00531d
AH		 3321 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3322 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3323 * is less anyway.
d129bceb 3324 */
55db890a 3325 mmc->max_req_size = 524288;
d129bceb
PO		 3326
3327 /*
3328 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3329 * of bytes. When doing hardware scatter/gather, each entry cannot
3330 * be larger than 64 KiB though.
d129bceb 3331 */
30652aa3
OJ		 3332 if (host->flags & SDHCI_USE_ADMA) {
3333 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3334 mmc->max_seg_size = 65535;
3335 else
3336 mmc->max_seg_size = 65536;
3337 } else {
2134a922 3338 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3339 }
d129bceb 3340
fe4a3c7a
PO		 3341 /*
3342 * Maximum block size. This varies from controller to controller and
3343 * is specified in the capabilities register.
3344 */
0633f654
AV		 3345 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3346 mmc->max_blk_size = 2;
3347 } else {
f2119df6 3348 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3349 SDHCI_MAX_BLOCK_SHIFT;
3350 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3351 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3352 mmc_hostname(mmc));
0633f654
AV		 3353 mmc->max_blk_size = 0;
3354 }
3355 }
3356
3357 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3358
55db890a
PO		 3359 /*
3360 * Maximum block count.
3361 */
1388eefd 3362 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3363
d129bceb
PO		 3364 /*
3365 * Init tasklets.
3366 */
d129bceb
PO		 3367 tasklet_init(&host->finish_tasklet,
3368 sdhci_tasklet_finish, (unsigned long)host);
3369
e4cad1b5 3370 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3371
250fb7b4 3372 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3373
2af502ca
SG		 3374 sdhci_init(host, 0);
3375
781e989c
RK		 3376 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3377 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3378 if (ret) {
3379 pr_err("%s: Failed to request IRQ %d: %d\n",
3380 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3381 goto untasklet;
0fc81ee3 3382 }
d129bceb 3383
d129bceb
PO		 3384#ifdef CONFIG_MMC_DEBUG
3385 sdhci_dumpregs(host);
3386#endif
3387
f9134319 3388#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3389 snprintf(host->led_name, sizeof(host->led_name),
3390 "%s::", mmc_hostname(mmc));
3391 host->led.name = host->led_name;
2f730fec
PO		 3392 host->led.brightness = LED_OFF;
3393 host->led.default_trigger = mmc_hostname(mmc);
3394 host->led.brightness_set = sdhci_led_control;
3395
b8c86fc5 3396 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3397 if (ret) {
3398 pr_err("%s: Failed to register LED device: %d\n",
3399 mmc_hostname(mmc), ret);
2f730fec 3400 goto reset;
0fc81ee3 3401 }
2f730fec
PO		 3402#endif
3403
5f25a66f
PO		 3404 mmiowb();
3405
d129bceb
PO		 3406 mmc_add_host(mmc);
3407
a3c76eb9 3408 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3409 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3410 (host->flags & SDHCI_USE_ADMA) ?
3411 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3412 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3413
7260cf5e
AV		 3414 sdhci_enable_card_detection(host);
3415
d129bceb
PO		 3416 return 0;
3417
f9134319 3418#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3419reset:
03231f9b 3420 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3421 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3422 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3423 free_irq(host->irq, host);
3424#endif
8ef1a143 3425untasklet:
d129bceb 3426 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3427
3428 return ret;
3429}
3430
b8c86fc5 3431EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3432
1e72859e 3433void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3434{
3a48edc4 3435 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3436 unsigned long flags;
3437
3438 if (dead) {
3439 spin_lock_irqsave(&host->lock, flags);
3440
3441 host->flags |= SDHCI_DEVICE_DEAD;
3442
3443 if (host->mrq) {
a3c76eb9 3444 pr_err("%s: Controller removed during "
4e743f1f 3445 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3446
3447 host->mrq->cmd->error = -ENOMEDIUM;
3448 tasklet_schedule(&host->finish_tasklet);
3449 }
3450
3451 spin_unlock_irqrestore(&host->lock, flags);
3452 }
3453
7260cf5e
AV		 3454 sdhci_disable_card_detection(host);
3455
4e743f1f 3456 mmc_remove_host(mmc);
d129bceb 3457
f9134319 3458#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3459 led_classdev_unregister(&host->led);
3460#endif
3461
1e72859e 3462 if (!dead)
03231f9b 3463 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3464
b537f94c
RK		 3465 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3466 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3467 free_irq(host->irq, host);
3468
3469 del_timer_sync(&host->timer);
3470
d129bceb 3471 tasklet_kill(&host->finish_tasklet);
2134a922 3472
3a48edc4
TK		 3473 if (!IS_ERR(mmc->supply.vqmmc))
3474 regulator_disable(mmc->supply.vqmmc);
6231f3de 3475
4efaa6fb 3476 if (host->adma_table)
76fe379a 3477 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3478 host->adma_table, host->adma_addr);
edd63fcc
RK		 3479 if (host->align_buffer)
3480 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz,
3481 host->align_buffer, host->align_addr);
2134a922 3482
4efaa6fb 3483 host->adma_table = NULL;
2134a922 3484 host->align_buffer = NULL;
d129bceb
PO		 3485}
3486
b8c86fc5 3487EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3488
b8c86fc5 3489void sdhci_free_host(struct sdhci_host *host)
d129bceb 3490{
b8c86fc5 3491 mmc_free_host(host->mmc);
d129bceb
PO		 3492}
3493
b8c86fc5 3494EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3495
3496/*****************************************************************************\
3497 * *
3498 * Driver init/exit *
3499 * *
3500\*****************************************************************************/
3501
3502static int __init sdhci_drv_init(void)
3503{
a3c76eb9 3504 pr_info(DRIVER_NAME
52fbf9c9 3505 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3506 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3507
b8c86fc5 3508 return 0;
d129bceb
PO		 3509}
3510
3511static void __exit sdhci_drv_exit(void)
3512{
d129bceb
PO		 3513}
3514
3515module_init(sdhci_drv_init);
3516module_exit(sdhci_drv_exit);
3517
df673b22 3518module_param(debug_quirks, uint, 0444);
66fd8ad5 3519module_param(debug_quirks2, uint, 0444);
67435274 3520
32710e8f 3521MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3522MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3523MODULE_LICENSE("GPL");
67435274 3524
df673b22 3525MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3526MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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