Commit | Line | Data |
---|---|---|
d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
88b47679 | 19 | #include <linux/module.h> |
d129bceb | 20 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
11763609 | 22 | #include <linux/scatterlist.h> |
9bea3c85 | 23 | #include <linux/regulator/consumer.h> |
66fd8ad5 | 24 | #include <linux/pm_runtime.h> |
d129bceb | 25 | |
2f730fec PO |
26 | #include <linux/leds.h> |
27 | ||
22113efd | 28 | #include <linux/mmc/mmc.h> |
d129bceb | 29 | #include <linux/mmc/host.h> |
473b095a | 30 | #include <linux/mmc/card.h> |
85cc1c33 | 31 | #include <linux/mmc/sdio.h> |
bec9d4e5 | 32 | #include <linux/mmc/slot-gpio.h> |
d129bceb | 33 | |
d129bceb PO |
34 | #include "sdhci.h" |
35 | ||
36 | #define DRIVER_NAME "sdhci" | |
d129bceb | 37 | |
d129bceb | 38 | #define DBG(f, x...) \ |
c6563178 | 39 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 40 | |
f9134319 PO |
41 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
42 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
43 | #define SDHCI_USE_LEDS_CLASS | |
44 | #endif | |
45 | ||
b513ea25 AN |
46 | #define MAX_TUNING_LOOP 40 |
47 | ||
df673b22 | 48 | static unsigned int debug_quirks = 0; |
66fd8ad5 | 49 | static unsigned int debug_quirks2; |
67435274 | 50 | |
d129bceb PO |
51 | static void sdhci_finish_data(struct sdhci_host *); |
52 | ||
d129bceb | 53 | static void sdhci_finish_command(struct sdhci_host *); |
069c9f14 | 54 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); |
52983382 | 55 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); |
04e079cf | 56 | static int sdhci_do_get_cd(struct sdhci_host *host); |
d129bceb | 57 | |
162d6f98 | 58 | #ifdef CONFIG_PM |
66fd8ad5 AH |
59 | static int sdhci_runtime_pm_get(struct sdhci_host *host); |
60 | static int sdhci_runtime_pm_put(struct sdhci_host *host); | |
f0710a55 AH |
61 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); |
62 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); | |
66fd8ad5 AH |
63 | #else |
64 | static inline int sdhci_runtime_pm_get(struct sdhci_host *host) | |
65 | { | |
66 | return 0; | |
67 | } | |
68 | static inline int sdhci_runtime_pm_put(struct sdhci_host *host) | |
69 | { | |
70 | return 0; | |
71 | } | |
f0710a55 AH |
72 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
73 | { | |
74 | } | |
75 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) | |
76 | { | |
77 | } | |
66fd8ad5 AH |
78 | #endif |
79 | ||
d129bceb PO |
80 | static void sdhci_dumpregs(struct sdhci_host *host) |
81 | { | |
a3c76eb9 | 82 | pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
412ab659 | 83 | mmc_hostname(host->mmc)); |
d129bceb | 84 | |
a3c76eb9 | 85 | pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", |
4e4141a5 AV |
86 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
87 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
a3c76eb9 | 88 | pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
89 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
90 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
a3c76eb9 | 91 | pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
92 | sdhci_readl(host, SDHCI_ARGUMENT), |
93 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
a3c76eb9 | 94 | pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
95 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
96 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
a3c76eb9 | 97 | pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
98 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
99 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
a3c76eb9 | 100 | pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
101 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
102 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
a3c76eb9 | 103 | pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
104 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
105 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
a3c76eb9 | 106 | pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
107 | sdhci_readl(host, SDHCI_INT_ENABLE), |
108 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
a3c76eb9 | 109 | pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
110 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
111 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
a3c76eb9 | 112 | pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
4e4141a5 | 113 | sdhci_readl(host, SDHCI_CAPABILITIES), |
e8120ad1 | 114 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
a3c76eb9 | 115 | pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", |
e8120ad1 | 116 | sdhci_readw(host, SDHCI_COMMAND), |
4e4141a5 | 117 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
a3c76eb9 | 118 | pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", |
f2119df6 | 119 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); |
d129bceb | 120 | |
e57a5f61 AH |
121 | if (host->flags & SDHCI_USE_ADMA) { |
122 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
123 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", | |
124 | readl(host->ioaddr + SDHCI_ADMA_ERROR), | |
125 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), | |
126 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
127 | else | |
128 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", | |
129 | readl(host->ioaddr + SDHCI_ADMA_ERROR), | |
130 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
131 | } | |
be3f4ae0 | 132 | |
a3c76eb9 | 133 | pr_debug(DRIVER_NAME ": ===========================================\n"); |
d129bceb PO |
134 | } |
135 | ||
136 | /*****************************************************************************\ | |
137 | * * | |
138 | * Low level functions * | |
139 | * * | |
140 | \*****************************************************************************/ | |
141 | ||
7260cf5e AV |
142 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) |
143 | { | |
5b4f1f6c | 144 | u32 present; |
7260cf5e | 145 | |
c79396c1 | 146 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
87b87a3f | 147 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
66fd8ad5 AH |
148 | return; |
149 | ||
5b4f1f6c RK |
150 | if (enable) { |
151 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
152 | SDHCI_CARD_PRESENT; | |
d25928d1 | 153 | |
5b4f1f6c RK |
154 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
155 | SDHCI_INT_CARD_INSERT; | |
156 | } else { | |
157 | host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); | |
158 | } | |
b537f94c RK |
159 | |
160 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
161 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
7260cf5e AV |
162 | } |
163 | ||
164 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
165 | { | |
166 | sdhci_set_card_detection(host, true); | |
167 | } | |
168 | ||
169 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
170 | { | |
171 | sdhci_set_card_detection(host, false); | |
172 | } | |
173 | ||
03231f9b | 174 | void sdhci_reset(struct sdhci_host *host, u8 mask) |
d129bceb | 175 | { |
e16514d8 | 176 | unsigned long timeout; |
393c1a34 | 177 | |
4e4141a5 | 178 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 179 | |
f0710a55 | 180 | if (mask & SDHCI_RESET_ALL) { |
d129bceb | 181 | host->clock = 0; |
f0710a55 AH |
182 | /* Reset-all turns off SD Bus Power */ |
183 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) | |
184 | sdhci_runtime_pm_bus_off(host); | |
185 | } | |
d129bceb | 186 | |
e16514d8 PO |
187 | /* Wait max 100 ms */ |
188 | timeout = 100; | |
189 | ||
190 | /* hw clears the bit when it's done */ | |
4e4141a5 | 191 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 192 | if (timeout == 0) { |
a3c76eb9 | 193 | pr_err("%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
194 | mmc_hostname(host->mmc), (int)mask); |
195 | sdhci_dumpregs(host); | |
196 | return; | |
197 | } | |
198 | timeout--; | |
199 | mdelay(1); | |
d129bceb | 200 | } |
03231f9b RK |
201 | } |
202 | EXPORT_SYMBOL_GPL(sdhci_reset); | |
203 | ||
204 | static void sdhci_do_reset(struct sdhci_host *host, u8 mask) | |
205 | { | |
206 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { | |
135b0a28 | 207 | if (!sdhci_do_get_cd(host)) |
03231f9b RK |
208 | return; |
209 | } | |
063a9dbb | 210 | |
03231f9b | 211 | host->ops->reset(host, mask); |
393c1a34 | 212 | |
da91a8f9 RK |
213 | if (mask & SDHCI_RESET_ALL) { |
214 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
215 | if (host->ops->enable_dma) | |
216 | host->ops->enable_dma(host); | |
217 | } | |
218 | ||
219 | /* Resetting the controller clears many */ | |
220 | host->preset_enabled = false; | |
3abc1e80 | 221 | } |
d129bceb PO |
222 | } |
223 | ||
2f4cbb3d NP |
224 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
225 | ||
226 | static void sdhci_init(struct sdhci_host *host, int soft) | |
d129bceb | 227 | { |
2f4cbb3d | 228 | if (soft) |
03231f9b | 229 | sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); |
2f4cbb3d | 230 | else |
03231f9b | 231 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d129bceb | 232 | |
b537f94c RK |
233 | host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
234 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | | |
235 | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | | |
236 | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | | |
237 | SDHCI_INT_RESPONSE; | |
238 | ||
239 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
240 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
2f4cbb3d NP |
241 | |
242 | if (soft) { | |
243 | /* force clock reconfiguration */ | |
244 | host->clock = 0; | |
245 | sdhci_set_ios(host->mmc, &host->mmc->ios); | |
246 | } | |
7260cf5e | 247 | } |
d129bceb | 248 | |
7260cf5e AV |
249 | static void sdhci_reinit(struct sdhci_host *host) |
250 | { | |
2f4cbb3d | 251 | sdhci_init(host, 0); |
7260cf5e | 252 | sdhci_enable_card_detection(host); |
d129bceb PO |
253 | } |
254 | ||
255 | static void sdhci_activate_led(struct sdhci_host *host) | |
256 | { | |
257 | u8 ctrl; | |
258 | ||
4e4141a5 | 259 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 260 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 261 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
262 | } |
263 | ||
264 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
265 | { | |
266 | u8 ctrl; | |
267 | ||
4e4141a5 | 268 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 269 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 270 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
271 | } |
272 | ||
f9134319 | 273 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
274 | static void sdhci_led_control(struct led_classdev *led, |
275 | enum led_brightness brightness) | |
276 | { | |
277 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
278 | unsigned long flags; | |
279 | ||
280 | spin_lock_irqsave(&host->lock, flags); | |
281 | ||
66fd8ad5 AH |
282 | if (host->runtime_suspended) |
283 | goto out; | |
284 | ||
2f730fec PO |
285 | if (brightness == LED_OFF) |
286 | sdhci_deactivate_led(host); | |
287 | else | |
288 | sdhci_activate_led(host); | |
66fd8ad5 | 289 | out: |
2f730fec PO |
290 | spin_unlock_irqrestore(&host->lock, flags); |
291 | } | |
292 | #endif | |
293 | ||
d129bceb PO |
294 | /*****************************************************************************\ |
295 | * * | |
296 | * Core functions * | |
297 | * * | |
298 | \*****************************************************************************/ | |
299 | ||
a406f5a3 | 300 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 301 | { |
7659150c PO |
302 | unsigned long flags; |
303 | size_t blksize, len, chunk; | |
7244b85b | 304 | u32 uninitialized_var(scratch); |
7659150c | 305 | u8 *buf; |
d129bceb | 306 | |
a406f5a3 | 307 | DBG("PIO reading\n"); |
d129bceb | 308 | |
a406f5a3 | 309 | blksize = host->data->blksz; |
7659150c | 310 | chunk = 0; |
d129bceb | 311 | |
7659150c | 312 | local_irq_save(flags); |
d129bceb | 313 | |
a406f5a3 | 314 | while (blksize) { |
bf3a35ac | 315 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
d129bceb | 316 | |
7659150c | 317 | len = min(host->sg_miter.length, blksize); |
d129bceb | 318 | |
7659150c PO |
319 | blksize -= len; |
320 | host->sg_miter.consumed = len; | |
14d836e7 | 321 | |
7659150c | 322 | buf = host->sg_miter.addr; |
d129bceb | 323 | |
7659150c PO |
324 | while (len) { |
325 | if (chunk == 0) { | |
4e4141a5 | 326 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 327 | chunk = 4; |
a406f5a3 | 328 | } |
7659150c PO |
329 | |
330 | *buf = scratch & 0xFF; | |
331 | ||
332 | buf++; | |
333 | scratch >>= 8; | |
334 | chunk--; | |
335 | len--; | |
d129bceb | 336 | } |
a406f5a3 | 337 | } |
7659150c PO |
338 | |
339 | sg_miter_stop(&host->sg_miter); | |
340 | ||
341 | local_irq_restore(flags); | |
a406f5a3 | 342 | } |
d129bceb | 343 | |
a406f5a3 PO |
344 | static void sdhci_write_block_pio(struct sdhci_host *host) |
345 | { | |
7659150c PO |
346 | unsigned long flags; |
347 | size_t blksize, len, chunk; | |
348 | u32 scratch; | |
349 | u8 *buf; | |
d129bceb | 350 | |
a406f5a3 PO |
351 | DBG("PIO writing\n"); |
352 | ||
353 | blksize = host->data->blksz; | |
7659150c PO |
354 | chunk = 0; |
355 | scratch = 0; | |
d129bceb | 356 | |
7659150c | 357 | local_irq_save(flags); |
d129bceb | 358 | |
a406f5a3 | 359 | while (blksize) { |
bf3a35ac | 360 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
a406f5a3 | 361 | |
7659150c PO |
362 | len = min(host->sg_miter.length, blksize); |
363 | ||
364 | blksize -= len; | |
365 | host->sg_miter.consumed = len; | |
366 | ||
367 | buf = host->sg_miter.addr; | |
d129bceb | 368 | |
7659150c PO |
369 | while (len) { |
370 | scratch |= (u32)*buf << (chunk * 8); | |
371 | ||
372 | buf++; | |
373 | chunk++; | |
374 | len--; | |
375 | ||
376 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 377 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
378 | chunk = 0; |
379 | scratch = 0; | |
d129bceb | 380 | } |
d129bceb PO |
381 | } |
382 | } | |
7659150c PO |
383 | |
384 | sg_miter_stop(&host->sg_miter); | |
385 | ||
386 | local_irq_restore(flags); | |
a406f5a3 PO |
387 | } |
388 | ||
389 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
390 | { | |
391 | u32 mask; | |
392 | ||
393 | BUG_ON(!host->data); | |
394 | ||
7659150c | 395 | if (host->blocks == 0) |
a406f5a3 PO |
396 | return; |
397 | ||
398 | if (host->data->flags & MMC_DATA_READ) | |
399 | mask = SDHCI_DATA_AVAILABLE; | |
400 | else | |
401 | mask = SDHCI_SPACE_AVAILABLE; | |
402 | ||
4a3cba32 PO |
403 | /* |
404 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
405 | * for transfers < 4 bytes. As long as it is just one block, | |
406 | * we can ignore the bits. | |
407 | */ | |
408 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
409 | (host->data->blocks == 1)) | |
410 | mask = ~0; | |
411 | ||
4e4141a5 | 412 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
413 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
414 | udelay(100); | |
415 | ||
a406f5a3 PO |
416 | if (host->data->flags & MMC_DATA_READ) |
417 | sdhci_read_block_pio(host); | |
418 | else | |
419 | sdhci_write_block_pio(host); | |
d129bceb | 420 | |
7659150c PO |
421 | host->blocks--; |
422 | if (host->blocks == 0) | |
a406f5a3 | 423 | break; |
a406f5a3 | 424 | } |
d129bceb | 425 | |
a406f5a3 | 426 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
427 | } |
428 | ||
48857d9b | 429 | static int sdhci_pre_dma_transfer(struct sdhci_host *host, |
c0999b72 | 430 | struct mmc_data *data, int cookie) |
48857d9b RK |
431 | { |
432 | int sg_count; | |
433 | ||
94538e51 RK |
434 | /* |
435 | * If the data buffers are already mapped, return the previous | |
436 | * dma_map_sg() result. | |
437 | */ | |
438 | if (data->host_cookie == COOKIE_PRE_MAPPED) | |
48857d9b | 439 | return data->sg_count; |
48857d9b RK |
440 | |
441 | sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
442 | data->flags & MMC_DATA_WRITE ? | |
443 | DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
444 | ||
445 | if (sg_count == 0) | |
446 | return -ENOSPC; | |
447 | ||
448 | data->sg_count = sg_count; | |
c0999b72 | 449 | data->host_cookie = cookie; |
48857d9b RK |
450 | |
451 | return sg_count; | |
452 | } | |
453 | ||
2134a922 PO |
454 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
455 | { | |
456 | local_irq_save(*flags); | |
482fce99 | 457 | return kmap_atomic(sg_page(sg)) + sg->offset; |
2134a922 PO |
458 | } |
459 | ||
460 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
461 | { | |
482fce99 | 462 | kunmap_atomic(buffer); |
2134a922 PO |
463 | local_irq_restore(*flags); |
464 | } | |
465 | ||
e57a5f61 AH |
466 | static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, |
467 | dma_addr_t addr, int len, unsigned cmd) | |
118cd17d | 468 | { |
e57a5f61 | 469 | struct sdhci_adma2_64_desc *dma_desc = desc; |
118cd17d | 470 | |
e57a5f61 | 471 | /* 32-bit and 64-bit descriptors have these members in same position */ |
0545230f AH |
472 | dma_desc->cmd = cpu_to_le16(cmd); |
473 | dma_desc->len = cpu_to_le16(len); | |
e57a5f61 AH |
474 | dma_desc->addr_lo = cpu_to_le32((u32)addr); |
475 | ||
476 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
477 | dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); | |
118cd17d BD |
478 | } |
479 | ||
b5ffa674 AH |
480 | static void sdhci_adma_mark_end(void *desc) |
481 | { | |
e57a5f61 | 482 | struct sdhci_adma2_64_desc *dma_desc = desc; |
b5ffa674 | 483 | |
e57a5f61 | 484 | /* 32-bit and 64-bit descriptors have 'cmd' in same position */ |
0545230f | 485 | dma_desc->cmd |= cpu_to_le16(ADMA2_END); |
b5ffa674 AH |
486 | } |
487 | ||
60c64762 RK |
488 | static void sdhci_adma_table_pre(struct sdhci_host *host, |
489 | struct mmc_data *data, int sg_count) | |
2134a922 | 490 | { |
2134a922 | 491 | struct scatterlist *sg; |
2134a922 | 492 | unsigned long flags; |
acc3ad13 RK |
493 | dma_addr_t addr, align_addr; |
494 | void *desc, *align; | |
495 | char *buffer; | |
496 | int len, offset, i; | |
2134a922 PO |
497 | |
498 | /* | |
499 | * The spec does not specify endianness of descriptor table. | |
500 | * We currently guess that it is LE. | |
501 | */ | |
502 | ||
60c64762 | 503 | host->sg_count = sg_count; |
2134a922 | 504 | |
4efaa6fb | 505 | desc = host->adma_table; |
2134a922 PO |
506 | align = host->align_buffer; |
507 | ||
508 | align_addr = host->align_addr; | |
509 | ||
510 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
511 | addr = sg_dma_address(sg); | |
512 | len = sg_dma_len(sg); | |
513 | ||
514 | /* | |
acc3ad13 RK |
515 | * The SDHCI specification states that ADMA addresses must |
516 | * be 32-bit aligned. If they aren't, then we use a bounce | |
517 | * buffer for the (up to three) bytes that screw up the | |
2134a922 PO |
518 | * alignment. |
519 | */ | |
04a5ae6f AH |
520 | offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & |
521 | SDHCI_ADMA2_MASK; | |
2134a922 PO |
522 | if (offset) { |
523 | if (data->flags & MMC_DATA_WRITE) { | |
524 | buffer = sdhci_kmap_atomic(sg, &flags); | |
525 | memcpy(align, buffer, offset); | |
526 | sdhci_kunmap_atomic(buffer, &flags); | |
527 | } | |
528 | ||
118cd17d | 529 | /* tran, valid */ |
e57a5f61 | 530 | sdhci_adma_write_desc(host, desc, align_addr, offset, |
739d46dc | 531 | ADMA2_TRAN_VALID); |
2134a922 PO |
532 | |
533 | BUG_ON(offset > 65536); | |
534 | ||
04a5ae6f AH |
535 | align += SDHCI_ADMA2_ALIGN; |
536 | align_addr += SDHCI_ADMA2_ALIGN; | |
2134a922 | 537 | |
76fe379a | 538 | desc += host->desc_sz; |
2134a922 PO |
539 | |
540 | addr += offset; | |
541 | len -= offset; | |
542 | } | |
543 | ||
2134a922 PO |
544 | BUG_ON(len > 65536); |
545 | ||
347ea32d AH |
546 | if (len) { |
547 | /* tran, valid */ | |
548 | sdhci_adma_write_desc(host, desc, addr, len, | |
549 | ADMA2_TRAN_VALID); | |
550 | desc += host->desc_sz; | |
551 | } | |
2134a922 PO |
552 | |
553 | /* | |
554 | * If this triggers then we have a calculation bug | |
555 | * somewhere. :/ | |
556 | */ | |
76fe379a | 557 | WARN_ON((desc - host->adma_table) >= host->adma_table_sz); |
2134a922 PO |
558 | } |
559 | ||
70764a90 | 560 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
acc3ad13 | 561 | /* Mark the last descriptor as the terminating descriptor */ |
4efaa6fb | 562 | if (desc != host->adma_table) { |
76fe379a | 563 | desc -= host->desc_sz; |
b5ffa674 | 564 | sdhci_adma_mark_end(desc); |
70764a90 TA |
565 | } |
566 | } else { | |
acc3ad13 | 567 | /* Add a terminating entry - nop, end, valid */ |
e57a5f61 | 568 | sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); |
70764a90 | 569 | } |
2134a922 PO |
570 | } |
571 | ||
572 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
573 | struct mmc_data *data) | |
574 | { | |
2134a922 PO |
575 | struct scatterlist *sg; |
576 | int i, size; | |
1c3d5f6d | 577 | void *align; |
2134a922 PO |
578 | char *buffer; |
579 | unsigned long flags; | |
580 | ||
47fa9613 RK |
581 | if (data->flags & MMC_DATA_READ) { |
582 | bool has_unaligned = false; | |
de0b65a7 | 583 | |
47fa9613 RK |
584 | /* Do a quick scan of the SG list for any unaligned mappings */ |
585 | for_each_sg(data->sg, sg, host->sg_count, i) | |
586 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { | |
587 | has_unaligned = true; | |
588 | break; | |
589 | } | |
2134a922 | 590 | |
47fa9613 RK |
591 | if (has_unaligned) { |
592 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | |
f55c98f7 | 593 | data->sg_len, DMA_FROM_DEVICE); |
2134a922 | 594 | |
47fa9613 | 595 | align = host->align_buffer; |
2134a922 | 596 | |
47fa9613 RK |
597 | for_each_sg(data->sg, sg, host->sg_count, i) { |
598 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { | |
599 | size = SDHCI_ADMA2_ALIGN - | |
600 | (sg_dma_address(sg) & SDHCI_ADMA2_MASK); | |
601 | ||
602 | buffer = sdhci_kmap_atomic(sg, &flags); | |
603 | memcpy(buffer, align, size); | |
604 | sdhci_kunmap_atomic(buffer, &flags); | |
2134a922 | 605 | |
47fa9613 RK |
606 | align += SDHCI_ADMA2_ALIGN; |
607 | } | |
2134a922 PO |
608 | } |
609 | } | |
610 | } | |
2134a922 PO |
611 | } |
612 | ||
a3c7778f | 613 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb | 614 | { |
1c8cde92 | 615 | u8 count; |
a3c7778f | 616 | struct mmc_data *data = cmd->data; |
1c8cde92 | 617 | unsigned target_timeout, current_timeout; |
d129bceb | 618 | |
ee53ab5d PO |
619 | /* |
620 | * If the host controller provides us with an incorrect timeout | |
621 | * value, just skip the check and use 0xE. The hardware may take | |
622 | * longer to time out, but that's much better than having a too-short | |
623 | * timeout value. | |
624 | */ | |
11a2f1b7 | 625 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
ee53ab5d | 626 | return 0xE; |
e538fbe8 | 627 | |
a3c7778f | 628 | /* Unspecified timeout, assume max */ |
1d4d7744 | 629 | if (!data && !cmd->busy_timeout) |
a3c7778f | 630 | return 0xE; |
d129bceb | 631 | |
a3c7778f AW |
632 | /* timeout in us */ |
633 | if (!data) | |
1d4d7744 | 634 | target_timeout = cmd->busy_timeout * 1000; |
78a2ca27 | 635 | else { |
fafcfda9 | 636 | target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); |
7f05538a RK |
637 | if (host->clock && data->timeout_clks) { |
638 | unsigned long long val; | |
639 | ||
640 | /* | |
641 | * data->timeout_clks is in units of clock cycles. | |
642 | * host->clock is in Hz. target_timeout is in us. | |
643 | * Hence, us = 1000000 * cycles / Hz. Round up. | |
644 | */ | |
645 | val = 1000000 * data->timeout_clks; | |
646 | if (do_div(val, host->clock)) | |
647 | target_timeout++; | |
648 | target_timeout += val; | |
649 | } | |
78a2ca27 | 650 | } |
81b39802 | 651 | |
1c8cde92 PO |
652 | /* |
653 | * Figure out needed cycles. | |
654 | * We do this in steps in order to fit inside a 32 bit int. | |
655 | * The first step is the minimum timeout, which will have a | |
656 | * minimum resolution of 6 bits: | |
657 | * (1) 2^13*1000 > 2^22, | |
658 | * (2) host->timeout_clk < 2^16 | |
659 | * => | |
660 | * (1) / (2) > 2^6 | |
661 | */ | |
662 | count = 0; | |
663 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
664 | while (current_timeout < target_timeout) { | |
665 | count++; | |
666 | current_timeout <<= 1; | |
667 | if (count >= 0xF) | |
668 | break; | |
669 | } | |
670 | ||
671 | if (count >= 0xF) { | |
09eeff52 CB |
672 | DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", |
673 | mmc_hostname(host->mmc), count, cmd->opcode); | |
1c8cde92 PO |
674 | count = 0xE; |
675 | } | |
676 | ||
ee53ab5d PO |
677 | return count; |
678 | } | |
679 | ||
6aa943ab AV |
680 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
681 | { | |
682 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
683 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
684 | ||
685 | if (host->flags & SDHCI_REQ_USE_DMA) | |
b537f94c | 686 | host->ier = (host->ier & ~pio_irqs) | dma_irqs; |
6aa943ab | 687 | else |
b537f94c RK |
688 | host->ier = (host->ier & ~dma_irqs) | pio_irqs; |
689 | ||
690 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
691 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
6aa943ab AV |
692 | } |
693 | ||
b45e668a | 694 | static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
ee53ab5d PO |
695 | { |
696 | u8 count; | |
b45e668a AD |
697 | |
698 | if (host->ops->set_timeout) { | |
699 | host->ops->set_timeout(host, cmd); | |
700 | } else { | |
701 | count = sdhci_calc_timeout(host, cmd); | |
702 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); | |
703 | } | |
704 | } | |
705 | ||
706 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) | |
707 | { | |
2134a922 | 708 | u8 ctrl; |
a3c7778f | 709 | struct mmc_data *data = cmd->data; |
ee53ab5d PO |
710 | |
711 | WARN_ON(host->data); | |
712 | ||
b45e668a AD |
713 | if (data || (cmd->flags & MMC_RSP_BUSY)) |
714 | sdhci_set_timeout(host, cmd); | |
a3c7778f AW |
715 | |
716 | if (!data) | |
ee53ab5d PO |
717 | return; |
718 | ||
719 | /* Sanity checks */ | |
720 | BUG_ON(data->blksz * data->blocks > 524288); | |
721 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
722 | BUG_ON(data->blocks > 65535); | |
723 | ||
724 | host->data = data; | |
725 | host->data_early = 0; | |
f6a03cbf | 726 | host->data->bytes_xfered = 0; |
ee53ab5d | 727 | |
fce14421 | 728 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
2134a922 | 729 | struct scatterlist *sg; |
df953925 | 730 | unsigned int length_mask, offset_mask; |
a0eaf0f9 | 731 | int i; |
2134a922 | 732 | |
fce14421 RK |
733 | host->flags |= SDHCI_REQ_USE_DMA; |
734 | ||
735 | /* | |
736 | * FIXME: This doesn't account for merging when mapping the | |
737 | * scatterlist. | |
738 | * | |
739 | * The assumption here being that alignment and lengths are | |
740 | * the same after DMA mapping to device address space. | |
741 | */ | |
a0eaf0f9 | 742 | length_mask = 0; |
df953925 | 743 | offset_mask = 0; |
2134a922 | 744 | if (host->flags & SDHCI_USE_ADMA) { |
df953925 | 745 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { |
a0eaf0f9 | 746 | length_mask = 3; |
df953925 RK |
747 | /* |
748 | * As we use up to 3 byte chunks to work | |
749 | * around alignment problems, we need to | |
750 | * check the offset as well. | |
751 | */ | |
752 | offset_mask = 3; | |
753 | } | |
2134a922 PO |
754 | } else { |
755 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
a0eaf0f9 | 756 | length_mask = 3; |
df953925 RK |
757 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) |
758 | offset_mask = 3; | |
2134a922 PO |
759 | } |
760 | ||
df953925 | 761 | if (unlikely(length_mask | offset_mask)) { |
2134a922 | 762 | for_each_sg(data->sg, sg, data->sg_len, i) { |
a0eaf0f9 | 763 | if (sg->length & length_mask) { |
2e4456f0 | 764 | DBG("Reverting to PIO because of transfer size (%d)\n", |
a0eaf0f9 | 765 | sg->length); |
2134a922 PO |
766 | host->flags &= ~SDHCI_REQ_USE_DMA; |
767 | break; | |
768 | } | |
a0eaf0f9 | 769 | if (sg->offset & offset_mask) { |
2e4456f0 | 770 | DBG("Reverting to PIO because of bad alignment\n"); |
2134a922 PO |
771 | host->flags &= ~SDHCI_REQ_USE_DMA; |
772 | break; | |
773 | } | |
774 | } | |
775 | } | |
776 | } | |
777 | ||
8f1934ce | 778 | if (host->flags & SDHCI_REQ_USE_DMA) { |
c0999b72 | 779 | int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); |
60c64762 RK |
780 | |
781 | if (sg_cnt <= 0) { | |
782 | /* | |
783 | * This only happens when someone fed | |
784 | * us an invalid request. | |
785 | */ | |
786 | WARN_ON(1); | |
787 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
788 | } else if (host->flags & SDHCI_USE_ADMA) { | |
789 | sdhci_adma_table_pre(host, data, sg_cnt); | |
790 | ||
791 | sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); | |
792 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
793 | sdhci_writel(host, | |
794 | (u64)host->adma_addr >> 32, | |
795 | SDHCI_ADMA_ADDRESS_HI); | |
8f1934ce | 796 | } else { |
60c64762 RK |
797 | WARN_ON(sg_cnt != 1); |
798 | sdhci_writel(host, sg_dma_address(data->sg), | |
799 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
800 | } |
801 | } | |
802 | ||
2134a922 PO |
803 | /* |
804 | * Always adjust the DMA selection as some controllers | |
805 | * (e.g. JMicron) can't do PIO properly when the selection | |
806 | * is ADMA. | |
807 | */ | |
808 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 809 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
810 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
811 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
e57a5f61 AH |
812 | (host->flags & SDHCI_USE_ADMA)) { |
813 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
814 | ctrl |= SDHCI_CTRL_ADMA64; | |
815 | else | |
816 | ctrl |= SDHCI_CTRL_ADMA32; | |
817 | } else { | |
2134a922 | 818 | ctrl |= SDHCI_CTRL_SDMA; |
e57a5f61 | 819 | } |
4e4141a5 | 820 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
821 | } |
822 | ||
8f1934ce | 823 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
da60a91d SAS |
824 | int flags; |
825 | ||
826 | flags = SG_MITER_ATOMIC; | |
827 | if (host->data->flags & MMC_DATA_READ) | |
828 | flags |= SG_MITER_TO_SG; | |
829 | else | |
830 | flags |= SG_MITER_FROM_SG; | |
831 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
7659150c | 832 | host->blocks = data->blocks; |
d129bceb | 833 | } |
c7fa9963 | 834 | |
6aa943ab AV |
835 | sdhci_set_transfer_irqs(host); |
836 | ||
f6a03cbf MV |
837 | /* Set the DMA boundary value and block size */ |
838 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, | |
839 | data->blksz), SDHCI_BLOCK_SIZE); | |
4e4141a5 | 840 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
c7fa9963 PO |
841 | } |
842 | ||
843 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
e89d456f | 844 | struct mmc_command *cmd) |
c7fa9963 | 845 | { |
d3fc5d71 | 846 | u16 mode = 0; |
e89d456f | 847 | struct mmc_data *data = cmd->data; |
c7fa9963 | 848 | |
2b558c13 | 849 | if (data == NULL) { |
9b8ffea6 VW |
850 | if (host->quirks2 & |
851 | SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { | |
852 | sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); | |
853 | } else { | |
2b558c13 | 854 | /* clear Auto CMD settings for no data CMDs */ |
9b8ffea6 VW |
855 | mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); |
856 | sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | | |
2b558c13 | 857 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); |
9b8ffea6 | 858 | } |
c7fa9963 | 859 | return; |
2b558c13 | 860 | } |
c7fa9963 | 861 | |
e538fbe8 PO |
862 | WARN_ON(!host->data); |
863 | ||
d3fc5d71 VY |
864 | if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) |
865 | mode = SDHCI_TRNS_BLK_CNT_EN; | |
866 | ||
e89d456f | 867 | if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { |
d3fc5d71 | 868 | mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; |
e89d456f AW |
869 | /* |
870 | * If we are sending CMD23, CMD12 never gets sent | |
871 | * on successful completion (so no Auto-CMD12). | |
872 | */ | |
85cc1c33 CD |
873 | if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && |
874 | (cmd->opcode != SD_IO_RW_EXTENDED)) | |
e89d456f | 875 | mode |= SDHCI_TRNS_AUTO_CMD12; |
8edf6371 AW |
876 | else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { |
877 | mode |= SDHCI_TRNS_AUTO_CMD23; | |
878 | sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); | |
879 | } | |
c4512f79 | 880 | } |
8edf6371 | 881 | |
c7fa9963 PO |
882 | if (data->flags & MMC_DATA_READ) |
883 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 884 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
885 | mode |= SDHCI_TRNS_DMA; |
886 | ||
4e4141a5 | 887 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
888 | } |
889 | ||
890 | static void sdhci_finish_data(struct sdhci_host *host) | |
891 | { | |
892 | struct mmc_data *data; | |
d129bceb PO |
893 | |
894 | BUG_ON(!host->data); | |
895 | ||
896 | data = host->data; | |
897 | host->data = NULL; | |
898 | ||
add8913d RK |
899 | if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == |
900 | (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) | |
901 | sdhci_adma_table_post(host, data); | |
d129bceb PO |
902 | |
903 | /* | |
c9b74c5b PO |
904 | * The specification states that the block count register must |
905 | * be updated, but it does not specify at what point in the | |
906 | * data flow. That makes the register entirely useless to read | |
907 | * back so we have to assume that nothing made it to the card | |
908 | * in the event of an error. | |
d129bceb | 909 | */ |
c9b74c5b PO |
910 | if (data->error) |
911 | data->bytes_xfered = 0; | |
d129bceb | 912 | else |
c9b74c5b | 913 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 914 | |
e89d456f AW |
915 | /* |
916 | * Need to send CMD12 if - | |
917 | * a) open-ended multiblock transfer (no CMD23) | |
918 | * b) error in multiblock transfer | |
919 | */ | |
920 | if (data->stop && | |
921 | (data->error || | |
922 | !host->mrq->sbc)) { | |
923 | ||
d129bceb PO |
924 | /* |
925 | * The controller needs a reset of internal state machines | |
926 | * upon error conditions. | |
927 | */ | |
17b0429d | 928 | if (data->error) { |
03231f9b RK |
929 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
930 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb PO |
931 | } |
932 | ||
933 | sdhci_send_command(host, data->stop); | |
934 | } else | |
935 | tasklet_schedule(&host->finish_tasklet); | |
936 | } | |
937 | ||
c0e55129 | 938 | void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb PO |
939 | { |
940 | int flags; | |
fd2208d7 | 941 | u32 mask; |
7cb2c76f | 942 | unsigned long timeout; |
d129bceb PO |
943 | |
944 | WARN_ON(host->cmd); | |
945 | ||
96776200 RK |
946 | /* Initially, a command has no error */ |
947 | cmd->error = 0; | |
948 | ||
d129bceb | 949 | /* Wait max 10 ms */ |
7cb2c76f | 950 | timeout = 10; |
fd2208d7 PO |
951 | |
952 | mask = SDHCI_CMD_INHIBIT; | |
953 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
954 | mask |= SDHCI_DATA_INHIBIT; | |
955 | ||
956 | /* We shouldn't wait for data inihibit for stop commands, even | |
957 | though they might use busy signaling */ | |
958 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
959 | mask &= ~SDHCI_DATA_INHIBIT; | |
960 | ||
4e4141a5 | 961 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 962 | if (timeout == 0) { |
2e4456f0 MV |
963 | pr_err("%s: Controller never released inhibit bit(s).\n", |
964 | mmc_hostname(host->mmc)); | |
d129bceb | 965 | sdhci_dumpregs(host); |
17b0429d | 966 | cmd->error = -EIO; |
d129bceb PO |
967 | tasklet_schedule(&host->finish_tasklet); |
968 | return; | |
969 | } | |
7cb2c76f PO |
970 | timeout--; |
971 | mdelay(1); | |
972 | } | |
d129bceb | 973 | |
3e1a6892 | 974 | timeout = jiffies; |
1d4d7744 UH |
975 | if (!cmd->data && cmd->busy_timeout > 9000) |
976 | timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; | |
3e1a6892 AH |
977 | else |
978 | timeout += 10 * HZ; | |
979 | mod_timer(&host->timer, timeout); | |
d129bceb PO |
980 | |
981 | host->cmd = cmd; | |
e99783a4 | 982 | host->busy_handle = 0; |
d129bceb | 983 | |
a3c7778f | 984 | sdhci_prepare_data(host, cmd); |
d129bceb | 985 | |
4e4141a5 | 986 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 987 | |
e89d456f | 988 | sdhci_set_transfer_mode(host, cmd); |
c7fa9963 | 989 | |
d129bceb | 990 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
a3c76eb9 | 991 | pr_err("%s: Unsupported response type!\n", |
d129bceb | 992 | mmc_hostname(host->mmc)); |
17b0429d | 993 | cmd->error = -EINVAL; |
d129bceb PO |
994 | tasklet_schedule(&host->finish_tasklet); |
995 | return; | |
996 | } | |
997 | ||
998 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
999 | flags = SDHCI_CMD_RESP_NONE; | |
1000 | else if (cmd->flags & MMC_RSP_136) | |
1001 | flags = SDHCI_CMD_RESP_LONG; | |
1002 | else if (cmd->flags & MMC_RSP_BUSY) | |
1003 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
1004 | else | |
1005 | flags = SDHCI_CMD_RESP_SHORT; | |
1006 | ||
1007 | if (cmd->flags & MMC_RSP_CRC) | |
1008 | flags |= SDHCI_CMD_CRC; | |
1009 | if (cmd->flags & MMC_RSP_OPCODE) | |
1010 | flags |= SDHCI_CMD_INDEX; | |
b513ea25 AN |
1011 | |
1012 | /* CMD19 is special in that the Data Present Select should be set */ | |
069c9f14 G |
1013 | if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || |
1014 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) | |
d129bceb PO |
1015 | flags |= SDHCI_CMD_DATA; |
1016 | ||
4e4141a5 | 1017 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb | 1018 | } |
c0e55129 | 1019 | EXPORT_SYMBOL_GPL(sdhci_send_command); |
d129bceb PO |
1020 | |
1021 | static void sdhci_finish_command(struct sdhci_host *host) | |
1022 | { | |
1023 | int i; | |
1024 | ||
1025 | BUG_ON(host->cmd == NULL); | |
1026 | ||
1027 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
1028 | if (host->cmd->flags & MMC_RSP_136) { | |
1029 | /* CRC is stripped so we need to do some shifting. */ | |
1030 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 1031 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
1032 | SDHCI_RESPONSE + (3-i)*4) << 8; |
1033 | if (i != 3) | |
1034 | host->cmd->resp[i] |= | |
4e4141a5 | 1035 | sdhci_readb(host, |
d129bceb PO |
1036 | SDHCI_RESPONSE + (3-i)*4-1); |
1037 | } | |
1038 | } else { | |
4e4141a5 | 1039 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
1040 | } |
1041 | } | |
1042 | ||
e89d456f AW |
1043 | /* Finished CMD23, now send actual command. */ |
1044 | if (host->cmd == host->mrq->sbc) { | |
1045 | host->cmd = NULL; | |
1046 | sdhci_send_command(host, host->mrq->cmd); | |
1047 | } else { | |
e538fbe8 | 1048 | |
e89d456f AW |
1049 | /* Processed actual command. */ |
1050 | if (host->data && host->data_early) | |
1051 | sdhci_finish_data(host); | |
d129bceb | 1052 | |
e89d456f AW |
1053 | if (!host->cmd->data) |
1054 | tasklet_schedule(&host->finish_tasklet); | |
1055 | ||
1056 | host->cmd = NULL; | |
1057 | } | |
d129bceb PO |
1058 | } |
1059 | ||
52983382 KL |
1060 | static u16 sdhci_get_preset_value(struct sdhci_host *host) |
1061 | { | |
d975f121 | 1062 | u16 preset = 0; |
52983382 | 1063 | |
d975f121 RK |
1064 | switch (host->timing) { |
1065 | case MMC_TIMING_UHS_SDR12: | |
52983382 KL |
1066 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
1067 | break; | |
d975f121 | 1068 | case MMC_TIMING_UHS_SDR25: |
52983382 KL |
1069 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); |
1070 | break; | |
d975f121 | 1071 | case MMC_TIMING_UHS_SDR50: |
52983382 KL |
1072 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); |
1073 | break; | |
d975f121 RK |
1074 | case MMC_TIMING_UHS_SDR104: |
1075 | case MMC_TIMING_MMC_HS200: | |
52983382 KL |
1076 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); |
1077 | break; | |
d975f121 | 1078 | case MMC_TIMING_UHS_DDR50: |
0dafa60e | 1079 | case MMC_TIMING_MMC_DDR52: |
52983382 KL |
1080 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); |
1081 | break; | |
e9fb05d5 AH |
1082 | case MMC_TIMING_MMC_HS400: |
1083 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); | |
1084 | break; | |
52983382 KL |
1085 | default: |
1086 | pr_warn("%s: Invalid UHS-I mode selected\n", | |
1087 | mmc_hostname(host->mmc)); | |
1088 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); | |
1089 | break; | |
1090 | } | |
1091 | return preset; | |
1092 | } | |
1093 | ||
1771059c | 1094 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
d129bceb | 1095 | { |
c3ed3877 | 1096 | int div = 0; /* Initialized for compiler warning */ |
df16219f | 1097 | int real_div = div, clk_mul = 1; |
c3ed3877 | 1098 | u16 clk = 0; |
7cb2c76f | 1099 | unsigned long timeout; |
5497159c | 1100 | bool switch_base_clk = false; |
d129bceb | 1101 | |
1650d0c7 RK |
1102 | host->mmc->actual_clock = 0; |
1103 | ||
4e4141a5 | 1104 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
af951761 | 1105 | if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST) |
1106 | mdelay(1); | |
d129bceb PO |
1107 | |
1108 | if (clock == 0) | |
373073ef | 1109 | return; |
d129bceb | 1110 | |
85105c53 | 1111 | if (host->version >= SDHCI_SPEC_300) { |
da91a8f9 | 1112 | if (host->preset_enabled) { |
52983382 KL |
1113 | u16 pre_val; |
1114 | ||
1115 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1116 | pre_val = sdhci_get_preset_value(host); | |
1117 | div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) | |
1118 | >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; | |
1119 | if (host->clk_mul && | |
1120 | (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { | |
1121 | clk = SDHCI_PROG_CLOCK_MODE; | |
1122 | real_div = div + 1; | |
1123 | clk_mul = host->clk_mul; | |
1124 | } else { | |
1125 | real_div = max_t(int, 1, div << 1); | |
1126 | } | |
1127 | goto clock_set; | |
1128 | } | |
1129 | ||
c3ed3877 AN |
1130 | /* |
1131 | * Check if the Host Controller supports Programmable Clock | |
1132 | * Mode. | |
1133 | */ | |
1134 | if (host->clk_mul) { | |
52983382 KL |
1135 | for (div = 1; div <= 1024; div++) { |
1136 | if ((host->max_clk * host->clk_mul / div) | |
1137 | <= clock) | |
1138 | break; | |
1139 | } | |
5497159c | 1140 | if ((host->max_clk * host->clk_mul / div) <= clock) { |
1141 | /* | |
1142 | * Set Programmable Clock Mode in the Clock | |
1143 | * Control register. | |
1144 | */ | |
1145 | clk = SDHCI_PROG_CLOCK_MODE; | |
1146 | real_div = div; | |
1147 | clk_mul = host->clk_mul; | |
1148 | div--; | |
1149 | } else { | |
1150 | /* | |
1151 | * Divisor can be too small to reach clock | |
1152 | * speed requirement. Then use the base clock. | |
1153 | */ | |
1154 | switch_base_clk = true; | |
1155 | } | |
1156 | } | |
1157 | ||
1158 | if (!host->clk_mul || switch_base_clk) { | |
c3ed3877 AN |
1159 | /* Version 3.00 divisors must be a multiple of 2. */ |
1160 | if (host->max_clk <= clock) | |
1161 | div = 1; | |
1162 | else { | |
1163 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; | |
1164 | div += 2) { | |
1165 | if ((host->max_clk / div) <= clock) | |
1166 | break; | |
1167 | } | |
85105c53 | 1168 | } |
df16219f | 1169 | real_div = div; |
c3ed3877 | 1170 | div >>= 1; |
d1955c3a SG |
1171 | if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) |
1172 | && !div && host->max_clk <= 25000000) | |
1173 | div = 1; | |
85105c53 ZG |
1174 | } |
1175 | } else { | |
1176 | /* Version 2.00 divisors must be a power of 2. */ | |
0397526d | 1177 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
85105c53 ZG |
1178 | if ((host->max_clk / div) <= clock) |
1179 | break; | |
1180 | } | |
df16219f | 1181 | real_div = div; |
c3ed3877 | 1182 | div >>= 1; |
d129bceb | 1183 | } |
d129bceb | 1184 | |
52983382 | 1185 | clock_set: |
03d6f5ff | 1186 | if (real_div) |
df16219f | 1187 | host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; |
c3ed3877 | 1188 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
85105c53 ZG |
1189 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
1190 | << SDHCI_DIVIDER_HI_SHIFT; | |
d129bceb | 1191 | clk |= SDHCI_CLOCK_INT_EN; |
4e4141a5 | 1192 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1193 | |
27f6cb16 CB |
1194 | /* Wait max 20 ms */ |
1195 | timeout = 20; | |
4e4141a5 | 1196 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
1197 | & SDHCI_CLOCK_INT_STABLE)) { |
1198 | if (timeout == 0) { | |
2e4456f0 MV |
1199 | pr_err("%s: Internal clock never stabilised.\n", |
1200 | mmc_hostname(host->mmc)); | |
d129bceb PO |
1201 | sdhci_dumpregs(host); |
1202 | return; | |
1203 | } | |
7cb2c76f PO |
1204 | timeout--; |
1205 | mdelay(1); | |
1206 | } | |
d129bceb PO |
1207 | |
1208 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 1209 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1210 | } |
1771059c | 1211 | EXPORT_SYMBOL_GPL(sdhci_set_clock); |
d129bceb | 1212 | |
24fbb3ca RK |
1213 | static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
1214 | unsigned short vdd) | |
146ad66e | 1215 | { |
3a48edc4 | 1216 | struct mmc_host *mmc = host->mmc; |
8364248a | 1217 | u8 pwr = 0; |
146ad66e | 1218 | |
24fbb3ca RK |
1219 | if (mode != MMC_POWER_OFF) { |
1220 | switch (1 << vdd) { | |
ae628903 PO |
1221 | case MMC_VDD_165_195: |
1222 | pwr = SDHCI_POWER_180; | |
1223 | break; | |
1224 | case MMC_VDD_29_30: | |
1225 | case MMC_VDD_30_31: | |
1226 | pwr = SDHCI_POWER_300; | |
1227 | break; | |
1228 | case MMC_VDD_32_33: | |
1229 | case MMC_VDD_33_34: | |
1230 | pwr = SDHCI_POWER_330; | |
1231 | break; | |
1232 | default: | |
9d5de93f AH |
1233 | WARN(1, "%s: Invalid vdd %#x\n", |
1234 | mmc_hostname(host->mmc), vdd); | |
1235 | break; | |
ae628903 PO |
1236 | } |
1237 | } | |
1238 | ||
1239 | if (host->pwr == pwr) | |
e921a8b6 | 1240 | return; |
146ad66e | 1241 | |
ae628903 PO |
1242 | host->pwr = pwr; |
1243 | ||
1244 | if (pwr == 0) { | |
4e4141a5 | 1245 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
f0710a55 AH |
1246 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1247 | sdhci_runtime_pm_bus_off(host); | |
24fbb3ca | 1248 | vdd = 0; |
e921a8b6 RK |
1249 | } else { |
1250 | /* | |
1251 | * Spec says that we should clear the power reg before setting | |
1252 | * a new value. Some controllers don't seem to like this though. | |
1253 | */ | |
1254 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) | |
1255 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); | |
146ad66e | 1256 | |
e921a8b6 RK |
1257 | /* |
1258 | * At least the Marvell CaFe chip gets confused if we set the | |
1259 | * voltage and set turn on power at the same time, so set the | |
1260 | * voltage first. | |
1261 | */ | |
1262 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) | |
1263 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); | |
e08c1694 | 1264 | |
e921a8b6 | 1265 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1266 | |
e921a8b6 | 1267 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
557b0697 | 1268 | |
e921a8b6 RK |
1269 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1270 | sdhci_runtime_pm_bus_on(host); | |
f0710a55 | 1271 | |
e921a8b6 RK |
1272 | /* |
1273 | * Some controllers need an extra 10ms delay of 10ms before | |
1274 | * they can apply clock after applying power | |
1275 | */ | |
1276 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) | |
1277 | mdelay(10); | |
1278 | } | |
918f4cbd JZ |
1279 | |
1280 | if (!IS_ERR(mmc->supply.vmmc)) { | |
1281 | spin_unlock_irq(&host->lock); | |
1282 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); | |
1283 | spin_lock_irq(&host->lock); | |
1284 | } | |
146ad66e PO |
1285 | } |
1286 | ||
d129bceb PO |
1287 | /*****************************************************************************\ |
1288 | * * | |
1289 | * MMC callbacks * | |
1290 | * * | |
1291 | \*****************************************************************************/ | |
1292 | ||
1293 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1294 | { | |
1295 | struct sdhci_host *host; | |
505a8680 | 1296 | int present; |
d129bceb PO |
1297 | unsigned long flags; |
1298 | ||
1299 | host = mmc_priv(mmc); | |
1300 | ||
66fd8ad5 AH |
1301 | sdhci_runtime_pm_get(host); |
1302 | ||
04e079cf | 1303 | /* Firstly check card presence */ |
8d28b7a7 | 1304 | present = mmc->ops->get_cd(mmc); |
2836766a | 1305 | |
d129bceb PO |
1306 | spin_lock_irqsave(&host->lock, flags); |
1307 | ||
1308 | WARN_ON(host->mrq != NULL); | |
1309 | ||
f9134319 | 1310 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1311 | sdhci_activate_led(host); |
2f730fec | 1312 | #endif |
e89d456f AW |
1313 | |
1314 | /* | |
1315 | * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED | |
1316 | * requests if Auto-CMD12 is enabled. | |
1317 | */ | |
1318 | if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { | |
c4512f79 JH |
1319 | if (mrq->stop) { |
1320 | mrq->data->stop = NULL; | |
1321 | mrq->stop = NULL; | |
1322 | } | |
1323 | } | |
d129bceb PO |
1324 | |
1325 | host->mrq = mrq; | |
1326 | ||
68d1fb7e | 1327 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { |
17b0429d | 1328 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb | 1329 | tasklet_schedule(&host->finish_tasklet); |
cf2b5eea | 1330 | } else { |
8edf6371 | 1331 | if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) |
e89d456f AW |
1332 | sdhci_send_command(host, mrq->sbc); |
1333 | else | |
1334 | sdhci_send_command(host, mrq->cmd); | |
cf2b5eea | 1335 | } |
d129bceb | 1336 | |
5f25a66f | 1337 | mmiowb(); |
d129bceb PO |
1338 | spin_unlock_irqrestore(&host->lock, flags); |
1339 | } | |
1340 | ||
2317f56c RK |
1341 | void sdhci_set_bus_width(struct sdhci_host *host, int width) |
1342 | { | |
1343 | u8 ctrl; | |
1344 | ||
1345 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
1346 | if (width == MMC_BUS_WIDTH_8) { | |
1347 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1348 | if (host->version >= SDHCI_SPEC_300) | |
1349 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1350 | } else { | |
1351 | if (host->version >= SDHCI_SPEC_300) | |
1352 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1353 | if (width == MMC_BUS_WIDTH_4) | |
1354 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1355 | else | |
1356 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1357 | } | |
1358 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1359 | } | |
1360 | EXPORT_SYMBOL_GPL(sdhci_set_bus_width); | |
1361 | ||
96d7b78c RK |
1362 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
1363 | { | |
1364 | u16 ctrl_2; | |
1365 | ||
1366 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1367 | /* Select Bus Speed Mode for host */ | |
1368 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
1369 | if ((timing == MMC_TIMING_MMC_HS200) || | |
1370 | (timing == MMC_TIMING_UHS_SDR104)) | |
1371 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
1372 | else if (timing == MMC_TIMING_UHS_SDR12) | |
1373 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
1374 | else if (timing == MMC_TIMING_UHS_SDR25) | |
1375 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
1376 | else if (timing == MMC_TIMING_UHS_SDR50) | |
1377 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
1378 | else if ((timing == MMC_TIMING_UHS_DDR50) || | |
1379 | (timing == MMC_TIMING_MMC_DDR52)) | |
1380 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | |
e9fb05d5 AH |
1381 | else if (timing == MMC_TIMING_MMC_HS400) |
1382 | ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ | |
96d7b78c RK |
1383 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
1384 | } | |
1385 | EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); | |
1386 | ||
66fd8ad5 | 1387 | static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) |
d129bceb | 1388 | { |
d129bceb PO |
1389 | unsigned long flags; |
1390 | u8 ctrl; | |
3a48edc4 | 1391 | struct mmc_host *mmc = host->mmc; |
d129bceb | 1392 | |
d129bceb PO |
1393 | spin_lock_irqsave(&host->lock, flags); |
1394 | ||
ceb6143b AH |
1395 | if (host->flags & SDHCI_DEVICE_DEAD) { |
1396 | spin_unlock_irqrestore(&host->lock, flags); | |
3a48edc4 TK |
1397 | if (!IS_ERR(mmc->supply.vmmc) && |
1398 | ios->power_mode == MMC_POWER_OFF) | |
4e743f1f | 1399 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
ceb6143b AH |
1400 | return; |
1401 | } | |
1e72859e | 1402 | |
d129bceb PO |
1403 | /* |
1404 | * Reset the chip on each power off. | |
1405 | * Should clear out any weird states. | |
1406 | */ | |
1407 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1408 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1409 | sdhci_reinit(host); |
d129bceb PO |
1410 | } |
1411 | ||
52983382 | 1412 | if (host->version >= SDHCI_SPEC_300 && |
372c4634 DA |
1413 | (ios->power_mode == MMC_POWER_UP) && |
1414 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) | |
52983382 KL |
1415 | sdhci_enable_preset_value(host, false); |
1416 | ||
373073ef | 1417 | if (!ios->clock || ios->clock != host->clock) { |
1771059c | 1418 | host->ops->set_clock(host, ios->clock); |
373073ef | 1419 | host->clock = ios->clock; |
03d6f5ff AD |
1420 | |
1421 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && | |
1422 | host->clock) { | |
1423 | host->timeout_clk = host->mmc->actual_clock ? | |
1424 | host->mmc->actual_clock / 1000 : | |
1425 | host->clock / 1000; | |
1426 | host->mmc->max_busy_timeout = | |
1427 | host->ops->get_max_timeout_count ? | |
1428 | host->ops->get_max_timeout_count(host) : | |
1429 | 1 << 27; | |
1430 | host->mmc->max_busy_timeout /= host->timeout_clk; | |
1431 | } | |
373073ef | 1432 | } |
d129bceb | 1433 | |
24fbb3ca | 1434 | sdhci_set_power(host, ios->power_mode, ios->vdd); |
d129bceb | 1435 | |
643a81ff PR |
1436 | if (host->ops->platform_send_init_74_clocks) |
1437 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); | |
1438 | ||
2317f56c | 1439 | host->ops->set_bus_width(host, ios->bus_width); |
ae6d6c92 | 1440 | |
15ec4461 | 1441 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1442 | |
3ab9c8da PR |
1443 | if ((ios->timing == MMC_TIMING_SD_HS || |
1444 | ios->timing == MMC_TIMING_MMC_HS) | |
1445 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) | |
cd9277c0 PO |
1446 | ctrl |= SDHCI_CTRL_HISPD; |
1447 | else | |
1448 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1449 | ||
d6d50a15 | 1450 | if (host->version >= SDHCI_SPEC_300) { |
49c468fc | 1451 | u16 clk, ctrl_2; |
49c468fc AN |
1452 | |
1453 | /* In case of UHS-I modes, set High Speed Enable */ | |
e9fb05d5 AH |
1454 | if ((ios->timing == MMC_TIMING_MMC_HS400) || |
1455 | (ios->timing == MMC_TIMING_MMC_HS200) || | |
bb8175a8 | 1456 | (ios->timing == MMC_TIMING_MMC_DDR52) || |
069c9f14 | 1457 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
49c468fc AN |
1458 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
1459 | (ios->timing == MMC_TIMING_UHS_DDR50) || | |
dd8df17f | 1460 | (ios->timing == MMC_TIMING_UHS_SDR25)) |
49c468fc | 1461 | ctrl |= SDHCI_CTRL_HISPD; |
d6d50a15 | 1462 | |
da91a8f9 | 1463 | if (!host->preset_enabled) { |
758535c4 | 1464 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d6d50a15 AN |
1465 | /* |
1466 | * We only need to set Driver Strength if the | |
1467 | * preset value enable is not set. | |
1468 | */ | |
da91a8f9 | 1469 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
d6d50a15 AN |
1470 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; |
1471 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) | |
1472 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; | |
43e943a0 PG |
1473 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) |
1474 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; | |
d6d50a15 AN |
1475 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) |
1476 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; | |
43e943a0 PG |
1477 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) |
1478 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; | |
1479 | else { | |
2e4456f0 MV |
1480 | pr_warn("%s: invalid driver type, default to driver type B\n", |
1481 | mmc_hostname(mmc)); | |
43e943a0 PG |
1482 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; |
1483 | } | |
d6d50a15 AN |
1484 | |
1485 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
758535c4 AN |
1486 | } else { |
1487 | /* | |
1488 | * According to SDHC Spec v3.00, if the Preset Value | |
1489 | * Enable in the Host Control 2 register is set, we | |
1490 | * need to reset SD Clock Enable before changing High | |
1491 | * Speed Enable to avoid generating clock gliches. | |
1492 | */ | |
758535c4 AN |
1493 | |
1494 | /* Reset SD Clock Enable */ | |
1495 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1496 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1497 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1498 | ||
1499 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1500 | ||
1501 | /* Re-enable SD Clock */ | |
1771059c | 1502 | host->ops->set_clock(host, host->clock); |
d6d50a15 | 1503 | } |
49c468fc | 1504 | |
49c468fc AN |
1505 | /* Reset SD Clock Enable */ |
1506 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1507 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1508 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1509 | ||
96d7b78c | 1510 | host->ops->set_uhs_signaling(host, ios->timing); |
d975f121 | 1511 | host->timing = ios->timing; |
49c468fc | 1512 | |
52983382 KL |
1513 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && |
1514 | ((ios->timing == MMC_TIMING_UHS_SDR12) || | |
1515 | (ios->timing == MMC_TIMING_UHS_SDR25) || | |
1516 | (ios->timing == MMC_TIMING_UHS_SDR50) || | |
1517 | (ios->timing == MMC_TIMING_UHS_SDR104) || | |
0dafa60e JZ |
1518 | (ios->timing == MMC_TIMING_UHS_DDR50) || |
1519 | (ios->timing == MMC_TIMING_MMC_DDR52))) { | |
52983382 KL |
1520 | u16 preset; |
1521 | ||
1522 | sdhci_enable_preset_value(host, true); | |
1523 | preset = sdhci_get_preset_value(host); | |
1524 | ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) | |
1525 | >> SDHCI_PRESET_DRV_SHIFT; | |
1526 | } | |
1527 | ||
49c468fc | 1528 | /* Re-enable SD Clock */ |
1771059c | 1529 | host->ops->set_clock(host, host->clock); |
758535c4 AN |
1530 | } else |
1531 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
d6d50a15 | 1532 | |
b8352260 LD |
1533 | /* |
1534 | * Some (ENE) controllers go apeshit on some ios operation, | |
1535 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1536 | * it on each ios seems to solve the problem. | |
1537 | */ | |
c63705e1 | 1538 | if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
03231f9b | 1539 | sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
b8352260 | 1540 | |
5f25a66f | 1541 | mmiowb(); |
d129bceb PO |
1542 | spin_unlock_irqrestore(&host->lock, flags); |
1543 | } | |
1544 | ||
66fd8ad5 AH |
1545 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1546 | { | |
1547 | struct sdhci_host *host = mmc_priv(mmc); | |
1548 | ||
1549 | sdhci_runtime_pm_get(host); | |
1550 | sdhci_do_set_ios(host, ios); | |
1551 | sdhci_runtime_pm_put(host); | |
1552 | } | |
1553 | ||
94144a46 KL |
1554 | static int sdhci_do_get_cd(struct sdhci_host *host) |
1555 | { | |
1556 | int gpio_cd = mmc_gpio_get_cd(host->mmc); | |
1557 | ||
1558 | if (host->flags & SDHCI_DEVICE_DEAD) | |
1559 | return 0; | |
1560 | ||
88af5655 II |
1561 | /* If nonremovable, assume that the card is always present. */ |
1562 | if (host->mmc->caps & MMC_CAP_NONREMOVABLE) | |
94144a46 KL |
1563 | return 1; |
1564 | ||
88af5655 II |
1565 | /* |
1566 | * Try slot gpio detect, if defined it take precedence | |
1567 | * over build in controller functionality | |
1568 | */ | |
94144a46 KL |
1569 | if (!IS_ERR_VALUE(gpio_cd)) |
1570 | return !!gpio_cd; | |
1571 | ||
88af5655 II |
1572 | /* If polling, assume that the card is always present. */ |
1573 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1574 | return 1; | |
1575 | ||
94144a46 KL |
1576 | /* Host native card detect */ |
1577 | return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); | |
1578 | } | |
1579 | ||
1580 | static int sdhci_get_cd(struct mmc_host *mmc) | |
1581 | { | |
1582 | struct sdhci_host *host = mmc_priv(mmc); | |
1583 | int ret; | |
1584 | ||
1585 | sdhci_runtime_pm_get(host); | |
1586 | ret = sdhci_do_get_cd(host); | |
1587 | sdhci_runtime_pm_put(host); | |
1588 | return ret; | |
1589 | } | |
1590 | ||
66fd8ad5 | 1591 | static int sdhci_check_ro(struct sdhci_host *host) |
d129bceb | 1592 | { |
d129bceb | 1593 | unsigned long flags; |
2dfb579c | 1594 | int is_readonly; |
d129bceb | 1595 | |
d129bceb PO |
1596 | spin_lock_irqsave(&host->lock, flags); |
1597 | ||
1e72859e | 1598 | if (host->flags & SDHCI_DEVICE_DEAD) |
2dfb579c WS |
1599 | is_readonly = 0; |
1600 | else if (host->ops->get_ro) | |
1601 | is_readonly = host->ops->get_ro(host); | |
1e72859e | 1602 | else |
2dfb579c WS |
1603 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
1604 | & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1605 | |
1606 | spin_unlock_irqrestore(&host->lock, flags); | |
1607 | ||
2dfb579c WS |
1608 | /* This quirk needs to be replaced by a callback-function later */ |
1609 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? | |
1610 | !is_readonly : is_readonly; | |
d129bceb PO |
1611 | } |
1612 | ||
82b0e23a TI |
1613 | #define SAMPLE_COUNT 5 |
1614 | ||
66fd8ad5 | 1615 | static int sdhci_do_get_ro(struct sdhci_host *host) |
82b0e23a | 1616 | { |
82b0e23a TI |
1617 | int i, ro_count; |
1618 | ||
82b0e23a | 1619 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) |
66fd8ad5 | 1620 | return sdhci_check_ro(host); |
82b0e23a TI |
1621 | |
1622 | ro_count = 0; | |
1623 | for (i = 0; i < SAMPLE_COUNT; i++) { | |
66fd8ad5 | 1624 | if (sdhci_check_ro(host)) { |
82b0e23a TI |
1625 | if (++ro_count > SAMPLE_COUNT / 2) |
1626 | return 1; | |
1627 | } | |
1628 | msleep(30); | |
1629 | } | |
1630 | return 0; | |
1631 | } | |
1632 | ||
20758b66 AH |
1633 | static void sdhci_hw_reset(struct mmc_host *mmc) |
1634 | { | |
1635 | struct sdhci_host *host = mmc_priv(mmc); | |
1636 | ||
1637 | if (host->ops && host->ops->hw_reset) | |
1638 | host->ops->hw_reset(host); | |
1639 | } | |
1640 | ||
66fd8ad5 | 1641 | static int sdhci_get_ro(struct mmc_host *mmc) |
f75979b7 | 1642 | { |
66fd8ad5 AH |
1643 | struct sdhci_host *host = mmc_priv(mmc); |
1644 | int ret; | |
f75979b7 | 1645 | |
66fd8ad5 AH |
1646 | sdhci_runtime_pm_get(host); |
1647 | ret = sdhci_do_get_ro(host); | |
1648 | sdhci_runtime_pm_put(host); | |
1649 | return ret; | |
1650 | } | |
f75979b7 | 1651 | |
66fd8ad5 AH |
1652 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
1653 | { | |
be138554 | 1654 | if (!(host->flags & SDHCI_DEVICE_DEAD)) { |
ef104333 | 1655 | if (enable) |
b537f94c | 1656 | host->ier |= SDHCI_INT_CARD_INT; |
ef104333 | 1657 | else |
b537f94c RK |
1658 | host->ier &= ~SDHCI_INT_CARD_INT; |
1659 | ||
1660 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
1661 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
ef104333 RK |
1662 | mmiowb(); |
1663 | } | |
66fd8ad5 AH |
1664 | } |
1665 | ||
1666 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) | |
1667 | { | |
1668 | struct sdhci_host *host = mmc_priv(mmc); | |
1669 | unsigned long flags; | |
f75979b7 | 1670 | |
ef104333 RK |
1671 | sdhci_runtime_pm_get(host); |
1672 | ||
66fd8ad5 | 1673 | spin_lock_irqsave(&host->lock, flags); |
ef104333 RK |
1674 | if (enable) |
1675 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; | |
1676 | else | |
1677 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; | |
1678 | ||
66fd8ad5 | 1679 | sdhci_enable_sdio_irq_nolock(host, enable); |
f75979b7 | 1680 | spin_unlock_irqrestore(&host->lock, flags); |
ef104333 RK |
1681 | |
1682 | sdhci_runtime_pm_put(host); | |
f75979b7 PO |
1683 | } |
1684 | ||
20b92a30 | 1685 | static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, |
21f5998f | 1686 | struct mmc_ios *ios) |
f2119df6 | 1687 | { |
3a48edc4 | 1688 | struct mmc_host *mmc = host->mmc; |
20b92a30 | 1689 | u16 ctrl; |
6231f3de | 1690 | int ret; |
f2119df6 | 1691 | |
20b92a30 KL |
1692 | /* |
1693 | * Signal Voltage Switching is only applicable for Host Controllers | |
1694 | * v3.00 and above. | |
1695 | */ | |
1696 | if (host->version < SDHCI_SPEC_300) | |
1697 | return 0; | |
6231f3de | 1698 | |
f2119df6 | 1699 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
f2119df6 | 1700 | |
21f5998f | 1701 | switch (ios->signal_voltage) { |
20b92a30 KL |
1702 | case MMC_SIGNAL_VOLTAGE_330: |
1703 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ | |
1704 | ctrl &= ~SDHCI_CTRL_VDD_180; | |
1705 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
f2119df6 | 1706 | |
3a48edc4 TK |
1707 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1708 | ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, | |
1709 | 3600000); | |
20b92a30 | 1710 | if (ret) { |
6606110d JP |
1711 | pr_warn("%s: Switching to 3.3V signalling voltage failed\n", |
1712 | mmc_hostname(mmc)); | |
20b92a30 KL |
1713 | return -EIO; |
1714 | } | |
1715 | } | |
1716 | /* Wait for 5ms */ | |
1717 | usleep_range(5000, 5500); | |
f2119df6 | 1718 | |
20b92a30 KL |
1719 | /* 3.3V regulator output should be stable within 5 ms */ |
1720 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1721 | if (!(ctrl & SDHCI_CTRL_VDD_180)) | |
1722 | return 0; | |
6231f3de | 1723 | |
6606110d JP |
1724 | pr_warn("%s: 3.3V regulator output did not became stable\n", |
1725 | mmc_hostname(mmc)); | |
20b92a30 KL |
1726 | |
1727 | return -EAGAIN; | |
1728 | case MMC_SIGNAL_VOLTAGE_180: | |
3a48edc4 TK |
1729 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1730 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
20b92a30 KL |
1731 | 1700000, 1950000); |
1732 | if (ret) { | |
6606110d JP |
1733 | pr_warn("%s: Switching to 1.8V signalling voltage failed\n", |
1734 | mmc_hostname(mmc)); | |
20b92a30 KL |
1735 | return -EIO; |
1736 | } | |
1737 | } | |
6231f3de | 1738 | |
6231f3de PR |
1739 | /* |
1740 | * Enable 1.8V Signal Enable in the Host Control2 | |
1741 | * register | |
1742 | */ | |
20b92a30 KL |
1743 | ctrl |= SDHCI_CTRL_VDD_180; |
1744 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
6231f3de | 1745 | |
9d967a61 VY |
1746 | /* Some controller need to do more when switching */ |
1747 | if (host->ops->voltage_switch) | |
1748 | host->ops->voltage_switch(host); | |
1749 | ||
20b92a30 KL |
1750 | /* 1.8V regulator output should be stable within 5 ms */ |
1751 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1752 | if (ctrl & SDHCI_CTRL_VDD_180) | |
1753 | return 0; | |
f2119df6 | 1754 | |
6606110d JP |
1755 | pr_warn("%s: 1.8V regulator output did not became stable\n", |
1756 | mmc_hostname(mmc)); | |
f2119df6 | 1757 | |
20b92a30 KL |
1758 | return -EAGAIN; |
1759 | case MMC_SIGNAL_VOLTAGE_120: | |
3a48edc4 TK |
1760 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1761 | ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, | |
1762 | 1300000); | |
20b92a30 | 1763 | if (ret) { |
6606110d JP |
1764 | pr_warn("%s: Switching to 1.2V signalling voltage failed\n", |
1765 | mmc_hostname(mmc)); | |
20b92a30 | 1766 | return -EIO; |
f2119df6 AN |
1767 | } |
1768 | } | |
6231f3de | 1769 | return 0; |
20b92a30 | 1770 | default: |
f2119df6 AN |
1771 | /* No signal voltage switch required */ |
1772 | return 0; | |
20b92a30 | 1773 | } |
f2119df6 AN |
1774 | } |
1775 | ||
66fd8ad5 | 1776 | static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
21f5998f | 1777 | struct mmc_ios *ios) |
66fd8ad5 AH |
1778 | { |
1779 | struct sdhci_host *host = mmc_priv(mmc); | |
1780 | int err; | |
1781 | ||
1782 | if (host->version < SDHCI_SPEC_300) | |
1783 | return 0; | |
1784 | sdhci_runtime_pm_get(host); | |
21f5998f | 1785 | err = sdhci_do_start_signal_voltage_switch(host, ios); |
66fd8ad5 AH |
1786 | sdhci_runtime_pm_put(host); |
1787 | return err; | |
1788 | } | |
1789 | ||
20b92a30 KL |
1790 | static int sdhci_card_busy(struct mmc_host *mmc) |
1791 | { | |
1792 | struct sdhci_host *host = mmc_priv(mmc); | |
1793 | u32 present_state; | |
1794 | ||
1795 | sdhci_runtime_pm_get(host); | |
1796 | /* Check whether DAT[3:0] is 0000 */ | |
1797 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
1798 | sdhci_runtime_pm_put(host); | |
1799 | ||
1800 | return !(present_state & SDHCI_DATA_LVL_MASK); | |
1801 | } | |
1802 | ||
b5540ce1 AH |
1803 | static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) |
1804 | { | |
1805 | struct sdhci_host *host = mmc_priv(mmc); | |
1806 | unsigned long flags; | |
1807 | ||
1808 | spin_lock_irqsave(&host->lock, flags); | |
1809 | host->flags |= SDHCI_HS400_TUNING; | |
1810 | spin_unlock_irqrestore(&host->lock, flags); | |
1811 | ||
1812 | return 0; | |
1813 | } | |
1814 | ||
069c9f14 | 1815 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
b513ea25 | 1816 | { |
4b6f37d3 | 1817 | struct sdhci_host *host = mmc_priv(mmc); |
b513ea25 | 1818 | u16 ctrl; |
b513ea25 | 1819 | int tuning_loop_counter = MAX_TUNING_LOOP; |
b513ea25 | 1820 | int err = 0; |
2b35bd83 | 1821 | unsigned long flags; |
38e40bf5 | 1822 | unsigned int tuning_count = 0; |
b5540ce1 | 1823 | bool hs400_tuning; |
b513ea25 | 1824 | |
66fd8ad5 | 1825 | sdhci_runtime_pm_get(host); |
2b35bd83 | 1826 | spin_lock_irqsave(&host->lock, flags); |
b513ea25 | 1827 | |
b5540ce1 AH |
1828 | hs400_tuning = host->flags & SDHCI_HS400_TUNING; |
1829 | host->flags &= ~SDHCI_HS400_TUNING; | |
1830 | ||
38e40bf5 AH |
1831 | if (host->tuning_mode == SDHCI_TUNING_MODE_1) |
1832 | tuning_count = host->tuning_count; | |
1833 | ||
b513ea25 | 1834 | /* |
9faac7b9 WY |
1835 | * The Host Controller needs tuning in case of SDR104 and DDR50 |
1836 | * mode, and for SDR50 mode when Use Tuning for SDR50 is set in | |
1837 | * the Capabilities register. | |
069c9f14 G |
1838 | * If the Host Controller supports the HS200 mode then the |
1839 | * tuning function has to be executed. | |
b513ea25 | 1840 | */ |
4b6f37d3 | 1841 | switch (host->timing) { |
b5540ce1 | 1842 | /* HS400 tuning is done in HS200 mode */ |
e9fb05d5 | 1843 | case MMC_TIMING_MMC_HS400: |
b5540ce1 AH |
1844 | err = -EINVAL; |
1845 | goto out_unlock; | |
1846 | ||
4b6f37d3 | 1847 | case MMC_TIMING_MMC_HS200: |
b5540ce1 AH |
1848 | /* |
1849 | * Periodic re-tuning for HS400 is not expected to be needed, so | |
1850 | * disable it here. | |
1851 | */ | |
1852 | if (hs400_tuning) | |
1853 | tuning_count = 0; | |
1854 | break; | |
1855 | ||
4b6f37d3 | 1856 | case MMC_TIMING_UHS_SDR104: |
9faac7b9 | 1857 | case MMC_TIMING_UHS_DDR50: |
4b6f37d3 RK |
1858 | break; |
1859 | ||
1860 | case MMC_TIMING_UHS_SDR50: | |
1861 | if (host->flags & SDHCI_SDR50_NEEDS_TUNING || | |
1862 | host->flags & SDHCI_SDR104_NEEDS_TUNING) | |
1863 | break; | |
1864 | /* FALLTHROUGH */ | |
1865 | ||
1866 | default: | |
d519c863 | 1867 | goto out_unlock; |
b513ea25 AN |
1868 | } |
1869 | ||
45251812 | 1870 | if (host->ops->platform_execute_tuning) { |
2b35bd83 | 1871 | spin_unlock_irqrestore(&host->lock, flags); |
45251812 DA |
1872 | err = host->ops->platform_execute_tuning(host, opcode); |
1873 | sdhci_runtime_pm_put(host); | |
1874 | return err; | |
1875 | } | |
1876 | ||
4b6f37d3 RK |
1877 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
1878 | ctrl |= SDHCI_CTRL_EXEC_TUNING; | |
67d0d04a VY |
1879 | if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) |
1880 | ctrl |= SDHCI_CTRL_TUNED_CLK; | |
b513ea25 AN |
1881 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
1882 | ||
1883 | /* | |
1884 | * As per the Host Controller spec v3.00, tuning command | |
1885 | * generates Buffer Read Ready interrupt, so enable that. | |
1886 | * | |
1887 | * Note: The spec clearly says that when tuning sequence | |
1888 | * is being performed, the controller does not generate | |
1889 | * interrupts other than Buffer Read Ready interrupt. But | |
1890 | * to make sure we don't hit a controller bug, we _only_ | |
1891 | * enable Buffer Read Ready interrupt here. | |
1892 | */ | |
b537f94c RK |
1893 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
1894 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); | |
b513ea25 AN |
1895 | |
1896 | /* | |
1897 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number | |
1898 | * of loops reaches 40 times or a timeout of 150ms occurs. | |
1899 | */ | |
b513ea25 AN |
1900 | do { |
1901 | struct mmc_command cmd = {0}; | |
66fd8ad5 | 1902 | struct mmc_request mrq = {NULL}; |
b513ea25 | 1903 | |
069c9f14 | 1904 | cmd.opcode = opcode; |
b513ea25 AN |
1905 | cmd.arg = 0; |
1906 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; | |
1907 | cmd.retries = 0; | |
1908 | cmd.data = NULL; | |
1909 | cmd.error = 0; | |
1910 | ||
7ce45e95 AC |
1911 | if (tuning_loop_counter-- == 0) |
1912 | break; | |
1913 | ||
b513ea25 AN |
1914 | mrq.cmd = &cmd; |
1915 | host->mrq = &mrq; | |
1916 | ||
1917 | /* | |
1918 | * In response to CMD19, the card sends 64 bytes of tuning | |
1919 | * block to the Host Controller. So we set the block size | |
1920 | * to 64 here. | |
1921 | */ | |
069c9f14 G |
1922 | if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { |
1923 | if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
1924 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), | |
1925 | SDHCI_BLOCK_SIZE); | |
1926 | else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) | |
1927 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1928 | SDHCI_BLOCK_SIZE); | |
1929 | } else { | |
1930 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1931 | SDHCI_BLOCK_SIZE); | |
1932 | } | |
b513ea25 AN |
1933 | |
1934 | /* | |
1935 | * The tuning block is sent by the card to the host controller. | |
1936 | * So we set the TRNS_READ bit in the Transfer Mode register. | |
1937 | * This also takes care of setting DMA Enable and Multi Block | |
1938 | * Select in the same register to 0. | |
1939 | */ | |
1940 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); | |
1941 | ||
1942 | sdhci_send_command(host, &cmd); | |
1943 | ||
1944 | host->cmd = NULL; | |
1945 | host->mrq = NULL; | |
1946 | ||
2b35bd83 | 1947 | spin_unlock_irqrestore(&host->lock, flags); |
b513ea25 AN |
1948 | /* Wait for Buffer Read Ready interrupt */ |
1949 | wait_event_interruptible_timeout(host->buf_ready_int, | |
1950 | (host->tuning_done == 1), | |
1951 | msecs_to_jiffies(50)); | |
2b35bd83 | 1952 | spin_lock_irqsave(&host->lock, flags); |
b513ea25 AN |
1953 | |
1954 | if (!host->tuning_done) { | |
2e4456f0 | 1955 | pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n"); |
b513ea25 AN |
1956 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
1957 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; | |
1958 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; | |
1959 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
1960 | ||
1961 | err = -EIO; | |
1962 | goto out; | |
1963 | } | |
1964 | ||
1965 | host->tuning_done = 0; | |
1966 | ||
1967 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
197160d5 NS |
1968 | |
1969 | /* eMMC spec does not require a delay between tuning cycles */ | |
1970 | if (opcode == MMC_SEND_TUNING_BLOCK) | |
1971 | mdelay(1); | |
b513ea25 AN |
1972 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
1973 | ||
1974 | /* | |
1975 | * The Host Driver has exhausted the maximum number of loops allowed, | |
1976 | * so use fixed sampling frequency. | |
1977 | */ | |
7ce45e95 | 1978 | if (tuning_loop_counter < 0) { |
b513ea25 AN |
1979 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
1980 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
7ce45e95 AC |
1981 | } |
1982 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { | |
2e4456f0 | 1983 | pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n"); |
114f2bf6 | 1984 | err = -EIO; |
b513ea25 AN |
1985 | } |
1986 | ||
1987 | out: | |
38e40bf5 | 1988 | if (tuning_count) { |
66c39dfc AH |
1989 | /* |
1990 | * In case tuning fails, host controllers which support | |
1991 | * re-tuning can try tuning again at a later time, when the | |
1992 | * re-tuning timer expires. So for these controllers, we | |
1993 | * return 0. Since there might be other controllers who do not | |
1994 | * have this capability, we return error for them. | |
1995 | */ | |
1996 | err = 0; | |
cf2b5eea AN |
1997 | } |
1998 | ||
66c39dfc | 1999 | host->mmc->retune_period = err ? 0 : tuning_count; |
cf2b5eea | 2000 | |
b537f94c RK |
2001 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
2002 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
d519c863 | 2003 | out_unlock: |
2b35bd83 | 2004 | spin_unlock_irqrestore(&host->lock, flags); |
66fd8ad5 | 2005 | sdhci_runtime_pm_put(host); |
b513ea25 AN |
2006 | |
2007 | return err; | |
2008 | } | |
2009 | ||
cb849648 AH |
2010 | static int sdhci_select_drive_strength(struct mmc_card *card, |
2011 | unsigned int max_dtr, int host_drv, | |
2012 | int card_drv, int *drv_type) | |
2013 | { | |
2014 | struct sdhci_host *host = mmc_priv(card->host); | |
2015 | ||
2016 | if (!host->ops->select_drive_strength) | |
2017 | return 0; | |
2018 | ||
2019 | return host->ops->select_drive_strength(host, card, max_dtr, host_drv, | |
2020 | card_drv, drv_type); | |
2021 | } | |
52983382 KL |
2022 | |
2023 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) | |
4d55c5a1 | 2024 | { |
4d55c5a1 AN |
2025 | /* Host Controller v3.00 defines preset value registers */ |
2026 | if (host->version < SDHCI_SPEC_300) | |
2027 | return; | |
2028 | ||
4d55c5a1 AN |
2029 | /* |
2030 | * We only enable or disable Preset Value if they are not already | |
2031 | * enabled or disabled respectively. Otherwise, we bail out. | |
2032 | */ | |
da91a8f9 RK |
2033 | if (host->preset_enabled != enable) { |
2034 | u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
2035 | ||
2036 | if (enable) | |
2037 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2038 | else | |
2039 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2040 | ||
4d55c5a1 | 2041 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
da91a8f9 RK |
2042 | |
2043 | if (enable) | |
2044 | host->flags |= SDHCI_PV_ENABLED; | |
2045 | else | |
2046 | host->flags &= ~SDHCI_PV_ENABLED; | |
2047 | ||
2048 | host->preset_enabled = enable; | |
4d55c5a1 | 2049 | } |
66fd8ad5 AH |
2050 | } |
2051 | ||
348487cb HC |
2052 | static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
2053 | int err) | |
2054 | { | |
2055 | struct sdhci_host *host = mmc_priv(mmc); | |
2056 | struct mmc_data *data = mrq->data; | |
2057 | ||
f48f039c | 2058 | if (data->host_cookie != COOKIE_UNMAPPED) |
771a3dc2 RK |
2059 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
2060 | data->flags & MMC_DATA_WRITE ? | |
2061 | DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
2062 | ||
2063 | data->host_cookie = COOKIE_UNMAPPED; | |
348487cb HC |
2064 | } |
2065 | ||
348487cb HC |
2066 | static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, |
2067 | bool is_first_req) | |
2068 | { | |
2069 | struct sdhci_host *host = mmc_priv(mmc); | |
2070 | ||
d31911b9 | 2071 | mrq->data->host_cookie = COOKIE_UNMAPPED; |
348487cb HC |
2072 | |
2073 | if (host->flags & SDHCI_REQ_USE_DMA) | |
94538e51 | 2074 | sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); |
348487cb HC |
2075 | } |
2076 | ||
71e69211 | 2077 | static void sdhci_card_event(struct mmc_host *mmc) |
d129bceb | 2078 | { |
71e69211 | 2079 | struct sdhci_host *host = mmc_priv(mmc); |
d129bceb | 2080 | unsigned long flags; |
2836766a | 2081 | int present; |
d129bceb | 2082 | |
722e1280 CD |
2083 | /* First check if client has provided their own card event */ |
2084 | if (host->ops->card_event) | |
2085 | host->ops->card_event(host); | |
2086 | ||
2836766a KK |
2087 | present = sdhci_do_get_cd(host); |
2088 | ||
d129bceb PO |
2089 | spin_lock_irqsave(&host->lock, flags); |
2090 | ||
66fd8ad5 | 2091 | /* Check host->mrq first in case we are runtime suspended */ |
2836766a | 2092 | if (host->mrq && !present) { |
a3c76eb9 | 2093 | pr_err("%s: Card removed during transfer!\n", |
66fd8ad5 | 2094 | mmc_hostname(host->mmc)); |
a3c76eb9 | 2095 | pr_err("%s: Resetting controller.\n", |
66fd8ad5 | 2096 | mmc_hostname(host->mmc)); |
d129bceb | 2097 | |
03231f9b RK |
2098 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
2099 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb | 2100 | |
66fd8ad5 AH |
2101 | host->mrq->cmd->error = -ENOMEDIUM; |
2102 | tasklet_schedule(&host->finish_tasklet); | |
d129bceb PO |
2103 | } |
2104 | ||
2105 | spin_unlock_irqrestore(&host->lock, flags); | |
71e69211 GL |
2106 | } |
2107 | ||
2108 | static const struct mmc_host_ops sdhci_ops = { | |
2109 | .request = sdhci_request, | |
348487cb HC |
2110 | .post_req = sdhci_post_req, |
2111 | .pre_req = sdhci_pre_req, | |
71e69211 | 2112 | .set_ios = sdhci_set_ios, |
94144a46 | 2113 | .get_cd = sdhci_get_cd, |
71e69211 GL |
2114 | .get_ro = sdhci_get_ro, |
2115 | .hw_reset = sdhci_hw_reset, | |
2116 | .enable_sdio_irq = sdhci_enable_sdio_irq, | |
2117 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, | |
b5540ce1 | 2118 | .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, |
71e69211 | 2119 | .execute_tuning = sdhci_execute_tuning, |
cb849648 | 2120 | .select_drive_strength = sdhci_select_drive_strength, |
71e69211 | 2121 | .card_event = sdhci_card_event, |
20b92a30 | 2122 | .card_busy = sdhci_card_busy, |
71e69211 GL |
2123 | }; |
2124 | ||
2125 | /*****************************************************************************\ | |
2126 | * * | |
2127 | * Tasklets * | |
2128 | * * | |
2129 | \*****************************************************************************/ | |
2130 | ||
d129bceb PO |
2131 | static void sdhci_tasklet_finish(unsigned long param) |
2132 | { | |
2133 | struct sdhci_host *host; | |
2134 | unsigned long flags; | |
2135 | struct mmc_request *mrq; | |
2136 | ||
2137 | host = (struct sdhci_host*)param; | |
2138 | ||
66fd8ad5 AH |
2139 | spin_lock_irqsave(&host->lock, flags); |
2140 | ||
0c9c99a7 CB |
2141 | /* |
2142 | * If this tasklet gets rescheduled while running, it will | |
2143 | * be run again afterwards but without any active request. | |
2144 | */ | |
66fd8ad5 AH |
2145 | if (!host->mrq) { |
2146 | spin_unlock_irqrestore(&host->lock, flags); | |
0c9c99a7 | 2147 | return; |
66fd8ad5 | 2148 | } |
d129bceb PO |
2149 | |
2150 | del_timer(&host->timer); | |
2151 | ||
2152 | mrq = host->mrq; | |
2153 | ||
054cedff RK |
2154 | /* |
2155 | * Always unmap the data buffers if they were mapped by | |
2156 | * sdhci_prepare_data() whenever we finish with a request. | |
2157 | * This avoids leaking DMA mappings on error. | |
2158 | */ | |
2159 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
2160 | struct mmc_data *data = mrq->data; | |
2161 | ||
2162 | if (data && data->host_cookie == COOKIE_MAPPED) { | |
2163 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
2164 | (data->flags & MMC_DATA_READ) ? | |
2165 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
2166 | data->host_cookie = COOKIE_UNMAPPED; | |
2167 | } | |
2168 | } | |
2169 | ||
d129bceb PO |
2170 | /* |
2171 | * The controller needs a reset of internal state machines | |
2172 | * upon error conditions. | |
2173 | */ | |
1e72859e | 2174 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
b7b4d342 | 2175 | ((mrq->cmd && mrq->cmd->error) || |
fce9d33f AG |
2176 | (mrq->sbc && mrq->sbc->error) || |
2177 | (mrq->data && ((mrq->data->error && !mrq->data->stop) || | |
2178 | (mrq->data->stop && mrq->data->stop->error))) || | |
2179 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
2180 | |
2181 | /* Some controllers need this kick or reset won't work here */ | |
8213af3b | 2182 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) |
645289dc | 2183 | /* This is to force an update */ |
1771059c | 2184 | host->ops->set_clock(host, host->clock); |
645289dc PO |
2185 | |
2186 | /* Spec says we should do both at the same time, but Ricoh | |
2187 | controllers do not like that. */ | |
03231f9b RK |
2188 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
2189 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb PO |
2190 | } |
2191 | ||
2192 | host->mrq = NULL; | |
2193 | host->cmd = NULL; | |
2194 | host->data = NULL; | |
2195 | ||
f9134319 | 2196 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 2197 | sdhci_deactivate_led(host); |
2f730fec | 2198 | #endif |
d129bceb | 2199 | |
5f25a66f | 2200 | mmiowb(); |
d129bceb PO |
2201 | spin_unlock_irqrestore(&host->lock, flags); |
2202 | ||
2203 | mmc_request_done(host->mmc, mrq); | |
66fd8ad5 | 2204 | sdhci_runtime_pm_put(host); |
d129bceb PO |
2205 | } |
2206 | ||
2207 | static void sdhci_timeout_timer(unsigned long data) | |
2208 | { | |
2209 | struct sdhci_host *host; | |
2210 | unsigned long flags; | |
2211 | ||
2212 | host = (struct sdhci_host*)data; | |
2213 | ||
2214 | spin_lock_irqsave(&host->lock, flags); | |
2215 | ||
2216 | if (host->mrq) { | |
2e4456f0 MV |
2217 | pr_err("%s: Timeout waiting for hardware interrupt.\n", |
2218 | mmc_hostname(host->mmc)); | |
d129bceb PO |
2219 | sdhci_dumpregs(host); |
2220 | ||
2221 | if (host->data) { | |
17b0429d | 2222 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
2223 | sdhci_finish_data(host); |
2224 | } else { | |
2225 | if (host->cmd) | |
17b0429d | 2226 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 2227 | else |
17b0429d | 2228 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
2229 | |
2230 | tasklet_schedule(&host->finish_tasklet); | |
2231 | } | |
2232 | } | |
2233 | ||
5f25a66f | 2234 | mmiowb(); |
d129bceb PO |
2235 | spin_unlock_irqrestore(&host->lock, flags); |
2236 | } | |
2237 | ||
2238 | /*****************************************************************************\ | |
2239 | * * | |
2240 | * Interrupt handling * | |
2241 | * * | |
2242 | \*****************************************************************************/ | |
2243 | ||
61541397 | 2244 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) |
d129bceb PO |
2245 | { |
2246 | BUG_ON(intmask == 0); | |
2247 | ||
2248 | if (!host->cmd) { | |
2e4456f0 MV |
2249 | pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", |
2250 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2251 | sdhci_dumpregs(host); |
2252 | return; | |
2253 | } | |
2254 | ||
ec014cba RK |
2255 | if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | |
2256 | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { | |
2257 | if (intmask & SDHCI_INT_TIMEOUT) | |
2258 | host->cmd->error = -ETIMEDOUT; | |
2259 | else | |
2260 | host->cmd->error = -EILSEQ; | |
43b58b36 | 2261 | |
71fcbda0 RK |
2262 | /* |
2263 | * If this command initiates a data phase and a response | |
2264 | * CRC error is signalled, the card can start transferring | |
2265 | * data - the card may have received the command without | |
2266 | * error. We must not terminate the mmc_request early. | |
2267 | * | |
2268 | * If the card did not receive the command or returned an | |
2269 | * error which prevented it sending data, the data phase | |
2270 | * will time out. | |
2271 | */ | |
2272 | if (host->cmd->data && | |
2273 | (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == | |
2274 | SDHCI_INT_CRC) { | |
2275 | host->cmd = NULL; | |
2276 | return; | |
2277 | } | |
2278 | ||
d129bceb | 2279 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
2280 | return; |
2281 | } | |
2282 | ||
2283 | /* | |
2284 | * The host can send and interrupt when the busy state has | |
2285 | * ended, allowing us to wait without wasting CPU cycles. | |
2286 | * Unfortunately this is overloaded on the "data complete" | |
2287 | * interrupt, so we need to take some care when handling | |
2288 | * it. | |
2289 | * | |
2290 | * Note: The 1.0 specification is a bit ambiguous about this | |
2291 | * feature so there might be some problems with older | |
2292 | * controllers. | |
2293 | */ | |
2294 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
2295 | if (host->cmd->data) | |
2e4456f0 | 2296 | DBG("Cannot wait for busy signal when also doing a data transfer"); |
e99783a4 CM |
2297 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) |
2298 | && !host->busy_handle) { | |
2299 | /* Mark that command complete before busy is ended */ | |
2300 | host->busy_handle = 1; | |
e809517f | 2301 | return; |
e99783a4 | 2302 | } |
f945405c BD |
2303 | |
2304 | /* The controller does not support the end-of-busy IRQ, | |
2305 | * fall through and take the SDHCI_INT_RESPONSE */ | |
61541397 AH |
2306 | } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && |
2307 | host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) { | |
2308 | *mask &= ~SDHCI_INT_DATA_END; | |
e809517f PO |
2309 | } |
2310 | ||
2311 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 2312 | sdhci_finish_command(host); |
d129bceb PO |
2313 | } |
2314 | ||
0957c333 | 2315 | #ifdef CONFIG_MMC_DEBUG |
08621b18 | 2316 | static void sdhci_adma_show_error(struct sdhci_host *host) |
6882a8c0 BD |
2317 | { |
2318 | const char *name = mmc_hostname(host->mmc); | |
1c3d5f6d | 2319 | void *desc = host->adma_table; |
6882a8c0 BD |
2320 | |
2321 | sdhci_dumpregs(host); | |
2322 | ||
2323 | while (true) { | |
e57a5f61 AH |
2324 | struct sdhci_adma2_64_desc *dma_desc = desc; |
2325 | ||
2326 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
2327 | DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
2328 | name, desc, le32_to_cpu(dma_desc->addr_hi), | |
2329 | le32_to_cpu(dma_desc->addr_lo), | |
2330 | le16_to_cpu(dma_desc->len), | |
2331 | le16_to_cpu(dma_desc->cmd)); | |
2332 | else | |
2333 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
2334 | name, desc, le32_to_cpu(dma_desc->addr_lo), | |
2335 | le16_to_cpu(dma_desc->len), | |
2336 | le16_to_cpu(dma_desc->cmd)); | |
6882a8c0 | 2337 | |
76fe379a | 2338 | desc += host->desc_sz; |
6882a8c0 | 2339 | |
0545230f | 2340 | if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) |
6882a8c0 BD |
2341 | break; |
2342 | } | |
2343 | } | |
2344 | #else | |
08621b18 | 2345 | static void sdhci_adma_show_error(struct sdhci_host *host) { } |
6882a8c0 BD |
2346 | #endif |
2347 | ||
d129bceb PO |
2348 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
2349 | { | |
069c9f14 | 2350 | u32 command; |
d129bceb PO |
2351 | BUG_ON(intmask == 0); |
2352 | ||
b513ea25 AN |
2353 | /* CMD19 generates _only_ Buffer Read Ready interrupt */ |
2354 | if (intmask & SDHCI_INT_DATA_AVAIL) { | |
069c9f14 G |
2355 | command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); |
2356 | if (command == MMC_SEND_TUNING_BLOCK || | |
2357 | command == MMC_SEND_TUNING_BLOCK_HS200) { | |
b513ea25 AN |
2358 | host->tuning_done = 1; |
2359 | wake_up(&host->buf_ready_int); | |
2360 | return; | |
2361 | } | |
2362 | } | |
2363 | ||
d129bceb PO |
2364 | if (!host->data) { |
2365 | /* | |
e809517f PO |
2366 | * The "data complete" interrupt is also used to |
2367 | * indicate that a busy state has ended. See comment | |
2368 | * above in sdhci_cmd_irq(). | |
d129bceb | 2369 | */ |
e809517f | 2370 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
c5abd5e8 MC |
2371 | if (intmask & SDHCI_INT_DATA_TIMEOUT) { |
2372 | host->cmd->error = -ETIMEDOUT; | |
2373 | tasklet_schedule(&host->finish_tasklet); | |
2374 | return; | |
2375 | } | |
e809517f | 2376 | if (intmask & SDHCI_INT_DATA_END) { |
e99783a4 CM |
2377 | /* |
2378 | * Some cards handle busy-end interrupt | |
2379 | * before the command completed, so make | |
2380 | * sure we do things in the proper order. | |
2381 | */ | |
2382 | if (host->busy_handle) | |
2383 | sdhci_finish_command(host); | |
2384 | else | |
2385 | host->busy_handle = 1; | |
e809517f PO |
2386 | return; |
2387 | } | |
2388 | } | |
d129bceb | 2389 | |
2e4456f0 MV |
2390 | pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", |
2391 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2392 | sdhci_dumpregs(host); |
2393 | ||
2394 | return; | |
2395 | } | |
2396 | ||
2397 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d | 2398 | host->data->error = -ETIMEDOUT; |
22113efd AL |
2399 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
2400 | host->data->error = -EILSEQ; | |
2401 | else if ((intmask & SDHCI_INT_DATA_CRC) && | |
2402 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) | |
2403 | != MMC_BUS_TEST_R) | |
17b0429d | 2404 | host->data->error = -EILSEQ; |
6882a8c0 | 2405 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
a3c76eb9 | 2406 | pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); |
08621b18 | 2407 | sdhci_adma_show_error(host); |
2134a922 | 2408 | host->data->error = -EIO; |
a4071fbb HZ |
2409 | if (host->ops->adma_workaround) |
2410 | host->ops->adma_workaround(host, intmask); | |
6882a8c0 | 2411 | } |
d129bceb | 2412 | |
17b0429d | 2413 | if (host->data->error) |
d129bceb PO |
2414 | sdhci_finish_data(host); |
2415 | else { | |
a406f5a3 | 2416 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
2417 | sdhci_transfer_pio(host); |
2418 | ||
6ba736a1 PO |
2419 | /* |
2420 | * We currently don't do anything fancy with DMA | |
2421 | * boundaries, but as we can't disable the feature | |
2422 | * we need to at least restart the transfer. | |
f6a03cbf MV |
2423 | * |
2424 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) | |
2425 | * should return a valid address to continue from, but as | |
2426 | * some controllers are faulty, don't trust them. | |
6ba736a1 | 2427 | */ |
f6a03cbf MV |
2428 | if (intmask & SDHCI_INT_DMA_END) { |
2429 | u32 dmastart, dmanow; | |
2430 | dmastart = sg_dma_address(host->data->sg); | |
2431 | dmanow = dmastart + host->data->bytes_xfered; | |
2432 | /* | |
2433 | * Force update to the next DMA block boundary. | |
2434 | */ | |
2435 | dmanow = (dmanow & | |
2436 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + | |
2437 | SDHCI_DEFAULT_BOUNDARY_SIZE; | |
2438 | host->data->bytes_xfered = dmanow - dmastart; | |
2439 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," | |
2440 | " next 0x%08x\n", | |
2441 | mmc_hostname(host->mmc), dmastart, | |
2442 | host->data->bytes_xfered, dmanow); | |
2443 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); | |
2444 | } | |
6ba736a1 | 2445 | |
e538fbe8 PO |
2446 | if (intmask & SDHCI_INT_DATA_END) { |
2447 | if (host->cmd) { | |
2448 | /* | |
2449 | * Data managed to finish before the | |
2450 | * command completed. Make sure we do | |
2451 | * things in the proper order. | |
2452 | */ | |
2453 | host->data_early = 1; | |
2454 | } else { | |
2455 | sdhci_finish_data(host); | |
2456 | } | |
2457 | } | |
d129bceb PO |
2458 | } |
2459 | } | |
2460 | ||
7d12e780 | 2461 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb | 2462 | { |
781e989c | 2463 | irqreturn_t result = IRQ_NONE; |
66fd8ad5 | 2464 | struct sdhci_host *host = dev_id; |
41005003 | 2465 | u32 intmask, mask, unexpected = 0; |
781e989c | 2466 | int max_loops = 16; |
d129bceb PO |
2467 | |
2468 | spin_lock(&host->lock); | |
2469 | ||
be138554 | 2470 | if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { |
66fd8ad5 | 2471 | spin_unlock(&host->lock); |
655bca76 | 2472 | return IRQ_NONE; |
66fd8ad5 AH |
2473 | } |
2474 | ||
4e4141a5 | 2475 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
62df67a5 | 2476 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
2477 | result = IRQ_NONE; |
2478 | goto out; | |
2479 | } | |
2480 | ||
41005003 RK |
2481 | do { |
2482 | /* Clear selected interrupts. */ | |
2483 | mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | | |
2484 | SDHCI_INT_BUS_POWER); | |
2485 | sdhci_writel(host, mask, SDHCI_INT_STATUS); | |
d129bceb | 2486 | |
41005003 RK |
2487 | DBG("*** %s got interrupt: 0x%08x\n", |
2488 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 2489 | |
41005003 RK |
2490 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
2491 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
2492 | SDHCI_CARD_PRESENT; | |
d129bceb | 2493 | |
41005003 RK |
2494 | /* |
2495 | * There is a observation on i.mx esdhc. INSERT | |
2496 | * bit will be immediately set again when it gets | |
2497 | * cleared, if a card is inserted. We have to mask | |
2498 | * the irq to prevent interrupt storm which will | |
2499 | * freeze the system. And the REMOVE gets the | |
2500 | * same situation. | |
2501 | * | |
2502 | * More testing are needed here to ensure it works | |
2503 | * for other platforms though. | |
2504 | */ | |
b537f94c RK |
2505 | host->ier &= ~(SDHCI_INT_CARD_INSERT | |
2506 | SDHCI_INT_CARD_REMOVE); | |
2507 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : | |
2508 | SDHCI_INT_CARD_INSERT; | |
2509 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
2510 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
41005003 RK |
2511 | |
2512 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | | |
2513 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | |
3560db8e RK |
2514 | |
2515 | host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | | |
2516 | SDHCI_INT_CARD_REMOVE); | |
2517 | result = IRQ_WAKE_THREAD; | |
41005003 | 2518 | } |
d129bceb | 2519 | |
41005003 | 2520 | if (intmask & SDHCI_INT_CMD_MASK) |
61541397 AH |
2521 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, |
2522 | &intmask); | |
964f9ce2 | 2523 | |
41005003 RK |
2524 | if (intmask & SDHCI_INT_DATA_MASK) |
2525 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); | |
d129bceb | 2526 | |
41005003 RK |
2527 | if (intmask & SDHCI_INT_BUS_POWER) |
2528 | pr_err("%s: Card is consuming too much power!\n", | |
2529 | mmc_hostname(host->mmc)); | |
3192a28f | 2530 | |
781e989c RK |
2531 | if (intmask & SDHCI_INT_CARD_INT) { |
2532 | sdhci_enable_sdio_irq_nolock(host, false); | |
2533 | host->thread_isr |= SDHCI_INT_CARD_INT; | |
2534 | result = IRQ_WAKE_THREAD; | |
2535 | } | |
f75979b7 | 2536 | |
41005003 RK |
2537 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
2538 | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | | |
2539 | SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | | |
2540 | SDHCI_INT_CARD_INT); | |
f75979b7 | 2541 | |
41005003 RK |
2542 | if (intmask) { |
2543 | unexpected |= intmask; | |
2544 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); | |
2545 | } | |
d129bceb | 2546 | |
781e989c RK |
2547 | if (result == IRQ_NONE) |
2548 | result = IRQ_HANDLED; | |
d129bceb | 2549 | |
41005003 | 2550 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
41005003 | 2551 | } while (intmask && --max_loops); |
d129bceb PO |
2552 | out: |
2553 | spin_unlock(&host->lock); | |
2554 | ||
6379b237 AS |
2555 | if (unexpected) { |
2556 | pr_err("%s: Unexpected interrupt 0x%08x.\n", | |
2557 | mmc_hostname(host->mmc), unexpected); | |
2558 | sdhci_dumpregs(host); | |
2559 | } | |
f75979b7 | 2560 | |
d129bceb PO |
2561 | return result; |
2562 | } | |
2563 | ||
781e989c RK |
2564 | static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) |
2565 | { | |
2566 | struct sdhci_host *host = dev_id; | |
2567 | unsigned long flags; | |
2568 | u32 isr; | |
2569 | ||
2570 | spin_lock_irqsave(&host->lock, flags); | |
2571 | isr = host->thread_isr; | |
2572 | host->thread_isr = 0; | |
2573 | spin_unlock_irqrestore(&host->lock, flags); | |
2574 | ||
3560db8e RK |
2575 | if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
2576 | sdhci_card_event(host->mmc); | |
2577 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
2578 | } | |
2579 | ||
781e989c RK |
2580 | if (isr & SDHCI_INT_CARD_INT) { |
2581 | sdio_run_irqs(host->mmc); | |
2582 | ||
2583 | spin_lock_irqsave(&host->lock, flags); | |
2584 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) | |
2585 | sdhci_enable_sdio_irq_nolock(host, true); | |
2586 | spin_unlock_irqrestore(&host->lock, flags); | |
2587 | } | |
2588 | ||
2589 | return isr ? IRQ_HANDLED : IRQ_NONE; | |
2590 | } | |
2591 | ||
d129bceb PO |
2592 | /*****************************************************************************\ |
2593 | * * | |
2594 | * Suspend/resume * | |
2595 | * * | |
2596 | \*****************************************************************************/ | |
2597 | ||
2598 | #ifdef CONFIG_PM | |
ad080d79 KL |
2599 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
2600 | { | |
2601 | u8 val; | |
2602 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2603 | | SDHCI_WAKE_ON_INT; | |
2604 | ||
2605 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2606 | val |= mask ; | |
2607 | /* Avoid fake wake up */ | |
2608 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
2609 | val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); | |
2610 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2611 | } | |
2612 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); | |
2613 | ||
0b10f478 | 2614 | static void sdhci_disable_irq_wakeups(struct sdhci_host *host) |
ad080d79 KL |
2615 | { |
2616 | u8 val; | |
2617 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2618 | | SDHCI_WAKE_ON_INT; | |
2619 | ||
2620 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2621 | val &= ~mask; | |
2622 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2623 | } | |
d129bceb | 2624 | |
29495aa0 | 2625 | int sdhci_suspend_host(struct sdhci_host *host) |
d129bceb | 2626 | { |
7260cf5e AV |
2627 | sdhci_disable_card_detection(host); |
2628 | ||
66c39dfc AH |
2629 | mmc_retune_timer_stop(host->mmc); |
2630 | mmc_retune_needed(host->mmc); | |
cf2b5eea | 2631 | |
ad080d79 | 2632 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
b537f94c RK |
2633 | host->ier = 0; |
2634 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); | |
2635 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
ad080d79 KL |
2636 | free_irq(host->irq, host); |
2637 | } else { | |
2638 | sdhci_enable_irq_wakeups(host); | |
2639 | enable_irq_wake(host->irq); | |
2640 | } | |
4ee14ec6 | 2641 | return 0; |
d129bceb PO |
2642 | } |
2643 | ||
b8c86fc5 | 2644 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 2645 | |
b8c86fc5 PO |
2646 | int sdhci_resume_host(struct sdhci_host *host) |
2647 | { | |
4ee14ec6 | 2648 | int ret = 0; |
d129bceb | 2649 | |
a13abc7b | 2650 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
2651 | if (host->ops->enable_dma) |
2652 | host->ops->enable_dma(host); | |
2653 | } | |
d129bceb | 2654 | |
6308d290 AH |
2655 | if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && |
2656 | (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { | |
2657 | /* Card keeps power but host controller does not */ | |
2658 | sdhci_init(host, 0); | |
2659 | host->pwr = 0; | |
2660 | host->clock = 0; | |
2661 | sdhci_do_set_ios(host, &host->mmc->ios); | |
2662 | } else { | |
2663 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); | |
2664 | mmiowb(); | |
2665 | } | |
b8c86fc5 | 2666 | |
14a7b416 HC |
2667 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
2668 | ret = request_threaded_irq(host->irq, sdhci_irq, | |
2669 | sdhci_thread_irq, IRQF_SHARED, | |
2670 | mmc_hostname(host->mmc), host); | |
2671 | if (ret) | |
2672 | return ret; | |
2673 | } else { | |
2674 | sdhci_disable_irq_wakeups(host); | |
2675 | disable_irq_wake(host->irq); | |
2676 | } | |
2677 | ||
7260cf5e AV |
2678 | sdhci_enable_card_detection(host); |
2679 | ||
2f4cbb3d | 2680 | return ret; |
d129bceb PO |
2681 | } |
2682 | ||
b8c86fc5 | 2683 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
66fd8ad5 AH |
2684 | |
2685 | static int sdhci_runtime_pm_get(struct sdhci_host *host) | |
2686 | { | |
2687 | return pm_runtime_get_sync(host->mmc->parent); | |
2688 | } | |
2689 | ||
2690 | static int sdhci_runtime_pm_put(struct sdhci_host *host) | |
2691 | { | |
2692 | pm_runtime_mark_last_busy(host->mmc->parent); | |
2693 | return pm_runtime_put_autosuspend(host->mmc->parent); | |
2694 | } | |
2695 | ||
f0710a55 AH |
2696 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
2697 | { | |
5c671c41 | 2698 | if (host->bus_on) |
f0710a55 AH |
2699 | return; |
2700 | host->bus_on = true; | |
2701 | pm_runtime_get_noresume(host->mmc->parent); | |
2702 | } | |
2703 | ||
2704 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) | |
2705 | { | |
5c671c41 | 2706 | if (!host->bus_on) |
f0710a55 AH |
2707 | return; |
2708 | host->bus_on = false; | |
2709 | pm_runtime_put_noidle(host->mmc->parent); | |
2710 | } | |
2711 | ||
66fd8ad5 AH |
2712 | int sdhci_runtime_suspend_host(struct sdhci_host *host) |
2713 | { | |
2714 | unsigned long flags; | |
66fd8ad5 | 2715 | |
66c39dfc AH |
2716 | mmc_retune_timer_stop(host->mmc); |
2717 | mmc_retune_needed(host->mmc); | |
66fd8ad5 AH |
2718 | |
2719 | spin_lock_irqsave(&host->lock, flags); | |
b537f94c RK |
2720 | host->ier &= SDHCI_INT_CARD_INT; |
2721 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
2722 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
66fd8ad5 AH |
2723 | spin_unlock_irqrestore(&host->lock, flags); |
2724 | ||
781e989c | 2725 | synchronize_hardirq(host->irq); |
66fd8ad5 AH |
2726 | |
2727 | spin_lock_irqsave(&host->lock, flags); | |
2728 | host->runtime_suspended = true; | |
2729 | spin_unlock_irqrestore(&host->lock, flags); | |
2730 | ||
8a125bad | 2731 | return 0; |
66fd8ad5 AH |
2732 | } |
2733 | EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); | |
2734 | ||
2735 | int sdhci_runtime_resume_host(struct sdhci_host *host) | |
2736 | { | |
2737 | unsigned long flags; | |
8a125bad | 2738 | int host_flags = host->flags; |
66fd8ad5 AH |
2739 | |
2740 | if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
2741 | if (host->ops->enable_dma) | |
2742 | host->ops->enable_dma(host); | |
2743 | } | |
2744 | ||
2745 | sdhci_init(host, 0); | |
2746 | ||
2747 | /* Force clock and power re-program */ | |
2748 | host->pwr = 0; | |
2749 | host->clock = 0; | |
3396e736 | 2750 | sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); |
66fd8ad5 AH |
2751 | sdhci_do_set_ios(host, &host->mmc->ios); |
2752 | ||
52983382 KL |
2753 | if ((host_flags & SDHCI_PV_ENABLED) && |
2754 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { | |
2755 | spin_lock_irqsave(&host->lock, flags); | |
2756 | sdhci_enable_preset_value(host, true); | |
2757 | spin_unlock_irqrestore(&host->lock, flags); | |
2758 | } | |
66fd8ad5 | 2759 | |
66fd8ad5 AH |
2760 | spin_lock_irqsave(&host->lock, flags); |
2761 | ||
2762 | host->runtime_suspended = false; | |
2763 | ||
2764 | /* Enable SDIO IRQ */ | |
ef104333 | 2765 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
66fd8ad5 AH |
2766 | sdhci_enable_sdio_irq_nolock(host, true); |
2767 | ||
2768 | /* Enable Card Detection */ | |
2769 | sdhci_enable_card_detection(host); | |
2770 | ||
2771 | spin_unlock_irqrestore(&host->lock, flags); | |
2772 | ||
8a125bad | 2773 | return 0; |
66fd8ad5 AH |
2774 | } |
2775 | EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); | |
2776 | ||
162d6f98 | 2777 | #endif /* CONFIG_PM */ |
66fd8ad5 | 2778 | |
d129bceb PO |
2779 | /*****************************************************************************\ |
2780 | * * | |
b8c86fc5 | 2781 | * Device allocation/registration * |
d129bceb PO |
2782 | * * |
2783 | \*****************************************************************************/ | |
2784 | ||
b8c86fc5 PO |
2785 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
2786 | size_t priv_size) | |
d129bceb | 2787 | { |
d129bceb PO |
2788 | struct mmc_host *mmc; |
2789 | struct sdhci_host *host; | |
2790 | ||
b8c86fc5 | 2791 | WARN_ON(dev == NULL); |
d129bceb | 2792 | |
b8c86fc5 | 2793 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 2794 | if (!mmc) |
b8c86fc5 | 2795 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
2796 | |
2797 | host = mmc_priv(mmc); | |
2798 | host->mmc = mmc; | |
bf60e592 AH |
2799 | host->mmc_host_ops = sdhci_ops; |
2800 | mmc->ops = &host->mmc_host_ops; | |
d129bceb | 2801 | |
b8c86fc5 PO |
2802 | return host; |
2803 | } | |
8a4da143 | 2804 | |
b8c86fc5 | 2805 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 2806 | |
b8c86fc5 PO |
2807 | int sdhci_add_host(struct sdhci_host *host) |
2808 | { | |
2809 | struct mmc_host *mmc; | |
bd6a8c30 | 2810 | u32 caps[2] = {0, 0}; |
f2119df6 AN |
2811 | u32 max_current_caps; |
2812 | unsigned int ocr_avail; | |
f5fa92e5 | 2813 | unsigned int override_timeout_clk; |
59241757 | 2814 | u32 max_clk; |
b8c86fc5 | 2815 | int ret; |
d129bceb | 2816 | |
b8c86fc5 PO |
2817 | WARN_ON(host == NULL); |
2818 | if (host == NULL) | |
2819 | return -EINVAL; | |
d129bceb | 2820 | |
b8c86fc5 | 2821 | mmc = host->mmc; |
d129bceb | 2822 | |
b8c86fc5 PO |
2823 | if (debug_quirks) |
2824 | host->quirks = debug_quirks; | |
66fd8ad5 AH |
2825 | if (debug_quirks2) |
2826 | host->quirks2 = debug_quirks2; | |
d129bceb | 2827 | |
f5fa92e5 AH |
2828 | override_timeout_clk = host->timeout_clk; |
2829 | ||
03231f9b | 2830 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d96649ed | 2831 | |
4e4141a5 | 2832 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
2833 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
2834 | >> SDHCI_SPEC_VER_SHIFT; | |
85105c53 | 2835 | if (host->version > SDHCI_SPEC_300) { |
2e4456f0 MV |
2836 | pr_err("%s: Unknown controller version (%d). You may experience problems.\n", |
2837 | mmc_hostname(mmc), host->version); | |
4a965505 PO |
2838 | } |
2839 | ||
f2119df6 | 2840 | caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
ccc92c23 | 2841 | sdhci_readl(host, SDHCI_CAPABILITIES); |
d129bceb | 2842 | |
bd6a8c30 PR |
2843 | if (host->version >= SDHCI_SPEC_300) |
2844 | caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? | |
2845 | host->caps1 : | |
2846 | sdhci_readl(host, SDHCI_CAPABILITIES_1); | |
f2119df6 | 2847 | |
b8c86fc5 | 2848 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
a13abc7b | 2849 | host->flags |= SDHCI_USE_SDMA; |
f2119df6 | 2850 | else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) |
a13abc7b | 2851 | DBG("Controller doesn't have SDMA capability\n"); |
67435274 | 2852 | else |
a13abc7b | 2853 | host->flags |= SDHCI_USE_SDMA; |
d129bceb | 2854 | |
b8c86fc5 | 2855 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
a13abc7b | 2856 | (host->flags & SDHCI_USE_SDMA)) { |
cee687ce | 2857 | DBG("Disabling DMA as it is marked broken\n"); |
a13abc7b | 2858 | host->flags &= ~SDHCI_USE_SDMA; |
7c168e3d FT |
2859 | } |
2860 | ||
f2119df6 AN |
2861 | if ((host->version >= SDHCI_SPEC_200) && |
2862 | (caps[0] & SDHCI_CAN_DO_ADMA2)) | |
a13abc7b | 2863 | host->flags |= SDHCI_USE_ADMA; |
2134a922 PO |
2864 | |
2865 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
2866 | (host->flags & SDHCI_USE_ADMA)) { | |
2867 | DBG("Disabling ADMA as it is marked broken\n"); | |
2868 | host->flags &= ~SDHCI_USE_ADMA; | |
2869 | } | |
2870 | ||
e57a5f61 AH |
2871 | /* |
2872 | * It is assumed that a 64-bit capable device has set a 64-bit DMA mask | |
2873 | * and *must* do 64-bit DMA. A driver has the opportunity to change | |
2874 | * that during the first call to ->enable_dma(). Similarly | |
2875 | * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to | |
2876 | * implement. | |
2877 | */ | |
5eaa7476 | 2878 | if (caps[0] & SDHCI_CAN_64BIT) |
e57a5f61 AH |
2879 | host->flags |= SDHCI_USE_64_BIT_DMA; |
2880 | ||
a13abc7b | 2881 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
2882 | if (host->ops->enable_dma) { |
2883 | if (host->ops->enable_dma(host)) { | |
6606110d | 2884 | pr_warn("%s: No suitable DMA available - falling back to PIO\n", |
b8c86fc5 | 2885 | mmc_hostname(mmc)); |
a13abc7b RR |
2886 | host->flags &= |
2887 | ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); | |
b8c86fc5 | 2888 | } |
d129bceb PO |
2889 | } |
2890 | } | |
2891 | ||
e57a5f61 AH |
2892 | /* SDMA does not support 64-bit DMA */ |
2893 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
2894 | host->flags &= ~SDHCI_USE_SDMA; | |
2895 | ||
2134a922 | 2896 | if (host->flags & SDHCI_USE_ADMA) { |
e66e61cb RK |
2897 | dma_addr_t dma; |
2898 | void *buf; | |
2899 | ||
2134a922 | 2900 | /* |
76fe379a AH |
2901 | * The DMA descriptor table size is calculated as the maximum |
2902 | * number of segments times 2, to allow for an alignment | |
2903 | * descriptor for each segment, plus 1 for a nop end descriptor, | |
2904 | * all multipled by the descriptor size. | |
2134a922 | 2905 | */ |
e57a5f61 AH |
2906 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
2907 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * | |
2908 | SDHCI_ADMA2_64_DESC_SZ; | |
e57a5f61 | 2909 | host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; |
e57a5f61 AH |
2910 | } else { |
2911 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * | |
2912 | SDHCI_ADMA2_32_DESC_SZ; | |
e57a5f61 | 2913 | host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; |
e57a5f61 | 2914 | } |
e66e61cb | 2915 | |
04a5ae6f | 2916 | host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; |
e66e61cb RK |
2917 | buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + |
2918 | host->adma_table_sz, &dma, GFP_KERNEL); | |
2919 | if (!buf) { | |
6606110d | 2920 | pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", |
2134a922 PO |
2921 | mmc_hostname(mmc)); |
2922 | host->flags &= ~SDHCI_USE_ADMA; | |
e66e61cb RK |
2923 | } else if ((dma + host->align_buffer_sz) & |
2924 | (SDHCI_ADMA2_DESC_ALIGN - 1)) { | |
6606110d JP |
2925 | pr_warn("%s: unable to allocate aligned ADMA descriptor\n", |
2926 | mmc_hostname(mmc)); | |
d1e49f77 | 2927 | host->flags &= ~SDHCI_USE_ADMA; |
e66e61cb RK |
2928 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
2929 | host->adma_table_sz, buf, dma); | |
2930 | } else { | |
2931 | host->align_buffer = buf; | |
2932 | host->align_addr = dma; | |
edd63fcc | 2933 | |
e66e61cb RK |
2934 | host->adma_table = buf + host->align_buffer_sz; |
2935 | host->adma_addr = dma + host->align_buffer_sz; | |
2936 | } | |
2134a922 PO |
2937 | } |
2938 | ||
7659150c PO |
2939 | /* |
2940 | * If we use DMA, then it's up to the caller to set the DMA | |
2941 | * mask, but PIO does not need the hw shim so we set a new | |
2942 | * mask here in that case. | |
2943 | */ | |
a13abc7b | 2944 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
7659150c | 2945 | host->dma_mask = DMA_BIT_MASK(64); |
4e743f1f | 2946 | mmc_dev(mmc)->dma_mask = &host->dma_mask; |
7659150c | 2947 | } |
d129bceb | 2948 | |
c4687d5f | 2949 | if (host->version >= SDHCI_SPEC_300) |
f2119df6 | 2950 | host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) |
c4687d5f ZG |
2951 | >> SDHCI_CLOCK_BASE_SHIFT; |
2952 | else | |
f2119df6 | 2953 | host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) |
c4687d5f ZG |
2954 | >> SDHCI_CLOCK_BASE_SHIFT; |
2955 | ||
4240ff0a | 2956 | host->max_clk *= 1000000; |
f27f47ef AV |
2957 | if (host->max_clk == 0 || host->quirks & |
2958 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { | |
4240ff0a | 2959 | if (!host->ops->get_max_clock) { |
2e4456f0 MV |
2960 | pr_err("%s: Hardware doesn't specify base clock frequency.\n", |
2961 | mmc_hostname(mmc)); | |
4240ff0a BD |
2962 | return -ENODEV; |
2963 | } | |
2964 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 2965 | } |
d129bceb | 2966 | |
c3ed3877 AN |
2967 | /* |
2968 | * In case of Host Controller v3.00, find out whether clock | |
2969 | * multiplier is supported. | |
2970 | */ | |
2971 | host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> | |
2972 | SDHCI_CLOCK_MUL_SHIFT; | |
2973 | ||
2974 | /* | |
2975 | * In case the value in Clock Multiplier is 0, then programmable | |
2976 | * clock mode is not supported, otherwise the actual clock | |
2977 | * multiplier is one more than the value of Clock Multiplier | |
2978 | * in the Capabilities Register. | |
2979 | */ | |
2980 | if (host->clk_mul) | |
2981 | host->clk_mul += 1; | |
2982 | ||
d129bceb PO |
2983 | /* |
2984 | * Set host parameters. | |
2985 | */ | |
59241757 DA |
2986 | max_clk = host->max_clk; |
2987 | ||
ce5f036b | 2988 | if (host->ops->get_min_clock) |
a9e58f25 | 2989 | mmc->f_min = host->ops->get_min_clock(host); |
c3ed3877 AN |
2990 | else if (host->version >= SDHCI_SPEC_300) { |
2991 | if (host->clk_mul) { | |
2992 | mmc->f_min = (host->max_clk * host->clk_mul) / 1024; | |
59241757 | 2993 | max_clk = host->max_clk * host->clk_mul; |
c3ed3877 AN |
2994 | } else |
2995 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; | |
2996 | } else | |
0397526d | 2997 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
15ec4461 | 2998 | |
59241757 DA |
2999 | if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk))) |
3000 | mmc->f_max = max_clk; | |
3001 | ||
28aab053 AD |
3002 | if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { |
3003 | host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> | |
3004 | SDHCI_TIMEOUT_CLK_SHIFT; | |
3005 | if (host->timeout_clk == 0) { | |
3006 | if (host->ops->get_timeout_clock) { | |
3007 | host->timeout_clk = | |
3008 | host->ops->get_timeout_clock(host); | |
3009 | } else { | |
3010 | pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", | |
3011 | mmc_hostname(mmc)); | |
3012 | return -ENODEV; | |
3013 | } | |
272308ca | 3014 | } |
272308ca | 3015 | |
28aab053 AD |
3016 | if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) |
3017 | host->timeout_clk *= 1000; | |
272308ca | 3018 | |
99513624 AH |
3019 | if (override_timeout_clk) |
3020 | host->timeout_clk = override_timeout_clk; | |
3021 | ||
28aab053 | 3022 | mmc->max_busy_timeout = host->ops->get_max_timeout_count ? |
a6ff5aeb | 3023 | host->ops->get_max_timeout_count(host) : 1 << 27; |
28aab053 AD |
3024 | mmc->max_busy_timeout /= host->timeout_clk; |
3025 | } | |
58d1246d | 3026 | |
e89d456f | 3027 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; |
781e989c | 3028 | mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; |
e89d456f AW |
3029 | |
3030 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) | |
3031 | host->flags |= SDHCI_AUTO_CMD12; | |
5fe23c7f | 3032 | |
8edf6371 | 3033 | /* Auto-CMD23 stuff only works in ADMA or PIO. */ |
4f3d3e9b | 3034 | if ((host->version >= SDHCI_SPEC_300) && |
8edf6371 | 3035 | ((host->flags & SDHCI_USE_ADMA) || |
3bfa6f03 SB |
3036 | !(host->flags & SDHCI_USE_SDMA)) && |
3037 | !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { | |
8edf6371 AW |
3038 | host->flags |= SDHCI_AUTO_CMD23; |
3039 | DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); | |
3040 | } else { | |
3041 | DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); | |
3042 | } | |
3043 | ||
15ec4461 PR |
3044 | /* |
3045 | * A controller may support 8-bit width, but the board itself | |
3046 | * might not have the pins brought out. Boards that support | |
3047 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in | |
3048 | * their platform code before calling sdhci_add_host(), and we | |
3049 | * won't assume 8-bit width for hosts without that CAP. | |
3050 | */ | |
5fe23c7f | 3051 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
15ec4461 | 3052 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
d129bceb | 3053 | |
63ef5d8c JH |
3054 | if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) |
3055 | mmc->caps &= ~MMC_CAP_CMD23; | |
3056 | ||
f2119df6 | 3057 | if (caps[0] & SDHCI_CAN_DO_HISPD) |
a29e7e18 | 3058 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
cd9277c0 | 3059 | |
176d1ed4 | 3060 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
c31d22eb II |
3061 | !(mmc->caps & MMC_CAP_NONREMOVABLE) && |
3062 | IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc))) | |
68d1fb7e AV |
3063 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
3064 | ||
3a48edc4 TK |
3065 | /* If there are external regulators, get them */ |
3066 | if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER) | |
3067 | return -EPROBE_DEFER; | |
3068 | ||
6231f3de | 3069 | /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ |
3a48edc4 TK |
3070 | if (!IS_ERR(mmc->supply.vqmmc)) { |
3071 | ret = regulator_enable(mmc->supply.vqmmc); | |
3072 | if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, | |
3073 | 1950000)) | |
8363c374 KL |
3074 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | |
3075 | SDHCI_SUPPORT_SDR50 | | |
3076 | SDHCI_SUPPORT_DDR50); | |
a3361aba CB |
3077 | if (ret) { |
3078 | pr_warn("%s: Failed to enable vqmmc regulator: %d\n", | |
3079 | mmc_hostname(mmc), ret); | |
4bb74313 | 3080 | mmc->supply.vqmmc = ERR_PTR(-EINVAL); |
a3361aba | 3081 | } |
8363c374 | 3082 | } |
6231f3de | 3083 | |
6a66180a DD |
3084 | if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) |
3085 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
3086 | SDHCI_SUPPORT_DDR50); | |
3087 | ||
4188bba0 AC |
3088 | /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ |
3089 | if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
3090 | SDHCI_SUPPORT_DDR50)) | |
f2119df6 AN |
3091 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
3092 | ||
3093 | /* SDR104 supports also implies SDR50 support */ | |
156e14b1 | 3094 | if (caps[1] & SDHCI_SUPPORT_SDR104) { |
f2119df6 | 3095 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; |
156e14b1 GC |
3096 | /* SD3.0: SDR104 is supported so (for eMMC) the caps2 |
3097 | * field can be promoted to support HS200. | |
3098 | */ | |
549c0b18 | 3099 | if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) |
13868bf2 | 3100 | mmc->caps2 |= MMC_CAP2_HS200; |
156e14b1 | 3101 | } else if (caps[1] & SDHCI_SUPPORT_SDR50) |
f2119df6 AN |
3102 | mmc->caps |= MMC_CAP_UHS_SDR50; |
3103 | ||
e9fb05d5 AH |
3104 | if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && |
3105 | (caps[1] & SDHCI_SUPPORT_HS400)) | |
3106 | mmc->caps2 |= MMC_CAP2_HS400; | |
3107 | ||
549c0b18 AH |
3108 | if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && |
3109 | (IS_ERR(mmc->supply.vqmmc) || | |
3110 | !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, | |
3111 | 1300000))) | |
3112 | mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; | |
3113 | ||
9107ebbf MC |
3114 | if ((caps[1] & SDHCI_SUPPORT_DDR50) && |
3115 | !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) | |
f2119df6 AN |
3116 | mmc->caps |= MMC_CAP_UHS_DDR50; |
3117 | ||
069c9f14 | 3118 | /* Does the host need tuning for SDR50? */ |
b513ea25 AN |
3119 | if (caps[1] & SDHCI_USE_SDR50_TUNING) |
3120 | host->flags |= SDHCI_SDR50_NEEDS_TUNING; | |
3121 | ||
156e14b1 | 3122 | /* Does the host need tuning for SDR104 / HS200? */ |
069c9f14 | 3123 | if (mmc->caps2 & MMC_CAP2_HS200) |
156e14b1 | 3124 | host->flags |= SDHCI_SDR104_NEEDS_TUNING; |
069c9f14 | 3125 | |
d6d50a15 AN |
3126 | /* Driver Type(s) (A, C, D) supported by the host */ |
3127 | if (caps[1] & SDHCI_DRIVER_TYPE_A) | |
3128 | mmc->caps |= MMC_CAP_DRIVER_TYPE_A; | |
3129 | if (caps[1] & SDHCI_DRIVER_TYPE_C) | |
3130 | mmc->caps |= MMC_CAP_DRIVER_TYPE_C; | |
3131 | if (caps[1] & SDHCI_DRIVER_TYPE_D) | |
3132 | mmc->caps |= MMC_CAP_DRIVER_TYPE_D; | |
3133 | ||
cf2b5eea AN |
3134 | /* Initial value for re-tuning timer count */ |
3135 | host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> | |
3136 | SDHCI_RETUNING_TIMER_COUNT_SHIFT; | |
3137 | ||
3138 | /* | |
3139 | * In case Re-tuning Timer is not disabled, the actual value of | |
3140 | * re-tuning timer will be 2 ^ (n - 1). | |
3141 | */ | |
3142 | if (host->tuning_count) | |
3143 | host->tuning_count = 1 << (host->tuning_count - 1); | |
3144 | ||
3145 | /* Re-tuning mode supported by the Host Controller */ | |
3146 | host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> | |
3147 | SDHCI_RETUNING_MODE_SHIFT; | |
3148 | ||
8f230f45 | 3149 | ocr_avail = 0; |
bad37e1a | 3150 | |
f2119df6 AN |
3151 | /* |
3152 | * According to SD Host Controller spec v3.00, if the Host System | |
3153 | * can afford more than 150mA, Host Driver should set XPC to 1. Also | |
3154 | * the value is meaningful only if Voltage Support in the Capabilities | |
3155 | * register is set. The actual current value is 4 times the register | |
3156 | * value. | |
3157 | */ | |
3158 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); | |
3a48edc4 | 3159 | if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { |
ae906037 | 3160 | int curr = regulator_get_current_limit(mmc->supply.vmmc); |
bad37e1a PR |
3161 | if (curr > 0) { |
3162 | ||
3163 | /* convert to SDHCI_MAX_CURRENT format */ | |
3164 | curr = curr/1000; /* convert to mA */ | |
3165 | curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; | |
3166 | ||
3167 | curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); | |
3168 | max_current_caps = | |
3169 | (curr << SDHCI_MAX_CURRENT_330_SHIFT) | | |
3170 | (curr << SDHCI_MAX_CURRENT_300_SHIFT) | | |
3171 | (curr << SDHCI_MAX_CURRENT_180_SHIFT); | |
3172 | } | |
3173 | } | |
f2119df6 AN |
3174 | |
3175 | if (caps[0] & SDHCI_CAN_VDD_330) { | |
8f230f45 | 3176 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
f2119df6 | 3177 | |
55c4665e | 3178 | mmc->max_current_330 = ((max_current_caps & |
f2119df6 AN |
3179 | SDHCI_MAX_CURRENT_330_MASK) >> |
3180 | SDHCI_MAX_CURRENT_330_SHIFT) * | |
3181 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3182 | } |
3183 | if (caps[0] & SDHCI_CAN_VDD_300) { | |
8f230f45 | 3184 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
f2119df6 | 3185 | |
55c4665e | 3186 | mmc->max_current_300 = ((max_current_caps & |
f2119df6 AN |
3187 | SDHCI_MAX_CURRENT_300_MASK) >> |
3188 | SDHCI_MAX_CURRENT_300_SHIFT) * | |
3189 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3190 | } |
3191 | if (caps[0] & SDHCI_CAN_VDD_180) { | |
8f230f45 TI |
3192 | ocr_avail |= MMC_VDD_165_195; |
3193 | ||
55c4665e | 3194 | mmc->max_current_180 = ((max_current_caps & |
f2119df6 AN |
3195 | SDHCI_MAX_CURRENT_180_MASK) >> |
3196 | SDHCI_MAX_CURRENT_180_SHIFT) * | |
3197 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3198 | } |
3199 | ||
5fd26c7e UH |
3200 | /* If OCR set by host, use it instead. */ |
3201 | if (host->ocr_mask) | |
3202 | ocr_avail = host->ocr_mask; | |
3203 | ||
3204 | /* If OCR set by external regulators, give it highest prio. */ | |
3a48edc4 | 3205 | if (mmc->ocr_avail) |
52221610 | 3206 | ocr_avail = mmc->ocr_avail; |
3a48edc4 | 3207 | |
8f230f45 TI |
3208 | mmc->ocr_avail = ocr_avail; |
3209 | mmc->ocr_avail_sdio = ocr_avail; | |
3210 | if (host->ocr_avail_sdio) | |
3211 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; | |
3212 | mmc->ocr_avail_sd = ocr_avail; | |
3213 | if (host->ocr_avail_sd) | |
3214 | mmc->ocr_avail_sd &= host->ocr_avail_sd; | |
3215 | else /* normal SD controllers don't support 1.8V */ | |
3216 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; | |
3217 | mmc->ocr_avail_mmc = ocr_avail; | |
3218 | if (host->ocr_avail_mmc) | |
3219 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; | |
146ad66e PO |
3220 | |
3221 | if (mmc->ocr_avail == 0) { | |
2e4456f0 MV |
3222 | pr_err("%s: Hardware doesn't report any support voltages.\n", |
3223 | mmc_hostname(mmc)); | |
b8c86fc5 | 3224 | return -ENODEV; |
146ad66e PO |
3225 | } |
3226 | ||
d129bceb PO |
3227 | spin_lock_init(&host->lock); |
3228 | ||
3229 | /* | |
2134a922 PO |
3230 | * Maximum number of segments. Depends on if the hardware |
3231 | * can do scatter/gather or not. | |
d129bceb | 3232 | */ |
2134a922 | 3233 | if (host->flags & SDHCI_USE_ADMA) |
4fb213f8 | 3234 | mmc->max_segs = SDHCI_MAX_SEGS; |
a13abc7b | 3235 | else if (host->flags & SDHCI_USE_SDMA) |
a36274e0 | 3236 | mmc->max_segs = 1; |
2134a922 | 3237 | else /* PIO */ |
4fb213f8 | 3238 | mmc->max_segs = SDHCI_MAX_SEGS; |
d129bceb PO |
3239 | |
3240 | /* | |
ac00531d AH |
3241 | * Maximum number of sectors in one transfer. Limited by SDMA boundary |
3242 | * size (512KiB). Note some tuning modes impose a 4MiB limit, but this | |
3243 | * is less anyway. | |
d129bceb | 3244 | */ |
55db890a | 3245 | mmc->max_req_size = 524288; |
d129bceb PO |
3246 | |
3247 | /* | |
3248 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
3249 | * of bytes. When doing hardware scatter/gather, each entry cannot |
3250 | * be larger than 64 KiB though. | |
d129bceb | 3251 | */ |
30652aa3 OJ |
3252 | if (host->flags & SDHCI_USE_ADMA) { |
3253 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) | |
3254 | mmc->max_seg_size = 65535; | |
3255 | else | |
3256 | mmc->max_seg_size = 65536; | |
3257 | } else { | |
2134a922 | 3258 | mmc->max_seg_size = mmc->max_req_size; |
30652aa3 | 3259 | } |
d129bceb | 3260 | |
fe4a3c7a PO |
3261 | /* |
3262 | * Maximum block size. This varies from controller to controller and | |
3263 | * is specified in the capabilities register. | |
3264 | */ | |
0633f654 AV |
3265 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
3266 | mmc->max_blk_size = 2; | |
3267 | } else { | |
f2119df6 | 3268 | mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> |
0633f654 AV |
3269 | SDHCI_MAX_BLOCK_SHIFT; |
3270 | if (mmc->max_blk_size >= 3) { | |
6606110d JP |
3271 | pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", |
3272 | mmc_hostname(mmc)); | |
0633f654 AV |
3273 | mmc->max_blk_size = 0; |
3274 | } | |
3275 | } | |
3276 | ||
3277 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 3278 | |
55db890a PO |
3279 | /* |
3280 | * Maximum block count. | |
3281 | */ | |
1388eefd | 3282 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
55db890a | 3283 | |
d129bceb PO |
3284 | /* |
3285 | * Init tasklets. | |
3286 | */ | |
d129bceb PO |
3287 | tasklet_init(&host->finish_tasklet, |
3288 | sdhci_tasklet_finish, (unsigned long)host); | |
3289 | ||
e4cad1b5 | 3290 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 3291 | |
250fb7b4 | 3292 | init_waitqueue_head(&host->buf_ready_int); |
b513ea25 | 3293 | |
2af502ca SG |
3294 | sdhci_init(host, 0); |
3295 | ||
781e989c RK |
3296 | ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, |
3297 | IRQF_SHARED, mmc_hostname(mmc), host); | |
0fc81ee3 MB |
3298 | if (ret) { |
3299 | pr_err("%s: Failed to request IRQ %d: %d\n", | |
3300 | mmc_hostname(mmc), host->irq, ret); | |
8ef1a143 | 3301 | goto untasklet; |
0fc81ee3 | 3302 | } |
d129bceb | 3303 | |
d129bceb PO |
3304 | #ifdef CONFIG_MMC_DEBUG |
3305 | sdhci_dumpregs(host); | |
3306 | #endif | |
3307 | ||
f9134319 | 3308 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
3309 | snprintf(host->led_name, sizeof(host->led_name), |
3310 | "%s::", mmc_hostname(mmc)); | |
3311 | host->led.name = host->led_name; | |
2f730fec PO |
3312 | host->led.brightness = LED_OFF; |
3313 | host->led.default_trigger = mmc_hostname(mmc); | |
3314 | host->led.brightness_set = sdhci_led_control; | |
3315 | ||
b8c86fc5 | 3316 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
0fc81ee3 MB |
3317 | if (ret) { |
3318 | pr_err("%s: Failed to register LED device: %d\n", | |
3319 | mmc_hostname(mmc), ret); | |
2f730fec | 3320 | goto reset; |
0fc81ee3 | 3321 | } |
2f730fec PO |
3322 | #endif |
3323 | ||
5f25a66f PO |
3324 | mmiowb(); |
3325 | ||
d129bceb PO |
3326 | mmc_add_host(mmc); |
3327 | ||
a3c76eb9 | 3328 | pr_info("%s: SDHCI controller on %s [%s] using %s\n", |
d1b26863 | 3329 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
e57a5f61 AH |
3330 | (host->flags & SDHCI_USE_ADMA) ? |
3331 | (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : | |
a13abc7b | 3332 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); |
d129bceb | 3333 | |
7260cf5e AV |
3334 | sdhci_enable_card_detection(host); |
3335 | ||
d129bceb PO |
3336 | return 0; |
3337 | ||
f9134319 | 3338 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec | 3339 | reset: |
03231f9b | 3340 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
b537f94c RK |
3341 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3342 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
2f730fec PO |
3343 | free_irq(host->irq, host); |
3344 | #endif | |
8ef1a143 | 3345 | untasklet: |
d129bceb | 3346 | tasklet_kill(&host->finish_tasklet); |
d129bceb PO |
3347 | |
3348 | return ret; | |
3349 | } | |
3350 | ||
b8c86fc5 | 3351 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 3352 | |
1e72859e | 3353 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 3354 | { |
3a48edc4 | 3355 | struct mmc_host *mmc = host->mmc; |
1e72859e PO |
3356 | unsigned long flags; |
3357 | ||
3358 | if (dead) { | |
3359 | spin_lock_irqsave(&host->lock, flags); | |
3360 | ||
3361 | host->flags |= SDHCI_DEVICE_DEAD; | |
3362 | ||
3363 | if (host->mrq) { | |
a3c76eb9 | 3364 | pr_err("%s: Controller removed during " |
4e743f1f | 3365 | " transfer!\n", mmc_hostname(mmc)); |
1e72859e PO |
3366 | |
3367 | host->mrq->cmd->error = -ENOMEDIUM; | |
3368 | tasklet_schedule(&host->finish_tasklet); | |
3369 | } | |
3370 | ||
3371 | spin_unlock_irqrestore(&host->lock, flags); | |
3372 | } | |
3373 | ||
7260cf5e AV |
3374 | sdhci_disable_card_detection(host); |
3375 | ||
4e743f1f | 3376 | mmc_remove_host(mmc); |
d129bceb | 3377 | |
f9134319 | 3378 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
3379 | led_classdev_unregister(&host->led); |
3380 | #endif | |
3381 | ||
1e72859e | 3382 | if (!dead) |
03231f9b | 3383 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d129bceb | 3384 | |
b537f94c RK |
3385 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3386 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
d129bceb PO |
3387 | free_irq(host->irq, host); |
3388 | ||
3389 | del_timer_sync(&host->timer); | |
3390 | ||
d129bceb | 3391 | tasklet_kill(&host->finish_tasklet); |
2134a922 | 3392 | |
3a48edc4 TK |
3393 | if (!IS_ERR(mmc->supply.vqmmc)) |
3394 | regulator_disable(mmc->supply.vqmmc); | |
6231f3de | 3395 | |
edd63fcc | 3396 | if (host->align_buffer) |
e66e61cb RK |
3397 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
3398 | host->adma_table_sz, host->align_buffer, | |
3399 | host->align_addr); | |
2134a922 | 3400 | |
4efaa6fb | 3401 | host->adma_table = NULL; |
2134a922 | 3402 | host->align_buffer = NULL; |
d129bceb PO |
3403 | } |
3404 | ||
b8c86fc5 | 3405 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 3406 | |
b8c86fc5 | 3407 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 3408 | { |
b8c86fc5 | 3409 | mmc_free_host(host->mmc); |
d129bceb PO |
3410 | } |
3411 | ||
b8c86fc5 | 3412 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
3413 | |
3414 | /*****************************************************************************\ | |
3415 | * * | |
3416 | * Driver init/exit * | |
3417 | * * | |
3418 | \*****************************************************************************/ | |
3419 | ||
3420 | static int __init sdhci_drv_init(void) | |
3421 | { | |
a3c76eb9 | 3422 | pr_info(DRIVER_NAME |
52fbf9c9 | 3423 | ": Secure Digital Host Controller Interface driver\n"); |
a3c76eb9 | 3424 | pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
d129bceb | 3425 | |
b8c86fc5 | 3426 | return 0; |
d129bceb PO |
3427 | } |
3428 | ||
3429 | static void __exit sdhci_drv_exit(void) | |
3430 | { | |
d129bceb PO |
3431 | } |
3432 | ||
3433 | module_init(sdhci_drv_init); | |
3434 | module_exit(sdhci_drv_exit); | |
3435 | ||
df673b22 | 3436 | module_param(debug_quirks, uint, 0444); |
66fd8ad5 | 3437 | module_param(debug_quirks2, uint, 0444); |
67435274 | 3438 | |
32710e8f | 3439 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 3440 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 3441 | MODULE_LICENSE("GPL"); |
67435274 | 3442 | |
df673b22 | 3443 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |
66fd8ad5 | 3444 | MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); |