Commit | Line | Data |
---|---|---|
d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
88b47679 | 19 | #include <linux/module.h> |
d129bceb | 20 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
11763609 | 22 | #include <linux/scatterlist.h> |
9bea3c85 | 23 | #include <linux/regulator/consumer.h> |
66fd8ad5 | 24 | #include <linux/pm_runtime.h> |
d129bceb | 25 | |
2f730fec PO |
26 | #include <linux/leds.h> |
27 | ||
22113efd | 28 | #include <linux/mmc/mmc.h> |
d129bceb | 29 | #include <linux/mmc/host.h> |
473b095a | 30 | #include <linux/mmc/card.h> |
bec9d4e5 | 31 | #include <linux/mmc/slot-gpio.h> |
d129bceb | 32 | |
d129bceb PO |
33 | #include "sdhci.h" |
34 | ||
35 | #define DRIVER_NAME "sdhci" | |
d129bceb | 36 | |
d129bceb | 37 | #define DBG(f, x...) \ |
c6563178 | 38 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 39 | |
f9134319 PO |
40 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
41 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
42 | #define SDHCI_USE_LEDS_CLASS | |
43 | #endif | |
44 | ||
b513ea25 AN |
45 | #define MAX_TUNING_LOOP 40 |
46 | ||
d1e49f77 RK |
47 | #define ADMA_SIZE ((128 * 2 + 1) * 4) |
48 | ||
df673b22 | 49 | static unsigned int debug_quirks = 0; |
66fd8ad5 | 50 | static unsigned int debug_quirks2; |
67435274 | 51 | |
d129bceb PO |
52 | static void sdhci_finish_data(struct sdhci_host *); |
53 | ||
d129bceb | 54 | static void sdhci_finish_command(struct sdhci_host *); |
069c9f14 | 55 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); |
cf2b5eea | 56 | static void sdhci_tuning_timer(unsigned long data); |
52983382 | 57 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); |
d129bceb | 58 | |
66fd8ad5 AH |
59 | #ifdef CONFIG_PM_RUNTIME |
60 | static int sdhci_runtime_pm_get(struct sdhci_host *host); | |
61 | static int sdhci_runtime_pm_put(struct sdhci_host *host); | |
f0710a55 AH |
62 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); |
63 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); | |
66fd8ad5 AH |
64 | #else |
65 | static inline int sdhci_runtime_pm_get(struct sdhci_host *host) | |
66 | { | |
67 | return 0; | |
68 | } | |
69 | static inline int sdhci_runtime_pm_put(struct sdhci_host *host) | |
70 | { | |
71 | return 0; | |
72 | } | |
f0710a55 AH |
73 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
74 | { | |
75 | } | |
76 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) | |
77 | { | |
78 | } | |
66fd8ad5 AH |
79 | #endif |
80 | ||
d129bceb PO |
81 | static void sdhci_dumpregs(struct sdhci_host *host) |
82 | { | |
a3c76eb9 | 83 | pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
412ab659 | 84 | mmc_hostname(host->mmc)); |
d129bceb | 85 | |
a3c76eb9 | 86 | pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", |
4e4141a5 AV |
87 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
88 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
a3c76eb9 | 89 | pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
90 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
91 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
a3c76eb9 | 92 | pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
93 | sdhci_readl(host, SDHCI_ARGUMENT), |
94 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
a3c76eb9 | 95 | pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
96 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
97 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
a3c76eb9 | 98 | pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
99 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
100 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
a3c76eb9 | 101 | pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
102 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
103 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
a3c76eb9 | 104 | pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
105 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
106 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
a3c76eb9 | 107 | pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
108 | sdhci_readl(host, SDHCI_INT_ENABLE), |
109 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
a3c76eb9 | 110 | pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
111 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
112 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
a3c76eb9 | 113 | pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
4e4141a5 | 114 | sdhci_readl(host, SDHCI_CAPABILITIES), |
e8120ad1 | 115 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
a3c76eb9 | 116 | pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", |
e8120ad1 | 117 | sdhci_readw(host, SDHCI_COMMAND), |
4e4141a5 | 118 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
a3c76eb9 | 119 | pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", |
f2119df6 | 120 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); |
d129bceb | 121 | |
be3f4ae0 | 122 | if (host->flags & SDHCI_USE_ADMA) |
a3c76eb9 | 123 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", |
be3f4ae0 BD |
124 | readl(host->ioaddr + SDHCI_ADMA_ERROR), |
125 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
126 | ||
a3c76eb9 | 127 | pr_debug(DRIVER_NAME ": ===========================================\n"); |
d129bceb PO |
128 | } |
129 | ||
130 | /*****************************************************************************\ | |
131 | * * | |
132 | * Low level functions * | |
133 | * * | |
134 | \*****************************************************************************/ | |
135 | ||
7260cf5e AV |
136 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) |
137 | { | |
5b4f1f6c | 138 | u32 present; |
7260cf5e | 139 | |
c79396c1 | 140 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
87b87a3f | 141 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
66fd8ad5 AH |
142 | return; |
143 | ||
5b4f1f6c RK |
144 | if (enable) { |
145 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
146 | SDHCI_CARD_PRESENT; | |
d25928d1 | 147 | |
5b4f1f6c RK |
148 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
149 | SDHCI_INT_CARD_INSERT; | |
150 | } else { | |
151 | host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); | |
152 | } | |
b537f94c RK |
153 | |
154 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
155 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
7260cf5e AV |
156 | } |
157 | ||
158 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
159 | { | |
160 | sdhci_set_card_detection(host, true); | |
161 | } | |
162 | ||
163 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
164 | { | |
165 | sdhci_set_card_detection(host, false); | |
166 | } | |
167 | ||
03231f9b | 168 | void sdhci_reset(struct sdhci_host *host, u8 mask) |
d129bceb | 169 | { |
e16514d8 | 170 | unsigned long timeout; |
393c1a34 | 171 | |
4e4141a5 | 172 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 173 | |
f0710a55 | 174 | if (mask & SDHCI_RESET_ALL) { |
d129bceb | 175 | host->clock = 0; |
f0710a55 AH |
176 | /* Reset-all turns off SD Bus Power */ |
177 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) | |
178 | sdhci_runtime_pm_bus_off(host); | |
179 | } | |
d129bceb | 180 | |
e16514d8 PO |
181 | /* Wait max 100 ms */ |
182 | timeout = 100; | |
183 | ||
184 | /* hw clears the bit when it's done */ | |
4e4141a5 | 185 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 186 | if (timeout == 0) { |
a3c76eb9 | 187 | pr_err("%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
188 | mmc_hostname(host->mmc), (int)mask); |
189 | sdhci_dumpregs(host); | |
190 | return; | |
191 | } | |
192 | timeout--; | |
193 | mdelay(1); | |
d129bceb | 194 | } |
03231f9b RK |
195 | } |
196 | EXPORT_SYMBOL_GPL(sdhci_reset); | |
197 | ||
198 | static void sdhci_do_reset(struct sdhci_host *host, u8 mask) | |
199 | { | |
200 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { | |
201 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
202 | SDHCI_CARD_PRESENT)) | |
203 | return; | |
204 | } | |
063a9dbb | 205 | |
03231f9b | 206 | host->ops->reset(host, mask); |
393c1a34 | 207 | |
da91a8f9 RK |
208 | if (mask & SDHCI_RESET_ALL) { |
209 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
210 | if (host->ops->enable_dma) | |
211 | host->ops->enable_dma(host); | |
212 | } | |
213 | ||
214 | /* Resetting the controller clears many */ | |
215 | host->preset_enabled = false; | |
3abc1e80 | 216 | } |
d129bceb PO |
217 | } |
218 | ||
2f4cbb3d NP |
219 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
220 | ||
221 | static void sdhci_init(struct sdhci_host *host, int soft) | |
d129bceb | 222 | { |
2f4cbb3d | 223 | if (soft) |
03231f9b | 224 | sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); |
2f4cbb3d | 225 | else |
03231f9b | 226 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d129bceb | 227 | |
b537f94c RK |
228 | host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
229 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | | |
230 | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | | |
231 | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | | |
232 | SDHCI_INT_RESPONSE; | |
233 | ||
234 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
235 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
2f4cbb3d NP |
236 | |
237 | if (soft) { | |
238 | /* force clock reconfiguration */ | |
239 | host->clock = 0; | |
240 | sdhci_set_ios(host->mmc, &host->mmc->ios); | |
241 | } | |
7260cf5e | 242 | } |
d129bceb | 243 | |
7260cf5e AV |
244 | static void sdhci_reinit(struct sdhci_host *host) |
245 | { | |
2f4cbb3d | 246 | sdhci_init(host, 0); |
b67c6b41 AL |
247 | /* |
248 | * Retuning stuffs are affected by different cards inserted and only | |
249 | * applicable to UHS-I cards. So reset these fields to their initial | |
250 | * value when card is removed. | |
251 | */ | |
973905fe AL |
252 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
253 | host->flags &= ~SDHCI_USING_RETUNING_TIMER; | |
254 | ||
b67c6b41 AL |
255 | del_timer_sync(&host->tuning_timer); |
256 | host->flags &= ~SDHCI_NEEDS_RETUNING; | |
257 | host->mmc->max_blk_count = | |
258 | (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; | |
259 | } | |
7260cf5e | 260 | sdhci_enable_card_detection(host); |
d129bceb PO |
261 | } |
262 | ||
263 | static void sdhci_activate_led(struct sdhci_host *host) | |
264 | { | |
265 | u8 ctrl; | |
266 | ||
4e4141a5 | 267 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 268 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 269 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
270 | } |
271 | ||
272 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
273 | { | |
274 | u8 ctrl; | |
275 | ||
4e4141a5 | 276 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 277 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 278 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
279 | } |
280 | ||
f9134319 | 281 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
282 | static void sdhci_led_control(struct led_classdev *led, |
283 | enum led_brightness brightness) | |
284 | { | |
285 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
286 | unsigned long flags; | |
287 | ||
288 | spin_lock_irqsave(&host->lock, flags); | |
289 | ||
66fd8ad5 AH |
290 | if (host->runtime_suspended) |
291 | goto out; | |
292 | ||
2f730fec PO |
293 | if (brightness == LED_OFF) |
294 | sdhci_deactivate_led(host); | |
295 | else | |
296 | sdhci_activate_led(host); | |
66fd8ad5 | 297 | out: |
2f730fec PO |
298 | spin_unlock_irqrestore(&host->lock, flags); |
299 | } | |
300 | #endif | |
301 | ||
d129bceb PO |
302 | /*****************************************************************************\ |
303 | * * | |
304 | * Core functions * | |
305 | * * | |
306 | \*****************************************************************************/ | |
307 | ||
a406f5a3 | 308 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 309 | { |
7659150c PO |
310 | unsigned long flags; |
311 | size_t blksize, len, chunk; | |
7244b85b | 312 | u32 uninitialized_var(scratch); |
7659150c | 313 | u8 *buf; |
d129bceb | 314 | |
a406f5a3 | 315 | DBG("PIO reading\n"); |
d129bceb | 316 | |
a406f5a3 | 317 | blksize = host->data->blksz; |
7659150c | 318 | chunk = 0; |
d129bceb | 319 | |
7659150c | 320 | local_irq_save(flags); |
d129bceb | 321 | |
a406f5a3 | 322 | while (blksize) { |
7659150c PO |
323 | if (!sg_miter_next(&host->sg_miter)) |
324 | BUG(); | |
d129bceb | 325 | |
7659150c | 326 | len = min(host->sg_miter.length, blksize); |
d129bceb | 327 | |
7659150c PO |
328 | blksize -= len; |
329 | host->sg_miter.consumed = len; | |
14d836e7 | 330 | |
7659150c | 331 | buf = host->sg_miter.addr; |
d129bceb | 332 | |
7659150c PO |
333 | while (len) { |
334 | if (chunk == 0) { | |
4e4141a5 | 335 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 336 | chunk = 4; |
a406f5a3 | 337 | } |
7659150c PO |
338 | |
339 | *buf = scratch & 0xFF; | |
340 | ||
341 | buf++; | |
342 | scratch >>= 8; | |
343 | chunk--; | |
344 | len--; | |
d129bceb | 345 | } |
a406f5a3 | 346 | } |
7659150c PO |
347 | |
348 | sg_miter_stop(&host->sg_miter); | |
349 | ||
350 | local_irq_restore(flags); | |
a406f5a3 | 351 | } |
d129bceb | 352 | |
a406f5a3 PO |
353 | static void sdhci_write_block_pio(struct sdhci_host *host) |
354 | { | |
7659150c PO |
355 | unsigned long flags; |
356 | size_t blksize, len, chunk; | |
357 | u32 scratch; | |
358 | u8 *buf; | |
d129bceb | 359 | |
a406f5a3 PO |
360 | DBG("PIO writing\n"); |
361 | ||
362 | blksize = host->data->blksz; | |
7659150c PO |
363 | chunk = 0; |
364 | scratch = 0; | |
d129bceb | 365 | |
7659150c | 366 | local_irq_save(flags); |
d129bceb | 367 | |
a406f5a3 | 368 | while (blksize) { |
7659150c PO |
369 | if (!sg_miter_next(&host->sg_miter)) |
370 | BUG(); | |
a406f5a3 | 371 | |
7659150c PO |
372 | len = min(host->sg_miter.length, blksize); |
373 | ||
374 | blksize -= len; | |
375 | host->sg_miter.consumed = len; | |
376 | ||
377 | buf = host->sg_miter.addr; | |
d129bceb | 378 | |
7659150c PO |
379 | while (len) { |
380 | scratch |= (u32)*buf << (chunk * 8); | |
381 | ||
382 | buf++; | |
383 | chunk++; | |
384 | len--; | |
385 | ||
386 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 387 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
388 | chunk = 0; |
389 | scratch = 0; | |
d129bceb | 390 | } |
d129bceb PO |
391 | } |
392 | } | |
7659150c PO |
393 | |
394 | sg_miter_stop(&host->sg_miter); | |
395 | ||
396 | local_irq_restore(flags); | |
a406f5a3 PO |
397 | } |
398 | ||
399 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
400 | { | |
401 | u32 mask; | |
402 | ||
403 | BUG_ON(!host->data); | |
404 | ||
7659150c | 405 | if (host->blocks == 0) |
a406f5a3 PO |
406 | return; |
407 | ||
408 | if (host->data->flags & MMC_DATA_READ) | |
409 | mask = SDHCI_DATA_AVAILABLE; | |
410 | else | |
411 | mask = SDHCI_SPACE_AVAILABLE; | |
412 | ||
4a3cba32 PO |
413 | /* |
414 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
415 | * for transfers < 4 bytes. As long as it is just one block, | |
416 | * we can ignore the bits. | |
417 | */ | |
418 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
419 | (host->data->blocks == 1)) | |
420 | mask = ~0; | |
421 | ||
4e4141a5 | 422 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
423 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
424 | udelay(100); | |
425 | ||
a406f5a3 PO |
426 | if (host->data->flags & MMC_DATA_READ) |
427 | sdhci_read_block_pio(host); | |
428 | else | |
429 | sdhci_write_block_pio(host); | |
d129bceb | 430 | |
7659150c PO |
431 | host->blocks--; |
432 | if (host->blocks == 0) | |
a406f5a3 | 433 | break; |
a406f5a3 | 434 | } |
d129bceb | 435 | |
a406f5a3 | 436 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
437 | } |
438 | ||
2134a922 PO |
439 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
440 | { | |
441 | local_irq_save(*flags); | |
482fce99 | 442 | return kmap_atomic(sg_page(sg)) + sg->offset; |
2134a922 PO |
443 | } |
444 | ||
445 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
446 | { | |
482fce99 | 447 | kunmap_atomic(buffer); |
2134a922 PO |
448 | local_irq_restore(*flags); |
449 | } | |
450 | ||
118cd17d BD |
451 | static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) |
452 | { | |
9e506f35 BD |
453 | __le32 *dataddr = (__le32 __force *)(desc + 4); |
454 | __le16 *cmdlen = (__le16 __force *)desc; | |
118cd17d | 455 | |
9e506f35 BD |
456 | /* SDHCI specification says ADMA descriptors should be 4 byte |
457 | * aligned, so using 16 or 32bit operations should be safe. */ | |
118cd17d | 458 | |
9e506f35 BD |
459 | cmdlen[0] = cpu_to_le16(cmd); |
460 | cmdlen[1] = cpu_to_le16(len); | |
461 | ||
462 | dataddr[0] = cpu_to_le32(addr); | |
118cd17d BD |
463 | } |
464 | ||
8f1934ce | 465 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
2134a922 PO |
466 | struct mmc_data *data) |
467 | { | |
468 | int direction; | |
469 | ||
470 | u8 *desc; | |
471 | u8 *align; | |
472 | dma_addr_t addr; | |
473 | dma_addr_t align_addr; | |
474 | int len, offset; | |
475 | ||
476 | struct scatterlist *sg; | |
477 | int i; | |
478 | char *buffer; | |
479 | unsigned long flags; | |
480 | ||
481 | /* | |
482 | * The spec does not specify endianness of descriptor table. | |
483 | * We currently guess that it is LE. | |
484 | */ | |
485 | ||
486 | if (data->flags & MMC_DATA_READ) | |
487 | direction = DMA_FROM_DEVICE; | |
488 | else | |
489 | direction = DMA_TO_DEVICE; | |
490 | ||
2134a922 PO |
491 | host->align_addr = dma_map_single(mmc_dev(host->mmc), |
492 | host->align_buffer, 128 * 4, direction); | |
8d8bb39b | 493 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
8f1934ce | 494 | goto fail; |
2134a922 PO |
495 | BUG_ON(host->align_addr & 0x3); |
496 | ||
497 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), | |
498 | data->sg, data->sg_len, direction); | |
8f1934ce PO |
499 | if (host->sg_count == 0) |
500 | goto unmap_align; | |
2134a922 PO |
501 | |
502 | desc = host->adma_desc; | |
503 | align = host->align_buffer; | |
504 | ||
505 | align_addr = host->align_addr; | |
506 | ||
507 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
508 | addr = sg_dma_address(sg); | |
509 | len = sg_dma_len(sg); | |
510 | ||
511 | /* | |
512 | * The SDHCI specification states that ADMA | |
513 | * addresses must be 32-bit aligned. If they | |
514 | * aren't, then we use a bounce buffer for | |
515 | * the (up to three) bytes that screw up the | |
516 | * alignment. | |
517 | */ | |
518 | offset = (4 - (addr & 0x3)) & 0x3; | |
519 | if (offset) { | |
520 | if (data->flags & MMC_DATA_WRITE) { | |
521 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 522 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
523 | memcpy(align, buffer, offset); |
524 | sdhci_kunmap_atomic(buffer, &flags); | |
525 | } | |
526 | ||
118cd17d BD |
527 | /* tran, valid */ |
528 | sdhci_set_adma_desc(desc, align_addr, offset, 0x21); | |
2134a922 PO |
529 | |
530 | BUG_ON(offset > 65536); | |
531 | ||
2134a922 PO |
532 | align += 4; |
533 | align_addr += 4; | |
534 | ||
535 | desc += 8; | |
536 | ||
537 | addr += offset; | |
538 | len -= offset; | |
539 | } | |
540 | ||
2134a922 PO |
541 | BUG_ON(len > 65536); |
542 | ||
118cd17d BD |
543 | /* tran, valid */ |
544 | sdhci_set_adma_desc(desc, addr, len, 0x21); | |
2134a922 PO |
545 | desc += 8; |
546 | ||
547 | /* | |
548 | * If this triggers then we have a calculation bug | |
549 | * somewhere. :/ | |
550 | */ | |
d1e49f77 | 551 | WARN_ON((desc - host->adma_desc) > ADMA_SIZE); |
2134a922 PO |
552 | } |
553 | ||
70764a90 TA |
554 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
555 | /* | |
556 | * Mark the last descriptor as the terminating descriptor | |
557 | */ | |
558 | if (desc != host->adma_desc) { | |
559 | desc -= 8; | |
560 | desc[0] |= 0x2; /* end */ | |
561 | } | |
562 | } else { | |
563 | /* | |
564 | * Add a terminating entry. | |
565 | */ | |
2134a922 | 566 | |
70764a90 TA |
567 | /* nop, end, valid */ |
568 | sdhci_set_adma_desc(desc, 0, 0, 0x3); | |
569 | } | |
2134a922 PO |
570 | |
571 | /* | |
572 | * Resync align buffer as we might have changed it. | |
573 | */ | |
574 | if (data->flags & MMC_DATA_WRITE) { | |
575 | dma_sync_single_for_device(mmc_dev(host->mmc), | |
576 | host->align_addr, 128 * 4, direction); | |
577 | } | |
578 | ||
8f1934ce PO |
579 | return 0; |
580 | ||
8f1934ce PO |
581 | unmap_align: |
582 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
583 | 128 * 4, direction); | |
584 | fail: | |
585 | return -EINVAL; | |
2134a922 PO |
586 | } |
587 | ||
588 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
589 | struct mmc_data *data) | |
590 | { | |
591 | int direction; | |
592 | ||
593 | struct scatterlist *sg; | |
594 | int i, size; | |
595 | u8 *align; | |
596 | char *buffer; | |
597 | unsigned long flags; | |
de0b65a7 | 598 | bool has_unaligned; |
2134a922 PO |
599 | |
600 | if (data->flags & MMC_DATA_READ) | |
601 | direction = DMA_FROM_DEVICE; | |
602 | else | |
603 | direction = DMA_TO_DEVICE; | |
604 | ||
2134a922 PO |
605 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, |
606 | 128 * 4, direction); | |
607 | ||
de0b65a7 RK |
608 | /* Do a quick scan of the SG list for any unaligned mappings */ |
609 | has_unaligned = false; | |
610 | for_each_sg(data->sg, sg, host->sg_count, i) | |
611 | if (sg_dma_address(sg) & 3) { | |
612 | has_unaligned = true; | |
613 | break; | |
614 | } | |
615 | ||
616 | if (has_unaligned && data->flags & MMC_DATA_READ) { | |
2134a922 PO |
617 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, |
618 | data->sg_len, direction); | |
619 | ||
620 | align = host->align_buffer; | |
621 | ||
622 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
623 | if (sg_dma_address(sg) & 0x3) { | |
624 | size = 4 - (sg_dma_address(sg) & 0x3); | |
625 | ||
626 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 627 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
628 | memcpy(buffer, align, size); |
629 | sdhci_kunmap_atomic(buffer, &flags); | |
630 | ||
631 | align += 4; | |
632 | } | |
633 | } | |
634 | } | |
635 | ||
636 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
637 | data->sg_len, direction); | |
638 | } | |
639 | ||
a3c7778f | 640 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb | 641 | { |
1c8cde92 | 642 | u8 count; |
a3c7778f | 643 | struct mmc_data *data = cmd->data; |
1c8cde92 | 644 | unsigned target_timeout, current_timeout; |
d129bceb | 645 | |
ee53ab5d PO |
646 | /* |
647 | * If the host controller provides us with an incorrect timeout | |
648 | * value, just skip the check and use 0xE. The hardware may take | |
649 | * longer to time out, but that's much better than having a too-short | |
650 | * timeout value. | |
651 | */ | |
11a2f1b7 | 652 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
ee53ab5d | 653 | return 0xE; |
e538fbe8 | 654 | |
a3c7778f | 655 | /* Unspecified timeout, assume max */ |
1d4d7744 | 656 | if (!data && !cmd->busy_timeout) |
a3c7778f | 657 | return 0xE; |
d129bceb | 658 | |
a3c7778f AW |
659 | /* timeout in us */ |
660 | if (!data) | |
1d4d7744 | 661 | target_timeout = cmd->busy_timeout * 1000; |
78a2ca27 AS |
662 | else { |
663 | target_timeout = data->timeout_ns / 1000; | |
664 | if (host->clock) | |
665 | target_timeout += data->timeout_clks / host->clock; | |
666 | } | |
81b39802 | 667 | |
1c8cde92 PO |
668 | /* |
669 | * Figure out needed cycles. | |
670 | * We do this in steps in order to fit inside a 32 bit int. | |
671 | * The first step is the minimum timeout, which will have a | |
672 | * minimum resolution of 6 bits: | |
673 | * (1) 2^13*1000 > 2^22, | |
674 | * (2) host->timeout_clk < 2^16 | |
675 | * => | |
676 | * (1) / (2) > 2^6 | |
677 | */ | |
678 | count = 0; | |
679 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
680 | while (current_timeout < target_timeout) { | |
681 | count++; | |
682 | current_timeout <<= 1; | |
683 | if (count >= 0xF) | |
684 | break; | |
685 | } | |
686 | ||
687 | if (count >= 0xF) { | |
09eeff52 CB |
688 | DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", |
689 | mmc_hostname(host->mmc), count, cmd->opcode); | |
1c8cde92 PO |
690 | count = 0xE; |
691 | } | |
692 | ||
ee53ab5d PO |
693 | return count; |
694 | } | |
695 | ||
6aa943ab AV |
696 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
697 | { | |
698 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
699 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
700 | ||
701 | if (host->flags & SDHCI_REQ_USE_DMA) | |
b537f94c | 702 | host->ier = (host->ier & ~pio_irqs) | dma_irqs; |
6aa943ab | 703 | else |
b537f94c RK |
704 | host->ier = (host->ier & ~dma_irqs) | pio_irqs; |
705 | ||
706 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
707 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
6aa943ab AV |
708 | } |
709 | ||
a3c7778f | 710 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) |
ee53ab5d PO |
711 | { |
712 | u8 count; | |
2134a922 | 713 | u8 ctrl; |
a3c7778f | 714 | struct mmc_data *data = cmd->data; |
8f1934ce | 715 | int ret; |
ee53ab5d PO |
716 | |
717 | WARN_ON(host->data); | |
718 | ||
a3c7778f AW |
719 | if (data || (cmd->flags & MMC_RSP_BUSY)) { |
720 | count = sdhci_calc_timeout(host, cmd); | |
721 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); | |
722 | } | |
723 | ||
724 | if (!data) | |
ee53ab5d PO |
725 | return; |
726 | ||
727 | /* Sanity checks */ | |
728 | BUG_ON(data->blksz * data->blocks > 524288); | |
729 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
730 | BUG_ON(data->blocks > 65535); | |
731 | ||
732 | host->data = data; | |
733 | host->data_early = 0; | |
f6a03cbf | 734 | host->data->bytes_xfered = 0; |
ee53ab5d | 735 | |
a13abc7b | 736 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) |
c9fddbc4 PO |
737 | host->flags |= SDHCI_REQ_USE_DMA; |
738 | ||
2134a922 PO |
739 | /* |
740 | * FIXME: This doesn't account for merging when mapping the | |
741 | * scatterlist. | |
742 | */ | |
743 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
744 | int broken, i; | |
745 | struct scatterlist *sg; | |
746 | ||
747 | broken = 0; | |
748 | if (host->flags & SDHCI_USE_ADMA) { | |
749 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
750 | broken = 1; | |
751 | } else { | |
752 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
753 | broken = 1; | |
754 | } | |
755 | ||
756 | if (unlikely(broken)) { | |
757 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
758 | if (sg->length & 0x3) { | |
759 | DBG("Reverting to PIO because of " | |
760 | "transfer size (%d)\n", | |
761 | sg->length); | |
762 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
763 | break; | |
764 | } | |
765 | } | |
766 | } | |
c9fddbc4 PO |
767 | } |
768 | ||
769 | /* | |
770 | * The assumption here being that alignment is the same after | |
771 | * translation to device address space. | |
772 | */ | |
2134a922 PO |
773 | if (host->flags & SDHCI_REQ_USE_DMA) { |
774 | int broken, i; | |
775 | struct scatterlist *sg; | |
776 | ||
777 | broken = 0; | |
778 | if (host->flags & SDHCI_USE_ADMA) { | |
779 | /* | |
780 | * As we use 3 byte chunks to work around | |
781 | * alignment problems, we need to check this | |
782 | * quirk. | |
783 | */ | |
784 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
785 | broken = 1; | |
786 | } else { | |
787 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) | |
788 | broken = 1; | |
789 | } | |
790 | ||
791 | if (unlikely(broken)) { | |
792 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
793 | if (sg->offset & 0x3) { | |
794 | DBG("Reverting to PIO because of " | |
795 | "bad alignment\n"); | |
796 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
797 | break; | |
798 | } | |
799 | } | |
800 | } | |
801 | } | |
802 | ||
8f1934ce PO |
803 | if (host->flags & SDHCI_REQ_USE_DMA) { |
804 | if (host->flags & SDHCI_USE_ADMA) { | |
805 | ret = sdhci_adma_table_pre(host, data); | |
806 | if (ret) { | |
807 | /* | |
808 | * This only happens when someone fed | |
809 | * us an invalid request. | |
810 | */ | |
811 | WARN_ON(1); | |
ebd6d357 | 812 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 813 | } else { |
4e4141a5 AV |
814 | sdhci_writel(host, host->adma_addr, |
815 | SDHCI_ADMA_ADDRESS); | |
8f1934ce PO |
816 | } |
817 | } else { | |
c8b3e02e | 818 | int sg_cnt; |
8f1934ce | 819 | |
c8b3e02e | 820 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
8f1934ce PO |
821 | data->sg, data->sg_len, |
822 | (data->flags & MMC_DATA_READ) ? | |
823 | DMA_FROM_DEVICE : | |
824 | DMA_TO_DEVICE); | |
c8b3e02e | 825 | if (sg_cnt == 0) { |
8f1934ce PO |
826 | /* |
827 | * This only happens when someone fed | |
828 | * us an invalid request. | |
829 | */ | |
830 | WARN_ON(1); | |
ebd6d357 | 831 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 832 | } else { |
719a61b4 | 833 | WARN_ON(sg_cnt != 1); |
4e4141a5 AV |
834 | sdhci_writel(host, sg_dma_address(data->sg), |
835 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
836 | } |
837 | } | |
838 | } | |
839 | ||
2134a922 PO |
840 | /* |
841 | * Always adjust the DMA selection as some controllers | |
842 | * (e.g. JMicron) can't do PIO properly when the selection | |
843 | * is ADMA. | |
844 | */ | |
845 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 846 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
847 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
848 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
849 | (host->flags & SDHCI_USE_ADMA)) | |
850 | ctrl |= SDHCI_CTRL_ADMA32; | |
851 | else | |
852 | ctrl |= SDHCI_CTRL_SDMA; | |
4e4141a5 | 853 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
854 | } |
855 | ||
8f1934ce | 856 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
da60a91d SAS |
857 | int flags; |
858 | ||
859 | flags = SG_MITER_ATOMIC; | |
860 | if (host->data->flags & MMC_DATA_READ) | |
861 | flags |= SG_MITER_TO_SG; | |
862 | else | |
863 | flags |= SG_MITER_FROM_SG; | |
864 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
7659150c | 865 | host->blocks = data->blocks; |
d129bceb | 866 | } |
c7fa9963 | 867 | |
6aa943ab AV |
868 | sdhci_set_transfer_irqs(host); |
869 | ||
f6a03cbf MV |
870 | /* Set the DMA boundary value and block size */ |
871 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, | |
872 | data->blksz), SDHCI_BLOCK_SIZE); | |
4e4141a5 | 873 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
c7fa9963 PO |
874 | } |
875 | ||
876 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
e89d456f | 877 | struct mmc_command *cmd) |
c7fa9963 PO |
878 | { |
879 | u16 mode; | |
e89d456f | 880 | struct mmc_data *data = cmd->data; |
c7fa9963 | 881 | |
2b558c13 DA |
882 | if (data == NULL) { |
883 | /* clear Auto CMD settings for no data CMDs */ | |
884 | mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); | |
885 | sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | | |
886 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); | |
c7fa9963 | 887 | return; |
2b558c13 | 888 | } |
c7fa9963 | 889 | |
e538fbe8 PO |
890 | WARN_ON(!host->data); |
891 | ||
c7fa9963 | 892 | mode = SDHCI_TRNS_BLK_CNT_EN; |
e89d456f AW |
893 | if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { |
894 | mode |= SDHCI_TRNS_MULTI; | |
895 | /* | |
896 | * If we are sending CMD23, CMD12 never gets sent | |
897 | * on successful completion (so no Auto-CMD12). | |
898 | */ | |
899 | if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) | |
900 | mode |= SDHCI_TRNS_AUTO_CMD12; | |
8edf6371 AW |
901 | else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { |
902 | mode |= SDHCI_TRNS_AUTO_CMD23; | |
903 | sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); | |
904 | } | |
c4512f79 | 905 | } |
8edf6371 | 906 | |
c7fa9963 PO |
907 | if (data->flags & MMC_DATA_READ) |
908 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 909 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
910 | mode |= SDHCI_TRNS_DMA; |
911 | ||
4e4141a5 | 912 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
913 | } |
914 | ||
915 | static void sdhci_finish_data(struct sdhci_host *host) | |
916 | { | |
917 | struct mmc_data *data; | |
d129bceb PO |
918 | |
919 | BUG_ON(!host->data); | |
920 | ||
921 | data = host->data; | |
922 | host->data = NULL; | |
923 | ||
c9fddbc4 | 924 | if (host->flags & SDHCI_REQ_USE_DMA) { |
2134a922 PO |
925 | if (host->flags & SDHCI_USE_ADMA) |
926 | sdhci_adma_table_post(host, data); | |
927 | else { | |
928 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
929 | data->sg_len, (data->flags & MMC_DATA_READ) ? | |
930 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
931 | } | |
d129bceb PO |
932 | } |
933 | ||
934 | /* | |
c9b74c5b PO |
935 | * The specification states that the block count register must |
936 | * be updated, but it does not specify at what point in the | |
937 | * data flow. That makes the register entirely useless to read | |
938 | * back so we have to assume that nothing made it to the card | |
939 | * in the event of an error. | |
d129bceb | 940 | */ |
c9b74c5b PO |
941 | if (data->error) |
942 | data->bytes_xfered = 0; | |
d129bceb | 943 | else |
c9b74c5b | 944 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 945 | |
e89d456f AW |
946 | /* |
947 | * Need to send CMD12 if - | |
948 | * a) open-ended multiblock transfer (no CMD23) | |
949 | * b) error in multiblock transfer | |
950 | */ | |
951 | if (data->stop && | |
952 | (data->error || | |
953 | !host->mrq->sbc)) { | |
954 | ||
d129bceb PO |
955 | /* |
956 | * The controller needs a reset of internal state machines | |
957 | * upon error conditions. | |
958 | */ | |
17b0429d | 959 | if (data->error) { |
03231f9b RK |
960 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
961 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb PO |
962 | } |
963 | ||
964 | sdhci_send_command(host, data->stop); | |
965 | } else | |
966 | tasklet_schedule(&host->finish_tasklet); | |
967 | } | |
968 | ||
c0e55129 | 969 | void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb PO |
970 | { |
971 | int flags; | |
fd2208d7 | 972 | u32 mask; |
7cb2c76f | 973 | unsigned long timeout; |
d129bceb PO |
974 | |
975 | WARN_ON(host->cmd); | |
976 | ||
d129bceb | 977 | /* Wait max 10 ms */ |
7cb2c76f | 978 | timeout = 10; |
fd2208d7 PO |
979 | |
980 | mask = SDHCI_CMD_INHIBIT; | |
981 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
982 | mask |= SDHCI_DATA_INHIBIT; | |
983 | ||
984 | /* We shouldn't wait for data inihibit for stop commands, even | |
985 | though they might use busy signaling */ | |
986 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
987 | mask &= ~SDHCI_DATA_INHIBIT; | |
988 | ||
4e4141a5 | 989 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 990 | if (timeout == 0) { |
a3c76eb9 | 991 | pr_err("%s: Controller never released " |
acf1da45 | 992 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 993 | sdhci_dumpregs(host); |
17b0429d | 994 | cmd->error = -EIO; |
d129bceb PO |
995 | tasklet_schedule(&host->finish_tasklet); |
996 | return; | |
997 | } | |
7cb2c76f PO |
998 | timeout--; |
999 | mdelay(1); | |
1000 | } | |
d129bceb | 1001 | |
3e1a6892 | 1002 | timeout = jiffies; |
1d4d7744 UH |
1003 | if (!cmd->data && cmd->busy_timeout > 9000) |
1004 | timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; | |
3e1a6892 AH |
1005 | else |
1006 | timeout += 10 * HZ; | |
1007 | mod_timer(&host->timer, timeout); | |
d129bceb PO |
1008 | |
1009 | host->cmd = cmd; | |
1010 | ||
a3c7778f | 1011 | sdhci_prepare_data(host, cmd); |
d129bceb | 1012 | |
4e4141a5 | 1013 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 1014 | |
e89d456f | 1015 | sdhci_set_transfer_mode(host, cmd); |
c7fa9963 | 1016 | |
d129bceb | 1017 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
a3c76eb9 | 1018 | pr_err("%s: Unsupported response type!\n", |
d129bceb | 1019 | mmc_hostname(host->mmc)); |
17b0429d | 1020 | cmd->error = -EINVAL; |
d129bceb PO |
1021 | tasklet_schedule(&host->finish_tasklet); |
1022 | return; | |
1023 | } | |
1024 | ||
1025 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
1026 | flags = SDHCI_CMD_RESP_NONE; | |
1027 | else if (cmd->flags & MMC_RSP_136) | |
1028 | flags = SDHCI_CMD_RESP_LONG; | |
1029 | else if (cmd->flags & MMC_RSP_BUSY) | |
1030 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
1031 | else | |
1032 | flags = SDHCI_CMD_RESP_SHORT; | |
1033 | ||
1034 | if (cmd->flags & MMC_RSP_CRC) | |
1035 | flags |= SDHCI_CMD_CRC; | |
1036 | if (cmd->flags & MMC_RSP_OPCODE) | |
1037 | flags |= SDHCI_CMD_INDEX; | |
b513ea25 AN |
1038 | |
1039 | /* CMD19 is special in that the Data Present Select should be set */ | |
069c9f14 G |
1040 | if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || |
1041 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) | |
d129bceb PO |
1042 | flags |= SDHCI_CMD_DATA; |
1043 | ||
4e4141a5 | 1044 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb | 1045 | } |
c0e55129 | 1046 | EXPORT_SYMBOL_GPL(sdhci_send_command); |
d129bceb PO |
1047 | |
1048 | static void sdhci_finish_command(struct sdhci_host *host) | |
1049 | { | |
1050 | int i; | |
1051 | ||
1052 | BUG_ON(host->cmd == NULL); | |
1053 | ||
1054 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
1055 | if (host->cmd->flags & MMC_RSP_136) { | |
1056 | /* CRC is stripped so we need to do some shifting. */ | |
1057 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 1058 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
1059 | SDHCI_RESPONSE + (3-i)*4) << 8; |
1060 | if (i != 3) | |
1061 | host->cmd->resp[i] |= | |
4e4141a5 | 1062 | sdhci_readb(host, |
d129bceb PO |
1063 | SDHCI_RESPONSE + (3-i)*4-1); |
1064 | } | |
1065 | } else { | |
4e4141a5 | 1066 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
1067 | } |
1068 | } | |
1069 | ||
17b0429d | 1070 | host->cmd->error = 0; |
d129bceb | 1071 | |
e89d456f AW |
1072 | /* Finished CMD23, now send actual command. */ |
1073 | if (host->cmd == host->mrq->sbc) { | |
1074 | host->cmd = NULL; | |
1075 | sdhci_send_command(host, host->mrq->cmd); | |
1076 | } else { | |
e538fbe8 | 1077 | |
e89d456f AW |
1078 | /* Processed actual command. */ |
1079 | if (host->data && host->data_early) | |
1080 | sdhci_finish_data(host); | |
d129bceb | 1081 | |
e89d456f AW |
1082 | if (!host->cmd->data) |
1083 | tasklet_schedule(&host->finish_tasklet); | |
1084 | ||
1085 | host->cmd = NULL; | |
1086 | } | |
d129bceb PO |
1087 | } |
1088 | ||
52983382 KL |
1089 | static u16 sdhci_get_preset_value(struct sdhci_host *host) |
1090 | { | |
d975f121 | 1091 | u16 preset = 0; |
52983382 | 1092 | |
d975f121 RK |
1093 | switch (host->timing) { |
1094 | case MMC_TIMING_UHS_SDR12: | |
52983382 KL |
1095 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
1096 | break; | |
d975f121 | 1097 | case MMC_TIMING_UHS_SDR25: |
52983382 KL |
1098 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); |
1099 | break; | |
d975f121 | 1100 | case MMC_TIMING_UHS_SDR50: |
52983382 KL |
1101 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); |
1102 | break; | |
d975f121 RK |
1103 | case MMC_TIMING_UHS_SDR104: |
1104 | case MMC_TIMING_MMC_HS200: | |
52983382 KL |
1105 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); |
1106 | break; | |
d975f121 | 1107 | case MMC_TIMING_UHS_DDR50: |
52983382 KL |
1108 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); |
1109 | break; | |
1110 | default: | |
1111 | pr_warn("%s: Invalid UHS-I mode selected\n", | |
1112 | mmc_hostname(host->mmc)); | |
1113 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); | |
1114 | break; | |
1115 | } | |
1116 | return preset; | |
1117 | } | |
1118 | ||
1771059c | 1119 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
d129bceb | 1120 | { |
c3ed3877 | 1121 | int div = 0; /* Initialized for compiler warning */ |
df16219f | 1122 | int real_div = div, clk_mul = 1; |
c3ed3877 | 1123 | u16 clk = 0; |
7cb2c76f | 1124 | unsigned long timeout; |
d129bceb | 1125 | |
1650d0c7 RK |
1126 | host->mmc->actual_clock = 0; |
1127 | ||
4e4141a5 | 1128 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1129 | |
1130 | if (clock == 0) | |
373073ef | 1131 | return; |
d129bceb | 1132 | |
85105c53 | 1133 | if (host->version >= SDHCI_SPEC_300) { |
da91a8f9 | 1134 | if (host->preset_enabled) { |
52983382 KL |
1135 | u16 pre_val; |
1136 | ||
1137 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1138 | pre_val = sdhci_get_preset_value(host); | |
1139 | div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) | |
1140 | >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; | |
1141 | if (host->clk_mul && | |
1142 | (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { | |
1143 | clk = SDHCI_PROG_CLOCK_MODE; | |
1144 | real_div = div + 1; | |
1145 | clk_mul = host->clk_mul; | |
1146 | } else { | |
1147 | real_div = max_t(int, 1, div << 1); | |
1148 | } | |
1149 | goto clock_set; | |
1150 | } | |
1151 | ||
c3ed3877 AN |
1152 | /* |
1153 | * Check if the Host Controller supports Programmable Clock | |
1154 | * Mode. | |
1155 | */ | |
1156 | if (host->clk_mul) { | |
52983382 KL |
1157 | for (div = 1; div <= 1024; div++) { |
1158 | if ((host->max_clk * host->clk_mul / div) | |
1159 | <= clock) | |
1160 | break; | |
1161 | } | |
c3ed3877 | 1162 | /* |
52983382 KL |
1163 | * Set Programmable Clock Mode in the Clock |
1164 | * Control register. | |
c3ed3877 | 1165 | */ |
52983382 KL |
1166 | clk = SDHCI_PROG_CLOCK_MODE; |
1167 | real_div = div; | |
1168 | clk_mul = host->clk_mul; | |
1169 | div--; | |
c3ed3877 AN |
1170 | } else { |
1171 | /* Version 3.00 divisors must be a multiple of 2. */ | |
1172 | if (host->max_clk <= clock) | |
1173 | div = 1; | |
1174 | else { | |
1175 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; | |
1176 | div += 2) { | |
1177 | if ((host->max_clk / div) <= clock) | |
1178 | break; | |
1179 | } | |
85105c53 | 1180 | } |
df16219f | 1181 | real_div = div; |
c3ed3877 | 1182 | div >>= 1; |
85105c53 ZG |
1183 | } |
1184 | } else { | |
1185 | /* Version 2.00 divisors must be a power of 2. */ | |
0397526d | 1186 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
85105c53 ZG |
1187 | if ((host->max_clk / div) <= clock) |
1188 | break; | |
1189 | } | |
df16219f | 1190 | real_div = div; |
c3ed3877 | 1191 | div >>= 1; |
d129bceb | 1192 | } |
d129bceb | 1193 | |
52983382 | 1194 | clock_set: |
df16219f GC |
1195 | if (real_div) |
1196 | host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; | |
1197 | ||
c3ed3877 | 1198 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
85105c53 ZG |
1199 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
1200 | << SDHCI_DIVIDER_HI_SHIFT; | |
d129bceb | 1201 | clk |= SDHCI_CLOCK_INT_EN; |
4e4141a5 | 1202 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1203 | |
27f6cb16 CB |
1204 | /* Wait max 20 ms */ |
1205 | timeout = 20; | |
4e4141a5 | 1206 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
1207 | & SDHCI_CLOCK_INT_STABLE)) { |
1208 | if (timeout == 0) { | |
a3c76eb9 | 1209 | pr_err("%s: Internal clock never " |
acf1da45 | 1210 | "stabilised.\n", mmc_hostname(host->mmc)); |
d129bceb PO |
1211 | sdhci_dumpregs(host); |
1212 | return; | |
1213 | } | |
7cb2c76f PO |
1214 | timeout--; |
1215 | mdelay(1); | |
1216 | } | |
d129bceb PO |
1217 | |
1218 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 1219 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1220 | } |
1771059c | 1221 | EXPORT_SYMBOL_GPL(sdhci_set_clock); |
d129bceb | 1222 | |
24fbb3ca RK |
1223 | static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
1224 | unsigned short vdd) | |
146ad66e | 1225 | { |
3a48edc4 | 1226 | struct mmc_host *mmc = host->mmc; |
8364248a | 1227 | u8 pwr = 0; |
146ad66e | 1228 | |
24fbb3ca RK |
1229 | if (mode != MMC_POWER_OFF) { |
1230 | switch (1 << vdd) { | |
ae628903 PO |
1231 | case MMC_VDD_165_195: |
1232 | pwr = SDHCI_POWER_180; | |
1233 | break; | |
1234 | case MMC_VDD_29_30: | |
1235 | case MMC_VDD_30_31: | |
1236 | pwr = SDHCI_POWER_300; | |
1237 | break; | |
1238 | case MMC_VDD_32_33: | |
1239 | case MMC_VDD_33_34: | |
1240 | pwr = SDHCI_POWER_330; | |
1241 | break; | |
1242 | default: | |
1243 | BUG(); | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | if (host->pwr == pwr) | |
e921a8b6 | 1248 | return; |
146ad66e | 1249 | |
ae628903 PO |
1250 | host->pwr = pwr; |
1251 | ||
1252 | if (pwr == 0) { | |
4e4141a5 | 1253 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
f0710a55 AH |
1254 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1255 | sdhci_runtime_pm_bus_off(host); | |
24fbb3ca | 1256 | vdd = 0; |
e921a8b6 RK |
1257 | } else { |
1258 | /* | |
1259 | * Spec says that we should clear the power reg before setting | |
1260 | * a new value. Some controllers don't seem to like this though. | |
1261 | */ | |
1262 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) | |
1263 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); | |
146ad66e | 1264 | |
e921a8b6 RK |
1265 | /* |
1266 | * At least the Marvell CaFe chip gets confused if we set the | |
1267 | * voltage and set turn on power at the same time, so set the | |
1268 | * voltage first. | |
1269 | */ | |
1270 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) | |
1271 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); | |
e08c1694 | 1272 | |
e921a8b6 | 1273 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1274 | |
e921a8b6 | 1275 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
557b0697 | 1276 | |
e921a8b6 RK |
1277 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1278 | sdhci_runtime_pm_bus_on(host); | |
f0710a55 | 1279 | |
e921a8b6 RK |
1280 | /* |
1281 | * Some controllers need an extra 10ms delay of 10ms before | |
1282 | * they can apply clock after applying power | |
1283 | */ | |
1284 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) | |
1285 | mdelay(10); | |
1286 | } | |
ceb6143b | 1287 | |
3a48edc4 | 1288 | if (!IS_ERR(mmc->supply.vmmc)) { |
e921a8b6 | 1289 | spin_unlock_irq(&host->lock); |
3a48edc4 | 1290 | mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, vdd); |
e921a8b6 RK |
1291 | spin_lock_irq(&host->lock); |
1292 | } | |
146ad66e PO |
1293 | } |
1294 | ||
d129bceb PO |
1295 | /*****************************************************************************\ |
1296 | * * | |
1297 | * MMC callbacks * | |
1298 | * * | |
1299 | \*****************************************************************************/ | |
1300 | ||
1301 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1302 | { | |
1303 | struct sdhci_host *host; | |
505a8680 | 1304 | int present; |
d129bceb | 1305 | unsigned long flags; |
473b095a | 1306 | u32 tuning_opcode; |
d129bceb PO |
1307 | |
1308 | host = mmc_priv(mmc); | |
1309 | ||
66fd8ad5 AH |
1310 | sdhci_runtime_pm_get(host); |
1311 | ||
d129bceb PO |
1312 | spin_lock_irqsave(&host->lock, flags); |
1313 | ||
1314 | WARN_ON(host->mrq != NULL); | |
1315 | ||
f9134319 | 1316 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1317 | sdhci_activate_led(host); |
2f730fec | 1318 | #endif |
e89d456f AW |
1319 | |
1320 | /* | |
1321 | * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED | |
1322 | * requests if Auto-CMD12 is enabled. | |
1323 | */ | |
1324 | if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { | |
c4512f79 JH |
1325 | if (mrq->stop) { |
1326 | mrq->data->stop = NULL; | |
1327 | mrq->stop = NULL; | |
1328 | } | |
1329 | } | |
d129bceb PO |
1330 | |
1331 | host->mrq = mrq; | |
1332 | ||
505a8680 SG |
1333 | /* |
1334 | * Firstly check card presence from cd-gpio. The return could | |
1335 | * be one of the following possibilities: | |
1336 | * negative: cd-gpio is not available | |
1337 | * zero: cd-gpio is used, and card is removed | |
1338 | * one: cd-gpio is used, and card is present | |
1339 | */ | |
1340 | present = mmc_gpio_get_cd(host->mmc); | |
1341 | if (present < 0) { | |
1342 | /* If polling, assume that the card is always present. */ | |
1343 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1344 | present = 1; | |
1345 | else | |
1346 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
1347 | SDHCI_CARD_PRESENT; | |
bec9d4e5 GL |
1348 | } |
1349 | ||
68d1fb7e | 1350 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { |
17b0429d | 1351 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb | 1352 | tasklet_schedule(&host->finish_tasklet); |
cf2b5eea AN |
1353 | } else { |
1354 | u32 present_state; | |
1355 | ||
1356 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
1357 | /* | |
1358 | * Check if the re-tuning timer has already expired and there | |
1359 | * is no on-going data transfer. If so, we need to execute | |
1360 | * tuning procedure before sending command. | |
1361 | */ | |
1362 | if ((host->flags & SDHCI_NEEDS_RETUNING) && | |
1363 | !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { | |
14efd957 CB |
1364 | if (mmc->card) { |
1365 | /* eMMC uses cmd21 but sd and sdio use cmd19 */ | |
1366 | tuning_opcode = | |
1367 | mmc->card->type == MMC_TYPE_MMC ? | |
1368 | MMC_SEND_TUNING_BLOCK_HS200 : | |
1369 | MMC_SEND_TUNING_BLOCK; | |
63c21180 CL |
1370 | |
1371 | /* Here we need to set the host->mrq to NULL, | |
1372 | * in case the pending finish_tasklet | |
1373 | * finishes it incorrectly. | |
1374 | */ | |
1375 | host->mrq = NULL; | |
1376 | ||
14efd957 CB |
1377 | spin_unlock_irqrestore(&host->lock, flags); |
1378 | sdhci_execute_tuning(mmc, tuning_opcode); | |
1379 | spin_lock_irqsave(&host->lock, flags); | |
1380 | ||
1381 | /* Restore original mmc_request structure */ | |
1382 | host->mrq = mrq; | |
1383 | } | |
cf2b5eea AN |
1384 | } |
1385 | ||
8edf6371 | 1386 | if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) |
e89d456f AW |
1387 | sdhci_send_command(host, mrq->sbc); |
1388 | else | |
1389 | sdhci_send_command(host, mrq->cmd); | |
cf2b5eea | 1390 | } |
d129bceb | 1391 | |
5f25a66f | 1392 | mmiowb(); |
d129bceb PO |
1393 | spin_unlock_irqrestore(&host->lock, flags); |
1394 | } | |
1395 | ||
2317f56c RK |
1396 | void sdhci_set_bus_width(struct sdhci_host *host, int width) |
1397 | { | |
1398 | u8 ctrl; | |
1399 | ||
1400 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
1401 | if (width == MMC_BUS_WIDTH_8) { | |
1402 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1403 | if (host->version >= SDHCI_SPEC_300) | |
1404 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1405 | } else { | |
1406 | if (host->version >= SDHCI_SPEC_300) | |
1407 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1408 | if (width == MMC_BUS_WIDTH_4) | |
1409 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1410 | else | |
1411 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1412 | } | |
1413 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1414 | } | |
1415 | EXPORT_SYMBOL_GPL(sdhci_set_bus_width); | |
1416 | ||
96d7b78c RK |
1417 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
1418 | { | |
1419 | u16 ctrl_2; | |
1420 | ||
1421 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1422 | /* Select Bus Speed Mode for host */ | |
1423 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
1424 | if ((timing == MMC_TIMING_MMC_HS200) || | |
1425 | (timing == MMC_TIMING_UHS_SDR104)) | |
1426 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
1427 | else if (timing == MMC_TIMING_UHS_SDR12) | |
1428 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
1429 | else if (timing == MMC_TIMING_UHS_SDR25) | |
1430 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
1431 | else if (timing == MMC_TIMING_UHS_SDR50) | |
1432 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
1433 | else if ((timing == MMC_TIMING_UHS_DDR50) || | |
1434 | (timing == MMC_TIMING_MMC_DDR52)) | |
1435 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | |
1436 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
1437 | } | |
1438 | EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); | |
1439 | ||
66fd8ad5 | 1440 | static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) |
d129bceb | 1441 | { |
d129bceb PO |
1442 | unsigned long flags; |
1443 | u8 ctrl; | |
3a48edc4 | 1444 | struct mmc_host *mmc = host->mmc; |
d129bceb | 1445 | |
d129bceb PO |
1446 | spin_lock_irqsave(&host->lock, flags); |
1447 | ||
ceb6143b AH |
1448 | if (host->flags & SDHCI_DEVICE_DEAD) { |
1449 | spin_unlock_irqrestore(&host->lock, flags); | |
3a48edc4 TK |
1450 | if (!IS_ERR(mmc->supply.vmmc) && |
1451 | ios->power_mode == MMC_POWER_OFF) | |
1452 | mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, 0); | |
ceb6143b AH |
1453 | return; |
1454 | } | |
1e72859e | 1455 | |
d129bceb PO |
1456 | /* |
1457 | * Reset the chip on each power off. | |
1458 | * Should clear out any weird states. | |
1459 | */ | |
1460 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1461 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1462 | sdhci_reinit(host); |
d129bceb PO |
1463 | } |
1464 | ||
52983382 | 1465 | if (host->version >= SDHCI_SPEC_300 && |
372c4634 DA |
1466 | (ios->power_mode == MMC_POWER_UP) && |
1467 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) | |
52983382 KL |
1468 | sdhci_enable_preset_value(host, false); |
1469 | ||
373073ef | 1470 | if (!ios->clock || ios->clock != host->clock) { |
1771059c | 1471 | host->ops->set_clock(host, ios->clock); |
373073ef RK |
1472 | host->clock = ios->clock; |
1473 | } | |
d129bceb | 1474 | |
24fbb3ca | 1475 | sdhci_set_power(host, ios->power_mode, ios->vdd); |
d129bceb | 1476 | |
643a81ff PR |
1477 | if (host->ops->platform_send_init_74_clocks) |
1478 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); | |
1479 | ||
2317f56c | 1480 | host->ops->set_bus_width(host, ios->bus_width); |
ae6d6c92 | 1481 | |
15ec4461 | 1482 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1483 | |
3ab9c8da PR |
1484 | if ((ios->timing == MMC_TIMING_SD_HS || |
1485 | ios->timing == MMC_TIMING_MMC_HS) | |
1486 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) | |
cd9277c0 PO |
1487 | ctrl |= SDHCI_CTRL_HISPD; |
1488 | else | |
1489 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1490 | ||
d6d50a15 | 1491 | if (host->version >= SDHCI_SPEC_300) { |
49c468fc | 1492 | u16 clk, ctrl_2; |
49c468fc AN |
1493 | |
1494 | /* In case of UHS-I modes, set High Speed Enable */ | |
069c9f14 | 1495 | if ((ios->timing == MMC_TIMING_MMC_HS200) || |
bb8175a8 | 1496 | (ios->timing == MMC_TIMING_MMC_DDR52) || |
069c9f14 | 1497 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
49c468fc AN |
1498 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
1499 | (ios->timing == MMC_TIMING_UHS_DDR50) || | |
dd8df17f | 1500 | (ios->timing == MMC_TIMING_UHS_SDR25)) |
49c468fc | 1501 | ctrl |= SDHCI_CTRL_HISPD; |
d6d50a15 | 1502 | |
da91a8f9 | 1503 | if (!host->preset_enabled) { |
758535c4 | 1504 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d6d50a15 AN |
1505 | /* |
1506 | * We only need to set Driver Strength if the | |
1507 | * preset value enable is not set. | |
1508 | */ | |
da91a8f9 | 1509 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
d6d50a15 AN |
1510 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; |
1511 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) | |
1512 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; | |
1513 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) | |
1514 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; | |
1515 | ||
1516 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
758535c4 AN |
1517 | } else { |
1518 | /* | |
1519 | * According to SDHC Spec v3.00, if the Preset Value | |
1520 | * Enable in the Host Control 2 register is set, we | |
1521 | * need to reset SD Clock Enable before changing High | |
1522 | * Speed Enable to avoid generating clock gliches. | |
1523 | */ | |
758535c4 AN |
1524 | |
1525 | /* Reset SD Clock Enable */ | |
1526 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1527 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1528 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1529 | ||
1530 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1531 | ||
1532 | /* Re-enable SD Clock */ | |
1771059c | 1533 | host->ops->set_clock(host, host->clock); |
d6d50a15 | 1534 | } |
49c468fc | 1535 | |
49c468fc AN |
1536 | |
1537 | /* Reset SD Clock Enable */ | |
1538 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1539 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1540 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1541 | ||
96d7b78c | 1542 | host->ops->set_uhs_signaling(host, ios->timing); |
d975f121 | 1543 | host->timing = ios->timing; |
49c468fc | 1544 | |
52983382 KL |
1545 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && |
1546 | ((ios->timing == MMC_TIMING_UHS_SDR12) || | |
1547 | (ios->timing == MMC_TIMING_UHS_SDR25) || | |
1548 | (ios->timing == MMC_TIMING_UHS_SDR50) || | |
1549 | (ios->timing == MMC_TIMING_UHS_SDR104) || | |
1550 | (ios->timing == MMC_TIMING_UHS_DDR50))) { | |
1551 | u16 preset; | |
1552 | ||
1553 | sdhci_enable_preset_value(host, true); | |
1554 | preset = sdhci_get_preset_value(host); | |
1555 | ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) | |
1556 | >> SDHCI_PRESET_DRV_SHIFT; | |
1557 | } | |
1558 | ||
49c468fc | 1559 | /* Re-enable SD Clock */ |
1771059c | 1560 | host->ops->set_clock(host, host->clock); |
758535c4 AN |
1561 | } else |
1562 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
d6d50a15 | 1563 | |
b8352260 LD |
1564 | /* |
1565 | * Some (ENE) controllers go apeshit on some ios operation, | |
1566 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1567 | * it on each ios seems to solve the problem. | |
1568 | */ | |
b8c86fc5 | 1569 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
03231f9b | 1570 | sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
b8352260 | 1571 | |
5f25a66f | 1572 | mmiowb(); |
d129bceb PO |
1573 | spin_unlock_irqrestore(&host->lock, flags); |
1574 | } | |
1575 | ||
66fd8ad5 AH |
1576 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1577 | { | |
1578 | struct sdhci_host *host = mmc_priv(mmc); | |
1579 | ||
1580 | sdhci_runtime_pm_get(host); | |
1581 | sdhci_do_set_ios(host, ios); | |
1582 | sdhci_runtime_pm_put(host); | |
1583 | } | |
1584 | ||
94144a46 KL |
1585 | static int sdhci_do_get_cd(struct sdhci_host *host) |
1586 | { | |
1587 | int gpio_cd = mmc_gpio_get_cd(host->mmc); | |
1588 | ||
1589 | if (host->flags & SDHCI_DEVICE_DEAD) | |
1590 | return 0; | |
1591 | ||
1592 | /* If polling/nonremovable, assume that the card is always present. */ | |
1593 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || | |
1594 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) | |
1595 | return 1; | |
1596 | ||
1597 | /* Try slot gpio detect */ | |
1598 | if (!IS_ERR_VALUE(gpio_cd)) | |
1599 | return !!gpio_cd; | |
1600 | ||
1601 | /* Host native card detect */ | |
1602 | return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); | |
1603 | } | |
1604 | ||
1605 | static int sdhci_get_cd(struct mmc_host *mmc) | |
1606 | { | |
1607 | struct sdhci_host *host = mmc_priv(mmc); | |
1608 | int ret; | |
1609 | ||
1610 | sdhci_runtime_pm_get(host); | |
1611 | ret = sdhci_do_get_cd(host); | |
1612 | sdhci_runtime_pm_put(host); | |
1613 | return ret; | |
1614 | } | |
1615 | ||
66fd8ad5 | 1616 | static int sdhci_check_ro(struct sdhci_host *host) |
d129bceb | 1617 | { |
d129bceb | 1618 | unsigned long flags; |
2dfb579c | 1619 | int is_readonly; |
d129bceb | 1620 | |
d129bceb PO |
1621 | spin_lock_irqsave(&host->lock, flags); |
1622 | ||
1e72859e | 1623 | if (host->flags & SDHCI_DEVICE_DEAD) |
2dfb579c WS |
1624 | is_readonly = 0; |
1625 | else if (host->ops->get_ro) | |
1626 | is_readonly = host->ops->get_ro(host); | |
1e72859e | 1627 | else |
2dfb579c WS |
1628 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
1629 | & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1630 | |
1631 | spin_unlock_irqrestore(&host->lock, flags); | |
1632 | ||
2dfb579c WS |
1633 | /* This quirk needs to be replaced by a callback-function later */ |
1634 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? | |
1635 | !is_readonly : is_readonly; | |
d129bceb PO |
1636 | } |
1637 | ||
82b0e23a TI |
1638 | #define SAMPLE_COUNT 5 |
1639 | ||
66fd8ad5 | 1640 | static int sdhci_do_get_ro(struct sdhci_host *host) |
82b0e23a | 1641 | { |
82b0e23a TI |
1642 | int i, ro_count; |
1643 | ||
82b0e23a | 1644 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) |
66fd8ad5 | 1645 | return sdhci_check_ro(host); |
82b0e23a TI |
1646 | |
1647 | ro_count = 0; | |
1648 | for (i = 0; i < SAMPLE_COUNT; i++) { | |
66fd8ad5 | 1649 | if (sdhci_check_ro(host)) { |
82b0e23a TI |
1650 | if (++ro_count > SAMPLE_COUNT / 2) |
1651 | return 1; | |
1652 | } | |
1653 | msleep(30); | |
1654 | } | |
1655 | return 0; | |
1656 | } | |
1657 | ||
20758b66 AH |
1658 | static void sdhci_hw_reset(struct mmc_host *mmc) |
1659 | { | |
1660 | struct sdhci_host *host = mmc_priv(mmc); | |
1661 | ||
1662 | if (host->ops && host->ops->hw_reset) | |
1663 | host->ops->hw_reset(host); | |
1664 | } | |
1665 | ||
66fd8ad5 | 1666 | static int sdhci_get_ro(struct mmc_host *mmc) |
f75979b7 | 1667 | { |
66fd8ad5 AH |
1668 | struct sdhci_host *host = mmc_priv(mmc); |
1669 | int ret; | |
f75979b7 | 1670 | |
66fd8ad5 AH |
1671 | sdhci_runtime_pm_get(host); |
1672 | ret = sdhci_do_get_ro(host); | |
1673 | sdhci_runtime_pm_put(host); | |
1674 | return ret; | |
1675 | } | |
f75979b7 | 1676 | |
66fd8ad5 AH |
1677 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
1678 | { | |
be138554 | 1679 | if (!(host->flags & SDHCI_DEVICE_DEAD)) { |
ef104333 | 1680 | if (enable) |
b537f94c | 1681 | host->ier |= SDHCI_INT_CARD_INT; |
ef104333 | 1682 | else |
b537f94c RK |
1683 | host->ier &= ~SDHCI_INT_CARD_INT; |
1684 | ||
1685 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
1686 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
ef104333 RK |
1687 | mmiowb(); |
1688 | } | |
66fd8ad5 AH |
1689 | } |
1690 | ||
1691 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) | |
1692 | { | |
1693 | struct sdhci_host *host = mmc_priv(mmc); | |
1694 | unsigned long flags; | |
f75979b7 | 1695 | |
ef104333 RK |
1696 | sdhci_runtime_pm_get(host); |
1697 | ||
66fd8ad5 | 1698 | spin_lock_irqsave(&host->lock, flags); |
ef104333 RK |
1699 | if (enable) |
1700 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; | |
1701 | else | |
1702 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; | |
1703 | ||
66fd8ad5 | 1704 | sdhci_enable_sdio_irq_nolock(host, enable); |
f75979b7 | 1705 | spin_unlock_irqrestore(&host->lock, flags); |
ef104333 RK |
1706 | |
1707 | sdhci_runtime_pm_put(host); | |
f75979b7 PO |
1708 | } |
1709 | ||
20b92a30 | 1710 | static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, |
21f5998f | 1711 | struct mmc_ios *ios) |
f2119df6 | 1712 | { |
3a48edc4 | 1713 | struct mmc_host *mmc = host->mmc; |
20b92a30 | 1714 | u16 ctrl; |
6231f3de | 1715 | int ret; |
f2119df6 | 1716 | |
20b92a30 KL |
1717 | /* |
1718 | * Signal Voltage Switching is only applicable for Host Controllers | |
1719 | * v3.00 and above. | |
1720 | */ | |
1721 | if (host->version < SDHCI_SPEC_300) | |
1722 | return 0; | |
6231f3de | 1723 | |
f2119df6 | 1724 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
f2119df6 | 1725 | |
21f5998f | 1726 | switch (ios->signal_voltage) { |
20b92a30 KL |
1727 | case MMC_SIGNAL_VOLTAGE_330: |
1728 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ | |
1729 | ctrl &= ~SDHCI_CTRL_VDD_180; | |
1730 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
f2119df6 | 1731 | |
3a48edc4 TK |
1732 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1733 | ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, | |
1734 | 3600000); | |
20b92a30 KL |
1735 | if (ret) { |
1736 | pr_warning("%s: Switching to 3.3V signalling voltage " | |
1737 | " failed\n", mmc_hostname(host->mmc)); | |
1738 | return -EIO; | |
1739 | } | |
1740 | } | |
1741 | /* Wait for 5ms */ | |
1742 | usleep_range(5000, 5500); | |
f2119df6 | 1743 | |
20b92a30 KL |
1744 | /* 3.3V regulator output should be stable within 5 ms */ |
1745 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1746 | if (!(ctrl & SDHCI_CTRL_VDD_180)) | |
1747 | return 0; | |
6231f3de | 1748 | |
20b92a30 KL |
1749 | pr_warning("%s: 3.3V regulator output did not became stable\n", |
1750 | mmc_hostname(host->mmc)); | |
1751 | ||
1752 | return -EAGAIN; | |
1753 | case MMC_SIGNAL_VOLTAGE_180: | |
3a48edc4 TK |
1754 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1755 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
20b92a30 KL |
1756 | 1700000, 1950000); |
1757 | if (ret) { | |
1758 | pr_warning("%s: Switching to 1.8V signalling voltage " | |
1759 | " failed\n", mmc_hostname(host->mmc)); | |
1760 | return -EIO; | |
1761 | } | |
1762 | } | |
6231f3de | 1763 | |
6231f3de PR |
1764 | /* |
1765 | * Enable 1.8V Signal Enable in the Host Control2 | |
1766 | * register | |
1767 | */ | |
20b92a30 KL |
1768 | ctrl |= SDHCI_CTRL_VDD_180; |
1769 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
6231f3de | 1770 | |
20b92a30 KL |
1771 | /* Wait for 5ms */ |
1772 | usleep_range(5000, 5500); | |
f2119df6 | 1773 | |
20b92a30 KL |
1774 | /* 1.8V regulator output should be stable within 5 ms */ |
1775 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1776 | if (ctrl & SDHCI_CTRL_VDD_180) | |
1777 | return 0; | |
f2119df6 | 1778 | |
20b92a30 KL |
1779 | pr_warning("%s: 1.8V regulator output did not became stable\n", |
1780 | mmc_hostname(host->mmc)); | |
f2119df6 | 1781 | |
20b92a30 KL |
1782 | return -EAGAIN; |
1783 | case MMC_SIGNAL_VOLTAGE_120: | |
3a48edc4 TK |
1784 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1785 | ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, | |
1786 | 1300000); | |
20b92a30 KL |
1787 | if (ret) { |
1788 | pr_warning("%s: Switching to 1.2V signalling voltage " | |
1789 | " failed\n", mmc_hostname(host->mmc)); | |
1790 | return -EIO; | |
f2119df6 AN |
1791 | } |
1792 | } | |
6231f3de | 1793 | return 0; |
20b92a30 | 1794 | default: |
f2119df6 AN |
1795 | /* No signal voltage switch required */ |
1796 | return 0; | |
20b92a30 | 1797 | } |
f2119df6 AN |
1798 | } |
1799 | ||
66fd8ad5 | 1800 | static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
21f5998f | 1801 | struct mmc_ios *ios) |
66fd8ad5 AH |
1802 | { |
1803 | struct sdhci_host *host = mmc_priv(mmc); | |
1804 | int err; | |
1805 | ||
1806 | if (host->version < SDHCI_SPEC_300) | |
1807 | return 0; | |
1808 | sdhci_runtime_pm_get(host); | |
21f5998f | 1809 | err = sdhci_do_start_signal_voltage_switch(host, ios); |
66fd8ad5 AH |
1810 | sdhci_runtime_pm_put(host); |
1811 | return err; | |
1812 | } | |
1813 | ||
20b92a30 KL |
1814 | static int sdhci_card_busy(struct mmc_host *mmc) |
1815 | { | |
1816 | struct sdhci_host *host = mmc_priv(mmc); | |
1817 | u32 present_state; | |
1818 | ||
1819 | sdhci_runtime_pm_get(host); | |
1820 | /* Check whether DAT[3:0] is 0000 */ | |
1821 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
1822 | sdhci_runtime_pm_put(host); | |
1823 | ||
1824 | return !(present_state & SDHCI_DATA_LVL_MASK); | |
1825 | } | |
1826 | ||
069c9f14 | 1827 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
b513ea25 | 1828 | { |
4b6f37d3 | 1829 | struct sdhci_host *host = mmc_priv(mmc); |
b513ea25 | 1830 | u16 ctrl; |
b513ea25 | 1831 | int tuning_loop_counter = MAX_TUNING_LOOP; |
b513ea25 | 1832 | int err = 0; |
2b35bd83 | 1833 | unsigned long flags; |
b513ea25 | 1834 | |
66fd8ad5 | 1835 | sdhci_runtime_pm_get(host); |
2b35bd83 | 1836 | spin_lock_irqsave(&host->lock, flags); |
b513ea25 | 1837 | |
b513ea25 | 1838 | /* |
069c9f14 G |
1839 | * The Host Controller needs tuning only in case of SDR104 mode |
1840 | * and for SDR50 mode when Use Tuning for SDR50 is set in the | |
b513ea25 | 1841 | * Capabilities register. |
069c9f14 G |
1842 | * If the Host Controller supports the HS200 mode then the |
1843 | * tuning function has to be executed. | |
b513ea25 | 1844 | */ |
4b6f37d3 RK |
1845 | switch (host->timing) { |
1846 | case MMC_TIMING_MMC_HS200: | |
1847 | case MMC_TIMING_UHS_SDR104: | |
1848 | break; | |
1849 | ||
1850 | case MMC_TIMING_UHS_SDR50: | |
1851 | if (host->flags & SDHCI_SDR50_NEEDS_TUNING || | |
1852 | host->flags & SDHCI_SDR104_NEEDS_TUNING) | |
1853 | break; | |
1854 | /* FALLTHROUGH */ | |
1855 | ||
1856 | default: | |
2b35bd83 | 1857 | spin_unlock_irqrestore(&host->lock, flags); |
66fd8ad5 | 1858 | sdhci_runtime_pm_put(host); |
b513ea25 AN |
1859 | return 0; |
1860 | } | |
1861 | ||
45251812 | 1862 | if (host->ops->platform_execute_tuning) { |
2b35bd83 | 1863 | spin_unlock_irqrestore(&host->lock, flags); |
45251812 DA |
1864 | err = host->ops->platform_execute_tuning(host, opcode); |
1865 | sdhci_runtime_pm_put(host); | |
1866 | return err; | |
1867 | } | |
1868 | ||
4b6f37d3 RK |
1869 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
1870 | ctrl |= SDHCI_CTRL_EXEC_TUNING; | |
b513ea25 AN |
1871 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
1872 | ||
1873 | /* | |
1874 | * As per the Host Controller spec v3.00, tuning command | |
1875 | * generates Buffer Read Ready interrupt, so enable that. | |
1876 | * | |
1877 | * Note: The spec clearly says that when tuning sequence | |
1878 | * is being performed, the controller does not generate | |
1879 | * interrupts other than Buffer Read Ready interrupt. But | |
1880 | * to make sure we don't hit a controller bug, we _only_ | |
1881 | * enable Buffer Read Ready interrupt here. | |
1882 | */ | |
b537f94c RK |
1883 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
1884 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); | |
b513ea25 AN |
1885 | |
1886 | /* | |
1887 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number | |
1888 | * of loops reaches 40 times or a timeout of 150ms occurs. | |
1889 | */ | |
b513ea25 AN |
1890 | do { |
1891 | struct mmc_command cmd = {0}; | |
66fd8ad5 | 1892 | struct mmc_request mrq = {NULL}; |
b513ea25 | 1893 | |
069c9f14 | 1894 | cmd.opcode = opcode; |
b513ea25 AN |
1895 | cmd.arg = 0; |
1896 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; | |
1897 | cmd.retries = 0; | |
1898 | cmd.data = NULL; | |
1899 | cmd.error = 0; | |
1900 | ||
7ce45e95 AC |
1901 | if (tuning_loop_counter-- == 0) |
1902 | break; | |
1903 | ||
b513ea25 AN |
1904 | mrq.cmd = &cmd; |
1905 | host->mrq = &mrq; | |
1906 | ||
1907 | /* | |
1908 | * In response to CMD19, the card sends 64 bytes of tuning | |
1909 | * block to the Host Controller. So we set the block size | |
1910 | * to 64 here. | |
1911 | */ | |
069c9f14 G |
1912 | if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { |
1913 | if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
1914 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), | |
1915 | SDHCI_BLOCK_SIZE); | |
1916 | else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) | |
1917 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1918 | SDHCI_BLOCK_SIZE); | |
1919 | } else { | |
1920 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1921 | SDHCI_BLOCK_SIZE); | |
1922 | } | |
b513ea25 AN |
1923 | |
1924 | /* | |
1925 | * The tuning block is sent by the card to the host controller. | |
1926 | * So we set the TRNS_READ bit in the Transfer Mode register. | |
1927 | * This also takes care of setting DMA Enable and Multi Block | |
1928 | * Select in the same register to 0. | |
1929 | */ | |
1930 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); | |
1931 | ||
1932 | sdhci_send_command(host, &cmd); | |
1933 | ||
1934 | host->cmd = NULL; | |
1935 | host->mrq = NULL; | |
1936 | ||
2b35bd83 | 1937 | spin_unlock_irqrestore(&host->lock, flags); |
b513ea25 AN |
1938 | /* Wait for Buffer Read Ready interrupt */ |
1939 | wait_event_interruptible_timeout(host->buf_ready_int, | |
1940 | (host->tuning_done == 1), | |
1941 | msecs_to_jiffies(50)); | |
2b35bd83 | 1942 | spin_lock_irqsave(&host->lock, flags); |
b513ea25 AN |
1943 | |
1944 | if (!host->tuning_done) { | |
a3c76eb9 | 1945 | pr_info(DRIVER_NAME ": Timeout waiting for " |
b513ea25 AN |
1946 | "Buffer Read Ready interrupt during tuning " |
1947 | "procedure, falling back to fixed sampling " | |
1948 | "clock\n"); | |
1949 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1950 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; | |
1951 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; | |
1952 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
1953 | ||
1954 | err = -EIO; | |
1955 | goto out; | |
1956 | } | |
1957 | ||
1958 | host->tuning_done = 0; | |
1959 | ||
1960 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
197160d5 NS |
1961 | |
1962 | /* eMMC spec does not require a delay between tuning cycles */ | |
1963 | if (opcode == MMC_SEND_TUNING_BLOCK) | |
1964 | mdelay(1); | |
b513ea25 AN |
1965 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
1966 | ||
1967 | /* | |
1968 | * The Host Driver has exhausted the maximum number of loops allowed, | |
1969 | * so use fixed sampling frequency. | |
1970 | */ | |
7ce45e95 | 1971 | if (tuning_loop_counter < 0) { |
b513ea25 AN |
1972 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
1973 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
7ce45e95 AC |
1974 | } |
1975 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { | |
1976 | pr_info(DRIVER_NAME ": Tuning procedure" | |
1977 | " failed, falling back to fixed sampling" | |
1978 | " clock\n"); | |
114f2bf6 | 1979 | err = -EIO; |
b513ea25 AN |
1980 | } |
1981 | ||
1982 | out: | |
cf2b5eea AN |
1983 | /* |
1984 | * If this is the very first time we are here, we start the retuning | |
1985 | * timer. Since only during the first time, SDHCI_NEEDS_RETUNING | |
1986 | * flag won't be set, we check this condition before actually starting | |
1987 | * the timer. | |
1988 | */ | |
1989 | if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && | |
1990 | (host->tuning_mode == SDHCI_TUNING_MODE_1)) { | |
973905fe | 1991 | host->flags |= SDHCI_USING_RETUNING_TIMER; |
cf2b5eea AN |
1992 | mod_timer(&host->tuning_timer, jiffies + |
1993 | host->tuning_count * HZ); | |
1994 | /* Tuning mode 1 limits the maximum data length to 4MB */ | |
1995 | mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; | |
2bc02485 | 1996 | } else if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
cf2b5eea AN |
1997 | host->flags &= ~SDHCI_NEEDS_RETUNING; |
1998 | /* Reload the new initial value for timer */ | |
2bc02485 AS |
1999 | mod_timer(&host->tuning_timer, jiffies + |
2000 | host->tuning_count * HZ); | |
cf2b5eea AN |
2001 | } |
2002 | ||
2003 | /* | |
2004 | * In case tuning fails, host controllers which support re-tuning can | |
2005 | * try tuning again at a later time, when the re-tuning timer expires. | |
2006 | * So for these controllers, we return 0. Since there might be other | |
2007 | * controllers who do not have this capability, we return error for | |
973905fe AL |
2008 | * them. SDHCI_USING_RETUNING_TIMER means the host is currently using |
2009 | * a retuning timer to do the retuning for the card. | |
cf2b5eea | 2010 | */ |
973905fe | 2011 | if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) |
cf2b5eea AN |
2012 | err = 0; |
2013 | ||
b537f94c RK |
2014 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
2015 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
2b35bd83 | 2016 | spin_unlock_irqrestore(&host->lock, flags); |
66fd8ad5 | 2017 | sdhci_runtime_pm_put(host); |
b513ea25 AN |
2018 | |
2019 | return err; | |
2020 | } | |
2021 | ||
52983382 KL |
2022 | |
2023 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) | |
4d55c5a1 | 2024 | { |
4d55c5a1 AN |
2025 | /* Host Controller v3.00 defines preset value registers */ |
2026 | if (host->version < SDHCI_SPEC_300) | |
2027 | return; | |
2028 | ||
4d55c5a1 AN |
2029 | /* |
2030 | * We only enable or disable Preset Value if they are not already | |
2031 | * enabled or disabled respectively. Otherwise, we bail out. | |
2032 | */ | |
da91a8f9 RK |
2033 | if (host->preset_enabled != enable) { |
2034 | u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
2035 | ||
2036 | if (enable) | |
2037 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2038 | else | |
2039 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2040 | ||
4d55c5a1 | 2041 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
da91a8f9 RK |
2042 | |
2043 | if (enable) | |
2044 | host->flags |= SDHCI_PV_ENABLED; | |
2045 | else | |
2046 | host->flags &= ~SDHCI_PV_ENABLED; | |
2047 | ||
2048 | host->preset_enabled = enable; | |
4d55c5a1 | 2049 | } |
66fd8ad5 AH |
2050 | } |
2051 | ||
71e69211 | 2052 | static void sdhci_card_event(struct mmc_host *mmc) |
d129bceb | 2053 | { |
71e69211 | 2054 | struct sdhci_host *host = mmc_priv(mmc); |
d129bceb PO |
2055 | unsigned long flags; |
2056 | ||
722e1280 CD |
2057 | /* First check if client has provided their own card event */ |
2058 | if (host->ops->card_event) | |
2059 | host->ops->card_event(host); | |
2060 | ||
d129bceb PO |
2061 | spin_lock_irqsave(&host->lock, flags); |
2062 | ||
66fd8ad5 | 2063 | /* Check host->mrq first in case we are runtime suspended */ |
9668d765 | 2064 | if (host->mrq && !sdhci_do_get_cd(host)) { |
a3c76eb9 | 2065 | pr_err("%s: Card removed during transfer!\n", |
66fd8ad5 | 2066 | mmc_hostname(host->mmc)); |
a3c76eb9 | 2067 | pr_err("%s: Resetting controller.\n", |
66fd8ad5 | 2068 | mmc_hostname(host->mmc)); |
d129bceb | 2069 | |
03231f9b RK |
2070 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
2071 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb | 2072 | |
66fd8ad5 AH |
2073 | host->mrq->cmd->error = -ENOMEDIUM; |
2074 | tasklet_schedule(&host->finish_tasklet); | |
d129bceb PO |
2075 | } |
2076 | ||
2077 | spin_unlock_irqrestore(&host->lock, flags); | |
71e69211 GL |
2078 | } |
2079 | ||
2080 | static const struct mmc_host_ops sdhci_ops = { | |
2081 | .request = sdhci_request, | |
2082 | .set_ios = sdhci_set_ios, | |
94144a46 | 2083 | .get_cd = sdhci_get_cd, |
71e69211 GL |
2084 | .get_ro = sdhci_get_ro, |
2085 | .hw_reset = sdhci_hw_reset, | |
2086 | .enable_sdio_irq = sdhci_enable_sdio_irq, | |
2087 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, | |
2088 | .execute_tuning = sdhci_execute_tuning, | |
71e69211 | 2089 | .card_event = sdhci_card_event, |
20b92a30 | 2090 | .card_busy = sdhci_card_busy, |
71e69211 GL |
2091 | }; |
2092 | ||
2093 | /*****************************************************************************\ | |
2094 | * * | |
2095 | * Tasklets * | |
2096 | * * | |
2097 | \*****************************************************************************/ | |
2098 | ||
d129bceb PO |
2099 | static void sdhci_tasklet_finish(unsigned long param) |
2100 | { | |
2101 | struct sdhci_host *host; | |
2102 | unsigned long flags; | |
2103 | struct mmc_request *mrq; | |
2104 | ||
2105 | host = (struct sdhci_host*)param; | |
2106 | ||
66fd8ad5 AH |
2107 | spin_lock_irqsave(&host->lock, flags); |
2108 | ||
0c9c99a7 CB |
2109 | /* |
2110 | * If this tasklet gets rescheduled while running, it will | |
2111 | * be run again afterwards but without any active request. | |
2112 | */ | |
66fd8ad5 AH |
2113 | if (!host->mrq) { |
2114 | spin_unlock_irqrestore(&host->lock, flags); | |
0c9c99a7 | 2115 | return; |
66fd8ad5 | 2116 | } |
d129bceb PO |
2117 | |
2118 | del_timer(&host->timer); | |
2119 | ||
2120 | mrq = host->mrq; | |
2121 | ||
d129bceb PO |
2122 | /* |
2123 | * The controller needs a reset of internal state machines | |
2124 | * upon error conditions. | |
2125 | */ | |
1e72859e | 2126 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
b7b4d342 | 2127 | ((mrq->cmd && mrq->cmd->error) || |
1e72859e PO |
2128 | (mrq->data && (mrq->data->error || |
2129 | (mrq->data->stop && mrq->data->stop->error))) || | |
2130 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
2131 | |
2132 | /* Some controllers need this kick or reset won't work here */ | |
8213af3b | 2133 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) |
645289dc | 2134 | /* This is to force an update */ |
1771059c | 2135 | host->ops->set_clock(host, host->clock); |
645289dc PO |
2136 | |
2137 | /* Spec says we should do both at the same time, but Ricoh | |
2138 | controllers do not like that. */ | |
03231f9b RK |
2139 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
2140 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb PO |
2141 | } |
2142 | ||
2143 | host->mrq = NULL; | |
2144 | host->cmd = NULL; | |
2145 | host->data = NULL; | |
2146 | ||
f9134319 | 2147 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 2148 | sdhci_deactivate_led(host); |
2f730fec | 2149 | #endif |
d129bceb | 2150 | |
5f25a66f | 2151 | mmiowb(); |
d129bceb PO |
2152 | spin_unlock_irqrestore(&host->lock, flags); |
2153 | ||
2154 | mmc_request_done(host->mmc, mrq); | |
66fd8ad5 | 2155 | sdhci_runtime_pm_put(host); |
d129bceb PO |
2156 | } |
2157 | ||
2158 | static void sdhci_timeout_timer(unsigned long data) | |
2159 | { | |
2160 | struct sdhci_host *host; | |
2161 | unsigned long flags; | |
2162 | ||
2163 | host = (struct sdhci_host*)data; | |
2164 | ||
2165 | spin_lock_irqsave(&host->lock, flags); | |
2166 | ||
2167 | if (host->mrq) { | |
a3c76eb9 | 2168 | pr_err("%s: Timeout waiting for hardware " |
acf1da45 | 2169 | "interrupt.\n", mmc_hostname(host->mmc)); |
d129bceb PO |
2170 | sdhci_dumpregs(host); |
2171 | ||
2172 | if (host->data) { | |
17b0429d | 2173 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
2174 | sdhci_finish_data(host); |
2175 | } else { | |
2176 | if (host->cmd) | |
17b0429d | 2177 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 2178 | else |
17b0429d | 2179 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
2180 | |
2181 | tasklet_schedule(&host->finish_tasklet); | |
2182 | } | |
2183 | } | |
2184 | ||
5f25a66f | 2185 | mmiowb(); |
d129bceb PO |
2186 | spin_unlock_irqrestore(&host->lock, flags); |
2187 | } | |
2188 | ||
cf2b5eea AN |
2189 | static void sdhci_tuning_timer(unsigned long data) |
2190 | { | |
2191 | struct sdhci_host *host; | |
2192 | unsigned long flags; | |
2193 | ||
2194 | host = (struct sdhci_host *)data; | |
2195 | ||
2196 | spin_lock_irqsave(&host->lock, flags); | |
2197 | ||
2198 | host->flags |= SDHCI_NEEDS_RETUNING; | |
2199 | ||
2200 | spin_unlock_irqrestore(&host->lock, flags); | |
2201 | } | |
2202 | ||
d129bceb PO |
2203 | /*****************************************************************************\ |
2204 | * * | |
2205 | * Interrupt handling * | |
2206 | * * | |
2207 | \*****************************************************************************/ | |
2208 | ||
2209 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
2210 | { | |
2211 | BUG_ON(intmask == 0); | |
2212 | ||
2213 | if (!host->cmd) { | |
a3c76eb9 | 2214 | pr_err("%s: Got command interrupt 0x%08x even " |
b67ac3f3 PO |
2215 | "though no command operation was in progress.\n", |
2216 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2217 | sdhci_dumpregs(host); |
2218 | return; | |
2219 | } | |
2220 | ||
43b58b36 | 2221 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
2222 | host->cmd->error = -ETIMEDOUT; |
2223 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
2224 | SDHCI_INT_INDEX)) | |
2225 | host->cmd->error = -EILSEQ; | |
43b58b36 | 2226 | |
e809517f | 2227 | if (host->cmd->error) { |
d129bceb | 2228 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
2229 | return; |
2230 | } | |
2231 | ||
2232 | /* | |
2233 | * The host can send and interrupt when the busy state has | |
2234 | * ended, allowing us to wait without wasting CPU cycles. | |
2235 | * Unfortunately this is overloaded on the "data complete" | |
2236 | * interrupt, so we need to take some care when handling | |
2237 | * it. | |
2238 | * | |
2239 | * Note: The 1.0 specification is a bit ambiguous about this | |
2240 | * feature so there might be some problems with older | |
2241 | * controllers. | |
2242 | */ | |
2243 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
2244 | if (host->cmd->data) | |
2245 | DBG("Cannot wait for busy signal when also " | |
2246 | "doing a data transfer"); | |
f945405c | 2247 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) |
e809517f | 2248 | return; |
f945405c BD |
2249 | |
2250 | /* The controller does not support the end-of-busy IRQ, | |
2251 | * fall through and take the SDHCI_INT_RESPONSE */ | |
e809517f PO |
2252 | } |
2253 | ||
2254 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 2255 | sdhci_finish_command(host); |
d129bceb PO |
2256 | } |
2257 | ||
0957c333 | 2258 | #ifdef CONFIG_MMC_DEBUG |
6882a8c0 BD |
2259 | static void sdhci_show_adma_error(struct sdhci_host *host) |
2260 | { | |
2261 | const char *name = mmc_hostname(host->mmc); | |
2262 | u8 *desc = host->adma_desc; | |
2263 | __le32 *dma; | |
2264 | __le16 *len; | |
2265 | u8 attr; | |
2266 | ||
2267 | sdhci_dumpregs(host); | |
2268 | ||
2269 | while (true) { | |
2270 | dma = (__le32 *)(desc + 4); | |
2271 | len = (__le16 *)(desc + 2); | |
2272 | attr = *desc; | |
2273 | ||
2274 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
2275 | name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); | |
2276 | ||
2277 | desc += 8; | |
2278 | ||
2279 | if (attr & 2) | |
2280 | break; | |
2281 | } | |
2282 | } | |
2283 | #else | |
2284 | static void sdhci_show_adma_error(struct sdhci_host *host) { } | |
2285 | #endif | |
2286 | ||
d129bceb PO |
2287 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
2288 | { | |
069c9f14 | 2289 | u32 command; |
d129bceb PO |
2290 | BUG_ON(intmask == 0); |
2291 | ||
b513ea25 AN |
2292 | /* CMD19 generates _only_ Buffer Read Ready interrupt */ |
2293 | if (intmask & SDHCI_INT_DATA_AVAIL) { | |
069c9f14 G |
2294 | command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); |
2295 | if (command == MMC_SEND_TUNING_BLOCK || | |
2296 | command == MMC_SEND_TUNING_BLOCK_HS200) { | |
b513ea25 AN |
2297 | host->tuning_done = 1; |
2298 | wake_up(&host->buf_ready_int); | |
2299 | return; | |
2300 | } | |
2301 | } | |
2302 | ||
d129bceb PO |
2303 | if (!host->data) { |
2304 | /* | |
e809517f PO |
2305 | * The "data complete" interrupt is also used to |
2306 | * indicate that a busy state has ended. See comment | |
2307 | * above in sdhci_cmd_irq(). | |
d129bceb | 2308 | */ |
e809517f PO |
2309 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
2310 | if (intmask & SDHCI_INT_DATA_END) { | |
2311 | sdhci_finish_command(host); | |
2312 | return; | |
2313 | } | |
2314 | } | |
d129bceb | 2315 | |
a3c76eb9 | 2316 | pr_err("%s: Got data interrupt 0x%08x even " |
b67ac3f3 PO |
2317 | "though no data operation was in progress.\n", |
2318 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2319 | sdhci_dumpregs(host); |
2320 | ||
2321 | return; | |
2322 | } | |
2323 | ||
2324 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d | 2325 | host->data->error = -ETIMEDOUT; |
22113efd AL |
2326 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
2327 | host->data->error = -EILSEQ; | |
2328 | else if ((intmask & SDHCI_INT_DATA_CRC) && | |
2329 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) | |
2330 | != MMC_BUS_TEST_R) | |
17b0429d | 2331 | host->data->error = -EILSEQ; |
6882a8c0 | 2332 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
a3c76eb9 | 2333 | pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); |
6882a8c0 | 2334 | sdhci_show_adma_error(host); |
2134a922 | 2335 | host->data->error = -EIO; |
a4071fbb HZ |
2336 | if (host->ops->adma_workaround) |
2337 | host->ops->adma_workaround(host, intmask); | |
6882a8c0 | 2338 | } |
d129bceb | 2339 | |
17b0429d | 2340 | if (host->data->error) |
d129bceb PO |
2341 | sdhci_finish_data(host); |
2342 | else { | |
a406f5a3 | 2343 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
2344 | sdhci_transfer_pio(host); |
2345 | ||
6ba736a1 PO |
2346 | /* |
2347 | * We currently don't do anything fancy with DMA | |
2348 | * boundaries, but as we can't disable the feature | |
2349 | * we need to at least restart the transfer. | |
f6a03cbf MV |
2350 | * |
2351 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) | |
2352 | * should return a valid address to continue from, but as | |
2353 | * some controllers are faulty, don't trust them. | |
6ba736a1 | 2354 | */ |
f6a03cbf MV |
2355 | if (intmask & SDHCI_INT_DMA_END) { |
2356 | u32 dmastart, dmanow; | |
2357 | dmastart = sg_dma_address(host->data->sg); | |
2358 | dmanow = dmastart + host->data->bytes_xfered; | |
2359 | /* | |
2360 | * Force update to the next DMA block boundary. | |
2361 | */ | |
2362 | dmanow = (dmanow & | |
2363 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + | |
2364 | SDHCI_DEFAULT_BOUNDARY_SIZE; | |
2365 | host->data->bytes_xfered = dmanow - dmastart; | |
2366 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," | |
2367 | " next 0x%08x\n", | |
2368 | mmc_hostname(host->mmc), dmastart, | |
2369 | host->data->bytes_xfered, dmanow); | |
2370 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); | |
2371 | } | |
6ba736a1 | 2372 | |
e538fbe8 PO |
2373 | if (intmask & SDHCI_INT_DATA_END) { |
2374 | if (host->cmd) { | |
2375 | /* | |
2376 | * Data managed to finish before the | |
2377 | * command completed. Make sure we do | |
2378 | * things in the proper order. | |
2379 | */ | |
2380 | host->data_early = 1; | |
2381 | } else { | |
2382 | sdhci_finish_data(host); | |
2383 | } | |
2384 | } | |
d129bceb PO |
2385 | } |
2386 | } | |
2387 | ||
7d12e780 | 2388 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb | 2389 | { |
781e989c | 2390 | irqreturn_t result = IRQ_NONE; |
66fd8ad5 | 2391 | struct sdhci_host *host = dev_id; |
41005003 | 2392 | u32 intmask, mask, unexpected = 0; |
781e989c | 2393 | int max_loops = 16; |
d129bceb PO |
2394 | |
2395 | spin_lock(&host->lock); | |
2396 | ||
be138554 | 2397 | if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { |
66fd8ad5 | 2398 | spin_unlock(&host->lock); |
655bca76 | 2399 | return IRQ_NONE; |
66fd8ad5 AH |
2400 | } |
2401 | ||
4e4141a5 | 2402 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
62df67a5 | 2403 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
2404 | result = IRQ_NONE; |
2405 | goto out; | |
2406 | } | |
2407 | ||
41005003 RK |
2408 | do { |
2409 | /* Clear selected interrupts. */ | |
2410 | mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | | |
2411 | SDHCI_INT_BUS_POWER); | |
2412 | sdhci_writel(host, mask, SDHCI_INT_STATUS); | |
d129bceb | 2413 | |
41005003 RK |
2414 | DBG("*** %s got interrupt: 0x%08x\n", |
2415 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 2416 | |
41005003 RK |
2417 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
2418 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
2419 | SDHCI_CARD_PRESENT; | |
d129bceb | 2420 | |
41005003 RK |
2421 | /* |
2422 | * There is a observation on i.mx esdhc. INSERT | |
2423 | * bit will be immediately set again when it gets | |
2424 | * cleared, if a card is inserted. We have to mask | |
2425 | * the irq to prevent interrupt storm which will | |
2426 | * freeze the system. And the REMOVE gets the | |
2427 | * same situation. | |
2428 | * | |
2429 | * More testing are needed here to ensure it works | |
2430 | * for other platforms though. | |
2431 | */ | |
b537f94c RK |
2432 | host->ier &= ~(SDHCI_INT_CARD_INSERT | |
2433 | SDHCI_INT_CARD_REMOVE); | |
2434 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : | |
2435 | SDHCI_INT_CARD_INSERT; | |
2436 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
2437 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
41005003 RK |
2438 | |
2439 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | | |
2440 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | |
3560db8e RK |
2441 | |
2442 | host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | | |
2443 | SDHCI_INT_CARD_REMOVE); | |
2444 | result = IRQ_WAKE_THREAD; | |
41005003 | 2445 | } |
d129bceb | 2446 | |
41005003 RK |
2447 | if (intmask & SDHCI_INT_CMD_MASK) |
2448 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); | |
964f9ce2 | 2449 | |
41005003 RK |
2450 | if (intmask & SDHCI_INT_DATA_MASK) |
2451 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); | |
d129bceb | 2452 | |
41005003 RK |
2453 | if (intmask & SDHCI_INT_BUS_POWER) |
2454 | pr_err("%s: Card is consuming too much power!\n", | |
2455 | mmc_hostname(host->mmc)); | |
3192a28f | 2456 | |
781e989c RK |
2457 | if (intmask & SDHCI_INT_CARD_INT) { |
2458 | sdhci_enable_sdio_irq_nolock(host, false); | |
2459 | host->thread_isr |= SDHCI_INT_CARD_INT; | |
2460 | result = IRQ_WAKE_THREAD; | |
2461 | } | |
f75979b7 | 2462 | |
41005003 RK |
2463 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
2464 | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | | |
2465 | SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | | |
2466 | SDHCI_INT_CARD_INT); | |
f75979b7 | 2467 | |
41005003 RK |
2468 | if (intmask) { |
2469 | unexpected |= intmask; | |
2470 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); | |
2471 | } | |
d129bceb | 2472 | |
781e989c RK |
2473 | if (result == IRQ_NONE) |
2474 | result = IRQ_HANDLED; | |
d129bceb | 2475 | |
41005003 | 2476 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
41005003 | 2477 | } while (intmask && --max_loops); |
d129bceb PO |
2478 | out: |
2479 | spin_unlock(&host->lock); | |
2480 | ||
6379b237 AS |
2481 | if (unexpected) { |
2482 | pr_err("%s: Unexpected interrupt 0x%08x.\n", | |
2483 | mmc_hostname(host->mmc), unexpected); | |
2484 | sdhci_dumpregs(host); | |
2485 | } | |
f75979b7 | 2486 | |
d129bceb PO |
2487 | return result; |
2488 | } | |
2489 | ||
781e989c RK |
2490 | static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) |
2491 | { | |
2492 | struct sdhci_host *host = dev_id; | |
2493 | unsigned long flags; | |
2494 | u32 isr; | |
2495 | ||
2496 | spin_lock_irqsave(&host->lock, flags); | |
2497 | isr = host->thread_isr; | |
2498 | host->thread_isr = 0; | |
2499 | spin_unlock_irqrestore(&host->lock, flags); | |
2500 | ||
3560db8e RK |
2501 | if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
2502 | sdhci_card_event(host->mmc); | |
2503 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
2504 | } | |
2505 | ||
781e989c RK |
2506 | if (isr & SDHCI_INT_CARD_INT) { |
2507 | sdio_run_irqs(host->mmc); | |
2508 | ||
2509 | spin_lock_irqsave(&host->lock, flags); | |
2510 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) | |
2511 | sdhci_enable_sdio_irq_nolock(host, true); | |
2512 | spin_unlock_irqrestore(&host->lock, flags); | |
2513 | } | |
2514 | ||
2515 | return isr ? IRQ_HANDLED : IRQ_NONE; | |
2516 | } | |
2517 | ||
d129bceb PO |
2518 | /*****************************************************************************\ |
2519 | * * | |
2520 | * Suspend/resume * | |
2521 | * * | |
2522 | \*****************************************************************************/ | |
2523 | ||
2524 | #ifdef CONFIG_PM | |
ad080d79 KL |
2525 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
2526 | { | |
2527 | u8 val; | |
2528 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2529 | | SDHCI_WAKE_ON_INT; | |
2530 | ||
2531 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2532 | val |= mask ; | |
2533 | /* Avoid fake wake up */ | |
2534 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
2535 | val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); | |
2536 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2537 | } | |
2538 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); | |
2539 | ||
2540 | void sdhci_disable_irq_wakeups(struct sdhci_host *host) | |
2541 | { | |
2542 | u8 val; | |
2543 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2544 | | SDHCI_WAKE_ON_INT; | |
2545 | ||
2546 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2547 | val &= ~mask; | |
2548 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2549 | } | |
2550 | EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups); | |
d129bceb | 2551 | |
29495aa0 | 2552 | int sdhci_suspend_host(struct sdhci_host *host) |
d129bceb | 2553 | { |
7260cf5e AV |
2554 | sdhci_disable_card_detection(host); |
2555 | ||
cf2b5eea | 2556 | /* Disable tuning since we are suspending */ |
973905fe | 2557 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
c6ced0db | 2558 | del_timer_sync(&host->tuning_timer); |
cf2b5eea | 2559 | host->flags &= ~SDHCI_NEEDS_RETUNING; |
cf2b5eea AN |
2560 | } |
2561 | ||
ad080d79 | 2562 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
b537f94c RK |
2563 | host->ier = 0; |
2564 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); | |
2565 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
ad080d79 KL |
2566 | free_irq(host->irq, host); |
2567 | } else { | |
2568 | sdhci_enable_irq_wakeups(host); | |
2569 | enable_irq_wake(host->irq); | |
2570 | } | |
4ee14ec6 | 2571 | return 0; |
d129bceb PO |
2572 | } |
2573 | ||
b8c86fc5 | 2574 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 2575 | |
b8c86fc5 PO |
2576 | int sdhci_resume_host(struct sdhci_host *host) |
2577 | { | |
4ee14ec6 | 2578 | int ret = 0; |
d129bceb | 2579 | |
a13abc7b | 2580 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
2581 | if (host->ops->enable_dma) |
2582 | host->ops->enable_dma(host); | |
2583 | } | |
d129bceb | 2584 | |
ad080d79 | 2585 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
781e989c RK |
2586 | ret = request_threaded_irq(host->irq, sdhci_irq, |
2587 | sdhci_thread_irq, IRQF_SHARED, | |
2588 | mmc_hostname(host->mmc), host); | |
ad080d79 KL |
2589 | if (ret) |
2590 | return ret; | |
2591 | } else { | |
2592 | sdhci_disable_irq_wakeups(host); | |
2593 | disable_irq_wake(host->irq); | |
2594 | } | |
d129bceb | 2595 | |
6308d290 AH |
2596 | if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && |
2597 | (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { | |
2598 | /* Card keeps power but host controller does not */ | |
2599 | sdhci_init(host, 0); | |
2600 | host->pwr = 0; | |
2601 | host->clock = 0; | |
2602 | sdhci_do_set_ios(host, &host->mmc->ios); | |
2603 | } else { | |
2604 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); | |
2605 | mmiowb(); | |
2606 | } | |
b8c86fc5 | 2607 | |
7260cf5e AV |
2608 | sdhci_enable_card_detection(host); |
2609 | ||
cf2b5eea | 2610 | /* Set the re-tuning expiration flag */ |
973905fe | 2611 | if (host->flags & SDHCI_USING_RETUNING_TIMER) |
cf2b5eea AN |
2612 | host->flags |= SDHCI_NEEDS_RETUNING; |
2613 | ||
2f4cbb3d | 2614 | return ret; |
d129bceb PO |
2615 | } |
2616 | ||
b8c86fc5 | 2617 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
d129bceb PO |
2618 | #endif /* CONFIG_PM */ |
2619 | ||
66fd8ad5 AH |
2620 | #ifdef CONFIG_PM_RUNTIME |
2621 | ||
2622 | static int sdhci_runtime_pm_get(struct sdhci_host *host) | |
2623 | { | |
2624 | return pm_runtime_get_sync(host->mmc->parent); | |
2625 | } | |
2626 | ||
2627 | static int sdhci_runtime_pm_put(struct sdhci_host *host) | |
2628 | { | |
2629 | pm_runtime_mark_last_busy(host->mmc->parent); | |
2630 | return pm_runtime_put_autosuspend(host->mmc->parent); | |
2631 | } | |
2632 | ||
f0710a55 AH |
2633 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
2634 | { | |
2635 | if (host->runtime_suspended || host->bus_on) | |
2636 | return; | |
2637 | host->bus_on = true; | |
2638 | pm_runtime_get_noresume(host->mmc->parent); | |
2639 | } | |
2640 | ||
2641 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) | |
2642 | { | |
2643 | if (host->runtime_suspended || !host->bus_on) | |
2644 | return; | |
2645 | host->bus_on = false; | |
2646 | pm_runtime_put_noidle(host->mmc->parent); | |
2647 | } | |
2648 | ||
66fd8ad5 AH |
2649 | int sdhci_runtime_suspend_host(struct sdhci_host *host) |
2650 | { | |
2651 | unsigned long flags; | |
66fd8ad5 AH |
2652 | |
2653 | /* Disable tuning since we are suspending */ | |
973905fe | 2654 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
66fd8ad5 AH |
2655 | del_timer_sync(&host->tuning_timer); |
2656 | host->flags &= ~SDHCI_NEEDS_RETUNING; | |
2657 | } | |
2658 | ||
2659 | spin_lock_irqsave(&host->lock, flags); | |
b537f94c RK |
2660 | host->ier &= SDHCI_INT_CARD_INT; |
2661 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
2662 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
66fd8ad5 AH |
2663 | spin_unlock_irqrestore(&host->lock, flags); |
2664 | ||
781e989c | 2665 | synchronize_hardirq(host->irq); |
66fd8ad5 AH |
2666 | |
2667 | spin_lock_irqsave(&host->lock, flags); | |
2668 | host->runtime_suspended = true; | |
2669 | spin_unlock_irqrestore(&host->lock, flags); | |
2670 | ||
8a125bad | 2671 | return 0; |
66fd8ad5 AH |
2672 | } |
2673 | EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); | |
2674 | ||
2675 | int sdhci_runtime_resume_host(struct sdhci_host *host) | |
2676 | { | |
2677 | unsigned long flags; | |
8a125bad | 2678 | int host_flags = host->flags; |
66fd8ad5 AH |
2679 | |
2680 | if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
2681 | if (host->ops->enable_dma) | |
2682 | host->ops->enable_dma(host); | |
2683 | } | |
2684 | ||
2685 | sdhci_init(host, 0); | |
2686 | ||
2687 | /* Force clock and power re-program */ | |
2688 | host->pwr = 0; | |
2689 | host->clock = 0; | |
2690 | sdhci_do_set_ios(host, &host->mmc->ios); | |
2691 | ||
2692 | sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); | |
52983382 KL |
2693 | if ((host_flags & SDHCI_PV_ENABLED) && |
2694 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { | |
2695 | spin_lock_irqsave(&host->lock, flags); | |
2696 | sdhci_enable_preset_value(host, true); | |
2697 | spin_unlock_irqrestore(&host->lock, flags); | |
2698 | } | |
66fd8ad5 AH |
2699 | |
2700 | /* Set the re-tuning expiration flag */ | |
973905fe | 2701 | if (host->flags & SDHCI_USING_RETUNING_TIMER) |
66fd8ad5 AH |
2702 | host->flags |= SDHCI_NEEDS_RETUNING; |
2703 | ||
2704 | spin_lock_irqsave(&host->lock, flags); | |
2705 | ||
2706 | host->runtime_suspended = false; | |
2707 | ||
2708 | /* Enable SDIO IRQ */ | |
ef104333 | 2709 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
66fd8ad5 AH |
2710 | sdhci_enable_sdio_irq_nolock(host, true); |
2711 | ||
2712 | /* Enable Card Detection */ | |
2713 | sdhci_enable_card_detection(host); | |
2714 | ||
2715 | spin_unlock_irqrestore(&host->lock, flags); | |
2716 | ||
8a125bad | 2717 | return 0; |
66fd8ad5 AH |
2718 | } |
2719 | EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); | |
2720 | ||
2721 | #endif | |
2722 | ||
d129bceb PO |
2723 | /*****************************************************************************\ |
2724 | * * | |
b8c86fc5 | 2725 | * Device allocation/registration * |
d129bceb PO |
2726 | * * |
2727 | \*****************************************************************************/ | |
2728 | ||
b8c86fc5 PO |
2729 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
2730 | size_t priv_size) | |
d129bceb | 2731 | { |
d129bceb PO |
2732 | struct mmc_host *mmc; |
2733 | struct sdhci_host *host; | |
2734 | ||
b8c86fc5 | 2735 | WARN_ON(dev == NULL); |
d129bceb | 2736 | |
b8c86fc5 | 2737 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 2738 | if (!mmc) |
b8c86fc5 | 2739 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
2740 | |
2741 | host = mmc_priv(mmc); | |
2742 | host->mmc = mmc; | |
2743 | ||
b8c86fc5 PO |
2744 | return host; |
2745 | } | |
8a4da143 | 2746 | |
b8c86fc5 | 2747 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 2748 | |
b8c86fc5 PO |
2749 | int sdhci_add_host(struct sdhci_host *host) |
2750 | { | |
2751 | struct mmc_host *mmc; | |
bd6a8c30 | 2752 | u32 caps[2] = {0, 0}; |
f2119df6 AN |
2753 | u32 max_current_caps; |
2754 | unsigned int ocr_avail; | |
b8c86fc5 | 2755 | int ret; |
d129bceb | 2756 | |
b8c86fc5 PO |
2757 | WARN_ON(host == NULL); |
2758 | if (host == NULL) | |
2759 | return -EINVAL; | |
d129bceb | 2760 | |
b8c86fc5 | 2761 | mmc = host->mmc; |
d129bceb | 2762 | |
b8c86fc5 PO |
2763 | if (debug_quirks) |
2764 | host->quirks = debug_quirks; | |
66fd8ad5 AH |
2765 | if (debug_quirks2) |
2766 | host->quirks2 = debug_quirks2; | |
d129bceb | 2767 | |
03231f9b | 2768 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d96649ed | 2769 | |
4e4141a5 | 2770 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
2771 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
2772 | >> SDHCI_SPEC_VER_SHIFT; | |
85105c53 | 2773 | if (host->version > SDHCI_SPEC_300) { |
a3c76eb9 | 2774 | pr_err("%s: Unknown controller version (%d). " |
b69c9058 | 2775 | "You may experience problems.\n", mmc_hostname(mmc), |
2134a922 | 2776 | host->version); |
4a965505 PO |
2777 | } |
2778 | ||
f2119df6 | 2779 | caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
ccc92c23 | 2780 | sdhci_readl(host, SDHCI_CAPABILITIES); |
d129bceb | 2781 | |
bd6a8c30 PR |
2782 | if (host->version >= SDHCI_SPEC_300) |
2783 | caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? | |
2784 | host->caps1 : | |
2785 | sdhci_readl(host, SDHCI_CAPABILITIES_1); | |
f2119df6 | 2786 | |
b8c86fc5 | 2787 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
a13abc7b | 2788 | host->flags |= SDHCI_USE_SDMA; |
f2119df6 | 2789 | else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) |
a13abc7b | 2790 | DBG("Controller doesn't have SDMA capability\n"); |
67435274 | 2791 | else |
a13abc7b | 2792 | host->flags |= SDHCI_USE_SDMA; |
d129bceb | 2793 | |
b8c86fc5 | 2794 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
a13abc7b | 2795 | (host->flags & SDHCI_USE_SDMA)) { |
cee687ce | 2796 | DBG("Disabling DMA as it is marked broken\n"); |
a13abc7b | 2797 | host->flags &= ~SDHCI_USE_SDMA; |
7c168e3d FT |
2798 | } |
2799 | ||
f2119df6 AN |
2800 | if ((host->version >= SDHCI_SPEC_200) && |
2801 | (caps[0] & SDHCI_CAN_DO_ADMA2)) | |
a13abc7b | 2802 | host->flags |= SDHCI_USE_ADMA; |
2134a922 PO |
2803 | |
2804 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
2805 | (host->flags & SDHCI_USE_ADMA)) { | |
2806 | DBG("Disabling ADMA as it is marked broken\n"); | |
2807 | host->flags &= ~SDHCI_USE_ADMA; | |
2808 | } | |
2809 | ||
a13abc7b | 2810 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
2811 | if (host->ops->enable_dma) { |
2812 | if (host->ops->enable_dma(host)) { | |
a3c76eb9 | 2813 | pr_warning("%s: No suitable DMA " |
b8c86fc5 PO |
2814 | "available. Falling back to PIO.\n", |
2815 | mmc_hostname(mmc)); | |
a13abc7b RR |
2816 | host->flags &= |
2817 | ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); | |
b8c86fc5 | 2818 | } |
d129bceb PO |
2819 | } |
2820 | } | |
2821 | ||
2134a922 PO |
2822 | if (host->flags & SDHCI_USE_ADMA) { |
2823 | /* | |
2824 | * We need to allocate descriptors for all sg entries | |
2825 | * (128) and potentially one alignment transfer for | |
2826 | * each of those entries. | |
2827 | */ | |
d1e49f77 RK |
2828 | host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc), |
2829 | ADMA_SIZE, &host->adma_addr, | |
2830 | GFP_KERNEL); | |
2134a922 PO |
2831 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); |
2832 | if (!host->adma_desc || !host->align_buffer) { | |
d1e49f77 RK |
2833 | dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, |
2834 | host->adma_desc, host->adma_addr); | |
2134a922 | 2835 | kfree(host->align_buffer); |
a3c76eb9 | 2836 | pr_warning("%s: Unable to allocate ADMA " |
2134a922 PO |
2837 | "buffers. Falling back to standard DMA.\n", |
2838 | mmc_hostname(mmc)); | |
2839 | host->flags &= ~SDHCI_USE_ADMA; | |
d1e49f77 RK |
2840 | host->adma_desc = NULL; |
2841 | host->align_buffer = NULL; | |
2842 | } else if (host->adma_addr & 3) { | |
2843 | pr_warning("%s: unable to allocate aligned ADMA descriptor\n", | |
2844 | mmc_hostname(mmc)); | |
2845 | host->flags &= ~SDHCI_USE_ADMA; | |
2846 | dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, | |
2847 | host->adma_desc, host->adma_addr); | |
2848 | kfree(host->align_buffer); | |
2849 | host->adma_desc = NULL; | |
2850 | host->align_buffer = NULL; | |
2134a922 PO |
2851 | } |
2852 | } | |
2853 | ||
7659150c PO |
2854 | /* |
2855 | * If we use DMA, then it's up to the caller to set the DMA | |
2856 | * mask, but PIO does not need the hw shim so we set a new | |
2857 | * mask here in that case. | |
2858 | */ | |
a13abc7b | 2859 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
7659150c PO |
2860 | host->dma_mask = DMA_BIT_MASK(64); |
2861 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; | |
2862 | } | |
d129bceb | 2863 | |
c4687d5f | 2864 | if (host->version >= SDHCI_SPEC_300) |
f2119df6 | 2865 | host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) |
c4687d5f ZG |
2866 | >> SDHCI_CLOCK_BASE_SHIFT; |
2867 | else | |
f2119df6 | 2868 | host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) |
c4687d5f ZG |
2869 | >> SDHCI_CLOCK_BASE_SHIFT; |
2870 | ||
4240ff0a | 2871 | host->max_clk *= 1000000; |
f27f47ef AV |
2872 | if (host->max_clk == 0 || host->quirks & |
2873 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { | |
4240ff0a | 2874 | if (!host->ops->get_max_clock) { |
a3c76eb9 | 2875 | pr_err("%s: Hardware doesn't specify base clock " |
4240ff0a BD |
2876 | "frequency.\n", mmc_hostname(mmc)); |
2877 | return -ENODEV; | |
2878 | } | |
2879 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 2880 | } |
d129bceb | 2881 | |
c3ed3877 AN |
2882 | /* |
2883 | * In case of Host Controller v3.00, find out whether clock | |
2884 | * multiplier is supported. | |
2885 | */ | |
2886 | host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> | |
2887 | SDHCI_CLOCK_MUL_SHIFT; | |
2888 | ||
2889 | /* | |
2890 | * In case the value in Clock Multiplier is 0, then programmable | |
2891 | * clock mode is not supported, otherwise the actual clock | |
2892 | * multiplier is one more than the value of Clock Multiplier | |
2893 | * in the Capabilities Register. | |
2894 | */ | |
2895 | if (host->clk_mul) | |
2896 | host->clk_mul += 1; | |
2897 | ||
d129bceb PO |
2898 | /* |
2899 | * Set host parameters. | |
2900 | */ | |
2901 | mmc->ops = &sdhci_ops; | |
c3ed3877 | 2902 | mmc->f_max = host->max_clk; |
ce5f036b | 2903 | if (host->ops->get_min_clock) |
a9e58f25 | 2904 | mmc->f_min = host->ops->get_min_clock(host); |
c3ed3877 AN |
2905 | else if (host->version >= SDHCI_SPEC_300) { |
2906 | if (host->clk_mul) { | |
2907 | mmc->f_min = (host->max_clk * host->clk_mul) / 1024; | |
2908 | mmc->f_max = host->max_clk * host->clk_mul; | |
2909 | } else | |
2910 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; | |
2911 | } else | |
0397526d | 2912 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
15ec4461 | 2913 | |
272308ca AS |
2914 | host->timeout_clk = |
2915 | (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
2916 | if (host->timeout_clk == 0) { | |
2917 | if (host->ops->get_timeout_clock) { | |
2918 | host->timeout_clk = host->ops->get_timeout_clock(host); | |
2919 | } else if (!(host->quirks & | |
2920 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { | |
a3c76eb9 | 2921 | pr_err("%s: Hardware doesn't specify timeout clock " |
272308ca AS |
2922 | "frequency.\n", mmc_hostname(mmc)); |
2923 | return -ENODEV; | |
2924 | } | |
2925 | } | |
2926 | if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) | |
2927 | host->timeout_clk *= 1000; | |
2928 | ||
2929 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) | |
65be3fef | 2930 | host->timeout_clk = mmc->f_max / 1000; |
272308ca | 2931 | |
68eb80e0 | 2932 | mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; |
58d1246d | 2933 | |
e89d456f | 2934 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; |
781e989c | 2935 | mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; |
e89d456f AW |
2936 | |
2937 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) | |
2938 | host->flags |= SDHCI_AUTO_CMD12; | |
5fe23c7f | 2939 | |
8edf6371 | 2940 | /* Auto-CMD23 stuff only works in ADMA or PIO. */ |
4f3d3e9b | 2941 | if ((host->version >= SDHCI_SPEC_300) && |
8edf6371 | 2942 | ((host->flags & SDHCI_USE_ADMA) || |
4f3d3e9b | 2943 | !(host->flags & SDHCI_USE_SDMA))) { |
8edf6371 AW |
2944 | host->flags |= SDHCI_AUTO_CMD23; |
2945 | DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); | |
2946 | } else { | |
2947 | DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); | |
2948 | } | |
2949 | ||
15ec4461 PR |
2950 | /* |
2951 | * A controller may support 8-bit width, but the board itself | |
2952 | * might not have the pins brought out. Boards that support | |
2953 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in | |
2954 | * their platform code before calling sdhci_add_host(), and we | |
2955 | * won't assume 8-bit width for hosts without that CAP. | |
2956 | */ | |
5fe23c7f | 2957 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
15ec4461 | 2958 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
d129bceb | 2959 | |
63ef5d8c JH |
2960 | if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) |
2961 | mmc->caps &= ~MMC_CAP_CMD23; | |
2962 | ||
f2119df6 | 2963 | if (caps[0] & SDHCI_CAN_DO_HISPD) |
a29e7e18 | 2964 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
cd9277c0 | 2965 | |
176d1ed4 | 2966 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
eb6d5ae1 | 2967 | !(host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
68d1fb7e AV |
2968 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
2969 | ||
3a48edc4 TK |
2970 | /* If there are external regulators, get them */ |
2971 | if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER) | |
2972 | return -EPROBE_DEFER; | |
2973 | ||
6231f3de | 2974 | /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ |
3a48edc4 TK |
2975 | if (!IS_ERR(mmc->supply.vqmmc)) { |
2976 | ret = regulator_enable(mmc->supply.vqmmc); | |
2977 | if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, | |
2978 | 1950000)) | |
8363c374 KL |
2979 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | |
2980 | SDHCI_SUPPORT_SDR50 | | |
2981 | SDHCI_SUPPORT_DDR50); | |
a3361aba CB |
2982 | if (ret) { |
2983 | pr_warn("%s: Failed to enable vqmmc regulator: %d\n", | |
2984 | mmc_hostname(mmc), ret); | |
3a48edc4 | 2985 | mmc->supply.vqmmc = NULL; |
a3361aba | 2986 | } |
8363c374 | 2987 | } |
6231f3de | 2988 | |
6a66180a DD |
2989 | if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) |
2990 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
2991 | SDHCI_SUPPORT_DDR50); | |
2992 | ||
4188bba0 AC |
2993 | /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ |
2994 | if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
2995 | SDHCI_SUPPORT_DDR50)) | |
f2119df6 AN |
2996 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
2997 | ||
2998 | /* SDR104 supports also implies SDR50 support */ | |
156e14b1 | 2999 | if (caps[1] & SDHCI_SUPPORT_SDR104) { |
f2119df6 | 3000 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; |
156e14b1 GC |
3001 | /* SD3.0: SDR104 is supported so (for eMMC) the caps2 |
3002 | * field can be promoted to support HS200. | |
3003 | */ | |
13868bf2 DC |
3004 | if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) |
3005 | mmc->caps2 |= MMC_CAP2_HS200; | |
156e14b1 | 3006 | } else if (caps[1] & SDHCI_SUPPORT_SDR50) |
f2119df6 AN |
3007 | mmc->caps |= MMC_CAP_UHS_SDR50; |
3008 | ||
9107ebbf MC |
3009 | if ((caps[1] & SDHCI_SUPPORT_DDR50) && |
3010 | !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) | |
f2119df6 AN |
3011 | mmc->caps |= MMC_CAP_UHS_DDR50; |
3012 | ||
069c9f14 | 3013 | /* Does the host need tuning for SDR50? */ |
b513ea25 AN |
3014 | if (caps[1] & SDHCI_USE_SDR50_TUNING) |
3015 | host->flags |= SDHCI_SDR50_NEEDS_TUNING; | |
3016 | ||
156e14b1 | 3017 | /* Does the host need tuning for SDR104 / HS200? */ |
069c9f14 | 3018 | if (mmc->caps2 & MMC_CAP2_HS200) |
156e14b1 | 3019 | host->flags |= SDHCI_SDR104_NEEDS_TUNING; |
069c9f14 | 3020 | |
d6d50a15 AN |
3021 | /* Driver Type(s) (A, C, D) supported by the host */ |
3022 | if (caps[1] & SDHCI_DRIVER_TYPE_A) | |
3023 | mmc->caps |= MMC_CAP_DRIVER_TYPE_A; | |
3024 | if (caps[1] & SDHCI_DRIVER_TYPE_C) | |
3025 | mmc->caps |= MMC_CAP_DRIVER_TYPE_C; | |
3026 | if (caps[1] & SDHCI_DRIVER_TYPE_D) | |
3027 | mmc->caps |= MMC_CAP_DRIVER_TYPE_D; | |
3028 | ||
cf2b5eea AN |
3029 | /* Initial value for re-tuning timer count */ |
3030 | host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> | |
3031 | SDHCI_RETUNING_TIMER_COUNT_SHIFT; | |
3032 | ||
3033 | /* | |
3034 | * In case Re-tuning Timer is not disabled, the actual value of | |
3035 | * re-tuning timer will be 2 ^ (n - 1). | |
3036 | */ | |
3037 | if (host->tuning_count) | |
3038 | host->tuning_count = 1 << (host->tuning_count - 1); | |
3039 | ||
3040 | /* Re-tuning mode supported by the Host Controller */ | |
3041 | host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> | |
3042 | SDHCI_RETUNING_MODE_SHIFT; | |
3043 | ||
8f230f45 | 3044 | ocr_avail = 0; |
bad37e1a | 3045 | |
f2119df6 AN |
3046 | /* |
3047 | * According to SD Host Controller spec v3.00, if the Host System | |
3048 | * can afford more than 150mA, Host Driver should set XPC to 1. Also | |
3049 | * the value is meaningful only if Voltage Support in the Capabilities | |
3050 | * register is set. The actual current value is 4 times the register | |
3051 | * value. | |
3052 | */ | |
3053 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); | |
3a48edc4 TK |
3054 | if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { |
3055 | u32 curr = regulator_get_current_limit(mmc->supply.vmmc); | |
bad37e1a PR |
3056 | if (curr > 0) { |
3057 | ||
3058 | /* convert to SDHCI_MAX_CURRENT format */ | |
3059 | curr = curr/1000; /* convert to mA */ | |
3060 | curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; | |
3061 | ||
3062 | curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); | |
3063 | max_current_caps = | |
3064 | (curr << SDHCI_MAX_CURRENT_330_SHIFT) | | |
3065 | (curr << SDHCI_MAX_CURRENT_300_SHIFT) | | |
3066 | (curr << SDHCI_MAX_CURRENT_180_SHIFT); | |
3067 | } | |
3068 | } | |
f2119df6 AN |
3069 | |
3070 | if (caps[0] & SDHCI_CAN_VDD_330) { | |
8f230f45 | 3071 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
f2119df6 | 3072 | |
55c4665e | 3073 | mmc->max_current_330 = ((max_current_caps & |
f2119df6 AN |
3074 | SDHCI_MAX_CURRENT_330_MASK) >> |
3075 | SDHCI_MAX_CURRENT_330_SHIFT) * | |
3076 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3077 | } |
3078 | if (caps[0] & SDHCI_CAN_VDD_300) { | |
8f230f45 | 3079 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
f2119df6 | 3080 | |
55c4665e | 3081 | mmc->max_current_300 = ((max_current_caps & |
f2119df6 AN |
3082 | SDHCI_MAX_CURRENT_300_MASK) >> |
3083 | SDHCI_MAX_CURRENT_300_SHIFT) * | |
3084 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3085 | } |
3086 | if (caps[0] & SDHCI_CAN_VDD_180) { | |
8f230f45 TI |
3087 | ocr_avail |= MMC_VDD_165_195; |
3088 | ||
55c4665e | 3089 | mmc->max_current_180 = ((max_current_caps & |
f2119df6 AN |
3090 | SDHCI_MAX_CURRENT_180_MASK) >> |
3091 | SDHCI_MAX_CURRENT_180_SHIFT) * | |
3092 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3093 | } |
3094 | ||
3a48edc4 TK |
3095 | if (mmc->ocr_avail) |
3096 | ocr_avail &= mmc->ocr_avail; | |
3097 | ||
c0b887b6 | 3098 | if (host->ocr_mask) |
3a48edc4 | 3099 | ocr_avail &= host->ocr_mask; |
c0b887b6 | 3100 | |
8f230f45 TI |
3101 | mmc->ocr_avail = ocr_avail; |
3102 | mmc->ocr_avail_sdio = ocr_avail; | |
3103 | if (host->ocr_avail_sdio) | |
3104 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; | |
3105 | mmc->ocr_avail_sd = ocr_avail; | |
3106 | if (host->ocr_avail_sd) | |
3107 | mmc->ocr_avail_sd &= host->ocr_avail_sd; | |
3108 | else /* normal SD controllers don't support 1.8V */ | |
3109 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; | |
3110 | mmc->ocr_avail_mmc = ocr_avail; | |
3111 | if (host->ocr_avail_mmc) | |
3112 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; | |
146ad66e PO |
3113 | |
3114 | if (mmc->ocr_avail == 0) { | |
a3c76eb9 | 3115 | pr_err("%s: Hardware doesn't report any " |
b69c9058 | 3116 | "support voltages.\n", mmc_hostname(mmc)); |
b8c86fc5 | 3117 | return -ENODEV; |
146ad66e PO |
3118 | } |
3119 | ||
d129bceb PO |
3120 | spin_lock_init(&host->lock); |
3121 | ||
3122 | /* | |
2134a922 PO |
3123 | * Maximum number of segments. Depends on if the hardware |
3124 | * can do scatter/gather or not. | |
d129bceb | 3125 | */ |
2134a922 | 3126 | if (host->flags & SDHCI_USE_ADMA) |
a36274e0 | 3127 | mmc->max_segs = 128; |
a13abc7b | 3128 | else if (host->flags & SDHCI_USE_SDMA) |
a36274e0 | 3129 | mmc->max_segs = 1; |
2134a922 | 3130 | else /* PIO */ |
a36274e0 | 3131 | mmc->max_segs = 128; |
d129bceb PO |
3132 | |
3133 | /* | |
bab76961 | 3134 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 3135 | * size (512KiB). |
d129bceb | 3136 | */ |
55db890a | 3137 | mmc->max_req_size = 524288; |
d129bceb PO |
3138 | |
3139 | /* | |
3140 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
3141 | * of bytes. When doing hardware scatter/gather, each entry cannot |
3142 | * be larger than 64 KiB though. | |
d129bceb | 3143 | */ |
30652aa3 OJ |
3144 | if (host->flags & SDHCI_USE_ADMA) { |
3145 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) | |
3146 | mmc->max_seg_size = 65535; | |
3147 | else | |
3148 | mmc->max_seg_size = 65536; | |
3149 | } else { | |
2134a922 | 3150 | mmc->max_seg_size = mmc->max_req_size; |
30652aa3 | 3151 | } |
d129bceb | 3152 | |
fe4a3c7a PO |
3153 | /* |
3154 | * Maximum block size. This varies from controller to controller and | |
3155 | * is specified in the capabilities register. | |
3156 | */ | |
0633f654 AV |
3157 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
3158 | mmc->max_blk_size = 2; | |
3159 | } else { | |
f2119df6 | 3160 | mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> |
0633f654 AV |
3161 | SDHCI_MAX_BLOCK_SHIFT; |
3162 | if (mmc->max_blk_size >= 3) { | |
a3c76eb9 | 3163 | pr_warning("%s: Invalid maximum block size, " |
0633f654 AV |
3164 | "assuming 512 bytes\n", mmc_hostname(mmc)); |
3165 | mmc->max_blk_size = 0; | |
3166 | } | |
3167 | } | |
3168 | ||
3169 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 3170 | |
55db890a PO |
3171 | /* |
3172 | * Maximum block count. | |
3173 | */ | |
1388eefd | 3174 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
55db890a | 3175 | |
d129bceb PO |
3176 | /* |
3177 | * Init tasklets. | |
3178 | */ | |
d129bceb PO |
3179 | tasklet_init(&host->finish_tasklet, |
3180 | sdhci_tasklet_finish, (unsigned long)host); | |
3181 | ||
e4cad1b5 | 3182 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 3183 | |
cf2b5eea | 3184 | if (host->version >= SDHCI_SPEC_300) { |
b513ea25 AN |
3185 | init_waitqueue_head(&host->buf_ready_int); |
3186 | ||
cf2b5eea AN |
3187 | /* Initialize re-tuning timer */ |
3188 | init_timer(&host->tuning_timer); | |
3189 | host->tuning_timer.data = (unsigned long)host; | |
3190 | host->tuning_timer.function = sdhci_tuning_timer; | |
3191 | } | |
3192 | ||
2af502ca SG |
3193 | sdhci_init(host, 0); |
3194 | ||
781e989c RK |
3195 | ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, |
3196 | IRQF_SHARED, mmc_hostname(mmc), host); | |
0fc81ee3 MB |
3197 | if (ret) { |
3198 | pr_err("%s: Failed to request IRQ %d: %d\n", | |
3199 | mmc_hostname(mmc), host->irq, ret); | |
8ef1a143 | 3200 | goto untasklet; |
0fc81ee3 | 3201 | } |
d129bceb | 3202 | |
d129bceb PO |
3203 | #ifdef CONFIG_MMC_DEBUG |
3204 | sdhci_dumpregs(host); | |
3205 | #endif | |
3206 | ||
f9134319 | 3207 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
3208 | snprintf(host->led_name, sizeof(host->led_name), |
3209 | "%s::", mmc_hostname(mmc)); | |
3210 | host->led.name = host->led_name; | |
2f730fec PO |
3211 | host->led.brightness = LED_OFF; |
3212 | host->led.default_trigger = mmc_hostname(mmc); | |
3213 | host->led.brightness_set = sdhci_led_control; | |
3214 | ||
b8c86fc5 | 3215 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
0fc81ee3 MB |
3216 | if (ret) { |
3217 | pr_err("%s: Failed to register LED device: %d\n", | |
3218 | mmc_hostname(mmc), ret); | |
2f730fec | 3219 | goto reset; |
0fc81ee3 | 3220 | } |
2f730fec PO |
3221 | #endif |
3222 | ||
5f25a66f PO |
3223 | mmiowb(); |
3224 | ||
d129bceb PO |
3225 | mmc_add_host(mmc); |
3226 | ||
a3c76eb9 | 3227 | pr_info("%s: SDHCI controller on %s [%s] using %s\n", |
d1b26863 | 3228 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
a13abc7b RR |
3229 | (host->flags & SDHCI_USE_ADMA) ? "ADMA" : |
3230 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); | |
d129bceb | 3231 | |
7260cf5e AV |
3232 | sdhci_enable_card_detection(host); |
3233 | ||
d129bceb PO |
3234 | return 0; |
3235 | ||
f9134319 | 3236 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec | 3237 | reset: |
03231f9b | 3238 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
b537f94c RK |
3239 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3240 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
2f730fec PO |
3241 | free_irq(host->irq, host); |
3242 | #endif | |
8ef1a143 | 3243 | untasklet: |
d129bceb | 3244 | tasklet_kill(&host->finish_tasklet); |
d129bceb PO |
3245 | |
3246 | return ret; | |
3247 | } | |
3248 | ||
b8c86fc5 | 3249 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 3250 | |
1e72859e | 3251 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 3252 | { |
3a48edc4 | 3253 | struct mmc_host *mmc = host->mmc; |
1e72859e PO |
3254 | unsigned long flags; |
3255 | ||
3256 | if (dead) { | |
3257 | spin_lock_irqsave(&host->lock, flags); | |
3258 | ||
3259 | host->flags |= SDHCI_DEVICE_DEAD; | |
3260 | ||
3261 | if (host->mrq) { | |
a3c76eb9 | 3262 | pr_err("%s: Controller removed during " |
1e72859e PO |
3263 | " transfer!\n", mmc_hostname(host->mmc)); |
3264 | ||
3265 | host->mrq->cmd->error = -ENOMEDIUM; | |
3266 | tasklet_schedule(&host->finish_tasklet); | |
3267 | } | |
3268 | ||
3269 | spin_unlock_irqrestore(&host->lock, flags); | |
3270 | } | |
3271 | ||
7260cf5e AV |
3272 | sdhci_disable_card_detection(host); |
3273 | ||
b8c86fc5 | 3274 | mmc_remove_host(host->mmc); |
d129bceb | 3275 | |
f9134319 | 3276 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
3277 | led_classdev_unregister(&host->led); |
3278 | #endif | |
3279 | ||
1e72859e | 3280 | if (!dead) |
03231f9b | 3281 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d129bceb | 3282 | |
b537f94c RK |
3283 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3284 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
d129bceb PO |
3285 | free_irq(host->irq, host); |
3286 | ||
3287 | del_timer_sync(&host->timer); | |
3288 | ||
d129bceb | 3289 | tasklet_kill(&host->finish_tasklet); |
2134a922 | 3290 | |
3a48edc4 TK |
3291 | if (!IS_ERR(mmc->supply.vmmc)) |
3292 | regulator_disable(mmc->supply.vmmc); | |
9bea3c85 | 3293 | |
3a48edc4 TK |
3294 | if (!IS_ERR(mmc->supply.vqmmc)) |
3295 | regulator_disable(mmc->supply.vqmmc); | |
6231f3de | 3296 | |
d1e49f77 RK |
3297 | if (host->adma_desc) |
3298 | dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, | |
3299 | host->adma_desc, host->adma_addr); | |
2134a922 PO |
3300 | kfree(host->align_buffer); |
3301 | ||
3302 | host->adma_desc = NULL; | |
3303 | host->align_buffer = NULL; | |
d129bceb PO |
3304 | } |
3305 | ||
b8c86fc5 | 3306 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 3307 | |
b8c86fc5 | 3308 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 3309 | { |
b8c86fc5 | 3310 | mmc_free_host(host->mmc); |
d129bceb PO |
3311 | } |
3312 | ||
b8c86fc5 | 3313 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
3314 | |
3315 | /*****************************************************************************\ | |
3316 | * * | |
3317 | * Driver init/exit * | |
3318 | * * | |
3319 | \*****************************************************************************/ | |
3320 | ||
3321 | static int __init sdhci_drv_init(void) | |
3322 | { | |
a3c76eb9 | 3323 | pr_info(DRIVER_NAME |
52fbf9c9 | 3324 | ": Secure Digital Host Controller Interface driver\n"); |
a3c76eb9 | 3325 | pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
d129bceb | 3326 | |
b8c86fc5 | 3327 | return 0; |
d129bceb PO |
3328 | } |
3329 | ||
3330 | static void __exit sdhci_drv_exit(void) | |
3331 | { | |
d129bceb PO |
3332 | } |
3333 | ||
3334 | module_init(sdhci_drv_init); | |
3335 | module_exit(sdhci_drv_exit); | |
3336 | ||
df673b22 | 3337 | module_param(debug_quirks, uint, 0444); |
66fd8ad5 | 3338 | module_param(debug_quirks2, uint, 0444); |
67435274 | 3339 | |
32710e8f | 3340 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 3341 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 3342 | MODULE_LICENSE("GPL"); |
67435274 | 3343 | |
df673b22 | 3344 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |
66fd8ad5 | 3345 | MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); |