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mmc: host: use of_property_read_bool()
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
348487cb
HC		 56static int sdhci_pre_dma_transfer(struct sdhci_host *host,
57 struct mmc_data *data,
58 struct sdhci_host_next *next);
04e079cf 59static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 60
162d6f98 61#ifdef CONFIG_PM
66fd8ad5
AH		 62static int sdhci_runtime_pm_get(struct sdhci_host *host);
63static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 64static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
65static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 66#else
67static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
68{
69 return 0;
70}
71static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
72{
73 return 0;
74}
f0710a55
AH		 75static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
76{
77}
78static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
79{
80}
66fd8ad5
AH		 81#endif
82
d129bceb
PO		 83static void sdhci_dumpregs(struct sdhci_host *host)
84{
a3c76eb9 85 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 86 mmc_hostname(host->mmc));
d129bceb 87
a3c76eb9 88 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readl(host, SDHCI_DMA_ADDRESS),
90 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readw(host, SDHCI_BLOCK_SIZE),
93 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readl(host, SDHCI_ARGUMENT),
96 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readl(host, SDHCI_PRESENT_STATE),
99 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 100 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readb(host, SDHCI_POWER_CONTROL),
102 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 104 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
105 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 107 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
108 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 109 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 110 sdhci_readl(host, SDHCI_INT_ENABLE),
111 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 112 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 113 sdhci_readw(host, SDHCI_ACMD12_ERR),
114 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 115 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 116 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 117 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 118 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 119 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 120 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 121 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 122 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 123
e57a5f61
AH		 124 if (host->flags & SDHCI_USE_ADMA) {
125 if (host->flags & SDHCI_USE_64_BIT_DMA)
126 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
127 readl(host->ioaddr + SDHCI_ADMA_ERROR),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 else
131 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
132 readl(host->ioaddr + SDHCI_ADMA_ERROR),
133 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
134 }
be3f4ae0 135
a3c76eb9 136 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 137}
138
139/*****************************************************************************\
140 * *
141 * Low level functions *
142 * *
143\*****************************************************************************/
144
7260cf5e
AV		 145static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
146{
5b4f1f6c 147 u32 present;
7260cf5e 148
c79396c1 149 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 150 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 151 return;
152
5b4f1f6c
RK		 153 if (enable) {
154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT;
d25928d1 156
5b4f1f6c
RK		 157 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
158 SDHCI_INT_CARD_INSERT;
159 } else {
160 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
161 }
b537f94c
RK		 162
163 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
164 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 165}
166
167static void sdhci_enable_card_detection(struct sdhci_host *host)
168{
169 sdhci_set_card_detection(host, true);
170}
171
172static void sdhci_disable_card_detection(struct sdhci_host *host)
173{
174 sdhci_set_card_detection(host, false);
175}
176
03231f9b 177void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 178{
e16514d8 179 unsigned long timeout;
393c1a34 180
4e4141a5 181 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 182
f0710a55 183 if (mask & SDHCI_RESET_ALL) {
d129bceb 184 host->clock = 0;
f0710a55
AH		 185 /* Reset-all turns off SD Bus Power */
186 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
187 sdhci_runtime_pm_bus_off(host);
188 }
d129bceb 189
e16514d8
PO		 190 /* Wait max 100 ms */
191 timeout = 100;
192
193 /* hw clears the bit when it's done */
4e4141a5 194 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 195 if (timeout == 0) {
a3c76eb9 196 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 197 mmc_hostname(host->mmc), (int)mask);
198 sdhci_dumpregs(host);
199 return;
200 }
201 timeout--;
202 mdelay(1);
d129bceb 203 }
03231f9b
RK		 204}
205EXPORT_SYMBOL_GPL(sdhci_reset);
206
207static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
208{
209 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
135b0a28 210 if (!sdhci_do_get_cd(host))
03231f9b
RK		 211 return;
212 }
063a9dbb 213
03231f9b 214 host->ops->reset(host, mask);
393c1a34 215
da91a8f9
RK		 216 if (mask & SDHCI_RESET_ALL) {
217 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
218 if (host->ops->enable_dma)
219 host->ops->enable_dma(host);
220 }
221
222 /* Resetting the controller clears many */
223 host->preset_enabled = false;
3abc1e80 224 }
d129bceb
PO		 225}
226
2f4cbb3d
NP		 227static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
228
229static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 230{
2f4cbb3d 231 if (soft)
03231f9b 232 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 233 else
03231f9b 234 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 235
b537f94c
RK		 236 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
237 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
238 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
239 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
240 SDHCI_INT_RESPONSE;
241
242 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
243 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 244
245 if (soft) {
246 /* force clock reconfiguration */
247 host->clock = 0;
248 sdhci_set_ios(host->mmc, &host->mmc->ios);
249 }
7260cf5e 250}
d129bceb 251
7260cf5e
AV		 252static void sdhci_reinit(struct sdhci_host *host)
253{
2f4cbb3d 254 sdhci_init(host, 0);
7260cf5e 255 sdhci_enable_card_detection(host);
d129bceb
PO		 256}
257
258static void sdhci_activate_led(struct sdhci_host *host)
259{
260 u8 ctrl;
261
4e4141a5 262 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 263 ctrl |= SDHCI_CTRL_LED;
4e4141a5 264 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 265}
266
267static void sdhci_deactivate_led(struct sdhci_host *host)
268{
269 u8 ctrl;
270
4e4141a5 271 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 272 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 273 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 274}
275
f9134319 276#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 277static void sdhci_led_control(struct led_classdev *led,
278 enum led_brightness brightness)
279{
280 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
281 unsigned long flags;
282
283 spin_lock_irqsave(&host->lock, flags);
284
66fd8ad5
AH		 285 if (host->runtime_suspended)
286 goto out;
287
2f730fec
PO		 288 if (brightness == LED_OFF)
289 sdhci_deactivate_led(host);
290 else
291 sdhci_activate_led(host);
66fd8ad5 292out:
2f730fec
PO		 293 spin_unlock_irqrestore(&host->lock, flags);
294}
295#endif
296
d129bceb
PO		 297/*****************************************************************************\
298 * *
299 * Core functions *
300 * *
301\*****************************************************************************/
302
a406f5a3 303static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 304{
7659150c
PO		 305 unsigned long flags;
306 size_t blksize, len, chunk;
7244b85b 307 u32 uninitialized_var(scratch);
7659150c 308 u8 *buf;
d129bceb 309
a406f5a3 310 DBG("PIO reading\n");
d129bceb 311
a406f5a3 312 blksize = host->data->blksz;
7659150c 313 chunk = 0;
d129bceb 314
7659150c 315 local_irq_save(flags);
d129bceb 316
a406f5a3 317 while (blksize) {
bf3a35ac 318 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 319
7659150c 320 len = min(host->sg_miter.length, blksize);
d129bceb 321
7659150c
PO		 322 blksize -= len;
323 host->sg_miter.consumed = len;
14d836e7 324
7659150c 325 buf = host->sg_miter.addr;
d129bceb 326
7659150c
PO		 327 while (len) {
328 if (chunk == 0) {
4e4141a5 329 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 330 chunk = 4;
a406f5a3 331 }
7659150c
PO		 332
333 *buf = scratch & 0xFF;
334
335 buf++;
336 scratch >>= 8;
337 chunk--;
338 len--;
d129bceb 339 }
a406f5a3 340 }
7659150c
PO		 341
342 sg_miter_stop(&host->sg_miter);
343
344 local_irq_restore(flags);
a406f5a3 345}
d129bceb 346
a406f5a3
PO		 347static void sdhci_write_block_pio(struct sdhci_host *host)
348{
7659150c
PO		 349 unsigned long flags;
350 size_t blksize, len, chunk;
351 u32 scratch;
352 u8 *buf;
d129bceb 353
a406f5a3
PO		 354 DBG("PIO writing\n");
355
356 blksize = host->data->blksz;
7659150c
PO		 357 chunk = 0;
358 scratch = 0;
d129bceb 359
7659150c 360 local_irq_save(flags);
d129bceb 361
a406f5a3 362 while (blksize) {
bf3a35ac 363 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 364
7659150c
PO		 365 len = min(host->sg_miter.length, blksize);
366
367 blksize -= len;
368 host->sg_miter.consumed = len;
369
370 buf = host->sg_miter.addr;
d129bceb 371
7659150c
PO		 372 while (len) {
373 scratch |= (u32)*buf << (chunk * 8);
374
375 buf++;
376 chunk++;
377 len--;
378
379 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 380 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 381 chunk = 0;
382 scratch = 0;
d129bceb 383 }
d129bceb
PO		 384 }
385 }
7659150c
PO		 386
387 sg_miter_stop(&host->sg_miter);
388
389 local_irq_restore(flags);
a406f5a3
PO		 390}
391
392static void sdhci_transfer_pio(struct sdhci_host *host)
393{
394 u32 mask;
395
396 BUG_ON(!host->data);
397
7659150c 398 if (host->blocks == 0)
a406f5a3
PO		 399 return;
400
401 if (host->data->flags & MMC_DATA_READ)
402 mask = SDHCI_DATA_AVAILABLE;
403 else
404 mask = SDHCI_SPACE_AVAILABLE;
405
4a3cba32
PO		 406 /*
407 * Some controllers (JMicron JMB38x) mess up the buffer bits
408 * for transfers < 4 bytes. As long as it is just one block,
409 * we can ignore the bits.
410 */
411 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
412 (host->data->blocks == 1))
413 mask = ~0;
414
4e4141a5 415 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 416 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
417 udelay(100);
418
a406f5a3
PO		 419 if (host->data->flags & MMC_DATA_READ)
420 sdhci_read_block_pio(host);
421 else
422 sdhci_write_block_pio(host);
d129bceb 423
7659150c
PO		 424 host->blocks--;
425 if (host->blocks == 0)
a406f5a3 426 break;
a406f5a3 427 }
d129bceb 428
a406f5a3 429 DBG("PIO transfer complete.\n");
d129bceb
PO		 430}
431
2134a922
PO		 432static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
433{
434 local_irq_save(*flags);
482fce99 435 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 436}
437
438static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
439{
482fce99 440 kunmap_atomic(buffer);
2134a922
PO		 441 local_irq_restore(*flags);
442}
443
e57a5f61
AH		 444static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
445 dma_addr_t addr, int len, unsigned cmd)
118cd17d 446{
e57a5f61 447 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 448
e57a5f61 449 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 450 dma_desc->cmd = cpu_to_le16(cmd);
451 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 452 dma_desc->addr_lo = cpu_to_le32((u32)addr);
453
454 if (host->flags & SDHCI_USE_64_BIT_DMA)
455 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 456}
457
b5ffa674
AH		 458static void sdhci_adma_mark_end(void *desc)
459{
e57a5f61 460 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 461
e57a5f61 462 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 463 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 464}
465
8f1934ce 466static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 467 struct mmc_data *data)
468{
469 int direction;
470
1c3d5f6d
AH		 471 void *desc;
472 void *align;
2134a922
PO		 473 dma_addr_t addr;
474 dma_addr_t align_addr;
475 int len, offset;
476
477 struct scatterlist *sg;
478 int i;
479 char *buffer;
480 unsigned long flags;
481
482 /*
483 * The spec does not specify endianness of descriptor table.
484 * We currently guess that it is LE.
485 */
486
487 if (data->flags & MMC_DATA_READ)
488 direction = DMA_FROM_DEVICE;
489 else
490 direction = DMA_TO_DEVICE;
491
2134a922 492 host->align_addr = dma_map_single(mmc_dev(host->mmc),
76fe379a 493 host->align_buffer, host->align_buffer_sz, direction);
8d8bb39b 494 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 495 goto fail;
76fe379a 496 BUG_ON(host->align_addr & host->align_mask);
2134a922 497
348487cb
HC		 498 host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
499 if (host->sg_count < 0)
8f1934ce 500 goto unmap_align;
2134a922 501
4efaa6fb 502 desc = host->adma_table;
2134a922
PO		 503 align = host->align_buffer;
504
505 align_addr = host->align_addr;
506
507 for_each_sg(data->sg, sg, host->sg_count, i) {
508 addr = sg_dma_address(sg);
509 len = sg_dma_len(sg);
510
511 /*
512 * The SDHCI specification states that ADMA
513 * addresses must be 32-bit aligned. If they
514 * aren't, then we use a bounce buffer for
515 * the (up to three) bytes that screw up the
516 * alignment.
517 */
76fe379a
AH		 518 offset = (host->align_sz - (addr & host->align_mask)) &
519 host->align_mask;
2134a922
PO		 520 if (offset) {
521 if (data->flags & MMC_DATA_WRITE) {
522 buffer = sdhci_kmap_atomic(sg, &flags);
523 memcpy(align, buffer, offset);
524 sdhci_kunmap_atomic(buffer, &flags);
525 }
526
118cd17d 527 /* tran, valid */
e57a5f61 528 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 529 ADMA2_TRAN_VALID);
2134a922
PO		 530
531 BUG_ON(offset > 65536);
532
76fe379a
AH		 533 align += host->align_sz;
534 align_addr += host->align_sz;
2134a922 535
76fe379a 536 desc += host->desc_sz;
2134a922
PO		 537
538 addr += offset;
539 len -= offset;
540 }
541
2134a922
PO		 542 BUG_ON(len > 65536);
543
118cd17d 544 /* tran, valid */
e57a5f61 545 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
76fe379a 546 desc += host->desc_sz;
2134a922
PO		 547
548 /*
549 * If this triggers then we have a calculation bug
550 * somewhere. :/
551 */
76fe379a 552 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 553 }
554
70764a90
TA		 555 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
556 /*
557 * Mark the last descriptor as the terminating descriptor
558 */
4efaa6fb 559 if (desc != host->adma_table) {
76fe379a 560 desc -= host->desc_sz;
b5ffa674 561 sdhci_adma_mark_end(desc);
70764a90
TA		 562 }
563 } else {
564 /*
565 * Add a terminating entry.
566 */
2134a922 567
70764a90 568 /* nop, end, valid */
e57a5f61 569 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 570 }
2134a922
PO		 571
572 /*
573 * Resync align buffer as we might have changed it.
574 */
575 if (data->flags & MMC_DATA_WRITE) {
576 dma_sync_single_for_device(mmc_dev(host->mmc),
76fe379a 577 host->align_addr, host->align_buffer_sz, direction);
2134a922
PO		 578 }
579
8f1934ce
PO		 580 return 0;
581
8f1934ce
PO		 582unmap_align:
583 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 584 host->align_buffer_sz, direction);
8f1934ce
PO		 585fail:
586 return -EINVAL;
2134a922
PO		 587}
588
589static void sdhci_adma_table_post(struct sdhci_host *host,
590 struct mmc_data *data)
591{
592 int direction;
593
594 struct scatterlist *sg;
595 int i, size;
1c3d5f6d 596 void *align;
2134a922
PO		 597 char *buffer;
598 unsigned long flags;
de0b65a7 599 bool has_unaligned;
2134a922
PO		 600
601 if (data->flags & MMC_DATA_READ)
602 direction = DMA_FROM_DEVICE;
603 else
604 direction = DMA_TO_DEVICE;
605
2134a922 606 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 607 host->align_buffer_sz, direction);
2134a922 608
de0b65a7
RK		 609 /* Do a quick scan of the SG list for any unaligned mappings */
610 has_unaligned = false;
611 for_each_sg(data->sg, sg, host->sg_count, i)
76fe379a 612 if (sg_dma_address(sg) & host->align_mask) {
de0b65a7
RK		 613 has_unaligned = true;
614 break;
615 }
616
617 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 618 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
619 data->sg_len, direction);
620
621 align = host->align_buffer;
622
623 for_each_sg(data->sg, sg, host->sg_count, i) {
76fe379a
AH		 624 if (sg_dma_address(sg) & host->align_mask) {
625 size = host->align_sz -
626 (sg_dma_address(sg) & host->align_mask);
2134a922
PO		 627
628 buffer = sdhci_kmap_atomic(sg, &flags);
629 memcpy(buffer, align, size);
630 sdhci_kunmap_atomic(buffer, &flags);
631
76fe379a 632 align += host->align_sz;
2134a922
PO		 633 }
634 }
635 }
636
348487cb
HC		 637 if (!data->host_cookie)
638 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
639 data->sg_len, direction);
2134a922
PO		 640}
641
a3c7778f 642static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 643{
1c8cde92 644 u8 count;
a3c7778f 645 struct mmc_data *data = cmd->data;
1c8cde92 646 unsigned target_timeout, current_timeout;
d129bceb 647
ee53ab5d
PO		 648 /*
649 * If the host controller provides us with an incorrect timeout
650 * value, just skip the check and use 0xE. The hardware may take
651 * longer to time out, but that's much better than having a too-short
652 * timeout value.
653 */
11a2f1b7 654 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 655 return 0xE;
e538fbe8 656
a3c7778f 657 /* Unspecified timeout, assume max */
1d4d7744 658 if (!data && !cmd->busy_timeout)
a3c7778f 659 return 0xE;
d129bceb 660
a3c7778f
AW		 661 /* timeout in us */
662 if (!data)
1d4d7744 663 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 664 else {
665 target_timeout = data->timeout_ns / 1000;
666 if (host->clock)
667 target_timeout += data->timeout_clks / host->clock;
668 }
81b39802 669
1c8cde92
PO		 670 /*
671 * Figure out needed cycles.
672 * We do this in steps in order to fit inside a 32 bit int.
673 * The first step is the minimum timeout, which will have a
674 * minimum resolution of 6 bits:
675 * (1) 2^13*1000 > 2^22,
676 * (2) host->timeout_clk < 2^16
677 * =>
678 * (1) / (2) > 2^6
679 */
680 count = 0;
681 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
682 while (current_timeout < target_timeout) {
683 count++;
684 current_timeout <<= 1;
685 if (count >= 0xF)
686 break;
687 }
688
689 if (count >= 0xF) {
09eeff52
CB		 690 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
691 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 692 count = 0xE;
693 }
694
ee53ab5d
PO		 695 return count;
696}
697
6aa943ab
AV		 698static void sdhci_set_transfer_irqs(struct sdhci_host *host)
699{
700 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
701 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
702
703 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 704 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 705 else
b537f94c
RK		 706 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
707
708 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
709 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 710}
711
b45e668a 712static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 713{
714 u8 count;
b45e668a
AD		 715
716 if (host->ops->set_timeout) {
717 host->ops->set_timeout(host, cmd);
718 } else {
719 count = sdhci_calc_timeout(host, cmd);
720 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
721 }
722}
723
724static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
725{
2134a922 726 u8 ctrl;
a3c7778f 727 struct mmc_data *data = cmd->data;
8f1934ce 728 int ret;
ee53ab5d
PO		 729
730 WARN_ON(host->data);
731
b45e668a
AD		 732 if (data || (cmd->flags & MMC_RSP_BUSY))
733 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 734
735 if (!data)
ee53ab5d
PO		 736 return;
737
738 /* Sanity checks */
739 BUG_ON(data->blksz * data->blocks > 524288);
740 BUG_ON(data->blksz > host->mmc->max_blk_size);
741 BUG_ON(data->blocks > 65535);
742
743 host->data = data;
744 host->data_early = 0;
f6a03cbf 745 host->data->bytes_xfered = 0;
ee53ab5d 746
a13abc7b 747 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 748 host->flags |= SDHCI_REQ_USE_DMA;
749
2134a922
PO		 750 /*
751 * FIXME: This doesn't account for merging when mapping the
752 * scatterlist.
753 */
754 if (host->flags & SDHCI_REQ_USE_DMA) {
755 int broken, i;
756 struct scatterlist *sg;
757
758 broken = 0;
759 if (host->flags & SDHCI_USE_ADMA) {
760 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
761 broken = 1;
762 } else {
763 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
764 broken = 1;
765 }
766
767 if (unlikely(broken)) {
768 for_each_sg(data->sg, sg, data->sg_len, i) {
769 if (sg->length & 0x3) {
770 DBG("Reverting to PIO because of "
771 "transfer size (%d)\n",
772 sg->length);
773 host->flags &= ~SDHCI_REQ_USE_DMA;
774 break;
775 }
776 }
777 }
c9fddbc4
PO		 778 }
779
780 /*
781 * The assumption here being that alignment is the same after
782 * translation to device address space.
783 */
2134a922
PO		 784 if (host->flags & SDHCI_REQ_USE_DMA) {
785 int broken, i;
786 struct scatterlist *sg;
787
788 broken = 0;
789 if (host->flags & SDHCI_USE_ADMA) {
790 /*
791 * As we use 3 byte chunks to work around
792 * alignment problems, we need to check this
793 * quirk.
794 */
795 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
796 broken = 1;
797 } else {
798 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
799 broken = 1;
800 }
801
802 if (unlikely(broken)) {
803 for_each_sg(data->sg, sg, data->sg_len, i) {
804 if (sg->offset & 0x3) {
805 DBG("Reverting to PIO because of "
806 "bad alignment\n");
807 host->flags &= ~SDHCI_REQ_USE_DMA;
808 break;
809 }
810 }
811 }
812 }
813
8f1934ce
PO		 814 if (host->flags & SDHCI_REQ_USE_DMA) {
815 if (host->flags & SDHCI_USE_ADMA) {
816 ret = sdhci_adma_table_pre(host, data);
817 if (ret) {
818 /*
819 * This only happens when someone fed
820 * us an invalid request.
821 */
822 WARN_ON(1);
ebd6d357 823 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 824 } else {
4e4141a5
AV		 825 sdhci_writel(host, host->adma_addr,
826 SDHCI_ADMA_ADDRESS);
e57a5f61
AH		 827 if (host->flags & SDHCI_USE_64_BIT_DMA)
828 sdhci_writel(host,
829 (u64)host->adma_addr >> 32,
830 SDHCI_ADMA_ADDRESS_HI);
8f1934ce
PO		 831 }
832 } else {
c8b3e02e 833 int sg_cnt;
8f1934ce 834
348487cb 835 sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
62a7f368 836 if (sg_cnt <= 0) {
8f1934ce
PO		 837 /*
838 * This only happens when someone fed
839 * us an invalid request.
840 */
841 WARN_ON(1);
ebd6d357 842 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 843 } else {
719a61b4 844 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 845 sdhci_writel(host, sg_dma_address(data->sg),
846 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 847 }
848 }
849 }
850
2134a922
PO		 851 /*
852 * Always adjust the DMA selection as some controllers
853 * (e.g. JMicron) can't do PIO properly when the selection
854 * is ADMA.
855 */
856 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 857 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 858 ctrl &= ~SDHCI_CTRL_DMA_MASK;
859 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 860 (host->flags & SDHCI_USE_ADMA)) {
861 if (host->flags & SDHCI_USE_64_BIT_DMA)
862 ctrl |= SDHCI_CTRL_ADMA64;
863 else
864 ctrl |= SDHCI_CTRL_ADMA32;
865 } else {
2134a922 866 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 867 }
4e4141a5 868 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 869 }
870
8f1934ce 871 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 872 int flags;
873
874 flags = SG_MITER_ATOMIC;
875 if (host->data->flags & MMC_DATA_READ)
876 flags |= SG_MITER_TO_SG;
877 else
878 flags |= SG_MITER_FROM_SG;
879 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 880 host->blocks = data->blocks;
d129bceb 881 }
c7fa9963 882
6aa943ab
AV		 883 sdhci_set_transfer_irqs(host);
884
f6a03cbf
MV		 885 /* Set the DMA boundary value and block size */
886 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
887 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 888 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 889}
890
891static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 892 struct mmc_command *cmd)
c7fa9963 893{
d3fc5d71 894 u16 mode = 0;
e89d456f 895 struct mmc_data *data = cmd->data;
c7fa9963 896
2b558c13 897 if (data == NULL) {
9b8ffea6
VW		 898 if (host->quirks2 &
899 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
900 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
901 } else {
2b558c13 902 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 903 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
904 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 905 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 906 }
c7fa9963 907 return;
2b558c13 908 }
c7fa9963 909
e538fbe8
PO		 910 WARN_ON(!host->data);
911
d3fc5d71
VY		 912 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
913 mode = SDHCI_TRNS_BLK_CNT_EN;
914
e89d456f 915 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 916 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 917 /*
918 * If we are sending CMD23, CMD12 never gets sent
919 * on successful completion (so no Auto-CMD12).
920 */
85cc1c33
CD		 921 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
922 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 923 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 924 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
925 mode |= SDHCI_TRNS_AUTO_CMD23;
926 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
927 }
c4512f79 928 }
8edf6371 929
c7fa9963
PO		 930 if (data->flags & MMC_DATA_READ)
931 mode |= SDHCI_TRNS_READ;
c9fddbc4 932 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 933 mode |= SDHCI_TRNS_DMA;
934
4e4141a5 935 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 936}
937
938static void sdhci_finish_data(struct sdhci_host *host)
939{
940 struct mmc_data *data;
d129bceb
PO		 941
942 BUG_ON(!host->data);
943
944 data = host->data;
945 host->data = NULL;
946
c9fddbc4 947 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 948 if (host->flags & SDHCI_USE_ADMA)
949 sdhci_adma_table_post(host, data);
950 else {
348487cb
HC		 951 if (!data->host_cookie)
952 dma_unmap_sg(mmc_dev(host->mmc),
953 data->sg, data->sg_len,
954 (data->flags & MMC_DATA_READ) ?
2134a922
PO		 955 DMA_FROM_DEVICE : DMA_TO_DEVICE);
956 }
d129bceb
PO		 957 }
958
959 /*
c9b74c5b
PO		 960 * The specification states that the block count register must
961 * be updated, but it does not specify at what point in the
962 * data flow. That makes the register entirely useless to read
963 * back so we have to assume that nothing made it to the card
964 * in the event of an error.
d129bceb 965 */
c9b74c5b
PO		 966 if (data->error)
967 data->bytes_xfered = 0;
d129bceb 968 else
c9b74c5b 969 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 970
e89d456f
AW		 971 /*
972 * Need to send CMD12 if -
973 * a) open-ended multiblock transfer (no CMD23)
974 * b) error in multiblock transfer
975 */
976 if (data->stop &&
977 (data->error ||
978 !host->mrq->sbc)) {
979
d129bceb
PO		 980 /*
981 * The controller needs a reset of internal state machines
982 * upon error conditions.
983 */
17b0429d 984 if (data->error) {
03231f9b
RK		 985 sdhci_do_reset(host, SDHCI_RESET_CMD);
986 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 987 }
988
989 sdhci_send_command(host, data->stop);
990 } else
991 tasklet_schedule(&host->finish_tasklet);
992}
993
c0e55129 994void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 995{
996 int flags;
fd2208d7 997 u32 mask;
7cb2c76f 998 unsigned long timeout;
d129bceb
PO		 999
1000 WARN_ON(host->cmd);
1001
d129bceb 1002 /* Wait max 10 ms */
7cb2c76f 1003 timeout = 10;
fd2208d7
PO		 1004
1005 mask = SDHCI_CMD_INHIBIT;
1006 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1007 mask |= SDHCI_DATA_INHIBIT;
1008
1009 /* We shouldn't wait for data inihibit for stop commands, even
1010 though they might use busy signaling */
1011 if (host->mrq->data && (cmd == host->mrq->data->stop))
1012 mask &= ~SDHCI_DATA_INHIBIT;
1013
4e4141a5 1014 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1015 if (timeout == 0) {
a3c76eb9 1016 pr_err("%s: Controller never released "
acf1da45 1017 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1018 sdhci_dumpregs(host);
17b0429d 1019 cmd->error = -EIO;
d129bceb
PO		 1020 tasklet_schedule(&host->finish_tasklet);
1021 return;
1022 }
7cb2c76f
PO		 1023 timeout--;
1024 mdelay(1);
1025 }
d129bceb 1026
3e1a6892 1027 timeout = jiffies;
1d4d7744
UH		 1028 if (!cmd->data && cmd->busy_timeout > 9000)
1029 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1030 else
1031 timeout += 10 * HZ;
1032 mod_timer(&host->timer, timeout);
d129bceb
PO		 1033
1034 host->cmd = cmd;
e99783a4 1035 host->busy_handle = 0;
d129bceb 1036
a3c7778f 1037 sdhci_prepare_data(host, cmd);
d129bceb 1038
4e4141a5 1039 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1040
e89d456f 1041 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1042
d129bceb 1043 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1044 pr_err("%s: Unsupported response type!\n",
d129bceb 1045 mmc_hostname(host->mmc));
17b0429d 1046 cmd->error = -EINVAL;
d129bceb
PO		 1047 tasklet_schedule(&host->finish_tasklet);
1048 return;
1049 }
1050
1051 if (!(cmd->flags & MMC_RSP_PRESENT))
1052 flags = SDHCI_CMD_RESP_NONE;
1053 else if (cmd->flags & MMC_RSP_136)
1054 flags = SDHCI_CMD_RESP_LONG;
1055 else if (cmd->flags & MMC_RSP_BUSY)
1056 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1057 else
1058 flags = SDHCI_CMD_RESP_SHORT;
1059
1060 if (cmd->flags & MMC_RSP_CRC)
1061 flags |= SDHCI_CMD_CRC;
1062 if (cmd->flags & MMC_RSP_OPCODE)
1063 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1064
1065 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1066 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1067 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1068 flags |= SDHCI_CMD_DATA;
1069
4e4141a5 1070 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1071}
c0e55129 1072EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1073
1074static void sdhci_finish_command(struct sdhci_host *host)
1075{
1076 int i;
1077
1078 BUG_ON(host->cmd == NULL);
1079
1080 if (host->cmd->flags & MMC_RSP_PRESENT) {
1081 if (host->cmd->flags & MMC_RSP_136) {
1082 /* CRC is stripped so we need to do some shifting. */
1083 for (i = 0;i < 4;i++) {
4e4141a5 1084 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1085 SDHCI_RESPONSE + (3-i)*4) << 8;
1086 if (i != 3)
1087 host->cmd->resp[i] |=
4e4141a5 1088 sdhci_readb(host,
d129bceb
PO		 1089 SDHCI_RESPONSE + (3-i)*4-1);
1090 }
1091 } else {
4e4141a5 1092 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1093 }
1094 }
1095
17b0429d 1096 host->cmd->error = 0;
d129bceb 1097
e89d456f
AW		 1098 /* Finished CMD23, now send actual command. */
1099 if (host->cmd == host->mrq->sbc) {
1100 host->cmd = NULL;
1101 sdhci_send_command(host, host->mrq->cmd);
1102 } else {
e538fbe8 1103
e89d456f
AW		 1104 /* Processed actual command. */
1105 if (host->data && host->data_early)
1106 sdhci_finish_data(host);
d129bceb 1107
e89d456f
AW		 1108 if (!host->cmd->data)
1109 tasklet_schedule(&host->finish_tasklet);
1110
1111 host->cmd = NULL;
1112 }
d129bceb
PO		 1113}
1114
52983382
KL		 1115static u16 sdhci_get_preset_value(struct sdhci_host *host)
1116{
d975f121 1117 u16 preset = 0;
52983382 1118
d975f121
RK		 1119 switch (host->timing) {
1120 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1121 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1122 break;
d975f121 1123 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1124 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1125 break;
d975f121 1126 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1127 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1128 break;
d975f121
RK		 1129 case MMC_TIMING_UHS_SDR104:
1130 case MMC_TIMING_MMC_HS200:
52983382
KL		 1131 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1132 break;
d975f121 1133 case MMC_TIMING_UHS_DDR50:
52983382
KL		 1134 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1135 break;
e9fb05d5
AH		 1136 case MMC_TIMING_MMC_HS400:
1137 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1138 break;
52983382
KL		 1139 default:
1140 pr_warn("%s: Invalid UHS-I mode selected\n",
1141 mmc_hostname(host->mmc));
1142 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1143 break;
1144 }
1145 return preset;
1146}
1147
1771059c 1148void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1149{
c3ed3877 1150 int div = 0; /* Initialized for compiler warning */
df16219f 1151 int real_div = div, clk_mul = 1;
c3ed3877 1152 u16 clk = 0;
7cb2c76f 1153 unsigned long timeout;
5497159c 1154 bool switch_base_clk = false;
d129bceb 1155
1650d0c7
RK		 1156 host->mmc->actual_clock = 0;
1157
4e4141a5 1158 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1159
1160 if (clock == 0)
373073ef 1161 return;
d129bceb 1162
85105c53 1163 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1164 if (host->preset_enabled) {
52983382
KL		 1165 u16 pre_val;
1166
1167 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1168 pre_val = sdhci_get_preset_value(host);
1169 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1170 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1171 if (host->clk_mul &&
1172 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1173 clk = SDHCI_PROG_CLOCK_MODE;
1174 real_div = div + 1;
1175 clk_mul = host->clk_mul;
1176 } else {
1177 real_div = max_t(int, 1, div << 1);
1178 }
1179 goto clock_set;
1180 }
1181
c3ed3877
AN		 1182 /*
1183 * Check if the Host Controller supports Programmable Clock
1184 * Mode.
1185 */
1186 if (host->clk_mul) {
52983382
KL		 1187 for (div = 1; div <= 1024; div++) {
1188 if ((host->max_clk * host->clk_mul / div)
1189 <= clock)
1190 break;
1191 }
5497159c 1192 if ((host->max_clk * host->clk_mul / div) <= clock) {
1193 /*
1194 * Set Programmable Clock Mode in the Clock
1195 * Control register.
1196 */
1197 clk = SDHCI_PROG_CLOCK_MODE;
1198 real_div = div;
1199 clk_mul = host->clk_mul;
1200 div--;
1201 } else {
1202 /*
1203 * Divisor can be too small to reach clock
1204 * speed requirement. Then use the base clock.
1205 */
1206 switch_base_clk = true;
1207 }
1208 }
1209
1210 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1211 /* Version 3.00 divisors must be a multiple of 2. */
1212 if (host->max_clk <= clock)
1213 div = 1;
1214 else {
1215 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1216 div += 2) {
1217 if ((host->max_clk / div) <= clock)
1218 break;
1219 }
85105c53 1220 }
df16219f 1221 real_div = div;
c3ed3877 1222 div >>= 1;
d1955c3a
SG		 1223 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1224 && !div && host->max_clk <= 25000000)
1225 div = 1;
85105c53
ZG		 1226 }
1227 } else {
1228 /* Version 2.00 divisors must be a power of 2. */
0397526d 1229 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1230 if ((host->max_clk / div) <= clock)
1231 break;
1232 }
df16219f 1233 real_div = div;
c3ed3877 1234 div >>= 1;
d129bceb 1235 }
d129bceb 1236
52983382 1237clock_set:
03d6f5ff 1238 if (real_div)
df16219f 1239 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1240 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1241 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1242 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1243 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1244 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1245
27f6cb16
CB		 1246 /* Wait max 20 ms */
1247 timeout = 20;
4e4141a5 1248 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1249 & SDHCI_CLOCK_INT_STABLE)) {
1250 if (timeout == 0) {
a3c76eb9 1251 pr_err("%s: Internal clock never "
acf1da45 1252 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1253 sdhci_dumpregs(host);
1254 return;
1255 }
7cb2c76f
PO		 1256 timeout--;
1257 mdelay(1);
1258 }
d129bceb
PO		 1259
1260 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1261 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1262}
1771059c 1263EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1264
24fbb3ca
RK		 1265static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1266 unsigned short vdd)
146ad66e 1267{
3a48edc4 1268 struct mmc_host *mmc = host->mmc;
8364248a 1269 u8 pwr = 0;
146ad66e 1270
52221610
TK		 1271 if (!IS_ERR(mmc->supply.vmmc)) {
1272 spin_unlock_irq(&host->lock);
4e743f1f 1273 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
52221610 1274 spin_lock_irq(&host->lock);
3cbc6123
TK		 1275
1276 if (mode != MMC_POWER_OFF)
1277 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1278 else
1279 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1280
52221610
TK		 1281 return;
1282 }
1283
24fbb3ca
RK		 1284 if (mode != MMC_POWER_OFF) {
1285 switch (1 << vdd) {
ae628903
PO		 1286 case MMC_VDD_165_195:
1287 pwr = SDHCI_POWER_180;
1288 break;
1289 case MMC_VDD_29_30:
1290 case MMC_VDD_30_31:
1291 pwr = SDHCI_POWER_300;
1292 break;
1293 case MMC_VDD_32_33:
1294 case MMC_VDD_33_34:
1295 pwr = SDHCI_POWER_330;
1296 break;
1297 default:
1298 BUG();
1299 }
1300 }
1301
1302 if (host->pwr == pwr)
e921a8b6 1303 return;
146ad66e 1304
ae628903
PO		 1305 host->pwr = pwr;
1306
1307 if (pwr == 0) {
4e4141a5 1308 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1309 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1310 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1311 vdd = 0;
e921a8b6
RK		 1312 } else {
1313 /*
1314 * Spec says that we should clear the power reg before setting
1315 * a new value. Some controllers don't seem to like this though.
1316 */
1317 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1318 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1319
e921a8b6
RK		 1320 /*
1321 * At least the Marvell CaFe chip gets confused if we set the
1322 * voltage and set turn on power at the same time, so set the
1323 * voltage first.
1324 */
1325 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1326 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1327
e921a8b6 1328 pwr |= SDHCI_POWER_ON;
146ad66e 1329
e921a8b6 1330 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1331
e921a8b6
RK		 1332 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1333 sdhci_runtime_pm_bus_on(host);
f0710a55 1334
e921a8b6
RK		 1335 /*
1336 * Some controllers need an extra 10ms delay of 10ms before
1337 * they can apply clock after applying power
1338 */
1339 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1340 mdelay(10);
1341 }
146ad66e
PO		 1342}
1343
d129bceb
PO		 1344/*****************************************************************************\
1345 * *
1346 * MMC callbacks *
1347 * *
1348\*****************************************************************************/
1349
1350static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1351{
1352 struct sdhci_host *host;
505a8680 1353 int present;
d129bceb
PO		 1354 unsigned long flags;
1355
1356 host = mmc_priv(mmc);
1357
66fd8ad5
AH		 1358 sdhci_runtime_pm_get(host);
1359
04e079cf
SB		 1360 /* Firstly check card presence */
1361 present = sdhci_do_get_cd(host);
2836766a 1362
d129bceb
PO		 1363 spin_lock_irqsave(&host->lock, flags);
1364
1365 WARN_ON(host->mrq != NULL);
1366
f9134319 1367#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1368 sdhci_activate_led(host);
2f730fec 1369#endif
e89d456f
AW		 1370
1371 /*
1372 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1373 * requests if Auto-CMD12 is enabled.
1374 */
1375 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1376 if (mrq->stop) {
1377 mrq->data->stop = NULL;
1378 mrq->stop = NULL;
1379 }
1380 }
d129bceb
PO		 1381
1382 host->mrq = mrq;
1383
68d1fb7e 1384 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1385 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1386 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1387 } else {
8edf6371 1388 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1389 sdhci_send_command(host, mrq->sbc);
1390 else
1391 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1392 }
d129bceb 1393
5f25a66f 1394 mmiowb();
d129bceb
PO		 1395 spin_unlock_irqrestore(&host->lock, flags);
1396}
1397
2317f56c
RK		 1398void sdhci_set_bus_width(struct sdhci_host *host, int width)
1399{
1400 u8 ctrl;
1401
1402 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1403 if (width == MMC_BUS_WIDTH_8) {
1404 ctrl &= ~SDHCI_CTRL_4BITBUS;
1405 if (host->version >= SDHCI_SPEC_300)
1406 ctrl |= SDHCI_CTRL_8BITBUS;
1407 } else {
1408 if (host->version >= SDHCI_SPEC_300)
1409 ctrl &= ~SDHCI_CTRL_8BITBUS;
1410 if (width == MMC_BUS_WIDTH_4)
1411 ctrl |= SDHCI_CTRL_4BITBUS;
1412 else
1413 ctrl &= ~SDHCI_CTRL_4BITBUS;
1414 }
1415 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1416}
1417EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1418
96d7b78c
RK		 1419void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1420{
1421 u16 ctrl_2;
1422
1423 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1424 /* Select Bus Speed Mode for host */
1425 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1426 if ((timing == MMC_TIMING_MMC_HS200) ||
1427 (timing == MMC_TIMING_UHS_SDR104))
1428 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1429 else if (timing == MMC_TIMING_UHS_SDR12)
1430 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1431 else if (timing == MMC_TIMING_UHS_SDR25)
1432 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1433 else if (timing == MMC_TIMING_UHS_SDR50)
1434 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1435 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1436 (timing == MMC_TIMING_MMC_DDR52))
1437 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1438 else if (timing == MMC_TIMING_MMC_HS400)
1439 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1440 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1441}
1442EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1443
66fd8ad5 1444static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1445{
d129bceb
PO		 1446 unsigned long flags;
1447 u8 ctrl;
3a48edc4 1448 struct mmc_host *mmc = host->mmc;
d129bceb 1449
d129bceb
PO		 1450 spin_lock_irqsave(&host->lock, flags);
1451
ceb6143b
AH		 1452 if (host->flags & SDHCI_DEVICE_DEAD) {
1453 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1454 if (!IS_ERR(mmc->supply.vmmc) &&
1455 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1456 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1457 return;
1458 }
1e72859e 1459
d129bceb
PO		 1460 /*
1461 * Reset the chip on each power off.
1462 * Should clear out any weird states.
1463 */
1464 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1465 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1466 sdhci_reinit(host);
d129bceb
PO		 1467 }
1468
52983382 1469 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1470 (ios->power_mode == MMC_POWER_UP) &&
1471 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1472 sdhci_enable_preset_value(host, false);
1473
373073ef 1474 if (!ios->clock || ios->clock != host->clock) {
1771059c 1475 host->ops->set_clock(host, ios->clock);
373073ef 1476 host->clock = ios->clock;
03d6f5ff
AD		 1477
1478 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1479 host->clock) {
1480 host->timeout_clk = host->mmc->actual_clock ?
1481 host->mmc->actual_clock / 1000 :
1482 host->clock / 1000;
1483 host->mmc->max_busy_timeout =
1484 host->ops->get_max_timeout_count ?
1485 host->ops->get_max_timeout_count(host) :
1486 1 << 27;
1487 host->mmc->max_busy_timeout /= host->timeout_clk;
1488 }
373073ef 1489 }
d129bceb 1490
24fbb3ca 1491 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1492
643a81ff
PR		 1493 if (host->ops->platform_send_init_74_clocks)
1494 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1495
2317f56c 1496 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1497
15ec4461 1498 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1499
3ab9c8da
PR		 1500 if ((ios->timing == MMC_TIMING_SD_HS ||
1501 ios->timing == MMC_TIMING_MMC_HS)
1502 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1503 ctrl |= SDHCI_CTRL_HISPD;
1504 else
1505 ctrl &= ~SDHCI_CTRL_HISPD;
1506
d6d50a15 1507 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1508 u16 clk, ctrl_2;
49c468fc
AN		 1509
1510 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1511 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1512 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1513 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1514 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1515 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1516 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1517 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1518 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1519
da91a8f9 1520 if (!host->preset_enabled) {
758535c4 1521 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1522 /*
1523 * We only need to set Driver Strength if the
1524 * preset value enable is not set.
1525 */
da91a8f9 1526 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1527 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1528 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1529 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1530 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1531 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1532 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1533 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1534 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1535 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1536 else {
1537 pr_warn("%s: invalid driver type, default to "
1538 "driver type B\n", mmc_hostname(mmc));
1539 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1540 }
d6d50a15
AN		 1541
1542 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1543 } else {
1544 /*
1545 * According to SDHC Spec v3.00, if the Preset Value
1546 * Enable in the Host Control 2 register is set, we
1547 * need to reset SD Clock Enable before changing High
1548 * Speed Enable to avoid generating clock gliches.
1549 */
758535c4
AN		 1550
1551 /* Reset SD Clock Enable */
1552 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1553 clk &= ~SDHCI_CLOCK_CARD_EN;
1554 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1555
1556 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1557
1558 /* Re-enable SD Clock */
1771059c 1559 host->ops->set_clock(host, host->clock);
d6d50a15 1560 }
49c468fc 1561
49c468fc
AN		 1562 /* Reset SD Clock Enable */
1563 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1564 clk &= ~SDHCI_CLOCK_CARD_EN;
1565 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1566
96d7b78c 1567 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1568 host->timing = ios->timing;
49c468fc 1569
52983382
KL		 1570 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1571 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1572 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1573 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1574 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1575 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1576 u16 preset;
1577
1578 sdhci_enable_preset_value(host, true);
1579 preset = sdhci_get_preset_value(host);
1580 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1581 >> SDHCI_PRESET_DRV_SHIFT;
1582 }
1583
49c468fc 1584 /* Re-enable SD Clock */
1771059c 1585 host->ops->set_clock(host, host->clock);
758535c4
AN		 1586 } else
1587 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1588
b8352260
LD		 1589 /*
1590 * Some (ENE) controllers go apeshit on some ios operation,
1591 * signalling timeout and CRC errors even on CMD0. Resetting
1592 * it on each ios seems to solve the problem.
1593 */
c63705e1 1594 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1595 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1596
5f25a66f 1597 mmiowb();
d129bceb
PO		 1598 spin_unlock_irqrestore(&host->lock, flags);
1599}
1600
66fd8ad5
AH		 1601static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1602{
1603 struct sdhci_host *host = mmc_priv(mmc);
1604
1605 sdhci_runtime_pm_get(host);
1606 sdhci_do_set_ios(host, ios);
1607 sdhci_runtime_pm_put(host);
1608}
1609
94144a46
KL		 1610static int sdhci_do_get_cd(struct sdhci_host *host)
1611{
1612 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1613
1614 if (host->flags & SDHCI_DEVICE_DEAD)
1615 return 0;
1616
88af5655
II		 1617 /* If nonremovable, assume that the card is always present. */
1618 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
94144a46
KL		 1619 return 1;
1620
88af5655
II		 1621 /*
1622 * Try slot gpio detect, if defined it take precedence
1623 * over build in controller functionality
1624 */
94144a46
KL		 1625 if (!IS_ERR_VALUE(gpio_cd))
1626 return !!gpio_cd;
1627
88af5655
II		 1628 /* If polling, assume that the card is always present. */
1629 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1630 return 1;
1631
94144a46
KL		 1632 /* Host native card detect */
1633 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1634}
1635
1636static int sdhci_get_cd(struct mmc_host *mmc)
1637{
1638 struct sdhci_host *host = mmc_priv(mmc);
1639 int ret;
1640
1641 sdhci_runtime_pm_get(host);
1642 ret = sdhci_do_get_cd(host);
1643 sdhci_runtime_pm_put(host);
1644 return ret;
1645}
1646
66fd8ad5 1647static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1648{
d129bceb 1649 unsigned long flags;
2dfb579c 1650 int is_readonly;
d129bceb 1651
d129bceb
PO		 1652 spin_lock_irqsave(&host->lock, flags);
1653
1e72859e 1654 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1655 is_readonly = 0;
1656 else if (host->ops->get_ro)
1657 is_readonly = host->ops->get_ro(host);
1e72859e 1658 else
2dfb579c
WS		 1659 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1660 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1661
1662 spin_unlock_irqrestore(&host->lock, flags);
1663
2dfb579c
WS		 1664 /* This quirk needs to be replaced by a callback-function later */
1665 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1666 !is_readonly : is_readonly;
d129bceb
PO		 1667}
1668
82b0e23a
TI		 1669#define SAMPLE_COUNT 5
1670
66fd8ad5 1671static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1672{
82b0e23a
TI		 1673 int i, ro_count;
1674
82b0e23a 1675 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1676 return sdhci_check_ro(host);
82b0e23a
TI		 1677
1678 ro_count = 0;
1679 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1680 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1681 if (++ro_count > SAMPLE_COUNT / 2)
1682 return 1;
1683 }
1684 msleep(30);
1685 }
1686 return 0;
1687}
1688
20758b66
AH		 1689static void sdhci_hw_reset(struct mmc_host *mmc)
1690{
1691 struct sdhci_host *host = mmc_priv(mmc);
1692
1693 if (host->ops && host->ops->hw_reset)
1694 host->ops->hw_reset(host);
1695}
1696
66fd8ad5 1697static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1698{
66fd8ad5
AH		 1699 struct sdhci_host *host = mmc_priv(mmc);
1700 int ret;
f75979b7 1701
66fd8ad5
AH		 1702 sdhci_runtime_pm_get(host);
1703 ret = sdhci_do_get_ro(host);
1704 sdhci_runtime_pm_put(host);
1705 return ret;
1706}
f75979b7 1707
66fd8ad5
AH		 1708static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1709{
be138554 1710 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1711 if (enable)
b537f94c 1712 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1713 else
b537f94c
RK		 1714 host->ier &= ~SDHCI_INT_CARD_INT;
1715
1716 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1717 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1718 mmiowb();
1719 }
66fd8ad5
AH		 1720}
1721
1722static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1723{
1724 struct sdhci_host *host = mmc_priv(mmc);
1725 unsigned long flags;
f75979b7 1726
ef104333
RK		 1727 sdhci_runtime_pm_get(host);
1728
66fd8ad5 1729 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1730 if (enable)
1731 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1732 else
1733 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1734
66fd8ad5 1735 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1736 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1737
1738 sdhci_runtime_pm_put(host);
f75979b7
PO		 1739}
1740
20b92a30 1741static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1742 struct mmc_ios *ios)
f2119df6 1743{
3a48edc4 1744 struct mmc_host *mmc = host->mmc;
20b92a30 1745 u16 ctrl;
6231f3de 1746 int ret;
f2119df6 1747
20b92a30
KL		 1748 /*
1749 * Signal Voltage Switching is only applicable for Host Controllers
1750 * v3.00 and above.
1751 */
1752 if (host->version < SDHCI_SPEC_300)
1753 return 0;
6231f3de 1754
f2119df6 1755 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1756
21f5998f 1757 switch (ios->signal_voltage) {
20b92a30
KL		 1758 case MMC_SIGNAL_VOLTAGE_330:
1759 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1760 ctrl &= ~SDHCI_CTRL_VDD_180;
1761 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1762
3a48edc4
TK		 1763 if (!IS_ERR(mmc->supply.vqmmc)) {
1764 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1765 3600000);
20b92a30 1766 if (ret) {
6606110d
JP		 1767 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1768 mmc_hostname(mmc));
20b92a30
KL		 1769 return -EIO;
1770 }
1771 }
1772 /* Wait for 5ms */
1773 usleep_range(5000, 5500);
f2119df6 1774
20b92a30
KL		 1775 /* 3.3V regulator output should be stable within 5 ms */
1776 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1777 if (!(ctrl & SDHCI_CTRL_VDD_180))
1778 return 0;
6231f3de 1779
6606110d
JP		 1780 pr_warn("%s: 3.3V regulator output did not became stable\n",
1781 mmc_hostname(mmc));
20b92a30
KL		 1782
1783 return -EAGAIN;
1784 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1785 if (!IS_ERR(mmc->supply.vqmmc)) {
1786 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1787 1700000, 1950000);
1788 if (ret) {
6606110d
JP		 1789 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1790 mmc_hostname(mmc));
20b92a30
KL		 1791 return -EIO;
1792 }
1793 }
6231f3de 1794
6231f3de
PR		 1795 /*
1796 * Enable 1.8V Signal Enable in the Host Control2
1797 * register
1798 */
20b92a30
KL		 1799 ctrl |= SDHCI_CTRL_VDD_180;
1800 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1801
9d967a61
VY		 1802 /* Some controller need to do more when switching */
1803 if (host->ops->voltage_switch)
1804 host->ops->voltage_switch(host);
1805
20b92a30
KL		 1806 /* 1.8V regulator output should be stable within 5 ms */
1807 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1808 if (ctrl & SDHCI_CTRL_VDD_180)
1809 return 0;
f2119df6 1810
6606110d
JP		 1811 pr_warn("%s: 1.8V regulator output did not became stable\n",
1812 mmc_hostname(mmc));
f2119df6 1813
20b92a30
KL		 1814 return -EAGAIN;
1815 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1816 if (!IS_ERR(mmc->supply.vqmmc)) {
1817 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1818 1300000);
20b92a30 1819 if (ret) {
6606110d
JP		 1820 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1821 mmc_hostname(mmc));
20b92a30 1822 return -EIO;
f2119df6
AN		 1823 }
1824 }
6231f3de 1825 return 0;
20b92a30 1826 default:
f2119df6
AN		 1827 /* No signal voltage switch required */
1828 return 0;
20b92a30 1829 }
f2119df6
AN		 1830}
1831
66fd8ad5 1832static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1833 struct mmc_ios *ios)
66fd8ad5
AH		 1834{
1835 struct sdhci_host *host = mmc_priv(mmc);
1836 int err;
1837
1838 if (host->version < SDHCI_SPEC_300)
1839 return 0;
1840 sdhci_runtime_pm_get(host);
21f5998f 1841 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1842 sdhci_runtime_pm_put(host);
1843 return err;
1844}
1845
20b92a30
KL		 1846static int sdhci_card_busy(struct mmc_host *mmc)
1847{
1848 struct sdhci_host *host = mmc_priv(mmc);
1849 u32 present_state;
1850
1851 sdhci_runtime_pm_get(host);
1852 /* Check whether DAT[3:0] is 0000 */
1853 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1854 sdhci_runtime_pm_put(host);
1855
1856 return !(present_state & SDHCI_DATA_LVL_MASK);
1857}
1858
b5540ce1
AH		 1859static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1860{
1861 struct sdhci_host *host = mmc_priv(mmc);
1862 unsigned long flags;
1863
1864 spin_lock_irqsave(&host->lock, flags);
1865 host->flags |= SDHCI_HS400_TUNING;
1866 spin_unlock_irqrestore(&host->lock, flags);
1867
1868 return 0;
1869}
1870
069c9f14 1871static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1872{
4b6f37d3 1873 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1874 u16 ctrl;
b513ea25 1875 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1876 int err = 0;
2b35bd83 1877 unsigned long flags;
38e40bf5 1878 unsigned int tuning_count = 0;
b5540ce1 1879 bool hs400_tuning;
b513ea25 1880
66fd8ad5 1881 sdhci_runtime_pm_get(host);
2b35bd83 1882 spin_lock_irqsave(&host->lock, flags);
b513ea25 1883
b5540ce1
AH		 1884 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1885 host->flags &= ~SDHCI_HS400_TUNING;
1886
38e40bf5
AH		 1887 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1888 tuning_count = host->tuning_count;
1889
b513ea25 1890 /*
069c9f14
G		 1891 * The Host Controller needs tuning only in case of SDR104 mode
1892 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1893 * Capabilities register.
069c9f14
G		 1894 * If the Host Controller supports the HS200 mode then the
1895 * tuning function has to be executed.
b513ea25 1896 */
4b6f37d3 1897 switch (host->timing) {
b5540ce1 1898 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1899 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1900 err = -EINVAL;
1901 goto out_unlock;
1902
4b6f37d3 1903 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1904 /*
1905 * Periodic re-tuning for HS400 is not expected to be needed, so
1906 * disable it here.
1907 */
1908 if (hs400_tuning)
1909 tuning_count = 0;
1910 break;
1911
4b6f37d3
RK		 1912 case MMC_TIMING_UHS_SDR104:
1913 break;
1914
1915 case MMC_TIMING_UHS_SDR50:
1916 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1917 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1918 break;
1919 /* FALLTHROUGH */
1920
1921 default:
d519c863 1922 goto out_unlock;
b513ea25
AN		 1923 }
1924
45251812 1925 if (host->ops->platform_execute_tuning) {
2b35bd83 1926 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1927 err = host->ops->platform_execute_tuning(host, opcode);
1928 sdhci_runtime_pm_put(host);
1929 return err;
1930 }
1931
4b6f37d3
RK		 1932 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1933 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1934 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1935 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1936 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1937
1938 /*
1939 * As per the Host Controller spec v3.00, tuning command
1940 * generates Buffer Read Ready interrupt, so enable that.
1941 *
1942 * Note: The spec clearly says that when tuning sequence
1943 * is being performed, the controller does not generate
1944 * interrupts other than Buffer Read Ready interrupt. But
1945 * to make sure we don't hit a controller bug, we _only_
1946 * enable Buffer Read Ready interrupt here.
1947 */
b537f94c
RK		 1948 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1949 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1950
1951 /*
1952 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1953 * of loops reaches 40 times or a timeout of 150ms occurs.
1954 */
b513ea25
AN		 1955 do {
1956 struct mmc_command cmd = {0};
66fd8ad5 1957 struct mmc_request mrq = {NULL};
b513ea25 1958
069c9f14 1959 cmd.opcode = opcode;
b513ea25
AN		 1960 cmd.arg = 0;
1961 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1962 cmd.retries = 0;
1963 cmd.data = NULL;
1964 cmd.error = 0;
1965
7ce45e95
AC		 1966 if (tuning_loop_counter-- == 0)
1967 break;
1968
b513ea25
AN		 1969 mrq.cmd = &cmd;
1970 host->mrq = &mrq;
1971
1972 /*
1973 * In response to CMD19, the card sends 64 bytes of tuning
1974 * block to the Host Controller. So we set the block size
1975 * to 64 here.
1976 */
069c9f14
G		 1977 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1978 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1979 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1980 SDHCI_BLOCK_SIZE);
1981 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1982 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1983 SDHCI_BLOCK_SIZE);
1984 } else {
1985 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1986 SDHCI_BLOCK_SIZE);
1987 }
b513ea25
AN		 1988
1989 /*
1990 * The tuning block is sent by the card to the host controller.
1991 * So we set the TRNS_READ bit in the Transfer Mode register.
1992 * This also takes care of setting DMA Enable and Multi Block
1993 * Select in the same register to 0.
1994 */
1995 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1996
1997 sdhci_send_command(host, &cmd);
1998
1999 host->cmd = NULL;
2000 host->mrq = NULL;
2001
2b35bd83 2002 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2003 /* Wait for Buffer Read Ready interrupt */
2004 wait_event_interruptible_timeout(host->buf_ready_int,
2005 (host->tuning_done == 1),
2006 msecs_to_jiffies(50));
2b35bd83 2007 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 2008
2009 if (!host->tuning_done) {
a3c76eb9 2010 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 2011 "Buffer Read Ready interrupt during tuning "
2012 "procedure, falling back to fixed sampling "
2013 "clock\n");
2014 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2015 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2016 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2017 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2018
2019 err = -EIO;
2020 goto out;
2021 }
2022
2023 host->tuning_done = 0;
2024
2025 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2026
2027 /* eMMC spec does not require a delay between tuning cycles */
2028 if (opcode == MMC_SEND_TUNING_BLOCK)
2029 mdelay(1);
b513ea25
AN		 2030 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2031
2032 /*
2033 * The Host Driver has exhausted the maximum number of loops allowed,
2034 * so use fixed sampling frequency.
2035 */
7ce45e95 2036 if (tuning_loop_counter < 0) {
b513ea25
AN		 2037 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2038 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2039 }
2040 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2041 pr_info(DRIVER_NAME ": Tuning procedure"
2042 " failed, falling back to fixed sampling"
2043 " clock\n");
114f2bf6 2044 err = -EIO;
b513ea25
AN		 2045 }
2046
2047out:
38e40bf5 2048 if (tuning_count) {
66c39dfc
AH		 2049 /*
2050 * In case tuning fails, host controllers which support
2051 * re-tuning can try tuning again at a later time, when the
2052 * re-tuning timer expires. So for these controllers, we
2053 * return 0. Since there might be other controllers who do not
2054 * have this capability, we return error for them.
2055 */
2056 err = 0;
cf2b5eea
AN		 2057 }
2058
66c39dfc 2059 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2060
b537f94c
RK		 2061 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2062 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2063out_unlock:
2b35bd83 2064 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2065 sdhci_runtime_pm_put(host);
b513ea25
AN		 2066
2067 return err;
2068}
2069
cb849648
AH		 2070static int sdhci_select_drive_strength(struct mmc_card *card,
2071 unsigned int max_dtr, int host_drv,
2072 int card_drv, int *drv_type)
2073{
2074 struct sdhci_host *host = mmc_priv(card->host);
2075
2076 if (!host->ops->select_drive_strength)
2077 return 0;
2078
2079 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2080 card_drv, drv_type);
2081}
52983382
KL		 2082
2083static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2084{
4d55c5a1
AN		 2085 /* Host Controller v3.00 defines preset value registers */
2086 if (host->version < SDHCI_SPEC_300)
2087 return;
2088
4d55c5a1
AN		 2089 /*
2090 * We only enable or disable Preset Value if they are not already
2091 * enabled or disabled respectively. Otherwise, we bail out.
2092 */
da91a8f9
RK		 2093 if (host->preset_enabled != enable) {
2094 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2095
2096 if (enable)
2097 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2098 else
2099 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2100
4d55c5a1 2101 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2102
2103 if (enable)
2104 host->flags |= SDHCI_PV_ENABLED;
2105 else
2106 host->flags &= ~SDHCI_PV_ENABLED;
2107
2108 host->preset_enabled = enable;
4d55c5a1 2109 }
66fd8ad5
AH		 2110}
2111
348487cb
HC		 2112static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2113 int err)
2114{
2115 struct sdhci_host *host = mmc_priv(mmc);
2116 struct mmc_data *data = mrq->data;
2117
2118 if (host->flags & SDHCI_REQ_USE_DMA) {
2119 if (data->host_cookie)
2120 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2121 data->flags & MMC_DATA_WRITE ?
2122 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2123 mrq->data->host_cookie = 0;
2124 }
2125}
2126
2127static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2128 struct mmc_data *data,
2129 struct sdhci_host_next *next)
2130{
2131 int sg_count;
2132
2133 if (!next && data->host_cookie &&
2134 data->host_cookie != host->next_data.cookie) {
2135 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2136 __func__, data->host_cookie, host->next_data.cookie);
2137 data->host_cookie = 0;
2138 }
2139
2140 /* Check if next job is already prepared */
2141 if (next ||
2142 (!next && data->host_cookie != host->next_data.cookie)) {
2143 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2144 data->sg_len,
2145 data->flags & MMC_DATA_WRITE ?
2146 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2147
2148 } else {
2149 sg_count = host->next_data.sg_count;
2150 host->next_data.sg_count = 0;
2151 }
2152
2153
2154 if (sg_count == 0)
2155 return -EINVAL;
2156
2157 if (next) {
2158 next->sg_count = sg_count;
2159 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2160 } else
2161 host->sg_count = sg_count;
2162
2163 return sg_count;
2164}
2165
2166static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2167 bool is_first_req)
2168{
2169 struct sdhci_host *host = mmc_priv(mmc);
2170
2171 if (mrq->data->host_cookie) {
2172 mrq->data->host_cookie = 0;
2173 return;
2174 }
2175
2176 if (host->flags & SDHCI_REQ_USE_DMA)
2177 if (sdhci_pre_dma_transfer(host,
2178 mrq->data,
2179 &host->next_data) < 0)
2180 mrq->data->host_cookie = 0;
2181}
2182
71e69211 2183static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2184{
71e69211 2185 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2186 unsigned long flags;
2836766a 2187 int present;
d129bceb 2188
722e1280
CD		 2189 /* First check if client has provided their own card event */
2190 if (host->ops->card_event)
2191 host->ops->card_event(host);
2192
2836766a
KK		 2193 present = sdhci_do_get_cd(host);
2194
d129bceb
PO		 2195 spin_lock_irqsave(&host->lock, flags);
2196
66fd8ad5 2197 /* Check host->mrq first in case we are runtime suspended */
2836766a 2198 if (host->mrq && !present) {
a3c76eb9 2199 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2200 mmc_hostname(host->mmc));
a3c76eb9 2201 pr_err("%s: Resetting controller.\n",
66fd8ad5 2202 mmc_hostname(host->mmc));
d129bceb 2203
03231f9b
RK		 2204 sdhci_do_reset(host, SDHCI_RESET_CMD);
2205 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2206
66fd8ad5
AH		 2207 host->mrq->cmd->error = -ENOMEDIUM;
2208 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2209 }
2210
2211 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2212}
2213
2214static const struct mmc_host_ops sdhci_ops = {
2215 .request = sdhci_request,
348487cb
HC		 2216 .post_req = sdhci_post_req,
2217 .pre_req = sdhci_pre_req,
71e69211 2218 .set_ios = sdhci_set_ios,
94144a46 2219 .get_cd = sdhci_get_cd,
71e69211
GL		 2220 .get_ro = sdhci_get_ro,
2221 .hw_reset = sdhci_hw_reset,
2222 .enable_sdio_irq = sdhci_enable_sdio_irq,
2223 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2224 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2225 .execute_tuning = sdhci_execute_tuning,
cb849648 2226 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2227 .card_event = sdhci_card_event,
20b92a30 2228 .card_busy = sdhci_card_busy,
71e69211
GL		 2229};
2230
2231/*****************************************************************************\
2232 * *
2233 * Tasklets *
2234 * *
2235\*****************************************************************************/
2236
d129bceb
PO		 2237static void sdhci_tasklet_finish(unsigned long param)
2238{
2239 struct sdhci_host *host;
2240 unsigned long flags;
2241 struct mmc_request *mrq;
2242
2243 host = (struct sdhci_host*)param;
2244
66fd8ad5
AH		 2245 spin_lock_irqsave(&host->lock, flags);
2246
0c9c99a7
CB		 2247 /*
2248 * If this tasklet gets rescheduled while running, it will
2249 * be run again afterwards but without any active request.
2250 */
66fd8ad5
AH		 2251 if (!host->mrq) {
2252 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2253 return;
66fd8ad5 2254 }
d129bceb
PO		 2255
2256 del_timer(&host->timer);
2257
2258 mrq = host->mrq;
2259
d129bceb
PO		 2260 /*
2261 * The controller needs a reset of internal state machines
2262 * upon error conditions.
2263 */
1e72859e 2264 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2265 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2266 (mrq->sbc && mrq->sbc->error) ||
2267 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2268 (mrq->data->stop && mrq->data->stop->error))) ||
2269 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2270
2271 /* Some controllers need this kick or reset won't work here */
8213af3b 2272 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2273 /* This is to force an update */
1771059c 2274 host->ops->set_clock(host, host->clock);
645289dc
PO		 2275
2276 /* Spec says we should do both at the same time, but Ricoh
2277 controllers do not like that. */
03231f9b
RK		 2278 sdhci_do_reset(host, SDHCI_RESET_CMD);
2279 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2280 }
2281
2282 host->mrq = NULL;
2283 host->cmd = NULL;
2284 host->data = NULL;
2285
f9134319 2286#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2287 sdhci_deactivate_led(host);
2f730fec 2288#endif
d129bceb 2289
5f25a66f 2290 mmiowb();
d129bceb
PO		 2291 spin_unlock_irqrestore(&host->lock, flags);
2292
2293 mmc_request_done(host->mmc, mrq);
66fd8ad5 2294 sdhci_runtime_pm_put(host);
d129bceb
PO		 2295}
2296
2297static void sdhci_timeout_timer(unsigned long data)
2298{
2299 struct sdhci_host *host;
2300 unsigned long flags;
2301
2302 host = (struct sdhci_host*)data;
2303
2304 spin_lock_irqsave(&host->lock, flags);
2305
2306 if (host->mrq) {
a3c76eb9 2307 pr_err("%s: Timeout waiting for hardware "
acf1da45 2308 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2309 sdhci_dumpregs(host);
2310
2311 if (host->data) {
17b0429d 2312 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2313 sdhci_finish_data(host);
2314 } else {
2315 if (host->cmd)
17b0429d 2316 host->cmd->error = -ETIMEDOUT;
d129bceb 2317 else
17b0429d 2318 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2319
2320 tasklet_schedule(&host->finish_tasklet);
2321 }
2322 }
2323
5f25a66f 2324 mmiowb();
d129bceb
PO		 2325 spin_unlock_irqrestore(&host->lock, flags);
2326}
2327
2328/*****************************************************************************\
2329 * *
2330 * Interrupt handling *
2331 * *
2332\*****************************************************************************/
2333
61541397 2334static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2335{
2336 BUG_ON(intmask == 0);
2337
2338 if (!host->cmd) {
a3c76eb9 2339 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2340 "though no command operation was in progress.\n",
2341 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2342 sdhci_dumpregs(host);
2343 return;
2344 }
2345
43b58b36 2346 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2347 host->cmd->error = -ETIMEDOUT;
2348 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2349 SDHCI_INT_INDEX))
2350 host->cmd->error = -EILSEQ;
43b58b36 2351
e809517f 2352 if (host->cmd->error) {
d129bceb 2353 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2354 return;
2355 }
2356
2357 /*
2358 * The host can send and interrupt when the busy state has
2359 * ended, allowing us to wait without wasting CPU cycles.
2360 * Unfortunately this is overloaded on the "data complete"
2361 * interrupt, so we need to take some care when handling
2362 * it.
2363 *
2364 * Note: The 1.0 specification is a bit ambiguous about this
2365 * feature so there might be some problems with older
2366 * controllers.
2367 */
2368 if (host->cmd->flags & MMC_RSP_BUSY) {
2369 if (host->cmd->data)
2370 DBG("Cannot wait for busy signal when also "
2371 "doing a data transfer");
e99783a4
CM		 2372 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2373 && !host->busy_handle) {
2374 /* Mark that command complete before busy is ended */
2375 host->busy_handle = 1;
e809517f 2376 return;
e99783a4 2377 }
f945405c
BD		 2378
2379 /* The controller does not support the end-of-busy IRQ,
2380 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2381 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2382 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2383 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2384 }
2385
2386 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2387 sdhci_finish_command(host);
d129bceb
PO		 2388}
2389
0957c333 2390#ifdef CONFIG_MMC_DEBUG
08621b18 2391static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2392{
2393 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2394 void *desc = host->adma_table;
6882a8c0
BD		 2395
2396 sdhci_dumpregs(host);
2397
2398 while (true) {
e57a5f61
AH		 2399 struct sdhci_adma2_64_desc *dma_desc = desc;
2400
2401 if (host->flags & SDHCI_USE_64_BIT_DMA)
2402 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2403 name, desc, le32_to_cpu(dma_desc->addr_hi),
2404 le32_to_cpu(dma_desc->addr_lo),
2405 le16_to_cpu(dma_desc->len),
2406 le16_to_cpu(dma_desc->cmd));
2407 else
2408 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2409 name, desc, le32_to_cpu(dma_desc->addr_lo),
2410 le16_to_cpu(dma_desc->len),
2411 le16_to_cpu(dma_desc->cmd));
6882a8c0 2412
76fe379a 2413 desc += host->desc_sz;
6882a8c0 2414
0545230f 2415 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2416 break;
2417 }
2418}
2419#else
08621b18 2420static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2421#endif
2422
d129bceb
PO		 2423static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2424{
069c9f14 2425 u32 command;
d129bceb
PO		 2426 BUG_ON(intmask == 0);
2427
b513ea25
AN		 2428 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2429 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2430 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2431 if (command == MMC_SEND_TUNING_BLOCK ||
2432 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2433 host->tuning_done = 1;
2434 wake_up(&host->buf_ready_int);
2435 return;
2436 }
2437 }
2438
d129bceb
PO		 2439 if (!host->data) {
2440 /*
e809517f
PO		 2441 * The "data complete" interrupt is also used to
2442 * indicate that a busy state has ended. See comment
2443 * above in sdhci_cmd_irq().
d129bceb 2444 */
e809517f 2445 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2446 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2447 host->cmd->error = -ETIMEDOUT;
2448 tasklet_schedule(&host->finish_tasklet);
2449 return;
2450 }
e809517f 2451 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2452 /*
2453 * Some cards handle busy-end interrupt
2454 * before the command completed, so make
2455 * sure we do things in the proper order.
2456 */
2457 if (host->busy_handle)
2458 sdhci_finish_command(host);
2459 else
2460 host->busy_handle = 1;
e809517f
PO		 2461 return;
2462 }
2463 }
d129bceb 2464
a3c76eb9 2465 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2466 "though no data operation was in progress.\n",
2467 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2468 sdhci_dumpregs(host);
2469
2470 return;
2471 }
2472
2473 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2474 host->data->error = -ETIMEDOUT;
22113efd
AL		 2475 else if (intmask & SDHCI_INT_DATA_END_BIT)
2476 host->data->error = -EILSEQ;
2477 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2478 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2479 != MMC_BUS_TEST_R)
17b0429d 2480 host->data->error = -EILSEQ;
6882a8c0 2481 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2482 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2483 sdhci_adma_show_error(host);
2134a922 2484 host->data->error = -EIO;
a4071fbb
HZ		 2485 if (host->ops->adma_workaround)
2486 host->ops->adma_workaround(host, intmask);
6882a8c0 2487 }
d129bceb 2488
17b0429d 2489 if (host->data->error)
d129bceb
PO		 2490 sdhci_finish_data(host);
2491 else {
a406f5a3 2492 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2493 sdhci_transfer_pio(host);
2494
6ba736a1
PO		 2495 /*
2496 * We currently don't do anything fancy with DMA
2497 * boundaries, but as we can't disable the feature
2498 * we need to at least restart the transfer.
f6a03cbf
MV		 2499 *
2500 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2501 * should return a valid address to continue from, but as
2502 * some controllers are faulty, don't trust them.
6ba736a1 2503 */
f6a03cbf
MV		 2504 if (intmask & SDHCI_INT_DMA_END) {
2505 u32 dmastart, dmanow;
2506 dmastart = sg_dma_address(host->data->sg);
2507 dmanow = dmastart + host->data->bytes_xfered;
2508 /*
2509 * Force update to the next DMA block boundary.
2510 */
2511 dmanow = (dmanow &
2512 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2513 SDHCI_DEFAULT_BOUNDARY_SIZE;
2514 host->data->bytes_xfered = dmanow - dmastart;
2515 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2516 " next 0x%08x\n",
2517 mmc_hostname(host->mmc), dmastart,
2518 host->data->bytes_xfered, dmanow);
2519 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2520 }
6ba736a1 2521
e538fbe8
PO		 2522 if (intmask & SDHCI_INT_DATA_END) {
2523 if (host->cmd) {
2524 /*
2525 * Data managed to finish before the
2526 * command completed. Make sure we do
2527 * things in the proper order.
2528 */
2529 host->data_early = 1;
2530 } else {
2531 sdhci_finish_data(host);
2532 }
2533 }
d129bceb
PO		 2534 }
2535}
2536
7d12e780 2537static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2538{
781e989c 2539 irqreturn_t result = IRQ_NONE;
66fd8ad5 2540 struct sdhci_host *host = dev_id;
41005003 2541 u32 intmask, mask, unexpected = 0;
781e989c 2542 int max_loops = 16;
d129bceb
PO		 2543
2544 spin_lock(&host->lock);
2545
be138554 2546 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2547 spin_unlock(&host->lock);
655bca76 2548 return IRQ_NONE;
66fd8ad5
AH		 2549 }
2550
4e4141a5 2551 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2552 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2553 result = IRQ_NONE;
2554 goto out;
2555 }
2556
41005003
RK		 2557 do {
2558 /* Clear selected interrupts. */
2559 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2560 SDHCI_INT_BUS_POWER);
2561 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2562
41005003
RK		 2563 DBG("*** %s got interrupt: 0x%08x\n",
2564 mmc_hostname(host->mmc), intmask);
d129bceb 2565
41005003
RK		 2566 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2567 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2568 SDHCI_CARD_PRESENT;
d129bceb 2569
41005003
RK		 2570 /*
2571 * There is a observation on i.mx esdhc. INSERT
2572 * bit will be immediately set again when it gets
2573 * cleared, if a card is inserted. We have to mask
2574 * the irq to prevent interrupt storm which will
2575 * freeze the system. And the REMOVE gets the
2576 * same situation.
2577 *
2578 * More testing are needed here to ensure it works
2579 * for other platforms though.
2580 */
b537f94c
RK		 2581 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2582 SDHCI_INT_CARD_REMOVE);
2583 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2584 SDHCI_INT_CARD_INSERT;
2585 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2586 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2587
2588 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2589 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2590
2591 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2592 SDHCI_INT_CARD_REMOVE);
2593 result = IRQ_WAKE_THREAD;
41005003 2594 }
d129bceb 2595
41005003 2596 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2597 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2598 &intmask);
964f9ce2 2599
41005003
RK		 2600 if (intmask & SDHCI_INT_DATA_MASK)
2601 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2602
41005003
RK		 2603 if (intmask & SDHCI_INT_BUS_POWER)
2604 pr_err("%s: Card is consuming too much power!\n",
2605 mmc_hostname(host->mmc));
3192a28f 2606
781e989c
RK		 2607 if (intmask & SDHCI_INT_CARD_INT) {
2608 sdhci_enable_sdio_irq_nolock(host, false);
2609 host->thread_isr |= SDHCI_INT_CARD_INT;
2610 result = IRQ_WAKE_THREAD;
2611 }
f75979b7 2612
41005003
RK		 2613 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2614 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2615 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2616 SDHCI_INT_CARD_INT);
f75979b7 2617
41005003
RK		 2618 if (intmask) {
2619 unexpected |= intmask;
2620 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2621 }
d129bceb 2622
781e989c
RK		 2623 if (result == IRQ_NONE)
2624 result = IRQ_HANDLED;
d129bceb 2625
41005003 2626 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2627 } while (intmask && --max_loops);
d129bceb
PO		 2628out:
2629 spin_unlock(&host->lock);
2630
6379b237
AS		 2631 if (unexpected) {
2632 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2633 mmc_hostname(host->mmc), unexpected);
2634 sdhci_dumpregs(host);
2635 }
f75979b7 2636
d129bceb
PO		 2637 return result;
2638}
2639
781e989c
RK		 2640static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2641{
2642 struct sdhci_host *host = dev_id;
2643 unsigned long flags;
2644 u32 isr;
2645
2646 spin_lock_irqsave(&host->lock, flags);
2647 isr = host->thread_isr;
2648 host->thread_isr = 0;
2649 spin_unlock_irqrestore(&host->lock, flags);
2650
3560db8e
RK		 2651 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2652 sdhci_card_event(host->mmc);
2653 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2654 }
2655
781e989c
RK		 2656 if (isr & SDHCI_INT_CARD_INT) {
2657 sdio_run_irqs(host->mmc);
2658
2659 spin_lock_irqsave(&host->lock, flags);
2660 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2661 sdhci_enable_sdio_irq_nolock(host, true);
2662 spin_unlock_irqrestore(&host->lock, flags);
2663 }
2664
2665 return isr ? IRQ_HANDLED : IRQ_NONE;
2666}
2667
d129bceb
PO		 2668/*****************************************************************************\
2669 * *
2670 * Suspend/resume *
2671 * *
2672\*****************************************************************************/
2673
2674#ifdef CONFIG_PM
ad080d79
KL		 2675void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2676{
2677 u8 val;
2678 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2679 | SDHCI_WAKE_ON_INT;
2680
2681 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2682 val |= mask ;
2683 /* Avoid fake wake up */
2684 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2685 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2686 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2687}
2688EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2689
0b10f478 2690static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2691{
2692 u8 val;
2693 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2694 | SDHCI_WAKE_ON_INT;
2695
2696 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2697 val &= ~mask;
2698 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2699}
d129bceb 2700
29495aa0 2701int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2702{
7260cf5e
AV		 2703 sdhci_disable_card_detection(host);
2704
66c39dfc
AH		 2705 mmc_retune_timer_stop(host->mmc);
2706 mmc_retune_needed(host->mmc);
cf2b5eea 2707
ad080d79 2708 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2709 host->ier = 0;
2710 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2711 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2712 free_irq(host->irq, host);
2713 } else {
2714 sdhci_enable_irq_wakeups(host);
2715 enable_irq_wake(host->irq);
2716 }
4ee14ec6 2717 return 0;
d129bceb
PO		 2718}
2719
b8c86fc5 2720EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2721
b8c86fc5
PO		 2722int sdhci_resume_host(struct sdhci_host *host)
2723{
4ee14ec6 2724 int ret = 0;
d129bceb 2725
a13abc7b 2726 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2727 if (host->ops->enable_dma)
2728 host->ops->enable_dma(host);
2729 }
d129bceb 2730
ad080d79 2731 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2732 ret = request_threaded_irq(host->irq, sdhci_irq,
2733 sdhci_thread_irq, IRQF_SHARED,
2734 mmc_hostname(host->mmc), host);
ad080d79
KL		 2735 if (ret)
2736 return ret;
2737 } else {
2738 sdhci_disable_irq_wakeups(host);
2739 disable_irq_wake(host->irq);
2740 }
d129bceb 2741
6308d290
AH		 2742 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2743 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2744 /* Card keeps power but host controller does not */
2745 sdhci_init(host, 0);
2746 host->pwr = 0;
2747 host->clock = 0;
2748 sdhci_do_set_ios(host, &host->mmc->ios);
2749 } else {
2750 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2751 mmiowb();
2752 }
b8c86fc5 2753
7260cf5e
AV		 2754 sdhci_enable_card_detection(host);
2755
2f4cbb3d 2756 return ret;
d129bceb
PO		 2757}
2758
b8c86fc5 2759EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2760
2761static int sdhci_runtime_pm_get(struct sdhci_host *host)
2762{
2763 return pm_runtime_get_sync(host->mmc->parent);
2764}
2765
2766static int sdhci_runtime_pm_put(struct sdhci_host *host)
2767{
2768 pm_runtime_mark_last_busy(host->mmc->parent);
2769 return pm_runtime_put_autosuspend(host->mmc->parent);
2770}
2771
f0710a55
AH		 2772static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2773{
2774 if (host->runtime_suspended || host->bus_on)
2775 return;
2776 host->bus_on = true;
2777 pm_runtime_get_noresume(host->mmc->parent);
2778}
2779
2780static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2781{
2782 if (host->runtime_suspended || !host->bus_on)
2783 return;
2784 host->bus_on = false;
2785 pm_runtime_put_noidle(host->mmc->parent);
2786}
2787
66fd8ad5
AH		 2788int sdhci_runtime_suspend_host(struct sdhci_host *host)
2789{
2790 unsigned long flags;
66fd8ad5 2791
66c39dfc
AH		 2792 mmc_retune_timer_stop(host->mmc);
2793 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2794
2795 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2796 host->ier &= SDHCI_INT_CARD_INT;
2797 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2798 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2799 spin_unlock_irqrestore(&host->lock, flags);
2800
781e989c 2801 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2802
2803 spin_lock_irqsave(&host->lock, flags);
2804 host->runtime_suspended = true;
2805 spin_unlock_irqrestore(&host->lock, flags);
2806
8a125bad 2807 return 0;
66fd8ad5
AH		 2808}
2809EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2810
2811int sdhci_runtime_resume_host(struct sdhci_host *host)
2812{
2813 unsigned long flags;
8a125bad 2814 int host_flags = host->flags;
66fd8ad5
AH		 2815
2816 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2817 if (host->ops->enable_dma)
2818 host->ops->enable_dma(host);
2819 }
2820
2821 sdhci_init(host, 0);
2822
2823 /* Force clock and power re-program */
2824 host->pwr = 0;
2825 host->clock = 0;
3396e736 2826 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2827 sdhci_do_set_ios(host, &host->mmc->ios);
2828
52983382
KL		 2829 if ((host_flags & SDHCI_PV_ENABLED) &&
2830 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2831 spin_lock_irqsave(&host->lock, flags);
2832 sdhci_enable_preset_value(host, true);
2833 spin_unlock_irqrestore(&host->lock, flags);
2834 }
66fd8ad5 2835
66fd8ad5
AH		 2836 spin_lock_irqsave(&host->lock, flags);
2837
2838 host->runtime_suspended = false;
2839
2840 /* Enable SDIO IRQ */
ef104333 2841 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2842 sdhci_enable_sdio_irq_nolock(host, true);
2843
2844 /* Enable Card Detection */
2845 sdhci_enable_card_detection(host);
2846
2847 spin_unlock_irqrestore(&host->lock, flags);
2848
8a125bad 2849 return 0;
66fd8ad5
AH		 2850}
2851EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2852
162d6f98 2853#endif /* CONFIG_PM */
66fd8ad5 2854
d129bceb
PO		 2855/*****************************************************************************\
2856 * *
b8c86fc5 2857 * Device allocation/registration *
d129bceb
PO		 2858 * *
2859\*****************************************************************************/
2860
b8c86fc5
PO		 2861struct sdhci_host *sdhci_alloc_host(struct device *dev,
2862 size_t priv_size)
d129bceb 2863{
d129bceb
PO		 2864 struct mmc_host *mmc;
2865 struct sdhci_host *host;
2866
b8c86fc5 2867 WARN_ON(dev == NULL);
d129bceb 2868
b8c86fc5 2869 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2870 if (!mmc)
b8c86fc5 2871 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2872
2873 host = mmc_priv(mmc);
2874 host->mmc = mmc;
2875
b8c86fc5
PO		 2876 return host;
2877}
8a4da143 2878
b8c86fc5 2879EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2880
b8c86fc5
PO		 2881int sdhci_add_host(struct sdhci_host *host)
2882{
2883 struct mmc_host *mmc;
bd6a8c30 2884 u32 caps[2] = {0, 0};
f2119df6
AN		 2885 u32 max_current_caps;
2886 unsigned int ocr_avail;
f5fa92e5 2887 unsigned int override_timeout_clk;
59241757 2888 u32 max_clk;
b8c86fc5 2889 int ret;
d129bceb 2890
b8c86fc5
PO		 2891 WARN_ON(host == NULL);
2892 if (host == NULL)
2893 return -EINVAL;
d129bceb 2894
b8c86fc5 2895 mmc = host->mmc;
d129bceb 2896
b8c86fc5
PO		 2897 if (debug_quirks)
2898 host->quirks = debug_quirks;
66fd8ad5
AH		 2899 if (debug_quirks2)
2900 host->quirks2 = debug_quirks2;
d129bceb 2901
f5fa92e5
AH		 2902 override_timeout_clk = host->timeout_clk;
2903
03231f9b 2904 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2905
4e4141a5 2906 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2907 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2908 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2909 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2910 pr_err("%s: Unknown controller version (%d). "
b69c9058 2911 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2912 host->version);
4a965505
PO		 2913 }
2914
f2119df6 2915 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2916 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2917
bd6a8c30
PR		 2918 if (host->version >= SDHCI_SPEC_300)
2919 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2920 host->caps1 :
2921 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2922
b8c86fc5 2923 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2924 host->flags |= SDHCI_USE_SDMA;
f2119df6 2925 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2926 DBG("Controller doesn't have SDMA capability\n");
67435274 2927 else
a13abc7b 2928 host->flags |= SDHCI_USE_SDMA;
d129bceb 2929
b8c86fc5 2930 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2931 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2932 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2933 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2934 }
2935
f2119df6
AN		 2936 if ((host->version >= SDHCI_SPEC_200) &&
2937 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2938 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2939
2940 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2941 (host->flags & SDHCI_USE_ADMA)) {
2942 DBG("Disabling ADMA as it is marked broken\n");
2943 host->flags &= ~SDHCI_USE_ADMA;
2944 }
2945
e57a5f61
AH		 2946 /*
2947 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2948 * and *must* do 64-bit DMA. A driver has the opportunity to change
2949 * that during the first call to ->enable_dma(). Similarly
2950 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2951 * implement.
2952 */
2953 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2954 host->flags |= SDHCI_USE_64_BIT_DMA;
2955
a13abc7b 2956 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2957 if (host->ops->enable_dma) {
2958 if (host->ops->enable_dma(host)) {
6606110d 2959 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2960 mmc_hostname(mmc));
a13abc7b
RR		 2961 host->flags &=
2962 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2963 }
d129bceb
PO		 2964 }
2965 }
2966
e57a5f61
AH		 2967 /* SDMA does not support 64-bit DMA */
2968 if (host->flags & SDHCI_USE_64_BIT_DMA)
2969 host->flags &= ~SDHCI_USE_SDMA;
2970
2134a922
PO		 2971 if (host->flags & SDHCI_USE_ADMA) {
2972 /*
76fe379a
AH		 2973 * The DMA descriptor table size is calculated as the maximum
2974 * number of segments times 2, to allow for an alignment
2975 * descriptor for each segment, plus 1 for a nop end descriptor,
2976 * all multipled by the descriptor size.
2134a922 2977 */
e57a5f61
AH		 2978 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2979 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2980 SDHCI_ADMA2_64_DESC_SZ;
2981 host->align_buffer_sz = SDHCI_MAX_SEGS *
2982 SDHCI_ADMA2_64_ALIGN;
2983 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2984 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2985 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2986 } else {
2987 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2988 SDHCI_ADMA2_32_DESC_SZ;
2989 host->align_buffer_sz = SDHCI_MAX_SEGS *
2990 SDHCI_ADMA2_32_ALIGN;
2991 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2992 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2993 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2994 }
4efaa6fb 2995 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
76fe379a 2996 host->adma_table_sz,
4efaa6fb
AH		 2997 &host->adma_addr,
2998 GFP_KERNEL);
76fe379a 2999 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
4efaa6fb 3000 if (!host->adma_table || !host->align_buffer) {
7ac02036
PF		 3001 if (host->adma_table)
3002 dma_free_coherent(mmc_dev(mmc),
3003 host->adma_table_sz,
3004 host->adma_table,
3005 host->adma_addr);
2134a922 3006 kfree(host->align_buffer);
6606110d 3007 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 3008 mmc_hostname(mmc));
3009 host->flags &= ~SDHCI_USE_ADMA;
4efaa6fb 3010 host->adma_table = NULL;
d1e49f77 3011 host->align_buffer = NULL;
76fe379a 3012 } else if (host->adma_addr & host->align_mask) {
6606110d
JP		 3013 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3014 mmc_hostname(mmc));
d1e49f77 3015 host->flags &= ~SDHCI_USE_ADMA;
76fe379a 3016 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3017 host->adma_table, host->adma_addr);
d1e49f77 3018 kfree(host->align_buffer);
4efaa6fb 3019 host->adma_table = NULL;
d1e49f77 3020 host->align_buffer = NULL;
2134a922
PO		 3021 }
3022 }
3023
7659150c
PO		 3024 /*
3025 * If we use DMA, then it's up to the caller to set the DMA
3026 * mask, but PIO does not need the hw shim so we set a new
3027 * mask here in that case.
3028 */
a13abc7b 3029 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3030 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3031 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3032 }
d129bceb 3033
c4687d5f 3034 if (host->version >= SDHCI_SPEC_300)
f2119df6 3035 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3036 >> SDHCI_CLOCK_BASE_SHIFT;
3037 else
f2119df6 3038 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3039 >> SDHCI_CLOCK_BASE_SHIFT;
3040
4240ff0a 3041 host->max_clk *= 1000000;
f27f47ef
AV		 3042 if (host->max_clk == 0 || host->quirks &
3043 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3044 if (!host->ops->get_max_clock) {
a3c76eb9 3045 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 3046 "frequency.\n", mmc_hostname(mmc));
3047 return -ENODEV;
3048 }
3049 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3050 }
d129bceb 3051
348487cb 3052 host->next_data.cookie = 1;
c3ed3877
AN		 3053 /*
3054 * In case of Host Controller v3.00, find out whether clock
3055 * multiplier is supported.
3056 */
3057 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3058 SDHCI_CLOCK_MUL_SHIFT;
3059
3060 /*
3061 * In case the value in Clock Multiplier is 0, then programmable
3062 * clock mode is not supported, otherwise the actual clock
3063 * multiplier is one more than the value of Clock Multiplier
3064 * in the Capabilities Register.
3065 */
3066 if (host->clk_mul)
3067 host->clk_mul += 1;
3068
d129bceb
PO		 3069 /*
3070 * Set host parameters.
3071 */
3072 mmc->ops = &sdhci_ops;
59241757
DA		 3073 max_clk = host->max_clk;
3074
ce5f036b 3075 if (host->ops->get_min_clock)
a9e58f25 3076 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3077 else if (host->version >= SDHCI_SPEC_300) {
3078 if (host->clk_mul) {
3079 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3080 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3081 } else
3082 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3083 } else
0397526d 3084 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3085
59241757
DA		 3086 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3087 mmc->f_max = max_clk;
3088
28aab053
AD		 3089 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3090 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3091 SDHCI_TIMEOUT_CLK_SHIFT;
3092 if (host->timeout_clk == 0) {
3093 if (host->ops->get_timeout_clock) {
3094 host->timeout_clk =
3095 host->ops->get_timeout_clock(host);
3096 } else {
3097 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3098 mmc_hostname(mmc));
3099 return -ENODEV;
3100 }
272308ca 3101 }
272308ca 3102
28aab053
AD		 3103 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3104 host->timeout_clk *= 1000;
272308ca 3105
28aab053 3106 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3107 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3108 mmc->max_busy_timeout /= host->timeout_clk;
3109 }
58d1246d 3110
f5fa92e5
AH		 3111 if (override_timeout_clk)
3112 host->timeout_clk = override_timeout_clk;
3113
e89d456f 3114 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3115 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3116
3117 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3118 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3119
8edf6371 3120 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3121 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3122 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3123 !(host->flags & SDHCI_USE_SDMA)) &&
3124 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3125 host->flags |= SDHCI_AUTO_CMD23;
3126 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3127 } else {
3128 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3129 }
3130
15ec4461
PR		 3131 /*
3132 * A controller may support 8-bit width, but the board itself
3133 * might not have the pins brought out. Boards that support
3134 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3135 * their platform code before calling sdhci_add_host(), and we
3136 * won't assume 8-bit width for hosts without that CAP.
3137 */
5fe23c7f 3138 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3139 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3140
63ef5d8c
JH		 3141 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3142 mmc->caps &= ~MMC_CAP_CMD23;
3143
f2119df6 3144 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3145 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3146
176d1ed4 3147 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
c31d22eb
II		 3148 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3149 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
68d1fb7e
AV		 3150 mmc->caps |= MMC_CAP_NEEDS_POLL;
3151
3a48edc4
TK		 3152 /* If there are external regulators, get them */
3153 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3154 return -EPROBE_DEFER;
3155
6231f3de 3156 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3157 if (!IS_ERR(mmc->supply.vqmmc)) {
3158 ret = regulator_enable(mmc->supply.vqmmc);
3159 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3160 1950000))
8363c374
KL		 3161 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3162 SDHCI_SUPPORT_SDR50 |
3163 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3164 if (ret) {
3165 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3166 mmc_hostname(mmc), ret);
4bb74313 3167 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3168 }
8363c374 3169 }
6231f3de 3170
6a66180a
DD		 3171 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3172 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3173 SDHCI_SUPPORT_DDR50);
3174
4188bba0
AC		 3175 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3176 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3177 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3178 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3179
3180 /* SDR104 supports also implies SDR50 support */
156e14b1 3181 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3182 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3183 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3184 * field can be promoted to support HS200.
3185 */
549c0b18 3186 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3187 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3188 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3189 mmc->caps |= MMC_CAP_UHS_SDR50;
3190
e9fb05d5
AH		 3191 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3192 (caps[1] & SDHCI_SUPPORT_HS400))
3193 mmc->caps2 |= MMC_CAP2_HS400;
3194
549c0b18
AH		 3195 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3196 (IS_ERR(mmc->supply.vqmmc) ||
3197 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3198 1300000)))
3199 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3200
9107ebbf
MC		 3201 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3202 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3203 mmc->caps |= MMC_CAP_UHS_DDR50;
3204
069c9f14 3205 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3206 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3207 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3208
156e14b1 3209 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3210 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3211 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3212
d6d50a15
AN		 3213 /* Driver Type(s) (A, C, D) supported by the host */
3214 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3215 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3216 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3217 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3218 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3219 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3220
cf2b5eea
AN		 3221 /* Initial value for re-tuning timer count */
3222 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3223 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3224
3225 /*
3226 * In case Re-tuning Timer is not disabled, the actual value of
3227 * re-tuning timer will be 2 ^ (n - 1).
3228 */
3229 if (host->tuning_count)
3230 host->tuning_count = 1 << (host->tuning_count - 1);
3231
3232 /* Re-tuning mode supported by the Host Controller */
3233 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3234 SDHCI_RETUNING_MODE_SHIFT;
3235
8f230f45 3236 ocr_avail = 0;
bad37e1a 3237
f2119df6
AN		 3238 /*
3239 * According to SD Host Controller spec v3.00, if the Host System
3240 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3241 * the value is meaningful only if Voltage Support in the Capabilities
3242 * register is set. The actual current value is 4 times the register
3243 * value.
3244 */
3245 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3246 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3247 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3248 if (curr > 0) {
3249
3250 /* convert to SDHCI_MAX_CURRENT format */
3251 curr = curr/1000; /* convert to mA */
3252 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3253
3254 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3255 max_current_caps =
3256 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3257 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3258 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3259 }
3260 }
f2119df6
AN		 3261
3262 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3263 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3264
55c4665e 3265 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3266 SDHCI_MAX_CURRENT_330_MASK) >>
3267 SDHCI_MAX_CURRENT_330_SHIFT) *
3268 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3269 }
3270 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3271 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3272
55c4665e 3273 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3274 SDHCI_MAX_CURRENT_300_MASK) >>
3275 SDHCI_MAX_CURRENT_300_SHIFT) *
3276 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3277 }
3278 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3279 ocr_avail |= MMC_VDD_165_195;
3280
55c4665e 3281 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3282 SDHCI_MAX_CURRENT_180_MASK) >>
3283 SDHCI_MAX_CURRENT_180_SHIFT) *
3284 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3285 }
3286
5fd26c7e
UH		 3287 /* If OCR set by host, use it instead. */
3288 if (host->ocr_mask)
3289 ocr_avail = host->ocr_mask;
3290
3291 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3292 if (mmc->ocr_avail)
52221610 3293 ocr_avail = mmc->ocr_avail;
3a48edc4 3294
8f230f45
TI		 3295 mmc->ocr_avail = ocr_avail;
3296 mmc->ocr_avail_sdio = ocr_avail;
3297 if (host->ocr_avail_sdio)
3298 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3299 mmc->ocr_avail_sd = ocr_avail;
3300 if (host->ocr_avail_sd)
3301 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3302 else /* normal SD controllers don't support 1.8V */
3303 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3304 mmc->ocr_avail_mmc = ocr_avail;
3305 if (host->ocr_avail_mmc)
3306 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3307
3308 if (mmc->ocr_avail == 0) {
a3c76eb9 3309 pr_err("%s: Hardware doesn't report any "
b69c9058 3310 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3311 return -ENODEV;
146ad66e
PO		 3312 }
3313
d129bceb
PO		 3314 spin_lock_init(&host->lock);
3315
3316 /*
2134a922
PO		 3317 * Maximum number of segments. Depends on if the hardware
3318 * can do scatter/gather or not.
d129bceb 3319 */
2134a922 3320 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3321 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3322 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3323 mmc->max_segs = 1;
2134a922 3324 else /* PIO */
4fb213f8 3325 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3326
3327 /*
ac00531d
AH		 3328 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3329 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3330 * is less anyway.
d129bceb 3331 */
55db890a 3332 mmc->max_req_size = 524288;
d129bceb
PO		 3333
3334 /*
3335 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3336 * of bytes. When doing hardware scatter/gather, each entry cannot
3337 * be larger than 64 KiB though.
d129bceb 3338 */
30652aa3
OJ		 3339 if (host->flags & SDHCI_USE_ADMA) {
3340 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3341 mmc->max_seg_size = 65535;
3342 else
3343 mmc->max_seg_size = 65536;
3344 } else {
2134a922 3345 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3346 }
d129bceb 3347
fe4a3c7a
PO		 3348 /*
3349 * Maximum block size. This varies from controller to controller and
3350 * is specified in the capabilities register.
3351 */
0633f654
AV		 3352 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3353 mmc->max_blk_size = 2;
3354 } else {
f2119df6 3355 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3356 SDHCI_MAX_BLOCK_SHIFT;
3357 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3358 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3359 mmc_hostname(mmc));
0633f654
AV		 3360 mmc->max_blk_size = 0;
3361 }
3362 }
3363
3364 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3365
55db890a
PO		 3366 /*
3367 * Maximum block count.
3368 */
1388eefd 3369 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3370
d129bceb
PO		 3371 /*
3372 * Init tasklets.
3373 */
d129bceb
PO		 3374 tasklet_init(&host->finish_tasklet,
3375 sdhci_tasklet_finish, (unsigned long)host);
3376
e4cad1b5 3377 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3378
250fb7b4 3379 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3380
2af502ca
SG		 3381 sdhci_init(host, 0);
3382
781e989c
RK		 3383 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3384 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3385 if (ret) {
3386 pr_err("%s: Failed to request IRQ %d: %d\n",
3387 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3388 goto untasklet;
0fc81ee3 3389 }
d129bceb 3390
d129bceb
PO		 3391#ifdef CONFIG_MMC_DEBUG
3392 sdhci_dumpregs(host);
3393#endif
3394
f9134319 3395#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3396 snprintf(host->led_name, sizeof(host->led_name),
3397 "%s::", mmc_hostname(mmc));
3398 host->led.name = host->led_name;
2f730fec
PO		 3399 host->led.brightness = LED_OFF;
3400 host->led.default_trigger = mmc_hostname(mmc);
3401 host->led.brightness_set = sdhci_led_control;
3402
b8c86fc5 3403 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3404 if (ret) {
3405 pr_err("%s: Failed to register LED device: %d\n",
3406 mmc_hostname(mmc), ret);
2f730fec 3407 goto reset;
0fc81ee3 3408 }
2f730fec
PO		 3409#endif
3410
5f25a66f
PO		 3411 mmiowb();
3412
d129bceb
PO		 3413 mmc_add_host(mmc);
3414
a3c76eb9 3415 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3416 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3417 (host->flags & SDHCI_USE_ADMA) ?
3418 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3419 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3420
7260cf5e
AV		 3421 sdhci_enable_card_detection(host);
3422
d129bceb
PO		 3423 return 0;
3424
f9134319 3425#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3426reset:
03231f9b 3427 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3428 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3429 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3430 free_irq(host->irq, host);
3431#endif
8ef1a143 3432untasklet:
d129bceb 3433 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3434
3435 return ret;
3436}
3437
b8c86fc5 3438EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3439
1e72859e 3440void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3441{
3a48edc4 3442 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3443 unsigned long flags;
3444
3445 if (dead) {
3446 spin_lock_irqsave(&host->lock, flags);
3447
3448 host->flags |= SDHCI_DEVICE_DEAD;
3449
3450 if (host->mrq) {
a3c76eb9 3451 pr_err("%s: Controller removed during "
4e743f1f 3452 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3453
3454 host->mrq->cmd->error = -ENOMEDIUM;
3455 tasklet_schedule(&host->finish_tasklet);
3456 }
3457
3458 spin_unlock_irqrestore(&host->lock, flags);
3459 }
3460
7260cf5e
AV		 3461 sdhci_disable_card_detection(host);
3462
4e743f1f 3463 mmc_remove_host(mmc);
d129bceb 3464
f9134319 3465#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3466 led_classdev_unregister(&host->led);
3467#endif
3468
1e72859e 3469 if (!dead)
03231f9b 3470 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3471
b537f94c
RK		 3472 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3473 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3474 free_irq(host->irq, host);
3475
3476 del_timer_sync(&host->timer);
3477
d129bceb 3478 tasklet_kill(&host->finish_tasklet);
2134a922 3479
3a48edc4
TK		 3480 if (!IS_ERR(mmc->supply.vqmmc))
3481 regulator_disable(mmc->supply.vqmmc);
6231f3de 3482
4efaa6fb 3483 if (host->adma_table)
76fe379a 3484 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3485 host->adma_table, host->adma_addr);
2134a922
PO		 3486 kfree(host->align_buffer);
3487
4efaa6fb 3488 host->adma_table = NULL;
2134a922 3489 host->align_buffer = NULL;
d129bceb
PO		 3490}
3491
b8c86fc5 3492EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3493
b8c86fc5 3494void sdhci_free_host(struct sdhci_host *host)
d129bceb 3495{
b8c86fc5 3496 mmc_free_host(host->mmc);
d129bceb
PO		 3497}
3498
b8c86fc5 3499EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3500
3501/*****************************************************************************\
3502 * *
3503 * Driver init/exit *
3504 * *
3505\*****************************************************************************/
3506
3507static int __init sdhci_drv_init(void)
3508{
a3c76eb9 3509 pr_info(DRIVER_NAME
52fbf9c9 3510 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3511 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3512
b8c86fc5 3513 return 0;
d129bceb
PO		 3514}
3515
3516static void __exit sdhci_drv_exit(void)
3517{
d129bceb
PO		 3518}
3519
3520module_init(sdhci_drv_init);
3521module_exit(sdhci_drv_exit);
3522
df673b22 3523module_param(debug_quirks, uint, 0444);
66fd8ad5 3524module_param(debug_quirks2, uint, 0444);
67435274 3525
32710e8f 3526MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3527MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3528MODULE_LICENSE("GPL");
67435274 3529
df673b22 3530MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3531MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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