Commit | Line | Data |
---|---|---|
d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
d129bceb | 19 | #include <linux/dma-mapping.h> |
11763609 | 20 | #include <linux/scatterlist.h> |
d129bceb | 21 | |
2f730fec PO |
22 | #include <linux/leds.h> |
23 | ||
d129bceb | 24 | #include <linux/mmc/host.h> |
d129bceb | 25 | |
d129bceb PO |
26 | #include "sdhci.h" |
27 | ||
28 | #define DRIVER_NAME "sdhci" | |
d129bceb | 29 | |
d129bceb | 30 | #define DBG(f, x...) \ |
c6563178 | 31 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 32 | |
f9134319 PO |
33 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
34 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
35 | #define SDHCI_USE_LEDS_CLASS | |
36 | #endif | |
37 | ||
df673b22 | 38 | static unsigned int debug_quirks = 0; |
67435274 | 39 | |
d129bceb PO |
40 | static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); |
41 | static void sdhci_finish_data(struct sdhci_host *); | |
42 | ||
43 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
44 | static void sdhci_finish_command(struct sdhci_host *); | |
45 | ||
46 | static void sdhci_dumpregs(struct sdhci_host *host) | |
47 | { | |
48 | printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n"); | |
49 | ||
50 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
51 | readl(host->ioaddr + SDHCI_DMA_ADDRESS), | |
52 | readw(host->ioaddr + SDHCI_HOST_VERSION)); | |
53 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", | |
54 | readw(host->ioaddr + SDHCI_BLOCK_SIZE), | |
55 | readw(host->ioaddr + SDHCI_BLOCK_COUNT)); | |
56 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", | |
57 | readl(host->ioaddr + SDHCI_ARGUMENT), | |
58 | readw(host->ioaddr + SDHCI_TRANSFER_MODE)); | |
59 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", | |
60 | readl(host->ioaddr + SDHCI_PRESENT_STATE), | |
61 | readb(host->ioaddr + SDHCI_HOST_CONTROL)); | |
62 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", | |
63 | readb(host->ioaddr + SDHCI_POWER_CONTROL), | |
64 | readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL)); | |
65 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", | |
2df3b71b | 66 | readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL), |
d129bceb PO |
67 | readw(host->ioaddr + SDHCI_CLOCK_CONTROL)); |
68 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", | |
69 | readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL), | |
70 | readl(host->ioaddr + SDHCI_INT_STATUS)); | |
71 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", | |
72 | readl(host->ioaddr + SDHCI_INT_ENABLE), | |
73 | readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)); | |
74 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", | |
75 | readw(host->ioaddr + SDHCI_ACMD12_ERR), | |
76 | readw(host->ioaddr + SDHCI_SLOT_INT_STATUS)); | |
77 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n", | |
78 | readl(host->ioaddr + SDHCI_CAPABILITIES), | |
79 | readl(host->ioaddr + SDHCI_MAX_CURRENT)); | |
80 | ||
81 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); | |
82 | } | |
83 | ||
84 | /*****************************************************************************\ | |
85 | * * | |
86 | * Low level functions * | |
87 | * * | |
88 | \*****************************************************************************/ | |
89 | ||
90 | static void sdhci_reset(struct sdhci_host *host, u8 mask) | |
91 | { | |
e16514d8 PO |
92 | unsigned long timeout; |
93 | ||
b8c86fc5 | 94 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
8a4da143 PO |
95 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & |
96 | SDHCI_CARD_PRESENT)) | |
97 | return; | |
98 | } | |
99 | ||
d129bceb PO |
100 | writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET); |
101 | ||
e16514d8 | 102 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
103 | host->clock = 0; |
104 | ||
e16514d8 PO |
105 | /* Wait max 100 ms */ |
106 | timeout = 100; | |
107 | ||
108 | /* hw clears the bit when it's done */ | |
109 | while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) { | |
110 | if (timeout == 0) { | |
acf1da45 | 111 | printk(KERN_ERR "%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
112 | mmc_hostname(host->mmc), (int)mask); |
113 | sdhci_dumpregs(host); | |
114 | return; | |
115 | } | |
116 | timeout--; | |
117 | mdelay(1); | |
d129bceb PO |
118 | } |
119 | } | |
120 | ||
121 | static void sdhci_init(struct sdhci_host *host) | |
122 | { | |
123 | u32 intmask; | |
124 | ||
125 | sdhci_reset(host, SDHCI_RESET_ALL); | |
126 | ||
3192a28f PO |
127 | intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
128 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | | |
129 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
130 | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | | |
a406f5a3 | 131 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | |
2134a922 PO |
132 | SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | |
133 | SDHCI_INT_ADMA_ERROR; | |
d129bceb PO |
134 | |
135 | writel(intmask, host->ioaddr + SDHCI_INT_ENABLE); | |
136 | writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb PO |
137 | } |
138 | ||
139 | static void sdhci_activate_led(struct sdhci_host *host) | |
140 | { | |
141 | u8 ctrl; | |
142 | ||
143 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
144 | ctrl |= SDHCI_CTRL_LED; | |
145 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
146 | } | |
147 | ||
148 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
149 | { | |
150 | u8 ctrl; | |
151 | ||
152 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
153 | ctrl &= ~SDHCI_CTRL_LED; | |
154 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
155 | } | |
156 | ||
f9134319 | 157 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
158 | static void sdhci_led_control(struct led_classdev *led, |
159 | enum led_brightness brightness) | |
160 | { | |
161 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
162 | unsigned long flags; | |
163 | ||
164 | spin_lock_irqsave(&host->lock, flags); | |
165 | ||
166 | if (brightness == LED_OFF) | |
167 | sdhci_deactivate_led(host); | |
168 | else | |
169 | sdhci_activate_led(host); | |
170 | ||
171 | spin_unlock_irqrestore(&host->lock, flags); | |
172 | } | |
173 | #endif | |
174 | ||
d129bceb PO |
175 | /*****************************************************************************\ |
176 | * * | |
177 | * Core functions * | |
178 | * * | |
179 | \*****************************************************************************/ | |
180 | ||
a406f5a3 | 181 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 182 | { |
7659150c PO |
183 | unsigned long flags; |
184 | size_t blksize, len, chunk; | |
7244b85b | 185 | u32 uninitialized_var(scratch); |
7659150c | 186 | u8 *buf; |
d129bceb | 187 | |
a406f5a3 | 188 | DBG("PIO reading\n"); |
d129bceb | 189 | |
a406f5a3 | 190 | blksize = host->data->blksz; |
7659150c | 191 | chunk = 0; |
d129bceb | 192 | |
7659150c | 193 | local_irq_save(flags); |
d129bceb | 194 | |
a406f5a3 | 195 | while (blksize) { |
7659150c PO |
196 | if (!sg_miter_next(&host->sg_miter)) |
197 | BUG(); | |
d129bceb | 198 | |
7659150c | 199 | len = min(host->sg_miter.length, blksize); |
d129bceb | 200 | |
7659150c PO |
201 | blksize -= len; |
202 | host->sg_miter.consumed = len; | |
14d836e7 | 203 | |
7659150c | 204 | buf = host->sg_miter.addr; |
d129bceb | 205 | |
7659150c PO |
206 | while (len) { |
207 | if (chunk == 0) { | |
208 | scratch = readl(host->ioaddr + SDHCI_BUFFER); | |
209 | chunk = 4; | |
a406f5a3 | 210 | } |
7659150c PO |
211 | |
212 | *buf = scratch & 0xFF; | |
213 | ||
214 | buf++; | |
215 | scratch >>= 8; | |
216 | chunk--; | |
217 | len--; | |
d129bceb | 218 | } |
a406f5a3 | 219 | } |
7659150c PO |
220 | |
221 | sg_miter_stop(&host->sg_miter); | |
222 | ||
223 | local_irq_restore(flags); | |
a406f5a3 | 224 | } |
d129bceb | 225 | |
a406f5a3 PO |
226 | static void sdhci_write_block_pio(struct sdhci_host *host) |
227 | { | |
7659150c PO |
228 | unsigned long flags; |
229 | size_t blksize, len, chunk; | |
230 | u32 scratch; | |
231 | u8 *buf; | |
d129bceb | 232 | |
a406f5a3 PO |
233 | DBG("PIO writing\n"); |
234 | ||
235 | blksize = host->data->blksz; | |
7659150c PO |
236 | chunk = 0; |
237 | scratch = 0; | |
d129bceb | 238 | |
7659150c | 239 | local_irq_save(flags); |
d129bceb | 240 | |
a406f5a3 | 241 | while (blksize) { |
7659150c PO |
242 | if (!sg_miter_next(&host->sg_miter)) |
243 | BUG(); | |
a406f5a3 | 244 | |
7659150c PO |
245 | len = min(host->sg_miter.length, blksize); |
246 | ||
247 | blksize -= len; | |
248 | host->sg_miter.consumed = len; | |
249 | ||
250 | buf = host->sg_miter.addr; | |
d129bceb | 251 | |
7659150c PO |
252 | while (len) { |
253 | scratch |= (u32)*buf << (chunk * 8); | |
254 | ||
255 | buf++; | |
256 | chunk++; | |
257 | len--; | |
258 | ||
259 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
260 | writel(scratch, host->ioaddr + SDHCI_BUFFER); | |
261 | chunk = 0; | |
262 | scratch = 0; | |
d129bceb | 263 | } |
d129bceb PO |
264 | } |
265 | } | |
7659150c PO |
266 | |
267 | sg_miter_stop(&host->sg_miter); | |
268 | ||
269 | local_irq_restore(flags); | |
a406f5a3 PO |
270 | } |
271 | ||
272 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
273 | { | |
274 | u32 mask; | |
275 | ||
276 | BUG_ON(!host->data); | |
277 | ||
7659150c | 278 | if (host->blocks == 0) |
a406f5a3 PO |
279 | return; |
280 | ||
281 | if (host->data->flags & MMC_DATA_READ) | |
282 | mask = SDHCI_DATA_AVAILABLE; | |
283 | else | |
284 | mask = SDHCI_SPACE_AVAILABLE; | |
285 | ||
4a3cba32 PO |
286 | /* |
287 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
288 | * for transfers < 4 bytes. As long as it is just one block, | |
289 | * we can ignore the bits. | |
290 | */ | |
291 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
292 | (host->data->blocks == 1)) | |
293 | mask = ~0; | |
294 | ||
a406f5a3 PO |
295 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { |
296 | if (host->data->flags & MMC_DATA_READ) | |
297 | sdhci_read_block_pio(host); | |
298 | else | |
299 | sdhci_write_block_pio(host); | |
d129bceb | 300 | |
7659150c PO |
301 | host->blocks--; |
302 | if (host->blocks == 0) | |
a406f5a3 | 303 | break; |
a406f5a3 | 304 | } |
d129bceb | 305 | |
a406f5a3 | 306 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
307 | } |
308 | ||
2134a922 PO |
309 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
310 | { | |
311 | local_irq_save(*flags); | |
312 | return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; | |
313 | } | |
314 | ||
315 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
316 | { | |
317 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); | |
318 | local_irq_restore(*flags); | |
319 | } | |
320 | ||
8f1934ce | 321 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
2134a922 PO |
322 | struct mmc_data *data) |
323 | { | |
324 | int direction; | |
325 | ||
326 | u8 *desc; | |
327 | u8 *align; | |
328 | dma_addr_t addr; | |
329 | dma_addr_t align_addr; | |
330 | int len, offset; | |
331 | ||
332 | struct scatterlist *sg; | |
333 | int i; | |
334 | char *buffer; | |
335 | unsigned long flags; | |
336 | ||
337 | /* | |
338 | * The spec does not specify endianness of descriptor table. | |
339 | * We currently guess that it is LE. | |
340 | */ | |
341 | ||
342 | if (data->flags & MMC_DATA_READ) | |
343 | direction = DMA_FROM_DEVICE; | |
344 | else | |
345 | direction = DMA_TO_DEVICE; | |
346 | ||
347 | /* | |
348 | * The ADMA descriptor table is mapped further down as we | |
349 | * need to fill it with data first. | |
350 | */ | |
351 | ||
352 | host->align_addr = dma_map_single(mmc_dev(host->mmc), | |
353 | host->align_buffer, 128 * 4, direction); | |
8d8bb39b | 354 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
8f1934ce | 355 | goto fail; |
2134a922 PO |
356 | BUG_ON(host->align_addr & 0x3); |
357 | ||
358 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), | |
359 | data->sg, data->sg_len, direction); | |
8f1934ce PO |
360 | if (host->sg_count == 0) |
361 | goto unmap_align; | |
2134a922 PO |
362 | |
363 | desc = host->adma_desc; | |
364 | align = host->align_buffer; | |
365 | ||
366 | align_addr = host->align_addr; | |
367 | ||
368 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
369 | addr = sg_dma_address(sg); | |
370 | len = sg_dma_len(sg); | |
371 | ||
372 | /* | |
373 | * The SDHCI specification states that ADMA | |
374 | * addresses must be 32-bit aligned. If they | |
375 | * aren't, then we use a bounce buffer for | |
376 | * the (up to three) bytes that screw up the | |
377 | * alignment. | |
378 | */ | |
379 | offset = (4 - (addr & 0x3)) & 0x3; | |
380 | if (offset) { | |
381 | if (data->flags & MMC_DATA_WRITE) { | |
382 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 383 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
384 | memcpy(align, buffer, offset); |
385 | sdhci_kunmap_atomic(buffer, &flags); | |
386 | } | |
387 | ||
388 | desc[7] = (align_addr >> 24) & 0xff; | |
389 | desc[6] = (align_addr >> 16) & 0xff; | |
390 | desc[5] = (align_addr >> 8) & 0xff; | |
391 | desc[4] = (align_addr >> 0) & 0xff; | |
392 | ||
393 | BUG_ON(offset > 65536); | |
394 | ||
395 | desc[3] = (offset >> 8) & 0xff; | |
396 | desc[2] = (offset >> 0) & 0xff; | |
397 | ||
398 | desc[1] = 0x00; | |
399 | desc[0] = 0x21; /* tran, valid */ | |
400 | ||
401 | align += 4; | |
402 | align_addr += 4; | |
403 | ||
404 | desc += 8; | |
405 | ||
406 | addr += offset; | |
407 | len -= offset; | |
408 | } | |
409 | ||
410 | desc[7] = (addr >> 24) & 0xff; | |
411 | desc[6] = (addr >> 16) & 0xff; | |
412 | desc[5] = (addr >> 8) & 0xff; | |
413 | desc[4] = (addr >> 0) & 0xff; | |
414 | ||
415 | BUG_ON(len > 65536); | |
416 | ||
417 | desc[3] = (len >> 8) & 0xff; | |
418 | desc[2] = (len >> 0) & 0xff; | |
419 | ||
420 | desc[1] = 0x00; | |
421 | desc[0] = 0x21; /* tran, valid */ | |
422 | ||
423 | desc += 8; | |
424 | ||
425 | /* | |
426 | * If this triggers then we have a calculation bug | |
427 | * somewhere. :/ | |
428 | */ | |
429 | WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); | |
430 | } | |
431 | ||
432 | /* | |
433 | * Add a terminating entry. | |
434 | */ | |
435 | desc[7] = 0; | |
436 | desc[6] = 0; | |
437 | desc[5] = 0; | |
438 | desc[4] = 0; | |
439 | ||
440 | desc[3] = 0; | |
441 | desc[2] = 0; | |
442 | ||
443 | desc[1] = 0x00; | |
444 | desc[0] = 0x03; /* nop, end, valid */ | |
445 | ||
446 | /* | |
447 | * Resync align buffer as we might have changed it. | |
448 | */ | |
449 | if (data->flags & MMC_DATA_WRITE) { | |
450 | dma_sync_single_for_device(mmc_dev(host->mmc), | |
451 | host->align_addr, 128 * 4, direction); | |
452 | } | |
453 | ||
454 | host->adma_addr = dma_map_single(mmc_dev(host->mmc), | |
455 | host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
980167b7 | 456 | if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) |
8f1934ce | 457 | goto unmap_entries; |
2134a922 | 458 | BUG_ON(host->adma_addr & 0x3); |
8f1934ce PO |
459 | |
460 | return 0; | |
461 | ||
462 | unmap_entries: | |
463 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
464 | data->sg_len, direction); | |
465 | unmap_align: | |
466 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
467 | 128 * 4, direction); | |
468 | fail: | |
469 | return -EINVAL; | |
2134a922 PO |
470 | } |
471 | ||
472 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
473 | struct mmc_data *data) | |
474 | { | |
475 | int direction; | |
476 | ||
477 | struct scatterlist *sg; | |
478 | int i, size; | |
479 | u8 *align; | |
480 | char *buffer; | |
481 | unsigned long flags; | |
482 | ||
483 | if (data->flags & MMC_DATA_READ) | |
484 | direction = DMA_FROM_DEVICE; | |
485 | else | |
486 | direction = DMA_TO_DEVICE; | |
487 | ||
488 | dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, | |
489 | (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
490 | ||
491 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
492 | 128 * 4, direction); | |
493 | ||
494 | if (data->flags & MMC_DATA_READ) { | |
495 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | |
496 | data->sg_len, direction); | |
497 | ||
498 | align = host->align_buffer; | |
499 | ||
500 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
501 | if (sg_dma_address(sg) & 0x3) { | |
502 | size = 4 - (sg_dma_address(sg) & 0x3); | |
503 | ||
504 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 505 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
506 | memcpy(buffer, align, size); |
507 | sdhci_kunmap_atomic(buffer, &flags); | |
508 | ||
509 | align += 4; | |
510 | } | |
511 | } | |
512 | } | |
513 | ||
514 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
515 | data->sg_len, direction); | |
516 | } | |
517 | ||
ee53ab5d | 518 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data) |
d129bceb | 519 | { |
1c8cde92 PO |
520 | u8 count; |
521 | unsigned target_timeout, current_timeout; | |
d129bceb | 522 | |
ee53ab5d PO |
523 | /* |
524 | * If the host controller provides us with an incorrect timeout | |
525 | * value, just skip the check and use 0xE. The hardware may take | |
526 | * longer to time out, but that's much better than having a too-short | |
527 | * timeout value. | |
528 | */ | |
529 | if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)) | |
530 | return 0xE; | |
e538fbe8 | 531 | |
1c8cde92 PO |
532 | /* timeout in us */ |
533 | target_timeout = data->timeout_ns / 1000 + | |
534 | data->timeout_clks / host->clock; | |
d129bceb | 535 | |
1c8cde92 PO |
536 | /* |
537 | * Figure out needed cycles. | |
538 | * We do this in steps in order to fit inside a 32 bit int. | |
539 | * The first step is the minimum timeout, which will have a | |
540 | * minimum resolution of 6 bits: | |
541 | * (1) 2^13*1000 > 2^22, | |
542 | * (2) host->timeout_clk < 2^16 | |
543 | * => | |
544 | * (1) / (2) > 2^6 | |
545 | */ | |
546 | count = 0; | |
547 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
548 | while (current_timeout < target_timeout) { | |
549 | count++; | |
550 | current_timeout <<= 1; | |
551 | if (count >= 0xF) | |
552 | break; | |
553 | } | |
554 | ||
555 | if (count >= 0xF) { | |
556 | printk(KERN_WARNING "%s: Too large timeout requested!\n", | |
557 | mmc_hostname(host->mmc)); | |
558 | count = 0xE; | |
559 | } | |
560 | ||
ee53ab5d PO |
561 | return count; |
562 | } | |
563 | ||
564 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) | |
565 | { | |
566 | u8 count; | |
2134a922 | 567 | u8 ctrl; |
8f1934ce | 568 | int ret; |
ee53ab5d PO |
569 | |
570 | WARN_ON(host->data); | |
571 | ||
572 | if (data == NULL) | |
573 | return; | |
574 | ||
575 | /* Sanity checks */ | |
576 | BUG_ON(data->blksz * data->blocks > 524288); | |
577 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
578 | BUG_ON(data->blocks > 65535); | |
579 | ||
580 | host->data = data; | |
581 | host->data_early = 0; | |
582 | ||
583 | count = sdhci_calc_timeout(host, data); | |
1c8cde92 | 584 | writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL); |
d129bceb | 585 | |
c9fddbc4 PO |
586 | if (host->flags & SDHCI_USE_DMA) |
587 | host->flags |= SDHCI_REQ_USE_DMA; | |
588 | ||
2134a922 PO |
589 | /* |
590 | * FIXME: This doesn't account for merging when mapping the | |
591 | * scatterlist. | |
592 | */ | |
593 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
594 | int broken, i; | |
595 | struct scatterlist *sg; | |
596 | ||
597 | broken = 0; | |
598 | if (host->flags & SDHCI_USE_ADMA) { | |
599 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
600 | broken = 1; | |
601 | } else { | |
602 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
603 | broken = 1; | |
604 | } | |
605 | ||
606 | if (unlikely(broken)) { | |
607 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
608 | if (sg->length & 0x3) { | |
609 | DBG("Reverting to PIO because of " | |
610 | "transfer size (%d)\n", | |
611 | sg->length); | |
612 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
613 | break; | |
614 | } | |
615 | } | |
616 | } | |
c9fddbc4 PO |
617 | } |
618 | ||
619 | /* | |
620 | * The assumption here being that alignment is the same after | |
621 | * translation to device address space. | |
622 | */ | |
2134a922 PO |
623 | if (host->flags & SDHCI_REQ_USE_DMA) { |
624 | int broken, i; | |
625 | struct scatterlist *sg; | |
626 | ||
627 | broken = 0; | |
628 | if (host->flags & SDHCI_USE_ADMA) { | |
629 | /* | |
630 | * As we use 3 byte chunks to work around | |
631 | * alignment problems, we need to check this | |
632 | * quirk. | |
633 | */ | |
634 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
635 | broken = 1; | |
636 | } else { | |
637 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) | |
638 | broken = 1; | |
639 | } | |
640 | ||
641 | if (unlikely(broken)) { | |
642 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
643 | if (sg->offset & 0x3) { | |
644 | DBG("Reverting to PIO because of " | |
645 | "bad alignment\n"); | |
646 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
647 | break; | |
648 | } | |
649 | } | |
650 | } | |
651 | } | |
652 | ||
8f1934ce PO |
653 | if (host->flags & SDHCI_REQ_USE_DMA) { |
654 | if (host->flags & SDHCI_USE_ADMA) { | |
655 | ret = sdhci_adma_table_pre(host, data); | |
656 | if (ret) { | |
657 | /* | |
658 | * This only happens when someone fed | |
659 | * us an invalid request. | |
660 | */ | |
661 | WARN_ON(1); | |
ebd6d357 | 662 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce PO |
663 | } else { |
664 | writel(host->adma_addr, | |
665 | host->ioaddr + SDHCI_ADMA_ADDRESS); | |
666 | } | |
667 | } else { | |
c8b3e02e | 668 | int sg_cnt; |
8f1934ce | 669 | |
c8b3e02e | 670 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
8f1934ce PO |
671 | data->sg, data->sg_len, |
672 | (data->flags & MMC_DATA_READ) ? | |
673 | DMA_FROM_DEVICE : | |
674 | DMA_TO_DEVICE); | |
c8b3e02e | 675 | if (sg_cnt == 0) { |
8f1934ce PO |
676 | /* |
677 | * This only happens when someone fed | |
678 | * us an invalid request. | |
679 | */ | |
680 | WARN_ON(1); | |
ebd6d357 | 681 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 682 | } else { |
719a61b4 | 683 | WARN_ON(sg_cnt != 1); |
8f1934ce PO |
684 | writel(sg_dma_address(data->sg), |
685 | host->ioaddr + SDHCI_DMA_ADDRESS); | |
686 | } | |
687 | } | |
688 | } | |
689 | ||
2134a922 PO |
690 | /* |
691 | * Always adjust the DMA selection as some controllers | |
692 | * (e.g. JMicron) can't do PIO properly when the selection | |
693 | * is ADMA. | |
694 | */ | |
695 | if (host->version >= SDHCI_SPEC_200) { | |
696 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
697 | ctrl &= ~SDHCI_CTRL_DMA_MASK; | |
698 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
699 | (host->flags & SDHCI_USE_ADMA)) | |
700 | ctrl |= SDHCI_CTRL_ADMA32; | |
701 | else | |
702 | ctrl |= SDHCI_CTRL_SDMA; | |
703 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
c9fddbc4 PO |
704 | } |
705 | ||
8f1934ce | 706 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
7659150c PO |
707 | sg_miter_start(&host->sg_miter, |
708 | data->sg, data->sg_len, SG_MITER_ATOMIC); | |
709 | host->blocks = data->blocks; | |
d129bceb | 710 | } |
c7fa9963 | 711 | |
bab76961 PO |
712 | /* We do not handle DMA boundaries, so set it to max (512 KiB) */ |
713 | writew(SDHCI_MAKE_BLKSZ(7, data->blksz), | |
714 | host->ioaddr + SDHCI_BLOCK_SIZE); | |
c7fa9963 PO |
715 | writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT); |
716 | } | |
717 | ||
718 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
719 | struct mmc_data *data) | |
720 | { | |
721 | u16 mode; | |
722 | ||
c7fa9963 PO |
723 | if (data == NULL) |
724 | return; | |
725 | ||
e538fbe8 PO |
726 | WARN_ON(!host->data); |
727 | ||
c7fa9963 PO |
728 | mode = SDHCI_TRNS_BLK_CNT_EN; |
729 | if (data->blocks > 1) | |
730 | mode |= SDHCI_TRNS_MULTI; | |
731 | if (data->flags & MMC_DATA_READ) | |
732 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 733 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
734 | mode |= SDHCI_TRNS_DMA; |
735 | ||
736 | writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); | |
d129bceb PO |
737 | } |
738 | ||
739 | static void sdhci_finish_data(struct sdhci_host *host) | |
740 | { | |
741 | struct mmc_data *data; | |
d129bceb PO |
742 | |
743 | BUG_ON(!host->data); | |
744 | ||
745 | data = host->data; | |
746 | host->data = NULL; | |
747 | ||
c9fddbc4 | 748 | if (host->flags & SDHCI_REQ_USE_DMA) { |
2134a922 PO |
749 | if (host->flags & SDHCI_USE_ADMA) |
750 | sdhci_adma_table_post(host, data); | |
751 | else { | |
752 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
753 | data->sg_len, (data->flags & MMC_DATA_READ) ? | |
754 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
755 | } | |
d129bceb PO |
756 | } |
757 | ||
758 | /* | |
c9b74c5b PO |
759 | * The specification states that the block count register must |
760 | * be updated, but it does not specify at what point in the | |
761 | * data flow. That makes the register entirely useless to read | |
762 | * back so we have to assume that nothing made it to the card | |
763 | * in the event of an error. | |
d129bceb | 764 | */ |
c9b74c5b PO |
765 | if (data->error) |
766 | data->bytes_xfered = 0; | |
d129bceb | 767 | else |
c9b74c5b | 768 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 769 | |
d129bceb PO |
770 | if (data->stop) { |
771 | /* | |
772 | * The controller needs a reset of internal state machines | |
773 | * upon error conditions. | |
774 | */ | |
17b0429d | 775 | if (data->error) { |
d129bceb PO |
776 | sdhci_reset(host, SDHCI_RESET_CMD); |
777 | sdhci_reset(host, SDHCI_RESET_DATA); | |
778 | } | |
779 | ||
780 | sdhci_send_command(host, data->stop); | |
781 | } else | |
782 | tasklet_schedule(&host->finish_tasklet); | |
783 | } | |
784 | ||
785 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
786 | { | |
787 | int flags; | |
fd2208d7 | 788 | u32 mask; |
7cb2c76f | 789 | unsigned long timeout; |
d129bceb PO |
790 | |
791 | WARN_ON(host->cmd); | |
792 | ||
d129bceb | 793 | /* Wait max 10 ms */ |
7cb2c76f | 794 | timeout = 10; |
fd2208d7 PO |
795 | |
796 | mask = SDHCI_CMD_INHIBIT; | |
797 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
798 | mask |= SDHCI_DATA_INHIBIT; | |
799 | ||
800 | /* We shouldn't wait for data inihibit for stop commands, even | |
801 | though they might use busy signaling */ | |
802 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
803 | mask &= ~SDHCI_DATA_INHIBIT; | |
804 | ||
805 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { | |
7cb2c76f | 806 | if (timeout == 0) { |
d129bceb | 807 | printk(KERN_ERR "%s: Controller never released " |
acf1da45 | 808 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 809 | sdhci_dumpregs(host); |
17b0429d | 810 | cmd->error = -EIO; |
d129bceb PO |
811 | tasklet_schedule(&host->finish_tasklet); |
812 | return; | |
813 | } | |
7cb2c76f PO |
814 | timeout--; |
815 | mdelay(1); | |
816 | } | |
d129bceb PO |
817 | |
818 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
819 | ||
820 | host->cmd = cmd; | |
821 | ||
822 | sdhci_prepare_data(host, cmd->data); | |
823 | ||
824 | writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT); | |
825 | ||
c7fa9963 PO |
826 | sdhci_set_transfer_mode(host, cmd->data); |
827 | ||
d129bceb | 828 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
acf1da45 | 829 | printk(KERN_ERR "%s: Unsupported response type!\n", |
d129bceb | 830 | mmc_hostname(host->mmc)); |
17b0429d | 831 | cmd->error = -EINVAL; |
d129bceb PO |
832 | tasklet_schedule(&host->finish_tasklet); |
833 | return; | |
834 | } | |
835 | ||
836 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
837 | flags = SDHCI_CMD_RESP_NONE; | |
838 | else if (cmd->flags & MMC_RSP_136) | |
839 | flags = SDHCI_CMD_RESP_LONG; | |
840 | else if (cmd->flags & MMC_RSP_BUSY) | |
841 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
842 | else | |
843 | flags = SDHCI_CMD_RESP_SHORT; | |
844 | ||
845 | if (cmd->flags & MMC_RSP_CRC) | |
846 | flags |= SDHCI_CMD_CRC; | |
847 | if (cmd->flags & MMC_RSP_OPCODE) | |
848 | flags |= SDHCI_CMD_INDEX; | |
849 | if (cmd->data) | |
850 | flags |= SDHCI_CMD_DATA; | |
851 | ||
fb61e289 | 852 | writew(SDHCI_MAKE_CMD(cmd->opcode, flags), |
d129bceb PO |
853 | host->ioaddr + SDHCI_COMMAND); |
854 | } | |
855 | ||
856 | static void sdhci_finish_command(struct sdhci_host *host) | |
857 | { | |
858 | int i; | |
859 | ||
860 | BUG_ON(host->cmd == NULL); | |
861 | ||
862 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
863 | if (host->cmd->flags & MMC_RSP_136) { | |
864 | /* CRC is stripped so we need to do some shifting. */ | |
865 | for (i = 0;i < 4;i++) { | |
866 | host->cmd->resp[i] = readl(host->ioaddr + | |
867 | SDHCI_RESPONSE + (3-i)*4) << 8; | |
868 | if (i != 3) | |
869 | host->cmd->resp[i] |= | |
870 | readb(host->ioaddr + | |
871 | SDHCI_RESPONSE + (3-i)*4-1); | |
872 | } | |
873 | } else { | |
874 | host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE); | |
875 | } | |
876 | } | |
877 | ||
17b0429d | 878 | host->cmd->error = 0; |
d129bceb | 879 | |
e538fbe8 PO |
880 | if (host->data && host->data_early) |
881 | sdhci_finish_data(host); | |
882 | ||
883 | if (!host->cmd->data) | |
d129bceb PO |
884 | tasklet_schedule(&host->finish_tasklet); |
885 | ||
886 | host->cmd = NULL; | |
887 | } | |
888 | ||
889 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
890 | { | |
891 | int div; | |
892 | u16 clk; | |
7cb2c76f | 893 | unsigned long timeout; |
d129bceb PO |
894 | |
895 | if (clock == host->clock) | |
896 | return; | |
897 | ||
898 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
899 | ||
900 | if (clock == 0) | |
901 | goto out; | |
902 | ||
903 | for (div = 1;div < 256;div *= 2) { | |
904 | if ((host->max_clk / div) <= clock) | |
905 | break; | |
906 | } | |
907 | div >>= 1; | |
908 | ||
909 | clk = div << SDHCI_DIVIDER_SHIFT; | |
910 | clk |= SDHCI_CLOCK_INT_EN; | |
911 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
912 | ||
913 | /* Wait max 10 ms */ | |
7cb2c76f PO |
914 | timeout = 10; |
915 | while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL)) | |
916 | & SDHCI_CLOCK_INT_STABLE)) { | |
917 | if (timeout == 0) { | |
acf1da45 PO |
918 | printk(KERN_ERR "%s: Internal clock never " |
919 | "stabilised.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
920 | sdhci_dumpregs(host); |
921 | return; | |
922 | } | |
7cb2c76f PO |
923 | timeout--; |
924 | mdelay(1); | |
925 | } | |
d129bceb PO |
926 | |
927 | clk |= SDHCI_CLOCK_CARD_EN; | |
928 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
929 | ||
930 | out: | |
931 | host->clock = clock; | |
932 | } | |
933 | ||
146ad66e PO |
934 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
935 | { | |
936 | u8 pwr; | |
937 | ||
938 | if (host->power == power) | |
939 | return; | |
940 | ||
9e9dc5f2 DS |
941 | if (power == (unsigned short)-1) { |
942 | writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); | |
146ad66e | 943 | goto out; |
9e9dc5f2 DS |
944 | } |
945 | ||
946 | /* | |
947 | * Spec says that we should clear the power reg before setting | |
948 | * a new value. Some controllers don't seem to like this though. | |
949 | */ | |
b8c86fc5 | 950 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
9e9dc5f2 | 951 | writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); |
146ad66e PO |
952 | |
953 | pwr = SDHCI_POWER_ON; | |
954 | ||
4be34c99 | 955 | switch (1 << power) { |
55556da0 | 956 | case MMC_VDD_165_195: |
146ad66e PO |
957 | pwr |= SDHCI_POWER_180; |
958 | break; | |
4be34c99 PL |
959 | case MMC_VDD_29_30: |
960 | case MMC_VDD_30_31: | |
146ad66e PO |
961 | pwr |= SDHCI_POWER_300; |
962 | break; | |
4be34c99 PL |
963 | case MMC_VDD_32_33: |
964 | case MMC_VDD_33_34: | |
146ad66e PO |
965 | pwr |= SDHCI_POWER_330; |
966 | break; | |
967 | default: | |
968 | BUG(); | |
969 | } | |
970 | ||
e08c1694 | 971 | /* |
c71f6512 | 972 | * At least the Marvell CaFe chip gets confused if we set the voltage |
e08c1694 AS |
973 | * and set turn on power at the same time, so set the voltage first. |
974 | */ | |
b8c86fc5 | 975 | if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)) |
e08c1694 AS |
976 | writeb(pwr & ~SDHCI_POWER_ON, |
977 | host->ioaddr + SDHCI_POWER_CONTROL); | |
978 | ||
146ad66e PO |
979 | writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); |
980 | ||
981 | out: | |
982 | host->power = power; | |
983 | } | |
984 | ||
d129bceb PO |
985 | /*****************************************************************************\ |
986 | * * | |
987 | * MMC callbacks * | |
988 | * * | |
989 | \*****************************************************************************/ | |
990 | ||
991 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
992 | { | |
993 | struct sdhci_host *host; | |
994 | unsigned long flags; | |
995 | ||
996 | host = mmc_priv(mmc); | |
997 | ||
998 | spin_lock_irqsave(&host->lock, flags); | |
999 | ||
1000 | WARN_ON(host->mrq != NULL); | |
1001 | ||
f9134319 | 1002 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1003 | sdhci_activate_led(host); |
2f730fec | 1004 | #endif |
d129bceb PO |
1005 | |
1006 | host->mrq = mrq; | |
1007 | ||
1e72859e PO |
1008 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) |
1009 | || (host->flags & SDHCI_DEVICE_DEAD)) { | |
17b0429d | 1010 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1011 | tasklet_schedule(&host->finish_tasklet); |
1012 | } else | |
1013 | sdhci_send_command(host, mrq->cmd); | |
1014 | ||
5f25a66f | 1015 | mmiowb(); |
d129bceb PO |
1016 | spin_unlock_irqrestore(&host->lock, flags); |
1017 | } | |
1018 | ||
1019 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1020 | { | |
1021 | struct sdhci_host *host; | |
1022 | unsigned long flags; | |
1023 | u8 ctrl; | |
1024 | ||
1025 | host = mmc_priv(mmc); | |
1026 | ||
1027 | spin_lock_irqsave(&host->lock, flags); | |
1028 | ||
1e72859e PO |
1029 | if (host->flags & SDHCI_DEVICE_DEAD) |
1030 | goto out; | |
1031 | ||
d129bceb PO |
1032 | /* |
1033 | * Reset the chip on each power off. | |
1034 | * Should clear out any weird states. | |
1035 | */ | |
1036 | if (ios->power_mode == MMC_POWER_OFF) { | |
1037 | writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb | 1038 | sdhci_init(host); |
d129bceb PO |
1039 | } |
1040 | ||
1041 | sdhci_set_clock(host, ios->clock); | |
1042 | ||
1043 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 1044 | sdhci_set_power(host, -1); |
d129bceb | 1045 | else |
146ad66e | 1046 | sdhci_set_power(host, ios->vdd); |
d129bceb PO |
1047 | |
1048 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
cd9277c0 | 1049 | |
d129bceb PO |
1050 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
1051 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1052 | else | |
1053 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
cd9277c0 PO |
1054 | |
1055 | if (ios->timing == MMC_TIMING_SD_HS) | |
1056 | ctrl |= SDHCI_CTRL_HISPD; | |
1057 | else | |
1058 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1059 | ||
d129bceb PO |
1060 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); |
1061 | ||
b8352260 LD |
1062 | /* |
1063 | * Some (ENE) controllers go apeshit on some ios operation, | |
1064 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1065 | * it on each ios seems to solve the problem. | |
1066 | */ | |
b8c86fc5 | 1067 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
b8352260 LD |
1068 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
1069 | ||
1e72859e | 1070 | out: |
5f25a66f | 1071 | mmiowb(); |
d129bceb PO |
1072 | spin_unlock_irqrestore(&host->lock, flags); |
1073 | } | |
1074 | ||
1075 | static int sdhci_get_ro(struct mmc_host *mmc) | |
1076 | { | |
1077 | struct sdhci_host *host; | |
1078 | unsigned long flags; | |
1079 | int present; | |
1080 | ||
1081 | host = mmc_priv(mmc); | |
1082 | ||
1083 | spin_lock_irqsave(&host->lock, flags); | |
1084 | ||
1e72859e PO |
1085 | if (host->flags & SDHCI_DEVICE_DEAD) |
1086 | present = 0; | |
1087 | else | |
1088 | present = readl(host->ioaddr + SDHCI_PRESENT_STATE); | |
d129bceb PO |
1089 | |
1090 | spin_unlock_irqrestore(&host->lock, flags); | |
1091 | ||
1092 | return !(present & SDHCI_WRITE_PROTECT); | |
1093 | } | |
1094 | ||
f75979b7 PO |
1095 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1096 | { | |
1097 | struct sdhci_host *host; | |
1098 | unsigned long flags; | |
1099 | u32 ier; | |
1100 | ||
1101 | host = mmc_priv(mmc); | |
1102 | ||
1103 | spin_lock_irqsave(&host->lock, flags); | |
1104 | ||
1e72859e PO |
1105 | if (host->flags & SDHCI_DEVICE_DEAD) |
1106 | goto out; | |
1107 | ||
f75979b7 PO |
1108 | ier = readl(host->ioaddr + SDHCI_INT_ENABLE); |
1109 | ||
1110 | ier &= ~SDHCI_INT_CARD_INT; | |
1111 | if (enable) | |
1112 | ier |= SDHCI_INT_CARD_INT; | |
1113 | ||
1114 | writel(ier, host->ioaddr + SDHCI_INT_ENABLE); | |
1115 | writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
1116 | ||
1e72859e | 1117 | out: |
f75979b7 PO |
1118 | mmiowb(); |
1119 | ||
1120 | spin_unlock_irqrestore(&host->lock, flags); | |
1121 | } | |
1122 | ||
ab7aefd0 | 1123 | static const struct mmc_host_ops sdhci_ops = { |
d129bceb PO |
1124 | .request = sdhci_request, |
1125 | .set_ios = sdhci_set_ios, | |
1126 | .get_ro = sdhci_get_ro, | |
f75979b7 | 1127 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
d129bceb PO |
1128 | }; |
1129 | ||
1130 | /*****************************************************************************\ | |
1131 | * * | |
1132 | * Tasklets * | |
1133 | * * | |
1134 | \*****************************************************************************/ | |
1135 | ||
1136 | static void sdhci_tasklet_card(unsigned long param) | |
1137 | { | |
1138 | struct sdhci_host *host; | |
1139 | unsigned long flags; | |
1140 | ||
1141 | host = (struct sdhci_host*)param; | |
1142 | ||
1143 | spin_lock_irqsave(&host->lock, flags); | |
1144 | ||
1145 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { | |
1146 | if (host->mrq) { | |
1147 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
1148 | mmc_hostname(host->mmc)); | |
1149 | printk(KERN_ERR "%s: Resetting controller.\n", | |
1150 | mmc_hostname(host->mmc)); | |
1151 | ||
1152 | sdhci_reset(host, SDHCI_RESET_CMD); | |
1153 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1154 | ||
17b0429d | 1155 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1156 | tasklet_schedule(&host->finish_tasklet); |
1157 | } | |
1158 | } | |
1159 | ||
1160 | spin_unlock_irqrestore(&host->lock, flags); | |
1161 | ||
04cf585d | 1162 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); |
d129bceb PO |
1163 | } |
1164 | ||
1165 | static void sdhci_tasklet_finish(unsigned long param) | |
1166 | { | |
1167 | struct sdhci_host *host; | |
1168 | unsigned long flags; | |
1169 | struct mmc_request *mrq; | |
1170 | ||
1171 | host = (struct sdhci_host*)param; | |
1172 | ||
1173 | spin_lock_irqsave(&host->lock, flags); | |
1174 | ||
1175 | del_timer(&host->timer); | |
1176 | ||
1177 | mrq = host->mrq; | |
1178 | ||
d129bceb PO |
1179 | /* |
1180 | * The controller needs a reset of internal state machines | |
1181 | * upon error conditions. | |
1182 | */ | |
1e72859e PO |
1183 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
1184 | (mrq->cmd->error || | |
1185 | (mrq->data && (mrq->data->error || | |
1186 | (mrq->data->stop && mrq->data->stop->error))) || | |
1187 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
1188 | |
1189 | /* Some controllers need this kick or reset won't work here */ | |
b8c86fc5 | 1190 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { |
645289dc PO |
1191 | unsigned int clock; |
1192 | ||
1193 | /* This is to force an update */ | |
1194 | clock = host->clock; | |
1195 | host->clock = 0; | |
1196 | sdhci_set_clock(host, clock); | |
1197 | } | |
1198 | ||
1199 | /* Spec says we should do both at the same time, but Ricoh | |
1200 | controllers do not like that. */ | |
d129bceb PO |
1201 | sdhci_reset(host, SDHCI_RESET_CMD); |
1202 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1203 | } | |
1204 | ||
1205 | host->mrq = NULL; | |
1206 | host->cmd = NULL; | |
1207 | host->data = NULL; | |
1208 | ||
f9134319 | 1209 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1210 | sdhci_deactivate_led(host); |
2f730fec | 1211 | #endif |
d129bceb | 1212 | |
5f25a66f | 1213 | mmiowb(); |
d129bceb PO |
1214 | spin_unlock_irqrestore(&host->lock, flags); |
1215 | ||
1216 | mmc_request_done(host->mmc, mrq); | |
1217 | } | |
1218 | ||
1219 | static void sdhci_timeout_timer(unsigned long data) | |
1220 | { | |
1221 | struct sdhci_host *host; | |
1222 | unsigned long flags; | |
1223 | ||
1224 | host = (struct sdhci_host*)data; | |
1225 | ||
1226 | spin_lock_irqsave(&host->lock, flags); | |
1227 | ||
1228 | if (host->mrq) { | |
acf1da45 PO |
1229 | printk(KERN_ERR "%s: Timeout waiting for hardware " |
1230 | "interrupt.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1231 | sdhci_dumpregs(host); |
1232 | ||
1233 | if (host->data) { | |
17b0429d | 1234 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
1235 | sdhci_finish_data(host); |
1236 | } else { | |
1237 | if (host->cmd) | |
17b0429d | 1238 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 1239 | else |
17b0429d | 1240 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
1241 | |
1242 | tasklet_schedule(&host->finish_tasklet); | |
1243 | } | |
1244 | } | |
1245 | ||
5f25a66f | 1246 | mmiowb(); |
d129bceb PO |
1247 | spin_unlock_irqrestore(&host->lock, flags); |
1248 | } | |
1249 | ||
1250 | /*****************************************************************************\ | |
1251 | * * | |
1252 | * Interrupt handling * | |
1253 | * * | |
1254 | \*****************************************************************************/ | |
1255 | ||
1256 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
1257 | { | |
1258 | BUG_ON(intmask == 0); | |
1259 | ||
1260 | if (!host->cmd) { | |
b67ac3f3 PO |
1261 | printk(KERN_ERR "%s: Got command interrupt 0x%08x even " |
1262 | "though no command operation was in progress.\n", | |
1263 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1264 | sdhci_dumpregs(host); |
1265 | return; | |
1266 | } | |
1267 | ||
43b58b36 | 1268 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
1269 | host->cmd->error = -ETIMEDOUT; |
1270 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
1271 | SDHCI_INT_INDEX)) | |
1272 | host->cmd->error = -EILSEQ; | |
43b58b36 | 1273 | |
e809517f | 1274 | if (host->cmd->error) { |
d129bceb | 1275 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
1276 | return; |
1277 | } | |
1278 | ||
1279 | /* | |
1280 | * The host can send and interrupt when the busy state has | |
1281 | * ended, allowing us to wait without wasting CPU cycles. | |
1282 | * Unfortunately this is overloaded on the "data complete" | |
1283 | * interrupt, so we need to take some care when handling | |
1284 | * it. | |
1285 | * | |
1286 | * Note: The 1.0 specification is a bit ambiguous about this | |
1287 | * feature so there might be some problems with older | |
1288 | * controllers. | |
1289 | */ | |
1290 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
1291 | if (host->cmd->data) | |
1292 | DBG("Cannot wait for busy signal when also " | |
1293 | "doing a data transfer"); | |
1294 | else | |
1295 | return; | |
1296 | } | |
1297 | ||
1298 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 1299 | sdhci_finish_command(host); |
d129bceb PO |
1300 | } |
1301 | ||
1302 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) | |
1303 | { | |
1304 | BUG_ON(intmask == 0); | |
1305 | ||
1306 | if (!host->data) { | |
1307 | /* | |
e809517f PO |
1308 | * The "data complete" interrupt is also used to |
1309 | * indicate that a busy state has ended. See comment | |
1310 | * above in sdhci_cmd_irq(). | |
d129bceb | 1311 | */ |
e809517f PO |
1312 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
1313 | if (intmask & SDHCI_INT_DATA_END) { | |
1314 | sdhci_finish_command(host); | |
1315 | return; | |
1316 | } | |
1317 | } | |
d129bceb | 1318 | |
b67ac3f3 PO |
1319 | printk(KERN_ERR "%s: Got data interrupt 0x%08x even " |
1320 | "though no data operation was in progress.\n", | |
1321 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1322 | sdhci_dumpregs(host); |
1323 | ||
1324 | return; | |
1325 | } | |
1326 | ||
1327 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d PO |
1328 | host->data->error = -ETIMEDOUT; |
1329 | else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) | |
1330 | host->data->error = -EILSEQ; | |
2134a922 PO |
1331 | else if (intmask & SDHCI_INT_ADMA_ERROR) |
1332 | host->data->error = -EIO; | |
d129bceb | 1333 | |
17b0429d | 1334 | if (host->data->error) |
d129bceb PO |
1335 | sdhci_finish_data(host); |
1336 | else { | |
a406f5a3 | 1337 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
1338 | sdhci_transfer_pio(host); |
1339 | ||
6ba736a1 PO |
1340 | /* |
1341 | * We currently don't do anything fancy with DMA | |
1342 | * boundaries, but as we can't disable the feature | |
1343 | * we need to at least restart the transfer. | |
1344 | */ | |
1345 | if (intmask & SDHCI_INT_DMA_END) | |
1346 | writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS), | |
1347 | host->ioaddr + SDHCI_DMA_ADDRESS); | |
1348 | ||
e538fbe8 PO |
1349 | if (intmask & SDHCI_INT_DATA_END) { |
1350 | if (host->cmd) { | |
1351 | /* | |
1352 | * Data managed to finish before the | |
1353 | * command completed. Make sure we do | |
1354 | * things in the proper order. | |
1355 | */ | |
1356 | host->data_early = 1; | |
1357 | } else { | |
1358 | sdhci_finish_data(host); | |
1359 | } | |
1360 | } | |
d129bceb PO |
1361 | } |
1362 | } | |
1363 | ||
7d12e780 | 1364 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
1365 | { |
1366 | irqreturn_t result; | |
1367 | struct sdhci_host* host = dev_id; | |
1368 | u32 intmask; | |
f75979b7 | 1369 | int cardint = 0; |
d129bceb PO |
1370 | |
1371 | spin_lock(&host->lock); | |
1372 | ||
1373 | intmask = readl(host->ioaddr + SDHCI_INT_STATUS); | |
1374 | ||
62df67a5 | 1375 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
1376 | result = IRQ_NONE; |
1377 | goto out; | |
1378 | } | |
1379 | ||
b69c9058 PO |
1380 | DBG("*** %s got interrupt: 0x%08x\n", |
1381 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 1382 | |
3192a28f PO |
1383 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
1384 | writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE), | |
1385 | host->ioaddr + SDHCI_INT_STATUS); | |
d129bceb | 1386 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 1387 | } |
d129bceb | 1388 | |
3192a28f | 1389 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 1390 | |
3192a28f | 1391 | if (intmask & SDHCI_INT_CMD_MASK) { |
d129bceb PO |
1392 | writel(intmask & SDHCI_INT_CMD_MASK, |
1393 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1394 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1395 | } |
1396 | ||
1397 | if (intmask & SDHCI_INT_DATA_MASK) { | |
d129bceb PO |
1398 | writel(intmask & SDHCI_INT_DATA_MASK, |
1399 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1400 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1401 | } |
1402 | ||
1403 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1404 | ||
964f9ce2 PO |
1405 | intmask &= ~SDHCI_INT_ERROR; |
1406 | ||
d129bceb | 1407 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1408 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1409 | mmc_hostname(host->mmc)); |
3192a28f | 1410 | writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS); |
d129bceb PO |
1411 | } |
1412 | ||
9d26a5d3 | 1413 | intmask &= ~SDHCI_INT_BUS_POWER; |
3192a28f | 1414 | |
f75979b7 PO |
1415 | if (intmask & SDHCI_INT_CARD_INT) |
1416 | cardint = 1; | |
1417 | ||
1418 | intmask &= ~SDHCI_INT_CARD_INT; | |
1419 | ||
3192a28f | 1420 | if (intmask) { |
acf1da45 | 1421 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", |
3192a28f | 1422 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1423 | sdhci_dumpregs(host); |
1424 | ||
d129bceb | 1425 | writel(intmask, host->ioaddr + SDHCI_INT_STATUS); |
3192a28f | 1426 | } |
d129bceb PO |
1427 | |
1428 | result = IRQ_HANDLED; | |
1429 | ||
5f25a66f | 1430 | mmiowb(); |
d129bceb PO |
1431 | out: |
1432 | spin_unlock(&host->lock); | |
1433 | ||
f75979b7 PO |
1434 | /* |
1435 | * We have to delay this as it calls back into the driver. | |
1436 | */ | |
1437 | if (cardint) | |
1438 | mmc_signal_sdio_irq(host->mmc); | |
1439 | ||
d129bceb PO |
1440 | return result; |
1441 | } | |
1442 | ||
1443 | /*****************************************************************************\ | |
1444 | * * | |
1445 | * Suspend/resume * | |
1446 | * * | |
1447 | \*****************************************************************************/ | |
1448 | ||
1449 | #ifdef CONFIG_PM | |
1450 | ||
b8c86fc5 | 1451 | int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state) |
d129bceb | 1452 | { |
b8c86fc5 | 1453 | int ret; |
a715dfc7 | 1454 | |
b8c86fc5 PO |
1455 | ret = mmc_suspend_host(host->mmc, state); |
1456 | if (ret) | |
1457 | return ret; | |
a715dfc7 | 1458 | |
b8c86fc5 | 1459 | free_irq(host->irq, host); |
d129bceb PO |
1460 | |
1461 | return 0; | |
1462 | } | |
1463 | ||
b8c86fc5 | 1464 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 1465 | |
b8c86fc5 PO |
1466 | int sdhci_resume_host(struct sdhci_host *host) |
1467 | { | |
1468 | int ret; | |
d129bceb | 1469 | |
b8c86fc5 PO |
1470 | if (host->flags & SDHCI_USE_DMA) { |
1471 | if (host->ops->enable_dma) | |
1472 | host->ops->enable_dma(host); | |
1473 | } | |
d129bceb | 1474 | |
b8c86fc5 PO |
1475 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
1476 | mmc_hostname(host->mmc), host); | |
df1c4b7b PO |
1477 | if (ret) |
1478 | return ret; | |
d129bceb | 1479 | |
b8c86fc5 PO |
1480 | sdhci_init(host); |
1481 | mmiowb(); | |
1482 | ||
1483 | ret = mmc_resume_host(host->mmc); | |
1484 | if (ret) | |
1485 | return ret; | |
d129bceb PO |
1486 | |
1487 | return 0; | |
1488 | } | |
1489 | ||
b8c86fc5 | 1490 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
d129bceb PO |
1491 | |
1492 | #endif /* CONFIG_PM */ | |
1493 | ||
1494 | /*****************************************************************************\ | |
1495 | * * | |
b8c86fc5 | 1496 | * Device allocation/registration * |
d129bceb PO |
1497 | * * |
1498 | \*****************************************************************************/ | |
1499 | ||
b8c86fc5 PO |
1500 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
1501 | size_t priv_size) | |
d129bceb | 1502 | { |
d129bceb PO |
1503 | struct mmc_host *mmc; |
1504 | struct sdhci_host *host; | |
1505 | ||
b8c86fc5 | 1506 | WARN_ON(dev == NULL); |
d129bceb | 1507 | |
b8c86fc5 | 1508 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 1509 | if (!mmc) |
b8c86fc5 | 1510 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
1511 | |
1512 | host = mmc_priv(mmc); | |
1513 | host->mmc = mmc; | |
1514 | ||
b8c86fc5 PO |
1515 | return host; |
1516 | } | |
8a4da143 | 1517 | |
b8c86fc5 | 1518 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 1519 | |
b8c86fc5 PO |
1520 | int sdhci_add_host(struct sdhci_host *host) |
1521 | { | |
1522 | struct mmc_host *mmc; | |
1523 | unsigned int caps; | |
b8c86fc5 | 1524 | int ret; |
d129bceb | 1525 | |
b8c86fc5 PO |
1526 | WARN_ON(host == NULL); |
1527 | if (host == NULL) | |
1528 | return -EINVAL; | |
d129bceb | 1529 | |
b8c86fc5 | 1530 | mmc = host->mmc; |
d129bceb | 1531 | |
b8c86fc5 PO |
1532 | if (debug_quirks) |
1533 | host->quirks = debug_quirks; | |
d129bceb | 1534 | |
d96649ed PO |
1535 | sdhci_reset(host, SDHCI_RESET_ALL); |
1536 | ||
2134a922 PO |
1537 | host->version = readw(host->ioaddr + SDHCI_HOST_VERSION); |
1538 | host->version = (host->version & SDHCI_SPEC_VER_MASK) | |
1539 | >> SDHCI_SPEC_VER_SHIFT; | |
1540 | if (host->version > SDHCI_SPEC_200) { | |
4a965505 | 1541 | printk(KERN_ERR "%s: Unknown controller version (%d). " |
b69c9058 | 1542 | "You may experience problems.\n", mmc_hostname(mmc), |
2134a922 | 1543 | host->version); |
4a965505 PO |
1544 | } |
1545 | ||
d129bceb PO |
1546 | caps = readl(host->ioaddr + SDHCI_CAPABILITIES); |
1547 | ||
b8c86fc5 | 1548 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
98608076 | 1549 | host->flags |= SDHCI_USE_DMA; |
67435274 PO |
1550 | else if (!(caps & SDHCI_CAN_DO_DMA)) |
1551 | DBG("Controller doesn't have DMA capability\n"); | |
1552 | else | |
d129bceb PO |
1553 | host->flags |= SDHCI_USE_DMA; |
1554 | ||
b8c86fc5 | 1555 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
7c168e3d | 1556 | (host->flags & SDHCI_USE_DMA)) { |
cee687ce | 1557 | DBG("Disabling DMA as it is marked broken\n"); |
7c168e3d FT |
1558 | host->flags &= ~SDHCI_USE_DMA; |
1559 | } | |
1560 | ||
2134a922 PO |
1561 | if (host->flags & SDHCI_USE_DMA) { |
1562 | if ((host->version >= SDHCI_SPEC_200) && | |
1563 | (caps & SDHCI_CAN_DO_ADMA2)) | |
1564 | host->flags |= SDHCI_USE_ADMA; | |
1565 | } | |
1566 | ||
1567 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
1568 | (host->flags & SDHCI_USE_ADMA)) { | |
1569 | DBG("Disabling ADMA as it is marked broken\n"); | |
1570 | host->flags &= ~SDHCI_USE_ADMA; | |
1571 | } | |
1572 | ||
d129bceb | 1573 | if (host->flags & SDHCI_USE_DMA) { |
b8c86fc5 PO |
1574 | if (host->ops->enable_dma) { |
1575 | if (host->ops->enable_dma(host)) { | |
1576 | printk(KERN_WARNING "%s: No suitable DMA " | |
1577 | "available. Falling back to PIO.\n", | |
1578 | mmc_hostname(mmc)); | |
2134a922 | 1579 | host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA); |
b8c86fc5 | 1580 | } |
d129bceb PO |
1581 | } |
1582 | } | |
1583 | ||
2134a922 PO |
1584 | if (host->flags & SDHCI_USE_ADMA) { |
1585 | /* | |
1586 | * We need to allocate descriptors for all sg entries | |
1587 | * (128) and potentially one alignment transfer for | |
1588 | * each of those entries. | |
1589 | */ | |
1590 | host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); | |
1591 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); | |
1592 | if (!host->adma_desc || !host->align_buffer) { | |
1593 | kfree(host->adma_desc); | |
1594 | kfree(host->align_buffer); | |
1595 | printk(KERN_WARNING "%s: Unable to allocate ADMA " | |
1596 | "buffers. Falling back to standard DMA.\n", | |
1597 | mmc_hostname(mmc)); | |
1598 | host->flags &= ~SDHCI_USE_ADMA; | |
1599 | } | |
1600 | } | |
1601 | ||
7659150c PO |
1602 | /* |
1603 | * If we use DMA, then it's up to the caller to set the DMA | |
1604 | * mask, but PIO does not need the hw shim so we set a new | |
1605 | * mask here in that case. | |
1606 | */ | |
1607 | if (!(host->flags & SDHCI_USE_DMA)) { | |
1608 | host->dma_mask = DMA_BIT_MASK(64); | |
1609 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; | |
1610 | } | |
d129bceb | 1611 | |
8ef1a143 PO |
1612 | host->max_clk = |
1613 | (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; | |
1614 | if (host->max_clk == 0) { | |
1615 | printk(KERN_ERR "%s: Hardware doesn't specify base clock " | |
b69c9058 | 1616 | "frequency.\n", mmc_hostname(mmc)); |
b8c86fc5 | 1617 | return -ENODEV; |
8ef1a143 | 1618 | } |
d129bceb PO |
1619 | host->max_clk *= 1000000; |
1620 | ||
1c8cde92 PO |
1621 | host->timeout_clk = |
1622 | (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
1623 | if (host->timeout_clk == 0) { | |
1624 | printk(KERN_ERR "%s: Hardware doesn't specify timeout clock " | |
b69c9058 | 1625 | "frequency.\n", mmc_hostname(mmc)); |
b8c86fc5 | 1626 | return -ENODEV; |
1c8cde92 PO |
1627 | } |
1628 | if (caps & SDHCI_TIMEOUT_CLK_UNIT) | |
1629 | host->timeout_clk *= 1000; | |
d129bceb PO |
1630 | |
1631 | /* | |
1632 | * Set host parameters. | |
1633 | */ | |
1634 | mmc->ops = &sdhci_ops; | |
1635 | mmc->f_min = host->max_clk / 256; | |
1636 | mmc->f_max = host->max_clk; | |
c9b74c5b | 1637 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; |
d129bceb | 1638 | |
a4b76193 PO |
1639 | if ((caps & SDHCI_CAN_DO_HISPD) || |
1640 | (host->quirks & SDHCI_QUIRK_FORCE_HIGHSPEED)) | |
cd9277c0 PO |
1641 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
1642 | ||
146ad66e PO |
1643 | mmc->ocr_avail = 0; |
1644 | if (caps & SDHCI_CAN_VDD_330) | |
1645 | mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34; | |
c70840e8 | 1646 | if (caps & SDHCI_CAN_VDD_300) |
146ad66e | 1647 | mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31; |
c70840e8 | 1648 | if (caps & SDHCI_CAN_VDD_180) |
55556da0 | 1649 | mmc->ocr_avail |= MMC_VDD_165_195; |
146ad66e PO |
1650 | |
1651 | if (mmc->ocr_avail == 0) { | |
1652 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
b69c9058 | 1653 | "support voltages.\n", mmc_hostname(mmc)); |
b8c86fc5 | 1654 | return -ENODEV; |
146ad66e PO |
1655 | } |
1656 | ||
d129bceb PO |
1657 | spin_lock_init(&host->lock); |
1658 | ||
1659 | /* | |
2134a922 PO |
1660 | * Maximum number of segments. Depends on if the hardware |
1661 | * can do scatter/gather or not. | |
d129bceb | 1662 | */ |
2134a922 PO |
1663 | if (host->flags & SDHCI_USE_ADMA) |
1664 | mmc->max_hw_segs = 128; | |
1665 | else if (host->flags & SDHCI_USE_DMA) | |
d129bceb | 1666 | mmc->max_hw_segs = 1; |
2134a922 PO |
1667 | else /* PIO */ |
1668 | mmc->max_hw_segs = 128; | |
1669 | mmc->max_phys_segs = 128; | |
d129bceb PO |
1670 | |
1671 | /* | |
bab76961 | 1672 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 1673 | * size (512KiB). |
d129bceb | 1674 | */ |
55db890a | 1675 | mmc->max_req_size = 524288; |
d129bceb PO |
1676 | |
1677 | /* | |
1678 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
1679 | * of bytes. When doing hardware scatter/gather, each entry cannot |
1680 | * be larger than 64 KiB though. | |
d129bceb | 1681 | */ |
2134a922 PO |
1682 | if (host->flags & SDHCI_USE_ADMA) |
1683 | mmc->max_seg_size = 65536; | |
1684 | else | |
1685 | mmc->max_seg_size = mmc->max_req_size; | |
d129bceb | 1686 | |
fe4a3c7a PO |
1687 | /* |
1688 | * Maximum block size. This varies from controller to controller and | |
1689 | * is specified in the capabilities register. | |
1690 | */ | |
1691 | mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT; | |
1692 | if (mmc->max_blk_size >= 3) { | |
b69c9058 PO |
1693 | printk(KERN_WARNING "%s: Invalid maximum block size, " |
1694 | "assuming 512 bytes\n", mmc_hostname(mmc)); | |
03f8590d DV |
1695 | mmc->max_blk_size = 512; |
1696 | } else | |
1697 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 1698 | |
55db890a PO |
1699 | /* |
1700 | * Maximum block count. | |
1701 | */ | |
1702 | mmc->max_blk_count = 65535; | |
1703 | ||
d129bceb PO |
1704 | /* |
1705 | * Init tasklets. | |
1706 | */ | |
1707 | tasklet_init(&host->card_tasklet, | |
1708 | sdhci_tasklet_card, (unsigned long)host); | |
1709 | tasklet_init(&host->finish_tasklet, | |
1710 | sdhci_tasklet_finish, (unsigned long)host); | |
1711 | ||
e4cad1b5 | 1712 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 1713 | |
dace1453 | 1714 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
b69c9058 | 1715 | mmc_hostname(mmc), host); |
d129bceb | 1716 | if (ret) |
8ef1a143 | 1717 | goto untasklet; |
d129bceb PO |
1718 | |
1719 | sdhci_init(host); | |
1720 | ||
1721 | #ifdef CONFIG_MMC_DEBUG | |
1722 | sdhci_dumpregs(host); | |
1723 | #endif | |
1724 | ||
f9134319 | 1725 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
1726 | host->led.name = mmc_hostname(mmc); |
1727 | host->led.brightness = LED_OFF; | |
1728 | host->led.default_trigger = mmc_hostname(mmc); | |
1729 | host->led.brightness_set = sdhci_led_control; | |
1730 | ||
b8c86fc5 | 1731 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
2f730fec PO |
1732 | if (ret) |
1733 | goto reset; | |
1734 | #endif | |
1735 | ||
5f25a66f PO |
1736 | mmiowb(); |
1737 | ||
d129bceb PO |
1738 | mmc_add_host(mmc); |
1739 | ||
2134a922 | 1740 | printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n", |
d1b26863 | 1741 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
2134a922 | 1742 | (host->flags & SDHCI_USE_ADMA)?"A":"", |
d129bceb PO |
1743 | (host->flags & SDHCI_USE_DMA)?"DMA":"PIO"); |
1744 | ||
1745 | return 0; | |
1746 | ||
f9134319 | 1747 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
1748 | reset: |
1749 | sdhci_reset(host, SDHCI_RESET_ALL); | |
1750 | free_irq(host->irq, host); | |
1751 | #endif | |
8ef1a143 | 1752 | untasklet: |
d129bceb PO |
1753 | tasklet_kill(&host->card_tasklet); |
1754 | tasklet_kill(&host->finish_tasklet); | |
d129bceb PO |
1755 | |
1756 | return ret; | |
1757 | } | |
1758 | ||
b8c86fc5 | 1759 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 1760 | |
1e72859e | 1761 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 1762 | { |
1e72859e PO |
1763 | unsigned long flags; |
1764 | ||
1765 | if (dead) { | |
1766 | spin_lock_irqsave(&host->lock, flags); | |
1767 | ||
1768 | host->flags |= SDHCI_DEVICE_DEAD; | |
1769 | ||
1770 | if (host->mrq) { | |
1771 | printk(KERN_ERR "%s: Controller removed during " | |
1772 | " transfer!\n", mmc_hostname(host->mmc)); | |
1773 | ||
1774 | host->mrq->cmd->error = -ENOMEDIUM; | |
1775 | tasklet_schedule(&host->finish_tasklet); | |
1776 | } | |
1777 | ||
1778 | spin_unlock_irqrestore(&host->lock, flags); | |
1779 | } | |
1780 | ||
b8c86fc5 | 1781 | mmc_remove_host(host->mmc); |
d129bceb | 1782 | |
f9134319 | 1783 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
1784 | led_classdev_unregister(&host->led); |
1785 | #endif | |
1786 | ||
1e72859e PO |
1787 | if (!dead) |
1788 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb PO |
1789 | |
1790 | free_irq(host->irq, host); | |
1791 | ||
1792 | del_timer_sync(&host->timer); | |
1793 | ||
1794 | tasklet_kill(&host->card_tasklet); | |
1795 | tasklet_kill(&host->finish_tasklet); | |
2134a922 PO |
1796 | |
1797 | kfree(host->adma_desc); | |
1798 | kfree(host->align_buffer); | |
1799 | ||
1800 | host->adma_desc = NULL; | |
1801 | host->align_buffer = NULL; | |
d129bceb PO |
1802 | } |
1803 | ||
b8c86fc5 | 1804 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 1805 | |
b8c86fc5 | 1806 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 1807 | { |
b8c86fc5 | 1808 | mmc_free_host(host->mmc); |
d129bceb PO |
1809 | } |
1810 | ||
b8c86fc5 | 1811 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
1812 | |
1813 | /*****************************************************************************\ | |
1814 | * * | |
1815 | * Driver init/exit * | |
1816 | * * | |
1817 | \*****************************************************************************/ | |
1818 | ||
1819 | static int __init sdhci_drv_init(void) | |
1820 | { | |
1821 | printk(KERN_INFO DRIVER_NAME | |
52fbf9c9 | 1822 | ": Secure Digital Host Controller Interface driver\n"); |
d129bceb PO |
1823 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
1824 | ||
b8c86fc5 | 1825 | return 0; |
d129bceb PO |
1826 | } |
1827 | ||
1828 | static void __exit sdhci_drv_exit(void) | |
1829 | { | |
d129bceb PO |
1830 | } |
1831 | ||
1832 | module_init(sdhci_drv_init); | |
1833 | module_exit(sdhci_drv_exit); | |
1834 | ||
df673b22 | 1835 | module_param(debug_quirks, uint, 0444); |
67435274 | 1836 | |
d129bceb | 1837 | MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>"); |
b8c86fc5 | 1838 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 1839 | MODULE_LICENSE("GPL"); |
67435274 | 1840 | |
df673b22 | 1841 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |