projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: sd: add support for tuning during uhs initialization
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
9bea3c85 22#include <linux/regulator/consumer.h>
d129bceb 23
2f730fec
PO		 24#include <linux/leds.h>
25
22113efd 26#include <linux/mmc/mmc.h>
d129bceb 27#include <linux/mmc/host.h>
d129bceb 28
d129bceb
PO		 29#include "sdhci.h"
30
31#define DRIVER_NAME "sdhci"
d129bceb 32
d129bceb 33#define DBG(f, x...) \
c6563178 34 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 35
f9134319
PO		 36#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
37 defined(CONFIG_MMC_SDHCI_MODULE))
38#define SDHCI_USE_LEDS_CLASS
39#endif
40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
67435274 44
d129bceb
PO		 45static void sdhci_finish_data(struct sdhci_host *);
46
47static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
48static void sdhci_finish_command(struct sdhci_host *);
49
50static void sdhci_dumpregs(struct sdhci_host *host)
51{
412ab659
PR		 52 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
53 mmc_hostname(host->mmc));
d129bceb
PO		 54
55 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 56 sdhci_readl(host, SDHCI_DMA_ADDRESS),
57 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 58 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 59 sdhci_readw(host, SDHCI_BLOCK_SIZE),
60 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 61 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 62 sdhci_readl(host, SDHCI_ARGUMENT),
63 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 64 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 65 sdhci_readl(host, SDHCI_PRESENT_STATE),
66 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 67 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 68 sdhci_readb(host, SDHCI_POWER_CONTROL),
69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 70 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
72 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 73 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
75 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 76 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 77 sdhci_readl(host, SDHCI_INT_ENABLE),
78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 79 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 80 sdhci_readw(host, SDHCI_ACMD12_ERR),
81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
e8120ad1 82 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 83 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1
PR		 84 sdhci_readl(host, SDHCI_CAPABILITIES_1));
85 printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
86 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 87 sdhci_readl(host, SDHCI_MAX_CURRENT));
f2119df6
AN		 88 printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
89 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 90
be3f4ae0
BD		 91 if (host->flags & SDHCI_USE_ADMA)
92 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
93 readl(host->ioaddr + SDHCI_ADMA_ERROR),
94 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
95
d129bceb
PO		 96 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
97}
98
99/*****************************************************************************\
100 * *
101 * Low level functions *
102 * *
103\*****************************************************************************/
104
7260cf5e
AV		 105static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
106{
107 u32 ier;
108
109 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
110 ier &= ~clear;
111 ier |= set;
112 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
113 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
114}
115
116static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
117{
118 sdhci_clear_set_irqs(host, 0, irqs);
119}
120
121static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
122{
123 sdhci_clear_set_irqs(host, irqs, 0);
124}
125
126static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
127{
128 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
129
68d1fb7e
AV		 130 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
131 return;
132
7260cf5e
AV		 133 if (enable)
134 sdhci_unmask_irqs(host, irqs);
135 else
136 sdhci_mask_irqs(host, irqs);
137}
138
139static void sdhci_enable_card_detection(struct sdhci_host *host)
140{
141 sdhci_set_card_detection(host, true);
142}
143
144static void sdhci_disable_card_detection(struct sdhci_host *host)
145{
146 sdhci_set_card_detection(host, false);
147}
148
d129bceb
PO		 149static void sdhci_reset(struct sdhci_host *host, u8 mask)
150{
e16514d8 151 unsigned long timeout;
063a9dbb 152 u32 uninitialized_var(ier);
e16514d8 153
b8c86fc5 154 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 155 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 156 SDHCI_CARD_PRESENT))
157 return;
158 }
159
063a9dbb
AV		 160 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
161 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
162
393c1a34
PR		 163 if (host->ops->platform_reset_enter)
164 host->ops->platform_reset_enter(host, mask);
165
4e4141a5 166 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 167
e16514d8 168 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 169 host->clock = 0;
170
e16514d8
PO		 171 /* Wait max 100 ms */
172 timeout = 100;
173
174 /* hw clears the bit when it's done */
4e4141a5 175 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 176 if (timeout == 0) {
acf1da45 177 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 178 mmc_hostname(host->mmc), (int)mask);
179 sdhci_dumpregs(host);
180 return;
181 }
182 timeout--;
183 mdelay(1);
d129bceb 184 }
063a9dbb 185
393c1a34
PR		 186 if (host->ops->platform_reset_exit)
187 host->ops->platform_reset_exit(host, mask);
188
063a9dbb
AV		 189 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
190 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 191}
192
2f4cbb3d
NP		 193static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
194
195static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 196{
2f4cbb3d
NP		 197 if (soft)
198 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
199 else
200 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 201
7260cf5e
AV		 202 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
203 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 204 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
205 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 206 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 207
208 if (soft) {
209 /* force clock reconfiguration */
210 host->clock = 0;
211 sdhci_set_ios(host->mmc, &host->mmc->ios);
212 }
7260cf5e 213}
d129bceb 214
7260cf5e
AV		 215static void sdhci_reinit(struct sdhci_host *host)
216{
2f4cbb3d 217 sdhci_init(host, 0);
7260cf5e 218 sdhci_enable_card_detection(host);
d129bceb
PO		 219}
220
221static void sdhci_activate_led(struct sdhci_host *host)
222{
223 u8 ctrl;
224
4e4141a5 225 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 226 ctrl |= SDHCI_CTRL_LED;
4e4141a5 227 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 228}
229
230static void sdhci_deactivate_led(struct sdhci_host *host)
231{
232 u8 ctrl;
233
4e4141a5 234 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 235 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 236 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 237}
238
f9134319 239#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 240static void sdhci_led_control(struct led_classdev *led,
241 enum led_brightness brightness)
242{
243 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
244 unsigned long flags;
245
246 spin_lock_irqsave(&host->lock, flags);
247
248 if (brightness == LED_OFF)
249 sdhci_deactivate_led(host);
250 else
251 sdhci_activate_led(host);
252
253 spin_unlock_irqrestore(&host->lock, flags);
254}
255#endif
256
d129bceb
PO		 257/*****************************************************************************\
258 * *
259 * Core functions *
260 * *
261\*****************************************************************************/
262
a406f5a3 263static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 264{
7659150c
PO		 265 unsigned long flags;
266 size_t blksize, len, chunk;
7244b85b 267 u32 uninitialized_var(scratch);
7659150c 268 u8 *buf;
d129bceb 269
a406f5a3 270 DBG("PIO reading\n");
d129bceb 271
a406f5a3 272 blksize = host->data->blksz;
7659150c 273 chunk = 0;
d129bceb 274
7659150c 275 local_irq_save(flags);
d129bceb 276
a406f5a3 277 while (blksize) {
7659150c
PO		 278 if (!sg_miter_next(&host->sg_miter))
279 BUG();
d129bceb 280
7659150c 281 len = min(host->sg_miter.length, blksize);
d129bceb 282
7659150c
PO		 283 blksize -= len;
284 host->sg_miter.consumed = len;
14d836e7 285
7659150c 286 buf = host->sg_miter.addr;
d129bceb 287
7659150c
PO		 288 while (len) {
289 if (chunk == 0) {
4e4141a5 290 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 291 chunk = 4;
a406f5a3 292 }
7659150c
PO		 293
294 *buf = scratch & 0xFF;
295
296 buf++;
297 scratch >>= 8;
298 chunk--;
299 len--;
d129bceb 300 }
a406f5a3 301 }
7659150c
PO		 302
303 sg_miter_stop(&host->sg_miter);
304
305 local_irq_restore(flags);
a406f5a3 306}
d129bceb 307
a406f5a3
PO		 308static void sdhci_write_block_pio(struct sdhci_host *host)
309{
7659150c
PO		 310 unsigned long flags;
311 size_t blksize, len, chunk;
312 u32 scratch;
313 u8 *buf;
d129bceb 314
a406f5a3
PO		 315 DBG("PIO writing\n");
316
317 blksize = host->data->blksz;
7659150c
PO		 318 chunk = 0;
319 scratch = 0;
d129bceb 320
7659150c 321 local_irq_save(flags);
d129bceb 322
a406f5a3 323 while (blksize) {
7659150c
PO		 324 if (!sg_miter_next(&host->sg_miter))
325 BUG();
a406f5a3 326
7659150c
PO		 327 len = min(host->sg_miter.length, blksize);
328
329 blksize -= len;
330 host->sg_miter.consumed = len;
331
332 buf = host->sg_miter.addr;
d129bceb 333
7659150c
PO		 334 while (len) {
335 scratch |= (u32)*buf << (chunk * 8);
336
337 buf++;
338 chunk++;
339 len--;
340
341 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 342 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 343 chunk = 0;
344 scratch = 0;
d129bceb 345 }
d129bceb
PO		 346 }
347 }
7659150c
PO		 348
349 sg_miter_stop(&host->sg_miter);
350
351 local_irq_restore(flags);
a406f5a3
PO		 352}
353
354static void sdhci_transfer_pio(struct sdhci_host *host)
355{
356 u32 mask;
357
358 BUG_ON(!host->data);
359
7659150c 360 if (host->blocks == 0)
a406f5a3
PO		 361 return;
362
363 if (host->data->flags & MMC_DATA_READ)
364 mask = SDHCI_DATA_AVAILABLE;
365 else
366 mask = SDHCI_SPACE_AVAILABLE;
367
4a3cba32
PO		 368 /*
369 * Some controllers (JMicron JMB38x) mess up the buffer bits
370 * for transfers < 4 bytes. As long as it is just one block,
371 * we can ignore the bits.
372 */
373 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
374 (host->data->blocks == 1))
375 mask = ~0;
376
4e4141a5 377 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 378 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
379 udelay(100);
380
a406f5a3
PO		 381 if (host->data->flags & MMC_DATA_READ)
382 sdhci_read_block_pio(host);
383 else
384 sdhci_write_block_pio(host);
d129bceb 385
7659150c
PO		 386 host->blocks--;
387 if (host->blocks == 0)
a406f5a3 388 break;
a406f5a3 389 }
d129bceb 390
a406f5a3 391 DBG("PIO transfer complete.\n");
d129bceb
PO		 392}
393
2134a922
PO		 394static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
395{
396 local_irq_save(*flags);
397 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
398}
399
400static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
401{
402 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
403 local_irq_restore(*flags);
404}
405
118cd17d
BD		 406static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
407{
9e506f35
BD		 408 __le32 *dataddr = (__le32 __force *)(desc + 4);
409 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 410
9e506f35
BD		 411 /* SDHCI specification says ADMA descriptors should be 4 byte
412 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 413
9e506f35
BD		 414 cmdlen[0] = cpu_to_le16(cmd);
415 cmdlen[1] = cpu_to_le16(len);
416
417 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 418}
419
8f1934ce 420static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 421 struct mmc_data *data)
422{
423 int direction;
424
425 u8 *desc;
426 u8 *align;
427 dma_addr_t addr;
428 dma_addr_t align_addr;
429 int len, offset;
430
431 struct scatterlist *sg;
432 int i;
433 char *buffer;
434 unsigned long flags;
435
436 /*
437 * The spec does not specify endianness of descriptor table.
438 * We currently guess that it is LE.
439 */
440
441 if (data->flags & MMC_DATA_READ)
442 direction = DMA_FROM_DEVICE;
443 else
444 direction = DMA_TO_DEVICE;
445
446 /*
447 * The ADMA descriptor table is mapped further down as we
448 * need to fill it with data first.
449 */
450
451 host->align_addr = dma_map_single(mmc_dev(host->mmc),
452 host->align_buffer, 128 * 4, direction);
8d8bb39b 453 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 454 goto fail;
2134a922
PO		 455 BUG_ON(host->align_addr & 0x3);
456
457 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
458 data->sg, data->sg_len, direction);
8f1934ce
PO		 459 if (host->sg_count == 0)
460 goto unmap_align;
2134a922
PO		 461
462 desc = host->adma_desc;
463 align = host->align_buffer;
464
465 align_addr = host->align_addr;
466
467 for_each_sg(data->sg, sg, host->sg_count, i) {
468 addr = sg_dma_address(sg);
469 len = sg_dma_len(sg);
470
471 /*
472 * The SDHCI specification states that ADMA
473 * addresses must be 32-bit aligned. If they
474 * aren't, then we use a bounce buffer for
475 * the (up to three) bytes that screw up the
476 * alignment.
477 */
478 offset = (4 - (addr & 0x3)) & 0x3;
479 if (offset) {
480 if (data->flags & MMC_DATA_WRITE) {
481 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 482 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 483 memcpy(align, buffer, offset);
484 sdhci_kunmap_atomic(buffer, &flags);
485 }
486
118cd17d
BD		 487 /* tran, valid */
488 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 489
490 BUG_ON(offset > 65536);
491
2134a922
PO		 492 align += 4;
493 align_addr += 4;
494
495 desc += 8;
496
497 addr += offset;
498 len -= offset;
499 }
500
2134a922
PO		 501 BUG_ON(len > 65536);
502
118cd17d
BD		 503 /* tran, valid */
504 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 505 desc += 8;
506
507 /*
508 * If this triggers then we have a calculation bug
509 * somewhere. :/
510 */
511 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
512 }
513
70764a90
TA		 514 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
515 /*
516 * Mark the last descriptor as the terminating descriptor
517 */
518 if (desc != host->adma_desc) {
519 desc -= 8;
520 desc[0] |= 0x2; /* end */
521 }
522 } else {
523 /*
524 * Add a terminating entry.
525 */
2134a922 526
70764a90
TA		 527 /* nop, end, valid */
528 sdhci_set_adma_desc(desc, 0, 0, 0x3);
529 }
2134a922
PO		 530
531 /*
532 * Resync align buffer as we might have changed it.
533 */
534 if (data->flags & MMC_DATA_WRITE) {
535 dma_sync_single_for_device(mmc_dev(host->mmc),
536 host->align_addr, 128 * 4, direction);
537 }
538
539 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
540 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 541 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 542 goto unmap_entries;
2134a922 543 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 544
545 return 0;
546
547unmap_entries:
548 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
549 data->sg_len, direction);
550unmap_align:
551 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
552 128 * 4, direction);
553fail:
554 return -EINVAL;
2134a922
PO		 555}
556
557static void sdhci_adma_table_post(struct sdhci_host *host,
558 struct mmc_data *data)
559{
560 int direction;
561
562 struct scatterlist *sg;
563 int i, size;
564 u8 *align;
565 char *buffer;
566 unsigned long flags;
567
568 if (data->flags & MMC_DATA_READ)
569 direction = DMA_FROM_DEVICE;
570 else
571 direction = DMA_TO_DEVICE;
572
573 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
574 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
575
576 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
577 128 * 4, direction);
578
579 if (data->flags & MMC_DATA_READ) {
580 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
581 data->sg_len, direction);
582
583 align = host->align_buffer;
584
585 for_each_sg(data->sg, sg, host->sg_count, i) {
586 if (sg_dma_address(sg) & 0x3) {
587 size = 4 - (sg_dma_address(sg) & 0x3);
588
589 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 590 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 591 memcpy(buffer, align, size);
592 sdhci_kunmap_atomic(buffer, &flags);
593
594 align += 4;
595 }
596 }
597 }
598
599 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
600 data->sg_len, direction);
601}
602
a3c7778f 603static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 604{
1c8cde92 605 u8 count;
a3c7778f 606 struct mmc_data *data = cmd->data;
1c8cde92 607 unsigned target_timeout, current_timeout;
d129bceb 608
ee53ab5d
PO		 609 /*
610 * If the host controller provides us with an incorrect timeout
611 * value, just skip the check and use 0xE. The hardware may take
612 * longer to time out, but that's much better than having a too-short
613 * timeout value.
614 */
11a2f1b7 615 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 616 return 0xE;
e538fbe8 617
a3c7778f
AW		 618 /* Unspecified timeout, assume max */
619 if (!data && !cmd->cmd_timeout_ms)
620 return 0xE;
d129bceb 621
a3c7778f
AW		 622 /* timeout in us */
623 if (!data)
624 target_timeout = cmd->cmd_timeout_ms * 1000;
625 else
626 target_timeout = data->timeout_ns / 1000 +
627 data->timeout_clks / host->clock;
81b39802 628
4b01681c
MB		 629 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
630 host->timeout_clk = host->clock / 1000;
631
1c8cde92
PO		 632 /*
633 * Figure out needed cycles.
634 * We do this in steps in order to fit inside a 32 bit int.
635 * The first step is the minimum timeout, which will have a
636 * minimum resolution of 6 bits:
637 * (1) 2^13*1000 > 2^22,
638 * (2) host->timeout_clk < 2^16
639 * =>
640 * (1) / (2) > 2^6
641 */
4b01681c 642 BUG_ON(!host->timeout_clk);
1c8cde92
PO		 643 count = 0;
644 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
645 while (current_timeout < target_timeout) {
646 count++;
647 current_timeout <<= 1;
648 if (count >= 0xF)
649 break;
650 }
651
652 if (count >= 0xF) {
a3c7778f
AW		 653 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
654 mmc_hostname(host->mmc), cmd->opcode);
1c8cde92
PO		 655 count = 0xE;
656 }
657
ee53ab5d
PO		 658 return count;
659}
660
6aa943ab
AV		 661static void sdhci_set_transfer_irqs(struct sdhci_host *host)
662{
663 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
664 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
665
666 if (host->flags & SDHCI_REQ_USE_DMA)
667 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
668 else
669 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
670}
671
a3c7778f 672static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 673{
674 u8 count;
2134a922 675 u8 ctrl;
a3c7778f 676 struct mmc_data *data = cmd->data;
8f1934ce 677 int ret;
ee53ab5d
PO		 678
679 WARN_ON(host->data);
680
a3c7778f
AW		 681 if (data || (cmd->flags & MMC_RSP_BUSY)) {
682 count = sdhci_calc_timeout(host, cmd);
683 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
684 }
685
686 if (!data)
ee53ab5d
PO		 687 return;
688
689 /* Sanity checks */
690 BUG_ON(data->blksz * data->blocks > 524288);
691 BUG_ON(data->blksz > host->mmc->max_blk_size);
692 BUG_ON(data->blocks > 65535);
693
694 host->data = data;
695 host->data_early = 0;
f6a03cbf 696 host->data->bytes_xfered = 0;
ee53ab5d 697
a13abc7b 698 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 699 host->flags |= SDHCI_REQ_USE_DMA;
700
2134a922
PO		 701 /*
702 * FIXME: This doesn't account for merging when mapping the
703 * scatterlist.
704 */
705 if (host->flags & SDHCI_REQ_USE_DMA) {
706 int broken, i;
707 struct scatterlist *sg;
708
709 broken = 0;
710 if (host->flags & SDHCI_USE_ADMA) {
711 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
712 broken = 1;
713 } else {
714 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
715 broken = 1;
716 }
717
718 if (unlikely(broken)) {
719 for_each_sg(data->sg, sg, data->sg_len, i) {
720 if (sg->length & 0x3) {
721 DBG("Reverting to PIO because of "
722 "transfer size (%d)\n",
723 sg->length);
724 host->flags &= ~SDHCI_REQ_USE_DMA;
725 break;
726 }
727 }
728 }
c9fddbc4
PO		 729 }
730
731 /*
732 * The assumption here being that alignment is the same after
733 * translation to device address space.
734 */
2134a922
PO		 735 if (host->flags & SDHCI_REQ_USE_DMA) {
736 int broken, i;
737 struct scatterlist *sg;
738
739 broken = 0;
740 if (host->flags & SDHCI_USE_ADMA) {
741 /*
742 * As we use 3 byte chunks to work around
743 * alignment problems, we need to check this
744 * quirk.
745 */
746 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
747 broken = 1;
748 } else {
749 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
750 broken = 1;
751 }
752
753 if (unlikely(broken)) {
754 for_each_sg(data->sg, sg, data->sg_len, i) {
755 if (sg->offset & 0x3) {
756 DBG("Reverting to PIO because of "
757 "bad alignment\n");
758 host->flags &= ~SDHCI_REQ_USE_DMA;
759 break;
760 }
761 }
762 }
763 }
764
8f1934ce
PO		 765 if (host->flags & SDHCI_REQ_USE_DMA) {
766 if (host->flags & SDHCI_USE_ADMA) {
767 ret = sdhci_adma_table_pre(host, data);
768 if (ret) {
769 /*
770 * This only happens when someone fed
771 * us an invalid request.
772 */
773 WARN_ON(1);
ebd6d357 774 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 775 } else {
4e4141a5
AV		 776 sdhci_writel(host, host->adma_addr,
777 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 778 }
779 } else {
c8b3e02e 780 int sg_cnt;
8f1934ce 781
c8b3e02e 782 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 783 data->sg, data->sg_len,
784 (data->flags & MMC_DATA_READ) ?
785 DMA_FROM_DEVICE :
786 DMA_TO_DEVICE);
c8b3e02e 787 if (sg_cnt == 0) {
8f1934ce
PO		 788 /*
789 * This only happens when someone fed
790 * us an invalid request.
791 */
792 WARN_ON(1);
ebd6d357 793 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 794 } else {
719a61b4 795 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 796 sdhci_writel(host, sg_dma_address(data->sg),
797 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 798 }
799 }
800 }
801
2134a922
PO		 802 /*
803 * Always adjust the DMA selection as some controllers
804 * (e.g. JMicron) can't do PIO properly when the selection
805 * is ADMA.
806 */
807 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 808 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 809 ctrl &= ~SDHCI_CTRL_DMA_MASK;
810 if ((host->flags & SDHCI_REQ_USE_DMA) &&
811 (host->flags & SDHCI_USE_ADMA))
812 ctrl |= SDHCI_CTRL_ADMA32;
813 else
814 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 815 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 816 }
817
8f1934ce 818 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 819 int flags;
820
821 flags = SG_MITER_ATOMIC;
822 if (host->data->flags & MMC_DATA_READ)
823 flags |= SG_MITER_TO_SG;
824 else
825 flags |= SG_MITER_FROM_SG;
826 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 827 host->blocks = data->blocks;
d129bceb 828 }
c7fa9963 829
6aa943ab
AV		 830 sdhci_set_transfer_irqs(host);
831
f6a03cbf
MV		 832 /* Set the DMA boundary value and block size */
833 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
834 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 835 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 836}
837
838static void sdhci_set_transfer_mode(struct sdhci_host *host,
839 struct mmc_data *data)
840{
841 u16 mode;
842
c7fa9963
PO		 843 if (data == NULL)
844 return;
845
e538fbe8
PO		 846 WARN_ON(!host->data);
847
c7fa9963 848 mode = SDHCI_TRNS_BLK_CNT_EN;
c4512f79
JH		 849 if (data->blocks > 1) {
850 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
851 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
852 else
853 mode |= SDHCI_TRNS_MULTI;
854 }
c7fa9963
PO		 855 if (data->flags & MMC_DATA_READ)
856 mode |= SDHCI_TRNS_READ;
c9fddbc4 857 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 858 mode |= SDHCI_TRNS_DMA;
859
4e4141a5 860 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 861}
862
863static void sdhci_finish_data(struct sdhci_host *host)
864{
865 struct mmc_data *data;
d129bceb
PO		 866
867 BUG_ON(!host->data);
868
869 data = host->data;
870 host->data = NULL;
871
c9fddbc4 872 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 873 if (host->flags & SDHCI_USE_ADMA)
874 sdhci_adma_table_post(host, data);
875 else {
876 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
877 data->sg_len, (data->flags & MMC_DATA_READ) ?
878 DMA_FROM_DEVICE : DMA_TO_DEVICE);
879 }
d129bceb
PO		 880 }
881
882 /*
c9b74c5b
PO		 883 * The specification states that the block count register must
884 * be updated, but it does not specify at what point in the
885 * data flow. That makes the register entirely useless to read
886 * back so we have to assume that nothing made it to the card
887 * in the event of an error.
d129bceb 888 */
c9b74c5b
PO		 889 if (data->error)
890 data->bytes_xfered = 0;
d129bceb 891 else
c9b74c5b 892 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 893
d129bceb
PO		 894 if (data->stop) {
895 /*
896 * The controller needs a reset of internal state machines
897 * upon error conditions.
898 */
17b0429d 899 if (data->error) {
d129bceb
PO		 900 sdhci_reset(host, SDHCI_RESET_CMD);
901 sdhci_reset(host, SDHCI_RESET_DATA);
902 }
903
904 sdhci_send_command(host, data->stop);
905 } else
906 tasklet_schedule(&host->finish_tasklet);
907}
908
909static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
910{
911 int flags;
fd2208d7 912 u32 mask;
7cb2c76f 913 unsigned long timeout;
d129bceb
PO		 914
915 WARN_ON(host->cmd);
916
d129bceb 917 /* Wait max 10 ms */
7cb2c76f 918 timeout = 10;
fd2208d7
PO		 919
920 mask = SDHCI_CMD_INHIBIT;
921 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
922 mask |= SDHCI_DATA_INHIBIT;
923
924 /* We shouldn't wait for data inihibit for stop commands, even
925 though they might use busy signaling */
926 if (host->mrq->data && (cmd == host->mrq->data->stop))
927 mask &= ~SDHCI_DATA_INHIBIT;
928
4e4141a5 929 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 930 if (timeout == 0) {
d129bceb 931 printk(KERN_ERR "%s: Controller never released "
acf1da45 932 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 933 sdhci_dumpregs(host);
17b0429d 934 cmd->error = -EIO;
d129bceb
PO		 935 tasklet_schedule(&host->finish_tasklet);
936 return;
937 }
7cb2c76f
PO		 938 timeout--;
939 mdelay(1);
940 }
d129bceb
PO		 941
942 mod_timer(&host->timer, jiffies + 10 * HZ);
943
944 host->cmd = cmd;
945
a3c7778f 946 sdhci_prepare_data(host, cmd);
d129bceb 947
4e4141a5 948 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 949
c7fa9963
PO		 950 sdhci_set_transfer_mode(host, cmd->data);
951
d129bceb 952 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 953 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 954 mmc_hostname(host->mmc));
17b0429d 955 cmd->error = -EINVAL;
d129bceb
PO		 956 tasklet_schedule(&host->finish_tasklet);
957 return;
958 }
959
960 if (!(cmd->flags & MMC_RSP_PRESENT))
961 flags = SDHCI_CMD_RESP_NONE;
962 else if (cmd->flags & MMC_RSP_136)
963 flags = SDHCI_CMD_RESP_LONG;
964 else if (cmd->flags & MMC_RSP_BUSY)
965 flags = SDHCI_CMD_RESP_SHORT_BUSY;
966 else
967 flags = SDHCI_CMD_RESP_SHORT;
968
969 if (cmd->flags & MMC_RSP_CRC)
970 flags |= SDHCI_CMD_CRC;
971 if (cmd->flags & MMC_RSP_OPCODE)
972 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 973
974 /* CMD19 is special in that the Data Present Select should be set */
975 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
d129bceb
PO		 976 flags |= SDHCI_CMD_DATA;
977
4e4141a5 978 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 979}
980
981static void sdhci_finish_command(struct sdhci_host *host)
982{
983 int i;
984
985 BUG_ON(host->cmd == NULL);
986
987 if (host->cmd->flags & MMC_RSP_PRESENT) {
988 if (host->cmd->flags & MMC_RSP_136) {
989 /* CRC is stripped so we need to do some shifting. */
990 for (i = 0;i < 4;i++) {
4e4141a5 991 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 992 SDHCI_RESPONSE + (3-i)*4) << 8;
993 if (i != 3)
994 host->cmd->resp[i] |=
4e4141a5 995 sdhci_readb(host,
d129bceb
PO		 996 SDHCI_RESPONSE + (3-i)*4-1);
997 }
998 } else {
4e4141a5 999 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1000 }
1001 }
1002
17b0429d 1003 host->cmd->error = 0;
d129bceb 1004
e538fbe8
PO		 1005 if (host->data && host->data_early)
1006 sdhci_finish_data(host);
1007
1008 if (!host->cmd->data)
d129bceb
PO		 1009 tasklet_schedule(&host->finish_tasklet);
1010
1011 host->cmd = NULL;
1012}
1013
1014static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1015{
1016 int div;
1017 u16 clk;
7cb2c76f 1018 unsigned long timeout;
d129bceb
PO		 1019
1020 if (clock == host->clock)
1021 return;
1022
8114634c
AV		 1023 if (host->ops->set_clock) {
1024 host->ops->set_clock(host, clock);
1025 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1026 return;
1027 }
1028
4e4141a5 1029 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1030
1031 if (clock == 0)
1032 goto out;
1033
85105c53
ZG		 1034 if (host->version >= SDHCI_SPEC_300) {
1035 /* Version 3.00 divisors must be a multiple of 2. */
1036 if (host->max_clk <= clock)
1037 div = 1;
1038 else {
0397526d 1039 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
85105c53
ZG		 1040 if ((host->max_clk / div) <= clock)
1041 break;
1042 }
1043 }
1044 } else {
1045 /* Version 2.00 divisors must be a power of 2. */
0397526d 1046 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1047 if ((host->max_clk / div) <= clock)
1048 break;
1049 }
d129bceb
PO		 1050 }
1051 div >>= 1;
1052
85105c53
ZG		 1053 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1054 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1055 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1056 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1057 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1058
27f6cb16
CB		 1059 /* Wait max 20 ms */
1060 timeout = 20;
4e4141a5 1061 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1062 & SDHCI_CLOCK_INT_STABLE)) {
1063 if (timeout == 0) {
acf1da45
PO		 1064 printk(KERN_ERR "%s: Internal clock never "
1065 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1066 sdhci_dumpregs(host);
1067 return;
1068 }
7cb2c76f
PO		 1069 timeout--;
1070 mdelay(1);
1071 }
d129bceb
PO		 1072
1073 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1074 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1075
1076out:
1077 host->clock = clock;
1078}
1079
146ad66e
PO		 1080static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1081{
8364248a 1082 u8 pwr = 0;
146ad66e 1083
8364248a 1084 if (power != (unsigned short)-1) {
ae628903
PO		 1085 switch (1 << power) {
1086 case MMC_VDD_165_195:
1087 pwr = SDHCI_POWER_180;
1088 break;
1089 case MMC_VDD_29_30:
1090 case MMC_VDD_30_31:
1091 pwr = SDHCI_POWER_300;
1092 break;
1093 case MMC_VDD_32_33:
1094 case MMC_VDD_33_34:
1095 pwr = SDHCI_POWER_330;
1096 break;
1097 default:
1098 BUG();
1099 }
1100 }
1101
1102 if (host->pwr == pwr)
146ad66e
PO		 1103 return;
1104
ae628903
PO		 1105 host->pwr = pwr;
1106
1107 if (pwr == 0) {
4e4141a5 1108 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1109 return;
9e9dc5f2
DS		 1110 }
1111
1112 /*
1113 * Spec says that we should clear the power reg before setting
1114 * a new value. Some controllers don't seem to like this though.
1115 */
b8c86fc5 1116 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1117 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1118
e08c1694 1119 /*
c71f6512 1120 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1121 * and set turn on power at the same time, so set the voltage first.
1122 */
11a2f1b7 1123 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1124 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1125
ae628903 1126 pwr |= SDHCI_POWER_ON;
146ad66e 1127
ae628903 1128 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1129
1130 /*
1131 * Some controllers need an extra 10ms delay of 10ms before they
1132 * can apply clock after applying power
1133 */
11a2f1b7 1134 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1135 mdelay(10);
146ad66e
PO		 1136}
1137
d129bceb
PO		 1138/*****************************************************************************\
1139 * *
1140 * MMC callbacks *
1141 * *
1142\*****************************************************************************/
1143
1144static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1145{
1146 struct sdhci_host *host;
68d1fb7e 1147 bool present;
d129bceb
PO		 1148 unsigned long flags;
1149
1150 host = mmc_priv(mmc);
1151
1152 spin_lock_irqsave(&host->lock, flags);
1153
1154 WARN_ON(host->mrq != NULL);
1155
f9134319 1156#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1157 sdhci_activate_led(host);
2f730fec 1158#endif
c4512f79
JH		 1159 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1160 if (mrq->stop) {
1161 mrq->data->stop = NULL;
1162 mrq->stop = NULL;
1163 }
1164 }
d129bceb
PO		 1165
1166 host->mrq = mrq;
1167
68d1fb7e
AV		 1168 /* If polling, assume that the card is always present. */
1169 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1170 present = true;
1171 else
1172 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1173 SDHCI_CARD_PRESENT;
1174
1175 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1176 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1177 tasklet_schedule(&host->finish_tasklet);
1178 } else
1179 sdhci_send_command(host, mrq->cmd);
1180
5f25a66f 1181 mmiowb();
d129bceb
PO		 1182 spin_unlock_irqrestore(&host->lock, flags);
1183}
1184
1185static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1186{
1187 struct sdhci_host *host;
1188 unsigned long flags;
1189 u8 ctrl;
1190
1191 host = mmc_priv(mmc);
1192
1193 spin_lock_irqsave(&host->lock, flags);
1194
1e72859e
PO		 1195 if (host->flags & SDHCI_DEVICE_DEAD)
1196 goto out;
1197
d129bceb
PO		 1198 /*
1199 * Reset the chip on each power off.
1200 * Should clear out any weird states.
1201 */
1202 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1203 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1204 sdhci_reinit(host);
d129bceb
PO		 1205 }
1206
1207 sdhci_set_clock(host, ios->clock);
1208
1209 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1210 sdhci_set_power(host, -1);
d129bceb 1211 else
146ad66e 1212 sdhci_set_power(host, ios->vdd);
d129bceb 1213
643a81ff
PR		 1214 if (host->ops->platform_send_init_74_clocks)
1215 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1216
15ec4461
PR		 1217 /*
1218 * If your platform has 8-bit width support but is not a v3 controller,
1219 * or if it requires special setup code, you should implement that in
1220 * platform_8bit_width().
1221 */
1222 if (host->ops->platform_8bit_width)
1223 host->ops->platform_8bit_width(host, ios->bus_width);
1224 else {
1225 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1226 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1227 ctrl &= ~SDHCI_CTRL_4BITBUS;
1228 if (host->version >= SDHCI_SPEC_300)
1229 ctrl |= SDHCI_CTRL_8BITBUS;
1230 } else {
1231 if (host->version >= SDHCI_SPEC_300)
1232 ctrl &= ~SDHCI_CTRL_8BITBUS;
1233 if (ios->bus_width == MMC_BUS_WIDTH_4)
1234 ctrl |= SDHCI_CTRL_4BITBUS;
1235 else
1236 ctrl &= ~SDHCI_CTRL_4BITBUS;
1237 }
1238 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1239 }
ae6d6c92 1240
15ec4461 1241 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1242
3ab9c8da
PR		 1243 if ((ios->timing == MMC_TIMING_SD_HS ||
1244 ios->timing == MMC_TIMING_MMC_HS)
1245 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1246 ctrl |= SDHCI_CTRL_HISPD;
1247 else
1248 ctrl &= ~SDHCI_CTRL_HISPD;
1249
d6d50a15 1250 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1251 u16 clk, ctrl_2;
1252 unsigned int clock;
1253
1254 /* In case of UHS-I modes, set High Speed Enable */
1255 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1256 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1257 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1258 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1259 (ios->timing == MMC_TIMING_UHS_SDR12))
1260 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1261
1262 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1263 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1264 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1265 /*
1266 * We only need to set Driver Strength if the
1267 * preset value enable is not set.
1268 */
1269 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1270 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1271 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1272 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1273 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1274
1275 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1276 } else {
1277 /*
1278 * According to SDHC Spec v3.00, if the Preset Value
1279 * Enable in the Host Control 2 register is set, we
1280 * need to reset SD Clock Enable before changing High
1281 * Speed Enable to avoid generating clock gliches.
1282 */
758535c4
AN		 1283
1284 /* Reset SD Clock Enable */
1285 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1286 clk &= ~SDHCI_CLOCK_CARD_EN;
1287 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1288
1289 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1290
1291 /* Re-enable SD Clock */
1292 clock = host->clock;
1293 host->clock = 0;
1294 sdhci_set_clock(host, clock);
d6d50a15 1295 }
49c468fc
AN		 1296
1297 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1298
1299 /* Select Bus Speed Mode for host */
1300 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1301 if (ios->timing == MMC_TIMING_UHS_SDR12)
1302 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1303 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1304 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1305 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1306 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1307 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1308 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1309 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1310 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1311
1312 /* Reset SD Clock Enable */
1313 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1314 clk &= ~SDHCI_CLOCK_CARD_EN;
1315 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1316
1317 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1318
1319 /* Re-enable SD Clock */
1320 clock = host->clock;
1321 host->clock = 0;
1322 sdhci_set_clock(host, clock);
758535c4
AN		 1323 } else
1324 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1325
b8352260
LD		 1326 /*
1327 * Some (ENE) controllers go apeshit on some ios operation,
1328 * signalling timeout and CRC errors even on CMD0. Resetting
1329 * it on each ios seems to solve the problem.
1330 */
b8c86fc5 1331 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1332 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1333
1e72859e 1334out:
5f25a66f 1335 mmiowb();
d129bceb
PO		 1336 spin_unlock_irqrestore(&host->lock, flags);
1337}
1338
82b0e23a 1339static int check_ro(struct sdhci_host *host)
d129bceb 1340{
d129bceb 1341 unsigned long flags;
2dfb579c 1342 int is_readonly;
d129bceb 1343
d129bceb
PO		 1344 spin_lock_irqsave(&host->lock, flags);
1345
1e72859e 1346 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1347 is_readonly = 0;
1348 else if (host->ops->get_ro)
1349 is_readonly = host->ops->get_ro(host);
1e72859e 1350 else
2dfb579c
WS		 1351 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1352 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1353
1354 spin_unlock_irqrestore(&host->lock, flags);
1355
2dfb579c
WS		 1356 /* This quirk needs to be replaced by a callback-function later */
1357 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1358 !is_readonly : is_readonly;
d129bceb
PO		 1359}
1360
82b0e23a
TI		 1361#define SAMPLE_COUNT 5
1362
1363static int sdhci_get_ro(struct mmc_host *mmc)
1364{
1365 struct sdhci_host *host;
1366 int i, ro_count;
1367
1368 host = mmc_priv(mmc);
1369
1370 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1371 return check_ro(host);
1372
1373 ro_count = 0;
1374 for (i = 0; i < SAMPLE_COUNT; i++) {
1375 if (check_ro(host)) {
1376 if (++ro_count > SAMPLE_COUNT / 2)
1377 return 1;
1378 }
1379 msleep(30);
1380 }
1381 return 0;
1382}
1383
f75979b7
PO		 1384static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1385{
1386 struct sdhci_host *host;
1387 unsigned long flags;
f75979b7
PO		 1388
1389 host = mmc_priv(mmc);
1390
1391 spin_lock_irqsave(&host->lock, flags);
1392
1e72859e
PO		 1393 if (host->flags & SDHCI_DEVICE_DEAD)
1394 goto out;
1395
f75979b7 1396 if (enable)
7260cf5e
AV		 1397 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1398 else
1399 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1400out:
f75979b7
PO		 1401 mmiowb();
1402
1403 spin_unlock_irqrestore(&host->lock, flags);
1404}
1405
f2119df6
AN		 1406static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1407 struct mmc_ios *ios)
1408{
1409 struct sdhci_host *host;
1410 u8 pwr;
1411 u16 clk, ctrl;
1412 u32 present_state;
1413
1414 host = mmc_priv(mmc);
1415
1416 /*
1417 * Signal Voltage Switching is only applicable for Host Controllers
1418 * v3.00 and above.
1419 */
1420 if (host->version < SDHCI_SPEC_300)
1421 return 0;
1422
1423 /*
1424 * We first check whether the request is to set signalling voltage
1425 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1426 */
1427 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1428 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1429 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1430 ctrl &= ~SDHCI_CTRL_VDD_180;
1431 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1432
1433 /* Wait for 5ms */
1434 usleep_range(5000, 5500);
1435
1436 /* 3.3V regulator output should be stable within 5 ms */
1437 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1438 if (!(ctrl & SDHCI_CTRL_VDD_180))
1439 return 0;
1440 else {
1441 printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1442 "signalling voltage failed\n");
1443 return -EIO;
1444 }
1445 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1446 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1447 /* Stop SDCLK */
1448 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1449 clk &= ~SDHCI_CLOCK_CARD_EN;
1450 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1451
1452 /* Check whether DAT[3:0] is 0000 */
1453 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1454 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1455 SDHCI_DATA_LVL_SHIFT)) {
1456 /*
1457 * Enable 1.8V Signal Enable in the Host Control2
1458 * register
1459 */
1460 ctrl |= SDHCI_CTRL_VDD_180;
1461 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1462
1463 /* Wait for 5ms */
1464 usleep_range(5000, 5500);
1465
1466 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1467 if (ctrl & SDHCI_CTRL_VDD_180) {
1468 /* Provide SDCLK again and wait for 1ms*/
1469 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1470 clk |= SDHCI_CLOCK_CARD_EN;
1471 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1472 usleep_range(1000, 1500);
1473
1474 /*
1475 * If DAT[3:0] level is 1111b, then the card
1476 * was successfully switched to 1.8V signaling.
1477 */
1478 present_state = sdhci_readl(host,
1479 SDHCI_PRESENT_STATE);
1480 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1481 SDHCI_DATA_LVL_MASK)
1482 return 0;
1483 }
1484 }
1485
1486 /*
1487 * If we are here, that means the switch to 1.8V signaling
1488 * failed. We power cycle the card, and retry initialization
1489 * sequence by setting S18R to 0.
1490 */
1491 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1492 pwr &= ~SDHCI_POWER_ON;
1493 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1494
1495 /* Wait for 1ms as per the spec */
1496 usleep_range(1000, 1500);
1497 pwr |= SDHCI_POWER_ON;
1498 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1499
1500 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1501 "voltage failed, retrying with S18R set to 0\n");
1502 return -EAGAIN;
1503 } else
1504 /* No signal voltage switch required */
1505 return 0;
1506}
1507
b513ea25
AN		 1508static int sdhci_execute_tuning(struct mmc_host *mmc)
1509{
1510 struct sdhci_host *host;
1511 u16 ctrl;
1512 u32 ier;
1513 int tuning_loop_counter = MAX_TUNING_LOOP;
1514 unsigned long timeout;
1515 int err = 0;
1516
1517 host = mmc_priv(mmc);
1518
1519 disable_irq(host->irq);
1520 spin_lock(&host->lock);
1521
1522 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1523
1524 /*
1525 * Host Controller needs tuning only in case of SDR104 mode
1526 * and for SDR50 mode when Use Tuning for SDR50 is set in
1527 * Capabilities register.
1528 */
1529 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1530 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1531 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1532 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1533 else {
1534 spin_unlock(&host->lock);
1535 enable_irq(host->irq);
1536 return 0;
1537 }
1538
1539 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1540
1541 /*
1542 * As per the Host Controller spec v3.00, tuning command
1543 * generates Buffer Read Ready interrupt, so enable that.
1544 *
1545 * Note: The spec clearly says that when tuning sequence
1546 * is being performed, the controller does not generate
1547 * interrupts other than Buffer Read Ready interrupt. But
1548 * to make sure we don't hit a controller bug, we _only_
1549 * enable Buffer Read Ready interrupt here.
1550 */
1551 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1552 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1553
1554 /*
1555 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1556 * of loops reaches 40 times or a timeout of 150ms occurs.
1557 */
1558 timeout = 150;
1559 do {
1560 struct mmc_command cmd = {0};
1561 struct mmc_request mrq = {0};
1562
1563 if (!tuning_loop_counter && !timeout)
1564 break;
1565
1566 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1567 cmd.arg = 0;
1568 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1569 cmd.retries = 0;
1570 cmd.data = NULL;
1571 cmd.error = 0;
1572
1573 mrq.cmd = &cmd;
1574 host->mrq = &mrq;
1575
1576 /*
1577 * In response to CMD19, the card sends 64 bytes of tuning
1578 * block to the Host Controller. So we set the block size
1579 * to 64 here.
1580 */
1581 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1582
1583 /*
1584 * The tuning block is sent by the card to the host controller.
1585 * So we set the TRNS_READ bit in the Transfer Mode register.
1586 * This also takes care of setting DMA Enable and Multi Block
1587 * Select in the same register to 0.
1588 */
1589 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1590
1591 sdhci_send_command(host, &cmd);
1592
1593 host->cmd = NULL;
1594 host->mrq = NULL;
1595
1596 spin_unlock(&host->lock);
1597 enable_irq(host->irq);
1598
1599 /* Wait for Buffer Read Ready interrupt */
1600 wait_event_interruptible_timeout(host->buf_ready_int,
1601 (host->tuning_done == 1),
1602 msecs_to_jiffies(50));
1603 disable_irq(host->irq);
1604 spin_lock(&host->lock);
1605
1606 if (!host->tuning_done) {
1607 printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1608 "Buffer Read Ready interrupt during tuning "
1609 "procedure, falling back to fixed sampling "
1610 "clock\n");
1611 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1612 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1613 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1614 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1615
1616 err = -EIO;
1617 goto out;
1618 }
1619
1620 host->tuning_done = 0;
1621
1622 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1623 tuning_loop_counter--;
1624 timeout--;
1625 mdelay(1);
1626 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1627
1628 /*
1629 * The Host Driver has exhausted the maximum number of loops allowed,
1630 * so use fixed sampling frequency.
1631 */
1632 if (!tuning_loop_counter || !timeout) {
1633 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1634 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1635 } else {
1636 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1637 printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1638 " failed, falling back to fixed sampling"
1639 " clock\n");
1640 err = -EIO;
1641 }
1642 }
1643
1644out:
1645 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1646 spin_unlock(&host->lock);
1647 enable_irq(host->irq);
1648
1649 return err;
1650}
1651
ab7aefd0 1652static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1653 .request = sdhci_request,
1654 .set_ios = sdhci_set_ios,
1655 .get_ro = sdhci_get_ro,
f75979b7 1656 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1657 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1658 .execute_tuning = sdhci_execute_tuning,
d129bceb
PO		 1659};
1660
1661/*****************************************************************************\
1662 * *
1663 * Tasklets *
1664 * *
1665\*****************************************************************************/
1666
1667static void sdhci_tasklet_card(unsigned long param)
1668{
1669 struct sdhci_host *host;
1670 unsigned long flags;
1671
1672 host = (struct sdhci_host*)param;
1673
1674 spin_lock_irqsave(&host->lock, flags);
1675
4e4141a5 1676 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1677 if (host->mrq) {
1678 printk(KERN_ERR "%s: Card removed during transfer!\n",
1679 mmc_hostname(host->mmc));
1680 printk(KERN_ERR "%s: Resetting controller.\n",
1681 mmc_hostname(host->mmc));
1682
1683 sdhci_reset(host, SDHCI_RESET_CMD);
1684 sdhci_reset(host, SDHCI_RESET_DATA);
1685
17b0429d 1686 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1687 tasklet_schedule(&host->finish_tasklet);
1688 }
1689 }
1690
1691 spin_unlock_irqrestore(&host->lock, flags);
1692
04cf585d 1693 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1694}
1695
1696static void sdhci_tasklet_finish(unsigned long param)
1697{
1698 struct sdhci_host *host;
1699 unsigned long flags;
1700 struct mmc_request *mrq;
1701
1702 host = (struct sdhci_host*)param;
1703
0c9c99a7
CB		 1704 /*
1705 * If this tasklet gets rescheduled while running, it will
1706 * be run again afterwards but without any active request.
1707 */
1708 if (!host->mrq)
1709 return;
1710
d129bceb
PO		 1711 spin_lock_irqsave(&host->lock, flags);
1712
1713 del_timer(&host->timer);
1714
1715 mrq = host->mrq;
1716
d129bceb
PO		 1717 /*
1718 * The controller needs a reset of internal state machines
1719 * upon error conditions.
1720 */
1e72859e 1721 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1722 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1723 (mrq->data && (mrq->data->error ||
1724 (mrq->data->stop && mrq->data->stop->error))) ||
1725 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1726
1727 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1728 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1729 unsigned int clock;
1730
1731 /* This is to force an update */
1732 clock = host->clock;
1733 host->clock = 0;
1734 sdhci_set_clock(host, clock);
1735 }
1736
1737 /* Spec says we should do both at the same time, but Ricoh
1738 controllers do not like that. */
d129bceb
PO		 1739 sdhci_reset(host, SDHCI_RESET_CMD);
1740 sdhci_reset(host, SDHCI_RESET_DATA);
1741 }
1742
1743 host->mrq = NULL;
1744 host->cmd = NULL;
1745 host->data = NULL;
1746
f9134319 1747#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1748 sdhci_deactivate_led(host);
2f730fec 1749#endif
d129bceb 1750
5f25a66f 1751 mmiowb();
d129bceb
PO		 1752 spin_unlock_irqrestore(&host->lock, flags);
1753
1754 mmc_request_done(host->mmc, mrq);
1755}
1756
1757static void sdhci_timeout_timer(unsigned long data)
1758{
1759 struct sdhci_host *host;
1760 unsigned long flags;
1761
1762 host = (struct sdhci_host*)data;
1763
1764 spin_lock_irqsave(&host->lock, flags);
1765
1766 if (host->mrq) {
acf1da45
PO		 1767 printk(KERN_ERR "%s: Timeout waiting for hardware "
1768 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1769 sdhci_dumpregs(host);
1770
1771 if (host->data) {
17b0429d 1772 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1773 sdhci_finish_data(host);
1774 } else {
1775 if (host->cmd)
17b0429d 1776 host->cmd->error = -ETIMEDOUT;
d129bceb 1777 else
17b0429d 1778 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1779
1780 tasklet_schedule(&host->finish_tasklet);
1781 }
1782 }
1783
5f25a66f 1784 mmiowb();
d129bceb
PO		 1785 spin_unlock_irqrestore(&host->lock, flags);
1786}
1787
1788/*****************************************************************************\
1789 * *
1790 * Interrupt handling *
1791 * *
1792\*****************************************************************************/
1793
1794static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1795{
1796 BUG_ON(intmask == 0);
1797
1798 if (!host->cmd) {
b67ac3f3
PO		 1799 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1800 "though no command operation was in progress.\n",
1801 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1802 sdhci_dumpregs(host);
1803 return;
1804 }
1805
43b58b36 1806 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1807 host->cmd->error = -ETIMEDOUT;
1808 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1809 SDHCI_INT_INDEX))
1810 host->cmd->error = -EILSEQ;
43b58b36 1811
e809517f 1812 if (host->cmd->error) {
d129bceb 1813 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1814 return;
1815 }
1816
1817 /*
1818 * The host can send and interrupt when the busy state has
1819 * ended, allowing us to wait without wasting CPU cycles.
1820 * Unfortunately this is overloaded on the "data complete"
1821 * interrupt, so we need to take some care when handling
1822 * it.
1823 *
1824 * Note: The 1.0 specification is a bit ambiguous about this
1825 * feature so there might be some problems with older
1826 * controllers.
1827 */
1828 if (host->cmd->flags & MMC_RSP_BUSY) {
1829 if (host->cmd->data)
1830 DBG("Cannot wait for busy signal when also "
1831 "doing a data transfer");
f945405c 1832 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1833 return;
f945405c
BD		 1834
1835 /* The controller does not support the end-of-busy IRQ,
1836 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 1837 }
1838
1839 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 1840 sdhci_finish_command(host);
d129bceb
PO		 1841}
1842
0957c333 1843#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 1844static void sdhci_show_adma_error(struct sdhci_host *host)
1845{
1846 const char *name = mmc_hostname(host->mmc);
1847 u8 *desc = host->adma_desc;
1848 __le32 *dma;
1849 __le16 *len;
1850 u8 attr;
1851
1852 sdhci_dumpregs(host);
1853
1854 while (true) {
1855 dma = (__le32 *)(desc + 4);
1856 len = (__le16 *)(desc + 2);
1857 attr = *desc;
1858
1859 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1860 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1861
1862 desc += 8;
1863
1864 if (attr & 2)
1865 break;
1866 }
1867}
1868#else
1869static void sdhci_show_adma_error(struct sdhci_host *host) { }
1870#endif
1871
d129bceb
PO		 1872static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1873{
1874 BUG_ON(intmask == 0);
1875
b513ea25
AN		 1876 /* CMD19 generates _only_ Buffer Read Ready interrupt */
1877 if (intmask & SDHCI_INT_DATA_AVAIL) {
1878 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
1879 MMC_SEND_TUNING_BLOCK) {
1880 host->tuning_done = 1;
1881 wake_up(&host->buf_ready_int);
1882 return;
1883 }
1884 }
1885
d129bceb
PO		 1886 if (!host->data) {
1887 /*
e809517f
PO		 1888 * The "data complete" interrupt is also used to
1889 * indicate that a busy state has ended. See comment
1890 * above in sdhci_cmd_irq().
d129bceb 1891 */
e809517f
PO		 1892 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1893 if (intmask & SDHCI_INT_DATA_END) {
1894 sdhci_finish_command(host);
1895 return;
1896 }
1897 }
d129bceb 1898
b67ac3f3
PO		 1899 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1900 "though no data operation was in progress.\n",
1901 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1902 sdhci_dumpregs(host);
1903
1904 return;
1905 }
1906
1907 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 1908 host->data->error = -ETIMEDOUT;
22113efd
AL		 1909 else if (intmask & SDHCI_INT_DATA_END_BIT)
1910 host->data->error = -EILSEQ;
1911 else if ((intmask & SDHCI_INT_DATA_CRC) &&
1912 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
1913 != MMC_BUS_TEST_R)
17b0429d 1914 host->data->error = -EILSEQ;
6882a8c0
BD		 1915 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1916 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1917 sdhci_show_adma_error(host);
2134a922 1918 host->data->error = -EIO;
6882a8c0 1919 }
d129bceb 1920
17b0429d 1921 if (host->data->error)
d129bceb
PO		 1922 sdhci_finish_data(host);
1923 else {
a406f5a3 1924 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1925 sdhci_transfer_pio(host);
1926
6ba736a1
PO		 1927 /*
1928 * We currently don't do anything fancy with DMA
1929 * boundaries, but as we can't disable the feature
1930 * we need to at least restart the transfer.
f6a03cbf
MV		 1931 *
1932 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
1933 * should return a valid address to continue from, but as
1934 * some controllers are faulty, don't trust them.
6ba736a1 1935 */
f6a03cbf
MV		 1936 if (intmask & SDHCI_INT_DMA_END) {
1937 u32 dmastart, dmanow;
1938 dmastart = sg_dma_address(host->data->sg);
1939 dmanow = dmastart + host->data->bytes_xfered;
1940 /*
1941 * Force update to the next DMA block boundary.
1942 */
1943 dmanow = (dmanow &
1944 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
1945 SDHCI_DEFAULT_BOUNDARY_SIZE;
1946 host->data->bytes_xfered = dmanow - dmastart;
1947 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
1948 " next 0x%08x\n",
1949 mmc_hostname(host->mmc), dmastart,
1950 host->data->bytes_xfered, dmanow);
1951 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
1952 }
6ba736a1 1953
e538fbe8
PO		 1954 if (intmask & SDHCI_INT_DATA_END) {
1955 if (host->cmd) {
1956 /*
1957 * Data managed to finish before the
1958 * command completed. Make sure we do
1959 * things in the proper order.
1960 */
1961 host->data_early = 1;
1962 } else {
1963 sdhci_finish_data(host);
1964 }
1965 }
d129bceb
PO		 1966 }
1967}
1968
7d12e780 1969static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1970{
1971 irqreturn_t result;
1972 struct sdhci_host* host = dev_id;
1973 u32 intmask;
f75979b7 1974 int cardint = 0;
d129bceb
PO		 1975
1976 spin_lock(&host->lock);
1977
4e4141a5 1978 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 1979
62df67a5 1980 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1981 result = IRQ_NONE;
1982 goto out;
1983 }
1984
b69c9058
PO		 1985 DBG("*** %s got interrupt: 0x%08x\n",
1986 mmc_hostname(host->mmc), intmask);
d129bceb 1987
3192a28f 1988 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
4e4141a5
AV		 1989 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1990 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
d129bceb 1991 tasklet_schedule(&host->card_tasklet);
3192a28f 1992 }
d129bceb 1993
3192a28f 1994 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1995
3192a28f 1996 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 1997 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1998 SDHCI_INT_STATUS);
3192a28f 1999 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2000 }
2001
2002 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2003 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2004 SDHCI_INT_STATUS);
3192a28f 2005 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2006 }
2007
2008 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2009
964f9ce2
PO		 2010 intmask &= ~SDHCI_INT_ERROR;
2011
d129bceb 2012 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 2013 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 2014 mmc_hostname(host->mmc));
4e4141a5 2015 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2016 }
2017
9d26a5d3 2018 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2019
f75979b7
PO		 2020 if (intmask & SDHCI_INT_CARD_INT)
2021 cardint = 1;
2022
2023 intmask &= ~SDHCI_INT_CARD_INT;
2024
3192a28f 2025 if (intmask) {
acf1da45 2026 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 2027 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 2028 sdhci_dumpregs(host);
2029
4e4141a5 2030 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2031 }
d129bceb
PO		 2032
2033 result = IRQ_HANDLED;
2034
5f25a66f 2035 mmiowb();
d129bceb
PO		 2036out:
2037 spin_unlock(&host->lock);
2038
f75979b7
PO		 2039 /*
2040 * We have to delay this as it calls back into the driver.
2041 */
2042 if (cardint)
2043 mmc_signal_sdio_irq(host->mmc);
2044
d129bceb
PO		 2045 return result;
2046}
2047
2048/*****************************************************************************\
2049 * *
2050 * Suspend/resume *
2051 * *
2052\*****************************************************************************/
2053
2054#ifdef CONFIG_PM
2055
b8c86fc5 2056int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 2057{
b8c86fc5 2058 int ret;
a715dfc7 2059
7260cf5e
AV		 2060 sdhci_disable_card_detection(host);
2061
1a13f8fa 2062 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 2063 if (ret)
2064 return ret;
a715dfc7 2065
b8c86fc5 2066 free_irq(host->irq, host);
d129bceb 2067
9bea3c85
MS		 2068 if (host->vmmc)
2069 ret = regulator_disable(host->vmmc);
2070
2071 return ret;
d129bceb
PO		 2072}
2073
b8c86fc5 2074EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2075
b8c86fc5
PO		 2076int sdhci_resume_host(struct sdhci_host *host)
2077{
2078 int ret;
d129bceb 2079
9bea3c85
MS		 2080 if (host->vmmc) {
2081 int ret = regulator_enable(host->vmmc);
2082 if (ret)
2083 return ret;
2084 }
2085
2086
a13abc7b 2087 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2088 if (host->ops->enable_dma)
2089 host->ops->enable_dma(host);
2090 }
d129bceb 2091
b8c86fc5
PO		 2092 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2093 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2094 if (ret)
2095 return ret;
d129bceb 2096
2f4cbb3d 2097 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 2098 mmiowb();
2099
2100 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2101 sdhci_enable_card_detection(host);
2102
2f4cbb3d 2103 return ret;
d129bceb
PO		 2104}
2105
b8c86fc5 2106EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2107
5f619704
DD		 2108void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2109{
2110 u8 val;
2111 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2112 val |= SDHCI_WAKE_ON_INT;
2113 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2114}
2115
2116EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2117
d129bceb
PO		 2118#endif /* CONFIG_PM */
2119
2120/*****************************************************************************\
2121 * *
b8c86fc5 2122 * Device allocation/registration *
d129bceb
PO		 2123 * *
2124\*****************************************************************************/
2125
b8c86fc5
PO		 2126struct sdhci_host *sdhci_alloc_host(struct device *dev,
2127 size_t priv_size)
d129bceb 2128{
d129bceb
PO		 2129 struct mmc_host *mmc;
2130 struct sdhci_host *host;
2131
b8c86fc5 2132 WARN_ON(dev == NULL);
d129bceb 2133
b8c86fc5 2134 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2135 if (!mmc)
b8c86fc5 2136 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2137
2138 host = mmc_priv(mmc);
2139 host->mmc = mmc;
2140
b8c86fc5
PO		 2141 return host;
2142}
8a4da143 2143
b8c86fc5 2144EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2145
b8c86fc5
PO		 2146int sdhci_add_host(struct sdhci_host *host)
2147{
2148 struct mmc_host *mmc;
f2119df6
AN		 2149 u32 caps[2];
2150 u32 max_current_caps;
2151 unsigned int ocr_avail;
b8c86fc5 2152 int ret;
d129bceb 2153
b8c86fc5
PO		 2154 WARN_ON(host == NULL);
2155 if (host == NULL)
2156 return -EINVAL;
d129bceb 2157
b8c86fc5 2158 mmc = host->mmc;
d129bceb 2159
b8c86fc5
PO		 2160 if (debug_quirks)
2161 host->quirks = debug_quirks;
d129bceb 2162
d96649ed
PO		 2163 sdhci_reset(host, SDHCI_RESET_ALL);
2164
4e4141a5 2165 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2166 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2167 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2168 if (host->version > SDHCI_SPEC_300) {
4a965505 2169 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 2170 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2171 host->version);
4a965505
PO		 2172 }
2173
f2119df6 2174 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2175 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2176
f2119df6
AN		 2177 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2178 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2179
b8c86fc5 2180 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2181 host->flags |= SDHCI_USE_SDMA;
f2119df6 2182 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2183 DBG("Controller doesn't have SDMA capability\n");
67435274 2184 else
a13abc7b 2185 host->flags |= SDHCI_USE_SDMA;
d129bceb 2186
b8c86fc5 2187 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2188 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2189 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2190 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2191 }
2192
f2119df6
AN		 2193 if ((host->version >= SDHCI_SPEC_200) &&
2194 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2195 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2196
2197 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2198 (host->flags & SDHCI_USE_ADMA)) {
2199 DBG("Disabling ADMA as it is marked broken\n");
2200 host->flags &= ~SDHCI_USE_ADMA;
2201 }
2202
a13abc7b 2203 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2204 if (host->ops->enable_dma) {
2205 if (host->ops->enable_dma(host)) {
2206 printk(KERN_WARNING "%s: No suitable DMA "
2207 "available. Falling back to PIO.\n",
2208 mmc_hostname(mmc));
a13abc7b
RR		 2209 host->flags &=
2210 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2211 }
d129bceb
PO		 2212 }
2213 }
2214
2134a922
PO		 2215 if (host->flags & SDHCI_USE_ADMA) {
2216 /*
2217 * We need to allocate descriptors for all sg entries
2218 * (128) and potentially one alignment transfer for
2219 * each of those entries.
2220 */
2221 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2222 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2223 if (!host->adma_desc || !host->align_buffer) {
2224 kfree(host->adma_desc);
2225 kfree(host->align_buffer);
2226 printk(KERN_WARNING "%s: Unable to allocate ADMA "
2227 "buffers. Falling back to standard DMA.\n",
2228 mmc_hostname(mmc));
2229 host->flags &= ~SDHCI_USE_ADMA;
2230 }
2231 }
2232
7659150c
PO		 2233 /*
2234 * If we use DMA, then it's up to the caller to set the DMA
2235 * mask, but PIO does not need the hw shim so we set a new
2236 * mask here in that case.
2237 */
a13abc7b 2238 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2239 host->dma_mask = DMA_BIT_MASK(64);
2240 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2241 }
d129bceb 2242
c4687d5f 2243 if (host->version >= SDHCI_SPEC_300)
f2119df6 2244 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2245 >> SDHCI_CLOCK_BASE_SHIFT;
2246 else
f2119df6 2247 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2248 >> SDHCI_CLOCK_BASE_SHIFT;
2249
4240ff0a 2250 host->max_clk *= 1000000;
f27f47ef
AV		 2251 if (host->max_clk == 0 || host->quirks &
2252 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a
BD		 2253 if (!host->ops->get_max_clock) {
2254 printk(KERN_ERR
2255 "%s: Hardware doesn't specify base clock "
2256 "frequency.\n", mmc_hostname(mmc));
2257 return -ENODEV;
2258 }
2259 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2260 }
d129bceb 2261
1c8cde92 2262 host->timeout_clk =
f2119df6 2263 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1c8cde92 2264 if (host->timeout_clk == 0) {
81b39802
AV		 2265 if (host->ops->get_timeout_clock) {
2266 host->timeout_clk = host->ops->get_timeout_clock(host);
2267 } else if (!(host->quirks &
2268 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4240ff0a
BD		 2269 printk(KERN_ERR
2270 "%s: Hardware doesn't specify timeout clock "
2271 "frequency.\n", mmc_hostname(mmc));
2272 return -ENODEV;
2273 }
1c8cde92 2274 }
f2119df6 2275 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
1c8cde92 2276 host->timeout_clk *= 1000;
d129bceb
PO		 2277
2278 /*
2279 * Set host parameters.
2280 */
2281 mmc->ops = &sdhci_ops;
ce5f036b 2282 if (host->ops->get_min_clock)
a9e58f25 2283 mmc->f_min = host->ops->get_min_clock(host);
0397526d
ZG		 2284 else if (host->version >= SDHCI_SPEC_300)
2285 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
a9e58f25 2286 else
0397526d 2287 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2288
d129bceb 2289 mmc->f_max = host->max_clk;
a3c7778f 2290 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE;
5fe23c7f 2291
15ec4461
PR		 2292 /*
2293 * A controller may support 8-bit width, but the board itself
2294 * might not have the pins brought out. Boards that support
2295 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2296 * their platform code before calling sdhci_add_host(), and we
2297 * won't assume 8-bit width for hosts without that CAP.
2298 */
5fe23c7f 2299 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2300 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2301
f2119df6 2302 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2303 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2304
176d1ed4
JC		 2305 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2306 mmc_card_is_removable(mmc))
68d1fb7e
AV		 2307 mmc->caps |= MMC_CAP_NEEDS_POLL;
2308
f2119df6
AN		 2309 /* UHS-I mode(s) supported by the host controller. */
2310 if (host->version >= SDHCI_SPEC_300)
2311 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2312
2313 /* SDR104 supports also implies SDR50 support */
2314 if (caps[1] & SDHCI_SUPPORT_SDR104)
2315 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2316 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2317 mmc->caps |= MMC_CAP_UHS_SDR50;
2318
2319 if (caps[1] & SDHCI_SUPPORT_DDR50)
2320 mmc->caps |= MMC_CAP_UHS_DDR50;
2321
b513ea25
AN		 2322 /* Does the host needs tuning for SDR50? */
2323 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2324 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2325
d6d50a15
AN		 2326 /* Driver Type(s) (A, C, D) supported by the host */
2327 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2328 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2329 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2330 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2331 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2332 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2333
8f230f45 2334 ocr_avail = 0;
f2119df6
AN		 2335 /*
2336 * According to SD Host Controller spec v3.00, if the Host System
2337 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2338 * the value is meaningful only if Voltage Support in the Capabilities
2339 * register is set. The actual current value is 4 times the register
2340 * value.
2341 */
2342 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2343
2344 if (caps[0] & SDHCI_CAN_VDD_330) {
2345 int max_current_330;
2346
8f230f45 2347 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6
AN		 2348
2349 max_current_330 = ((max_current_caps &
2350 SDHCI_MAX_CURRENT_330_MASK) >>
2351 SDHCI_MAX_CURRENT_330_SHIFT) *
2352 SDHCI_MAX_CURRENT_MULTIPLIER;
2353
2354 if (max_current_330 > 150)
2355 mmc->caps |= MMC_CAP_SET_XPC_330;
2356 }
2357 if (caps[0] & SDHCI_CAN_VDD_300) {
2358 int max_current_300;
2359
8f230f45 2360 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6
AN		 2361
2362 max_current_300 = ((max_current_caps &
2363 SDHCI_MAX_CURRENT_300_MASK) >>
2364 SDHCI_MAX_CURRENT_300_SHIFT) *
2365 SDHCI_MAX_CURRENT_MULTIPLIER;
2366
2367 if (max_current_300 > 150)
2368 mmc->caps |= MMC_CAP_SET_XPC_300;
2369 }
2370 if (caps[0] & SDHCI_CAN_VDD_180) {
2371 int max_current_180;
2372
8f230f45
TI		 2373 ocr_avail |= MMC_VDD_165_195;
2374
f2119df6
AN		 2375 max_current_180 = ((max_current_caps &
2376 SDHCI_MAX_CURRENT_180_MASK) >>
2377 SDHCI_MAX_CURRENT_180_SHIFT) *
2378 SDHCI_MAX_CURRENT_MULTIPLIER;
2379
2380 if (max_current_180 > 150)
2381 mmc->caps |= MMC_CAP_SET_XPC_180;
5371c927
AN		 2382
2383 /* Maximum current capabilities of the host at 1.8V */
2384 if (max_current_180 >= 800)
2385 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2386 else if (max_current_180 >= 600)
2387 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2388 else if (max_current_180 >= 400)
2389 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2390 else
2391 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
f2119df6
AN		 2392 }
2393
8f230f45
TI		 2394 mmc->ocr_avail = ocr_avail;
2395 mmc->ocr_avail_sdio = ocr_avail;
2396 if (host->ocr_avail_sdio)
2397 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2398 mmc->ocr_avail_sd = ocr_avail;
2399 if (host->ocr_avail_sd)
2400 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2401 else /* normal SD controllers don't support 1.8V */
2402 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2403 mmc->ocr_avail_mmc = ocr_avail;
2404 if (host->ocr_avail_mmc)
2405 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2406
2407 if (mmc->ocr_avail == 0) {
2408 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 2409 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2410 return -ENODEV;
146ad66e
PO		 2411 }
2412
d129bceb
PO		 2413 spin_lock_init(&host->lock);
2414
2415 /*
2134a922
PO		 2416 * Maximum number of segments. Depends on if the hardware
2417 * can do scatter/gather or not.
d129bceb 2418 */
2134a922 2419 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2420 mmc->max_segs = 128;
a13abc7b 2421 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2422 mmc->max_segs = 1;
2134a922 2423 else /* PIO */
a36274e0 2424 mmc->max_segs = 128;
d129bceb
PO		 2425
2426 /*
bab76961 2427 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2428 * size (512KiB).
d129bceb 2429 */
55db890a 2430 mmc->max_req_size = 524288;
d129bceb
PO		 2431
2432 /*
2433 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2434 * of bytes. When doing hardware scatter/gather, each entry cannot
2435 * be larger than 64 KiB though.
d129bceb 2436 */
30652aa3
OJ		 2437 if (host->flags & SDHCI_USE_ADMA) {
2438 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2439 mmc->max_seg_size = 65535;
2440 else
2441 mmc->max_seg_size = 65536;
2442 } else {
2134a922 2443 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2444 }
d129bceb 2445
fe4a3c7a
PO		 2446 /*
2447 * Maximum block size. This varies from controller to controller and
2448 * is specified in the capabilities register.
2449 */
0633f654
AV		 2450 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2451 mmc->max_blk_size = 2;
2452 } else {
f2119df6 2453 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2454 SDHCI_MAX_BLOCK_SHIFT;
2455 if (mmc->max_blk_size >= 3) {
2456 printk(KERN_WARNING "%s: Invalid maximum block size, "
2457 "assuming 512 bytes\n", mmc_hostname(mmc));
2458 mmc->max_blk_size = 0;
2459 }
2460 }
2461
2462 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 2463
55db890a
PO		 2464 /*
2465 * Maximum block count.
2466 */
1388eefd 2467 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 2468
d129bceb
PO		 2469 /*
2470 * Init tasklets.
2471 */
2472 tasklet_init(&host->card_tasklet,
2473 sdhci_tasklet_card, (unsigned long)host);
2474 tasklet_init(&host->finish_tasklet,
2475 sdhci_tasklet_finish, (unsigned long)host);
2476
e4cad1b5 2477 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2478
b513ea25
AN		 2479 if (host->version >= SDHCI_SPEC_300)
2480 init_waitqueue_head(&host->buf_ready_int);
2481
dace1453 2482 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2483 mmc_hostname(mmc), host);
d129bceb 2484 if (ret)
8ef1a143 2485 goto untasklet;
d129bceb 2486
9bea3c85
MS		 2487 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2488 if (IS_ERR(host->vmmc)) {
2489 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2490 host->vmmc = NULL;
2491 } else {
2492 regulator_enable(host->vmmc);
2493 }
2494
2f4cbb3d 2495 sdhci_init(host, 0);
d129bceb
PO		 2496
2497#ifdef CONFIG_MMC_DEBUG
2498 sdhci_dumpregs(host);
2499#endif
2500
f9134319 2501#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2502 snprintf(host->led_name, sizeof(host->led_name),
2503 "%s::", mmc_hostname(mmc));
2504 host->led.name = host->led_name;
2f730fec
PO		 2505 host->led.brightness = LED_OFF;
2506 host->led.default_trigger = mmc_hostname(mmc);
2507 host->led.brightness_set = sdhci_led_control;
2508
b8c86fc5 2509 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2510 if (ret)
2511 goto reset;
2512#endif
2513
5f25a66f
PO		 2514 mmiowb();
2515
d129bceb
PO		 2516 mmc_add_host(mmc);
2517
a13abc7b 2518 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2519 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2520 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2521 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2522
7260cf5e
AV		 2523 sdhci_enable_card_detection(host);
2524
d129bceb
PO		 2525 return 0;
2526
f9134319 2527#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2528reset:
2529 sdhci_reset(host, SDHCI_RESET_ALL);
2530 free_irq(host->irq, host);
2531#endif
8ef1a143 2532untasklet:
d129bceb
PO		 2533 tasklet_kill(&host->card_tasklet);
2534 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2535
2536 return ret;
2537}
2538
b8c86fc5 2539EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2540
1e72859e 2541void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2542{
1e72859e
PO		 2543 unsigned long flags;
2544
2545 if (dead) {
2546 spin_lock_irqsave(&host->lock, flags);
2547
2548 host->flags |= SDHCI_DEVICE_DEAD;
2549
2550 if (host->mrq) {
2551 printk(KERN_ERR "%s: Controller removed during "
2552 " transfer!\n", mmc_hostname(host->mmc));
2553
2554 host->mrq->cmd->error = -ENOMEDIUM;
2555 tasklet_schedule(&host->finish_tasklet);
2556 }
2557
2558 spin_unlock_irqrestore(&host->lock, flags);
2559 }
2560
7260cf5e
AV		 2561 sdhci_disable_card_detection(host);
2562
b8c86fc5 2563 mmc_remove_host(host->mmc);
d129bceb 2564
f9134319 2565#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2566 led_classdev_unregister(&host->led);
2567#endif
2568
1e72859e
PO		 2569 if (!dead)
2570 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 2571
2572 free_irq(host->irq, host);
2573
2574 del_timer_sync(&host->timer);
2575
2576 tasklet_kill(&host->card_tasklet);
2577 tasklet_kill(&host->finish_tasklet);
2134a922 2578
9bea3c85
MS		 2579 if (host->vmmc) {
2580 regulator_disable(host->vmmc);
2581 regulator_put(host->vmmc);
2582 }
2583
2134a922
PO		 2584 kfree(host->adma_desc);
2585 kfree(host->align_buffer);
2586
2587 host->adma_desc = NULL;
2588 host->align_buffer = NULL;
d129bceb
PO		 2589}
2590
b8c86fc5 2591EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 2592
b8c86fc5 2593void sdhci_free_host(struct sdhci_host *host)
d129bceb 2594{
b8c86fc5 2595 mmc_free_host(host->mmc);
d129bceb
PO		 2596}
2597
b8c86fc5 2598EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 2599
2600/*****************************************************************************\
2601 * *
2602 * Driver init/exit *
2603 * *
2604\*****************************************************************************/
2605
2606static int __init sdhci_drv_init(void)
2607{
2608 printk(KERN_INFO DRIVER_NAME
52fbf9c9 2609 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 2610 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2611
b8c86fc5 2612 return 0;
d129bceb
PO		 2613}
2614
2615static void __exit sdhci_drv_exit(void)
2616{
d129bceb
PO		 2617}
2618
2619module_init(sdhci_drv_init);
2620module_exit(sdhci_drv_exit);
2621
df673b22 2622module_param(debug_quirks, uint, 0444);
67435274 2623
32710e8f 2624MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 2625MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 2626MODULE_LICENSE("GPL");
67435274 2627
df673b22 2628MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux kernel - Deliverables
This page took 0.684574 seconds and 5 git commands to generate.