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mmc: sdhci: more efficient interrupt enable register handling
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
d129bceb 52static void sdhci_finish_command(struct sdhci_host *);
069c9f14 53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 54static void sdhci_tuning_timer(unsigned long data);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 56
66fd8ad5
AH		 57#ifdef CONFIG_PM_RUNTIME
58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 60static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 62#else
63static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
64{
65 return 0;
66}
67static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
68{
69 return 0;
70}
f0710a55
AH		 71static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
72{
73}
74static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
75{
76}
66fd8ad5
AH		 77#endif
78
d129bceb
PO		 79static void sdhci_dumpregs(struct sdhci_host *host)
80{
a3c76eb9 81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 82 mmc_hostname(host->mmc));
d129bceb 83
a3c76eb9 84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 112 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 115 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 116 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 119
be3f4ae0 120 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 121 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 122 readl(host->ioaddr + SDHCI_ADMA_ERROR),
123 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
124
a3c76eb9 125 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 126}
127
128/*****************************************************************************\
129 * *
130 * Low level functions *
131 * *
132\*****************************************************************************/
133
7260cf5e
AV		 134static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
135{
d25928d1 136 u32 present, irqs;
7260cf5e 137
c79396c1 138 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 139 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 140 return;
141
d25928d1
SG		 142 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
143 SDHCI_CARD_PRESENT;
144 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
145
7260cf5e 146 if (enable)
b537f94c 147 host->ier |= irqs;
7260cf5e 148 else
b537f94c
RK		 149 host->ier &= ~irqs;
150
151 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
152 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 153}
154
155static void sdhci_enable_card_detection(struct sdhci_host *host)
156{
157 sdhci_set_card_detection(host, true);
158}
159
160static void sdhci_disable_card_detection(struct sdhci_host *host)
161{
162 sdhci_set_card_detection(host, false);
163}
164
d129bceb
PO		 165static void sdhci_reset(struct sdhci_host *host, u8 mask)
166{
e16514d8 167 unsigned long timeout;
b8c86fc5 168 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 169 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 170 SDHCI_CARD_PRESENT))
171 return;
172 }
173
393c1a34
PR		 174 if (host->ops->platform_reset_enter)
175 host->ops->platform_reset_enter(host, mask);
176
4e4141a5 177 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 178
f0710a55 179 if (mask & SDHCI_RESET_ALL) {
d129bceb 180 host->clock = 0;
f0710a55
AH		 181 /* Reset-all turns off SD Bus Power */
182 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
183 sdhci_runtime_pm_bus_off(host);
184 }
d129bceb 185
e16514d8
PO		 186 /* Wait max 100 ms */
187 timeout = 100;
188
189 /* hw clears the bit when it's done */
4e4141a5 190 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 191 if (timeout == 0) {
a3c76eb9 192 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 193 mmc_hostname(host->mmc), (int)mask);
194 sdhci_dumpregs(host);
195 return;
196 }
197 timeout--;
198 mdelay(1);
d129bceb 199 }
063a9dbb 200
393c1a34
PR		 201 if (host->ops->platform_reset_exit)
202 host->ops->platform_reset_exit(host, mask);
203
b537f94c
RK		 204 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) {
205 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
206 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
207 }
3abc1e80
SX		 208
209 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
210 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
211 host->ops->enable_dma(host);
212 }
d129bceb
PO		 213}
214
2f4cbb3d
NP		 215static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
216
217static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 218{
2f4cbb3d
NP		 219 if (soft)
220 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
221 else
222 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 223
b537f94c
RK		 224 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
225 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
226 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
227 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
228 SDHCI_INT_RESPONSE;
229
230 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
231 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 232
233 if (soft) {
234 /* force clock reconfiguration */
235 host->clock = 0;
236 sdhci_set_ios(host->mmc, &host->mmc->ios);
237 }
7260cf5e 238}
d129bceb 239
7260cf5e
AV		 240static void sdhci_reinit(struct sdhci_host *host)
241{
2f4cbb3d 242 sdhci_init(host, 0);
b67c6b41
AL		 243 /*
244 * Retuning stuffs are affected by different cards inserted and only
245 * applicable to UHS-I cards. So reset these fields to their initial
246 * value when card is removed.
247 */
973905fe
AL		 248 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
249 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
250
b67c6b41
AL		 251 del_timer_sync(&host->tuning_timer);
252 host->flags &= ~SDHCI_NEEDS_RETUNING;
253 host->mmc->max_blk_count =
254 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
255 }
7260cf5e 256 sdhci_enable_card_detection(host);
d129bceb
PO		 257}
258
259static void sdhci_activate_led(struct sdhci_host *host)
260{
261 u8 ctrl;
262
4e4141a5 263 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 264 ctrl |= SDHCI_CTRL_LED;
4e4141a5 265 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 266}
267
268static void sdhci_deactivate_led(struct sdhci_host *host)
269{
270 u8 ctrl;
271
4e4141a5 272 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 273 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 274 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 275}
276
f9134319 277#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 278static void sdhci_led_control(struct led_classdev *led,
279 enum led_brightness brightness)
280{
281 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
282 unsigned long flags;
283
284 spin_lock_irqsave(&host->lock, flags);
285
66fd8ad5
AH		 286 if (host->runtime_suspended)
287 goto out;
288
2f730fec
PO		 289 if (brightness == LED_OFF)
290 sdhci_deactivate_led(host);
291 else
292 sdhci_activate_led(host);
66fd8ad5 293out:
2f730fec
PO		 294 spin_unlock_irqrestore(&host->lock, flags);
295}
296#endif
297
d129bceb
PO		 298/*****************************************************************************\
299 * *
300 * Core functions *
301 * *
302\*****************************************************************************/
303
a406f5a3 304static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 305{
7659150c
PO		 306 unsigned long flags;
307 size_t blksize, len, chunk;
7244b85b 308 u32 uninitialized_var(scratch);
7659150c 309 u8 *buf;
d129bceb 310
a406f5a3 311 DBG("PIO reading\n");
d129bceb 312
a406f5a3 313 blksize = host->data->blksz;
7659150c 314 chunk = 0;
d129bceb 315
7659150c 316 local_irq_save(flags);
d129bceb 317
a406f5a3 318 while (blksize) {
7659150c
PO		 319 if (!sg_miter_next(&host->sg_miter))
320 BUG();
d129bceb 321
7659150c 322 len = min(host->sg_miter.length, blksize);
d129bceb 323
7659150c
PO		 324 blksize -= len;
325 host->sg_miter.consumed = len;
14d836e7 326
7659150c 327 buf = host->sg_miter.addr;
d129bceb 328
7659150c
PO		 329 while (len) {
330 if (chunk == 0) {
4e4141a5 331 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 332 chunk = 4;
a406f5a3 333 }
7659150c
PO		 334
335 *buf = scratch & 0xFF;
336
337 buf++;
338 scratch >>= 8;
339 chunk--;
340 len--;
d129bceb 341 }
a406f5a3 342 }
7659150c
PO		 343
344 sg_miter_stop(&host->sg_miter);
345
346 local_irq_restore(flags);
a406f5a3 347}
d129bceb 348
a406f5a3
PO		 349static void sdhci_write_block_pio(struct sdhci_host *host)
350{
7659150c
PO		 351 unsigned long flags;
352 size_t blksize, len, chunk;
353 u32 scratch;
354 u8 *buf;
d129bceb 355
a406f5a3
PO		 356 DBG("PIO writing\n");
357
358 blksize = host->data->blksz;
7659150c
PO		 359 chunk = 0;
360 scratch = 0;
d129bceb 361
7659150c 362 local_irq_save(flags);
d129bceb 363
a406f5a3 364 while (blksize) {
7659150c
PO		 365 if (!sg_miter_next(&host->sg_miter))
366 BUG();
a406f5a3 367
7659150c
PO		 368 len = min(host->sg_miter.length, blksize);
369
370 blksize -= len;
371 host->sg_miter.consumed = len;
372
373 buf = host->sg_miter.addr;
d129bceb 374
7659150c
PO		 375 while (len) {
376 scratch |= (u32)*buf << (chunk * 8);
377
378 buf++;
379 chunk++;
380 len--;
381
382 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 383 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 384 chunk = 0;
385 scratch = 0;
d129bceb 386 }
d129bceb
PO		 387 }
388 }
7659150c
PO		 389
390 sg_miter_stop(&host->sg_miter);
391
392 local_irq_restore(flags);
a406f5a3
PO		 393}
394
395static void sdhci_transfer_pio(struct sdhci_host *host)
396{
397 u32 mask;
398
399 BUG_ON(!host->data);
400
7659150c 401 if (host->blocks == 0)
a406f5a3
PO		 402 return;
403
404 if (host->data->flags & MMC_DATA_READ)
405 mask = SDHCI_DATA_AVAILABLE;
406 else
407 mask = SDHCI_SPACE_AVAILABLE;
408
4a3cba32
PO		 409 /*
410 * Some controllers (JMicron JMB38x) mess up the buffer bits
411 * for transfers < 4 bytes. As long as it is just one block,
412 * we can ignore the bits.
413 */
414 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
415 (host->data->blocks == 1))
416 mask = ~0;
417
4e4141a5 418 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 419 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
420 udelay(100);
421
a406f5a3
PO		 422 if (host->data->flags & MMC_DATA_READ)
423 sdhci_read_block_pio(host);
424 else
425 sdhci_write_block_pio(host);
d129bceb 426
7659150c
PO		 427 host->blocks--;
428 if (host->blocks == 0)
a406f5a3 429 break;
a406f5a3 430 }
d129bceb 431
a406f5a3 432 DBG("PIO transfer complete.\n");
d129bceb
PO		 433}
434
2134a922
PO		 435static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
436{
437 local_irq_save(*flags);
482fce99 438 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 439}
440
441static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
442{
482fce99 443 kunmap_atomic(buffer);
2134a922
PO		 444 local_irq_restore(*flags);
445}
446
118cd17d
BD		 447static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
448{
9e506f35
BD		 449 __le32 *dataddr = (__le32 __force *)(desc + 4);
450 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 451
9e506f35
BD		 452 /* SDHCI specification says ADMA descriptors should be 4 byte
453 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 454
9e506f35
BD		 455 cmdlen[0] = cpu_to_le16(cmd);
456 cmdlen[1] = cpu_to_le16(len);
457
458 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 459}
460
8f1934ce 461static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 462 struct mmc_data *data)
463{
464 int direction;
465
466 u8 *desc;
467 u8 *align;
468 dma_addr_t addr;
469 dma_addr_t align_addr;
470 int len, offset;
471
472 struct scatterlist *sg;
473 int i;
474 char *buffer;
475 unsigned long flags;
476
477 /*
478 * The spec does not specify endianness of descriptor table.
479 * We currently guess that it is LE.
480 */
481
482 if (data->flags & MMC_DATA_READ)
483 direction = DMA_FROM_DEVICE;
484 else
485 direction = DMA_TO_DEVICE;
486
487 /*
488 * The ADMA descriptor table is mapped further down as we
489 * need to fill it with data first.
490 */
491
492 host->align_addr = dma_map_single(mmc_dev(host->mmc),
493 host->align_buffer, 128 * 4, direction);
8d8bb39b 494 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 495 goto fail;
2134a922
PO		 496 BUG_ON(host->align_addr & 0x3);
497
498 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
499 data->sg, data->sg_len, direction);
8f1934ce
PO		 500 if (host->sg_count == 0)
501 goto unmap_align;
2134a922
PO		 502
503 desc = host->adma_desc;
504 align = host->align_buffer;
505
506 align_addr = host->align_addr;
507
508 for_each_sg(data->sg, sg, host->sg_count, i) {
509 addr = sg_dma_address(sg);
510 len = sg_dma_len(sg);
511
512 /*
513 * The SDHCI specification states that ADMA
514 * addresses must be 32-bit aligned. If they
515 * aren't, then we use a bounce buffer for
516 * the (up to three) bytes that screw up the
517 * alignment.
518 */
519 offset = (4 - (addr & 0x3)) & 0x3;
520 if (offset) {
521 if (data->flags & MMC_DATA_WRITE) {
522 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 523 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 524 memcpy(align, buffer, offset);
525 sdhci_kunmap_atomic(buffer, &flags);
526 }
527
118cd17d
BD		 528 /* tran, valid */
529 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 530
531 BUG_ON(offset > 65536);
532
2134a922
PO		 533 align += 4;
534 align_addr += 4;
535
536 desc += 8;
537
538 addr += offset;
539 len -= offset;
540 }
541
2134a922
PO		 542 BUG_ON(len > 65536);
543
118cd17d
BD		 544 /* tran, valid */
545 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 546 desc += 8;
547
548 /*
549 * If this triggers then we have a calculation bug
550 * somewhere. :/
551 */
552 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
553 }
554
70764a90
TA		 555 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
556 /*
557 * Mark the last descriptor as the terminating descriptor
558 */
559 if (desc != host->adma_desc) {
560 desc -= 8;
561 desc[0] |= 0x2; /* end */
562 }
563 } else {
564 /*
565 * Add a terminating entry.
566 */
2134a922 567
70764a90
TA		 568 /* nop, end, valid */
569 sdhci_set_adma_desc(desc, 0, 0, 0x3);
570 }
2134a922
PO		 571
572 /*
573 * Resync align buffer as we might have changed it.
574 */
575 if (data->flags & MMC_DATA_WRITE) {
576 dma_sync_single_for_device(mmc_dev(host->mmc),
577 host->align_addr, 128 * 4, direction);
578 }
579
580 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
581 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 582 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 583 goto unmap_entries;
2134a922 584 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 585
586 return 0;
587
588unmap_entries:
589 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
590 data->sg_len, direction);
591unmap_align:
592 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
593 128 * 4, direction);
594fail:
595 return -EINVAL;
2134a922
PO		 596}
597
598static void sdhci_adma_table_post(struct sdhci_host *host,
599 struct mmc_data *data)
600{
601 int direction;
602
603 struct scatterlist *sg;
604 int i, size;
605 u8 *align;
606 char *buffer;
607 unsigned long flags;
608
609 if (data->flags & MMC_DATA_READ)
610 direction = DMA_FROM_DEVICE;
611 else
612 direction = DMA_TO_DEVICE;
613
614 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
615 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
616
617 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
618 128 * 4, direction);
619
620 if (data->flags & MMC_DATA_READ) {
621 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
622 data->sg_len, direction);
623
624 align = host->align_buffer;
625
626 for_each_sg(data->sg, sg, host->sg_count, i) {
627 if (sg_dma_address(sg) & 0x3) {
628 size = 4 - (sg_dma_address(sg) & 0x3);
629
630 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 631 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 632 memcpy(buffer, align, size);
633 sdhci_kunmap_atomic(buffer, &flags);
634
635 align += 4;
636 }
637 }
638 }
639
640 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
641 data->sg_len, direction);
642}
643
a3c7778f 644static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 645{
1c8cde92 646 u8 count;
a3c7778f 647 struct mmc_data *data = cmd->data;
1c8cde92 648 unsigned target_timeout, current_timeout;
d129bceb 649
ee53ab5d
PO		 650 /*
651 * If the host controller provides us with an incorrect timeout
652 * value, just skip the check and use 0xE. The hardware may take
653 * longer to time out, but that's much better than having a too-short
654 * timeout value.
655 */
11a2f1b7 656 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 657 return 0xE;
e538fbe8 658
a3c7778f 659 /* Unspecified timeout, assume max */
1d4d7744 660 if (!data && !cmd->busy_timeout)
a3c7778f 661 return 0xE;
d129bceb 662
a3c7778f
AW		 663 /* timeout in us */
664 if (!data)
1d4d7744 665 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 666 else {
667 target_timeout = data->timeout_ns / 1000;
668 if (host->clock)
669 target_timeout += data->timeout_clks / host->clock;
670 }
81b39802 671
1c8cde92
PO		 672 /*
673 * Figure out needed cycles.
674 * We do this in steps in order to fit inside a 32 bit int.
675 * The first step is the minimum timeout, which will have a
676 * minimum resolution of 6 bits:
677 * (1) 2^13*1000 > 2^22,
678 * (2) host->timeout_clk < 2^16
679 * =>
680 * (1) / (2) > 2^6
681 */
682 count = 0;
683 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
684 while (current_timeout < target_timeout) {
685 count++;
686 current_timeout <<= 1;
687 if (count >= 0xF)
688 break;
689 }
690
691 if (count >= 0xF) {
09eeff52
CB		 692 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
693 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 694 count = 0xE;
695 }
696
ee53ab5d
PO		 697 return count;
698}
699
6aa943ab
AV		 700static void sdhci_set_transfer_irqs(struct sdhci_host *host)
701{
702 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
703 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
704
705 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 706 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 707 else
b537f94c
RK		 708 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
709
710 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
711 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 712}
713
a3c7778f 714static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 715{
716 u8 count;
2134a922 717 u8 ctrl;
a3c7778f 718 struct mmc_data *data = cmd->data;
8f1934ce 719 int ret;
ee53ab5d
PO		 720
721 WARN_ON(host->data);
722
a3c7778f
AW		 723 if (data || (cmd->flags & MMC_RSP_BUSY)) {
724 count = sdhci_calc_timeout(host, cmd);
725 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
726 }
727
728 if (!data)
ee53ab5d
PO		 729 return;
730
731 /* Sanity checks */
732 BUG_ON(data->blksz * data->blocks > 524288);
733 BUG_ON(data->blksz > host->mmc->max_blk_size);
734 BUG_ON(data->blocks > 65535);
735
736 host->data = data;
737 host->data_early = 0;
f6a03cbf 738 host->data->bytes_xfered = 0;
ee53ab5d 739
a13abc7b 740 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 741 host->flags |= SDHCI_REQ_USE_DMA;
742
2134a922
PO		 743 /*
744 * FIXME: This doesn't account for merging when mapping the
745 * scatterlist.
746 */
747 if (host->flags & SDHCI_REQ_USE_DMA) {
748 int broken, i;
749 struct scatterlist *sg;
750
751 broken = 0;
752 if (host->flags & SDHCI_USE_ADMA) {
753 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
754 broken = 1;
755 } else {
756 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
757 broken = 1;
758 }
759
760 if (unlikely(broken)) {
761 for_each_sg(data->sg, sg, data->sg_len, i) {
762 if (sg->length & 0x3) {
763 DBG("Reverting to PIO because of "
764 "transfer size (%d)\n",
765 sg->length);
766 host->flags &= ~SDHCI_REQ_USE_DMA;
767 break;
768 }
769 }
770 }
c9fddbc4
PO		 771 }
772
773 /*
774 * The assumption here being that alignment is the same after
775 * translation to device address space.
776 */
2134a922
PO		 777 if (host->flags & SDHCI_REQ_USE_DMA) {
778 int broken, i;
779 struct scatterlist *sg;
780
781 broken = 0;
782 if (host->flags & SDHCI_USE_ADMA) {
783 /*
784 * As we use 3 byte chunks to work around
785 * alignment problems, we need to check this
786 * quirk.
787 */
788 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
789 broken = 1;
790 } else {
791 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
792 broken = 1;
793 }
794
795 if (unlikely(broken)) {
796 for_each_sg(data->sg, sg, data->sg_len, i) {
797 if (sg->offset & 0x3) {
798 DBG("Reverting to PIO because of "
799 "bad alignment\n");
800 host->flags &= ~SDHCI_REQ_USE_DMA;
801 break;
802 }
803 }
804 }
805 }
806
8f1934ce
PO		 807 if (host->flags & SDHCI_REQ_USE_DMA) {
808 if (host->flags & SDHCI_USE_ADMA) {
809 ret = sdhci_adma_table_pre(host, data);
810 if (ret) {
811 /*
812 * This only happens when someone fed
813 * us an invalid request.
814 */
815 WARN_ON(1);
ebd6d357 816 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 817 } else {
4e4141a5
AV		 818 sdhci_writel(host, host->adma_addr,
819 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 820 }
821 } else {
c8b3e02e 822 int sg_cnt;
8f1934ce 823
c8b3e02e 824 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 825 data->sg, data->sg_len,
826 (data->flags & MMC_DATA_READ) ?
827 DMA_FROM_DEVICE :
828 DMA_TO_DEVICE);
c8b3e02e 829 if (sg_cnt == 0) {
8f1934ce
PO		 830 /*
831 * This only happens when someone fed
832 * us an invalid request.
833 */
834 WARN_ON(1);
ebd6d357 835 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 836 } else {
719a61b4 837 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 838 sdhci_writel(host, sg_dma_address(data->sg),
839 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 840 }
841 }
842 }
843
2134a922
PO		 844 /*
845 * Always adjust the DMA selection as some controllers
846 * (e.g. JMicron) can't do PIO properly when the selection
847 * is ADMA.
848 */
849 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 850 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 851 ctrl &= ~SDHCI_CTRL_DMA_MASK;
852 if ((host->flags & SDHCI_REQ_USE_DMA) &&
853 (host->flags & SDHCI_USE_ADMA))
854 ctrl |= SDHCI_CTRL_ADMA32;
855 else
856 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 857 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 858 }
859
8f1934ce 860 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 861 int flags;
862
863 flags = SG_MITER_ATOMIC;
864 if (host->data->flags & MMC_DATA_READ)
865 flags |= SG_MITER_TO_SG;
866 else
867 flags |= SG_MITER_FROM_SG;
868 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 869 host->blocks = data->blocks;
d129bceb 870 }
c7fa9963 871
6aa943ab
AV		 872 sdhci_set_transfer_irqs(host);
873
f6a03cbf
MV		 874 /* Set the DMA boundary value and block size */
875 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
876 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 877 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 878}
879
880static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 881 struct mmc_command *cmd)
c7fa9963
PO		 882{
883 u16 mode;
e89d456f 884 struct mmc_data *data = cmd->data;
c7fa9963 885
2b558c13
DA		 886 if (data == NULL) {
887 /* clear Auto CMD settings for no data CMDs */
888 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
889 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
890 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
c7fa9963 891 return;
2b558c13 892 }
c7fa9963 893
e538fbe8
PO		 894 WARN_ON(!host->data);
895
c7fa9963 896 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 897 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
898 mode |= SDHCI_TRNS_MULTI;
899 /*
900 * If we are sending CMD23, CMD12 never gets sent
901 * on successful completion (so no Auto-CMD12).
902 */
903 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
904 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 905 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
906 mode |= SDHCI_TRNS_AUTO_CMD23;
907 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
908 }
c4512f79 909 }
8edf6371 910
c7fa9963
PO		 911 if (data->flags & MMC_DATA_READ)
912 mode |= SDHCI_TRNS_READ;
c9fddbc4 913 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 914 mode |= SDHCI_TRNS_DMA;
915
4e4141a5 916 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 917}
918
919static void sdhci_finish_data(struct sdhci_host *host)
920{
921 struct mmc_data *data;
d129bceb
PO		 922
923 BUG_ON(!host->data);
924
925 data = host->data;
926 host->data = NULL;
927
c9fddbc4 928 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 929 if (host->flags & SDHCI_USE_ADMA)
930 sdhci_adma_table_post(host, data);
931 else {
932 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
933 data->sg_len, (data->flags & MMC_DATA_READ) ?
934 DMA_FROM_DEVICE : DMA_TO_DEVICE);
935 }
d129bceb
PO		 936 }
937
938 /*
c9b74c5b
PO		 939 * The specification states that the block count register must
940 * be updated, but it does not specify at what point in the
941 * data flow. That makes the register entirely useless to read
942 * back so we have to assume that nothing made it to the card
943 * in the event of an error.
d129bceb 944 */
c9b74c5b
PO		 945 if (data->error)
946 data->bytes_xfered = 0;
d129bceb 947 else
c9b74c5b 948 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 949
e89d456f
AW		 950 /*
951 * Need to send CMD12 if -
952 * a) open-ended multiblock transfer (no CMD23)
953 * b) error in multiblock transfer
954 */
955 if (data->stop &&
956 (data->error ||
957 !host->mrq->sbc)) {
958
d129bceb
PO		 959 /*
960 * The controller needs a reset of internal state machines
961 * upon error conditions.
962 */
17b0429d 963 if (data->error) {
d129bceb
PO		 964 sdhci_reset(host, SDHCI_RESET_CMD);
965 sdhci_reset(host, SDHCI_RESET_DATA);
966 }
967
968 sdhci_send_command(host, data->stop);
969 } else
970 tasklet_schedule(&host->finish_tasklet);
971}
972
c0e55129 973void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 974{
975 int flags;
fd2208d7 976 u32 mask;
7cb2c76f 977 unsigned long timeout;
d129bceb
PO		 978
979 WARN_ON(host->cmd);
980
d129bceb 981 /* Wait max 10 ms */
7cb2c76f 982 timeout = 10;
fd2208d7
PO		 983
984 mask = SDHCI_CMD_INHIBIT;
985 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
986 mask |= SDHCI_DATA_INHIBIT;
987
988 /* We shouldn't wait for data inihibit for stop commands, even
989 though they might use busy signaling */
990 if (host->mrq->data && (cmd == host->mrq->data->stop))
991 mask &= ~SDHCI_DATA_INHIBIT;
992
4e4141a5 993 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 994 if (timeout == 0) {
a3c76eb9 995 pr_err("%s: Controller never released "
acf1da45 996 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 997 sdhci_dumpregs(host);
17b0429d 998 cmd->error = -EIO;
d129bceb
PO		 999 tasklet_schedule(&host->finish_tasklet);
1000 return;
1001 }
7cb2c76f
PO		 1002 timeout--;
1003 mdelay(1);
1004 }
d129bceb 1005
3e1a6892 1006 timeout = jiffies;
1d4d7744
UH		 1007 if (!cmd->data && cmd->busy_timeout > 9000)
1008 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1009 else
1010 timeout += 10 * HZ;
1011 mod_timer(&host->timer, timeout);
d129bceb
PO		 1012
1013 host->cmd = cmd;
1014
a3c7778f 1015 sdhci_prepare_data(host, cmd);
d129bceb 1016
4e4141a5 1017 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1018
e89d456f 1019 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1020
d129bceb 1021 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1022 pr_err("%s: Unsupported response type!\n",
d129bceb 1023 mmc_hostname(host->mmc));
17b0429d 1024 cmd->error = -EINVAL;
d129bceb
PO		 1025 tasklet_schedule(&host->finish_tasklet);
1026 return;
1027 }
1028
1029 if (!(cmd->flags & MMC_RSP_PRESENT))
1030 flags = SDHCI_CMD_RESP_NONE;
1031 else if (cmd->flags & MMC_RSP_136)
1032 flags = SDHCI_CMD_RESP_LONG;
1033 else if (cmd->flags & MMC_RSP_BUSY)
1034 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1035 else
1036 flags = SDHCI_CMD_RESP_SHORT;
1037
1038 if (cmd->flags & MMC_RSP_CRC)
1039 flags |= SDHCI_CMD_CRC;
1040 if (cmd->flags & MMC_RSP_OPCODE)
1041 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1042
1043 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1044 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1045 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1046 flags |= SDHCI_CMD_DATA;
1047
4e4141a5 1048 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1049}
c0e55129 1050EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1051
1052static void sdhci_finish_command(struct sdhci_host *host)
1053{
1054 int i;
1055
1056 BUG_ON(host->cmd == NULL);
1057
1058 if (host->cmd->flags & MMC_RSP_PRESENT) {
1059 if (host->cmd->flags & MMC_RSP_136) {
1060 /* CRC is stripped so we need to do some shifting. */
1061 for (i = 0;i < 4;i++) {
4e4141a5 1062 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1063 SDHCI_RESPONSE + (3-i)*4) << 8;
1064 if (i != 3)
1065 host->cmd->resp[i] |=
4e4141a5 1066 sdhci_readb(host,
d129bceb
PO		 1067 SDHCI_RESPONSE + (3-i)*4-1);
1068 }
1069 } else {
4e4141a5 1070 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1071 }
1072 }
1073
17b0429d 1074 host->cmd->error = 0;
d129bceb 1075
e89d456f
AW		 1076 /* Finished CMD23, now send actual command. */
1077 if (host->cmd == host->mrq->sbc) {
1078 host->cmd = NULL;
1079 sdhci_send_command(host, host->mrq->cmd);
1080 } else {
e538fbe8 1081
e89d456f
AW		 1082 /* Processed actual command. */
1083 if (host->data && host->data_early)
1084 sdhci_finish_data(host);
d129bceb 1085
e89d456f
AW		 1086 if (!host->cmd->data)
1087 tasklet_schedule(&host->finish_tasklet);
1088
1089 host->cmd = NULL;
1090 }
d129bceb
PO		 1091}
1092
52983382
KL		 1093static u16 sdhci_get_preset_value(struct sdhci_host *host)
1094{
1095 u16 ctrl, preset = 0;
1096
1097 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1098
1099 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1100 case SDHCI_CTRL_UHS_SDR12:
1101 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1102 break;
1103 case SDHCI_CTRL_UHS_SDR25:
1104 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1105 break;
1106 case SDHCI_CTRL_UHS_SDR50:
1107 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1108 break;
1109 case SDHCI_CTRL_UHS_SDR104:
1110 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1111 break;
1112 case SDHCI_CTRL_UHS_DDR50:
1113 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1114 break;
1115 default:
1116 pr_warn("%s: Invalid UHS-I mode selected\n",
1117 mmc_hostname(host->mmc));
1118 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1119 break;
1120 }
1121 return preset;
1122}
1123
d129bceb
PO		 1124static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1125{
c3ed3877 1126 int div = 0; /* Initialized for compiler warning */
df16219f 1127 int real_div = div, clk_mul = 1;
c3ed3877 1128 u16 clk = 0;
7cb2c76f 1129 unsigned long timeout;
d129bceb 1130
30832ab5 1131 if (clock && clock == host->clock)
d129bceb
PO		 1132 return;
1133
df16219f
GC		 1134 host->mmc->actual_clock = 0;
1135
8114634c
AV		 1136 if (host->ops->set_clock) {
1137 host->ops->set_clock(host, clock);
1138 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1139 return;
1140 }
1141
4e4141a5 1142 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1143
1144 if (clock == 0)
1145 goto out;
1146
85105c53 1147 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1148 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1149 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1150 u16 pre_val;
1151
1152 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1153 pre_val = sdhci_get_preset_value(host);
1154 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1155 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1156 if (host->clk_mul &&
1157 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1158 clk = SDHCI_PROG_CLOCK_MODE;
1159 real_div = div + 1;
1160 clk_mul = host->clk_mul;
1161 } else {
1162 real_div = max_t(int, 1, div << 1);
1163 }
1164 goto clock_set;
1165 }
1166
c3ed3877
AN		 1167 /*
1168 * Check if the Host Controller supports Programmable Clock
1169 * Mode.
1170 */
1171 if (host->clk_mul) {
52983382
KL		 1172 for (div = 1; div <= 1024; div++) {
1173 if ((host->max_clk * host->clk_mul / div)
1174 <= clock)
1175 break;
1176 }
c3ed3877 1177 /*
52983382
KL		 1178 * Set Programmable Clock Mode in the Clock
1179 * Control register.
c3ed3877 1180 */
52983382
KL		 1181 clk = SDHCI_PROG_CLOCK_MODE;
1182 real_div = div;
1183 clk_mul = host->clk_mul;
1184 div--;
c3ed3877
AN		 1185 } else {
1186 /* Version 3.00 divisors must be a multiple of 2. */
1187 if (host->max_clk <= clock)
1188 div = 1;
1189 else {
1190 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1191 div += 2) {
1192 if ((host->max_clk / div) <= clock)
1193 break;
1194 }
85105c53 1195 }
df16219f 1196 real_div = div;
c3ed3877 1197 div >>= 1;
85105c53
ZG		 1198 }
1199 } else {
1200 /* Version 2.00 divisors must be a power of 2. */
0397526d 1201 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1202 if ((host->max_clk / div) <= clock)
1203 break;
1204 }
df16219f 1205 real_div = div;
c3ed3877 1206 div >>= 1;
d129bceb 1207 }
d129bceb 1208
52983382 1209clock_set:
df16219f
GC		 1210 if (real_div)
1211 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1212
c3ed3877 1213 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1214 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1215 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1216 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1217 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1218
27f6cb16
CB		 1219 /* Wait max 20 ms */
1220 timeout = 20;
4e4141a5 1221 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1222 & SDHCI_CLOCK_INT_STABLE)) {
1223 if (timeout == 0) {
a3c76eb9 1224 pr_err("%s: Internal clock never "
acf1da45 1225 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1226 sdhci_dumpregs(host);
1227 return;
1228 }
7cb2c76f
PO		 1229 timeout--;
1230 mdelay(1);
1231 }
d129bceb
PO		 1232
1233 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1234 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1235
1236out:
1237 host->clock = clock;
1238}
1239
8213af3b
AS		 1240static inline void sdhci_update_clock(struct sdhci_host *host)
1241{
1242 unsigned int clock;
1243
1244 clock = host->clock;
1245 host->clock = 0;
1246 sdhci_set_clock(host, clock);
1247}
1248
ceb6143b 1249static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1250{
8364248a 1251 u8 pwr = 0;
146ad66e 1252
8364248a 1253 if (power != (unsigned short)-1) {
ae628903
PO		 1254 switch (1 << power) {
1255 case MMC_VDD_165_195:
1256 pwr = SDHCI_POWER_180;
1257 break;
1258 case MMC_VDD_29_30:
1259 case MMC_VDD_30_31:
1260 pwr = SDHCI_POWER_300;
1261 break;
1262 case MMC_VDD_32_33:
1263 case MMC_VDD_33_34:
1264 pwr = SDHCI_POWER_330;
1265 break;
1266 default:
1267 BUG();
1268 }
1269 }
1270
1271 if (host->pwr == pwr)
ceb6143b 1272 return -1;
146ad66e 1273
ae628903
PO		 1274 host->pwr = pwr;
1275
1276 if (pwr == 0) {
4e4141a5 1277 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1278 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1279 sdhci_runtime_pm_bus_off(host);
ceb6143b 1280 return 0;
9e9dc5f2
DS		 1281 }
1282
1283 /*
1284 * Spec says that we should clear the power reg before setting
1285 * a new value. Some controllers don't seem to like this though.
1286 */
b8c86fc5 1287 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1288 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1289
e08c1694 1290 /*
c71f6512 1291 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1292 * and set turn on power at the same time, so set the voltage first.
1293 */
11a2f1b7 1294 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1295 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1296
ae628903 1297 pwr |= SDHCI_POWER_ON;
146ad66e 1298
ae628903 1299 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1300
f0710a55
AH		 1301 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1302 sdhci_runtime_pm_bus_on(host);
1303
557b0697
HW		 1304 /*
1305 * Some controllers need an extra 10ms delay of 10ms before they
1306 * can apply clock after applying power
1307 */
11a2f1b7 1308 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1309 mdelay(10);
ceb6143b
AH		 1310
1311 return power;
146ad66e
PO		 1312}
1313
d129bceb
PO		 1314/*****************************************************************************\
1315 * *
1316 * MMC callbacks *
1317 * *
1318\*****************************************************************************/
1319
1320static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1321{
1322 struct sdhci_host *host;
505a8680 1323 int present;
d129bceb 1324 unsigned long flags;
473b095a 1325 u32 tuning_opcode;
d129bceb
PO		 1326
1327 host = mmc_priv(mmc);
1328
66fd8ad5
AH		 1329 sdhci_runtime_pm_get(host);
1330
d129bceb
PO		 1331 spin_lock_irqsave(&host->lock, flags);
1332
1333 WARN_ON(host->mrq != NULL);
1334
f9134319 1335#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1336 sdhci_activate_led(host);
2f730fec 1337#endif
e89d456f
AW		 1338
1339 /*
1340 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1341 * requests if Auto-CMD12 is enabled.
1342 */
1343 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1344 if (mrq->stop) {
1345 mrq->data->stop = NULL;
1346 mrq->stop = NULL;
1347 }
1348 }
d129bceb
PO		 1349
1350 host->mrq = mrq;
1351
505a8680
SG		 1352 /*
1353 * Firstly check card presence from cd-gpio. The return could
1354 * be one of the following possibilities:
1355 * negative: cd-gpio is not available
1356 * zero: cd-gpio is used, and card is removed
1357 * one: cd-gpio is used, and card is present
1358 */
1359 present = mmc_gpio_get_cd(host->mmc);
1360 if (present < 0) {
1361 /* If polling, assume that the card is always present. */
1362 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1363 present = 1;
1364 else
1365 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1366 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1367 }
1368
68d1fb7e 1369 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1370 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1371 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1372 } else {
1373 u32 present_state;
1374
1375 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1376 /*
1377 * Check if the re-tuning timer has already expired and there
1378 * is no on-going data transfer. If so, we need to execute
1379 * tuning procedure before sending command.
1380 */
1381 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1382 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1383 if (mmc->card) {
1384 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1385 tuning_opcode =
1386 mmc->card->type == MMC_TYPE_MMC ?
1387 MMC_SEND_TUNING_BLOCK_HS200 :
1388 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1389
1390 /* Here we need to set the host->mrq to NULL,
1391 * in case the pending finish_tasklet
1392 * finishes it incorrectly.
1393 */
1394 host->mrq = NULL;
1395
14efd957
CB		 1396 spin_unlock_irqrestore(&host->lock, flags);
1397 sdhci_execute_tuning(mmc, tuning_opcode);
1398 spin_lock_irqsave(&host->lock, flags);
1399
1400 /* Restore original mmc_request structure */
1401 host->mrq = mrq;
1402 }
cf2b5eea
AN		 1403 }
1404
8edf6371 1405 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1406 sdhci_send_command(host, mrq->sbc);
1407 else
1408 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1409 }
d129bceb 1410
5f25a66f 1411 mmiowb();
d129bceb
PO		 1412 spin_unlock_irqrestore(&host->lock, flags);
1413}
1414
66fd8ad5 1415static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1416{
d129bceb 1417 unsigned long flags;
ceb6143b 1418 int vdd_bit = -1;
d129bceb
PO		 1419 u8 ctrl;
1420
d129bceb
PO		 1421 spin_lock_irqsave(&host->lock, flags);
1422
ceb6143b
AH		 1423 if (host->flags & SDHCI_DEVICE_DEAD) {
1424 spin_unlock_irqrestore(&host->lock, flags);
1425 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1426 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1427 return;
1428 }
1e72859e 1429
d129bceb
PO		 1430 /*
1431 * Reset the chip on each power off.
1432 * Should clear out any weird states.
1433 */
1434 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1435 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1436 sdhci_reinit(host);
d129bceb
PO		 1437 }
1438
52983382 1439 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1440 (ios->power_mode == MMC_POWER_UP) &&
1441 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1442 sdhci_enable_preset_value(host, false);
1443
d129bceb
PO		 1444 sdhci_set_clock(host, ios->clock);
1445
1446 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1447 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1448 else
ceb6143b
AH		 1449 vdd_bit = sdhci_set_power(host, ios->vdd);
1450
1451 if (host->vmmc && vdd_bit != -1) {
1452 spin_unlock_irqrestore(&host->lock, flags);
1453 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1454 spin_lock_irqsave(&host->lock, flags);
1455 }
d129bceb 1456
643a81ff
PR		 1457 if (host->ops->platform_send_init_74_clocks)
1458 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1459
15ec4461
PR		 1460 /*
1461 * If your platform has 8-bit width support but is not a v3 controller,
1462 * or if it requires special setup code, you should implement that in
7bc088d3 1463 * platform_bus_width().
15ec4461 1464 */
7bc088d3
SH		 1465 if (host->ops->platform_bus_width) {
1466 host->ops->platform_bus_width(host, ios->bus_width);
1467 } else {
15ec4461
PR		 1468 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1469 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1470 ctrl &= ~SDHCI_CTRL_4BITBUS;
1471 if (host->version >= SDHCI_SPEC_300)
1472 ctrl |= SDHCI_CTRL_8BITBUS;
1473 } else {
1474 if (host->version >= SDHCI_SPEC_300)
1475 ctrl &= ~SDHCI_CTRL_8BITBUS;
1476 if (ios->bus_width == MMC_BUS_WIDTH_4)
1477 ctrl |= SDHCI_CTRL_4BITBUS;
1478 else
1479 ctrl &= ~SDHCI_CTRL_4BITBUS;
1480 }
1481 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1482 }
ae6d6c92 1483
15ec4461 1484 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1485
3ab9c8da
PR		 1486 if ((ios->timing == MMC_TIMING_SD_HS ||
1487 ios->timing == MMC_TIMING_MMC_HS)
1488 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1489 ctrl |= SDHCI_CTRL_HISPD;
1490 else
1491 ctrl &= ~SDHCI_CTRL_HISPD;
1492
d6d50a15 1493 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1494 u16 clk, ctrl_2;
49c468fc
AN		 1495
1496 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1497 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1498 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1499 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1500 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1501 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1502 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1503 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1504
1505 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1506 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1507 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1508 /*
1509 * We only need to set Driver Strength if the
1510 * preset value enable is not set.
1511 */
1512 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1513 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1514 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1515 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1516 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1517
1518 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1519 } else {
1520 /*
1521 * According to SDHC Spec v3.00, if the Preset Value
1522 * Enable in the Host Control 2 register is set, we
1523 * need to reset SD Clock Enable before changing High
1524 * Speed Enable to avoid generating clock gliches.
1525 */
758535c4
AN		 1526
1527 /* Reset SD Clock Enable */
1528 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1529 clk &= ~SDHCI_CLOCK_CARD_EN;
1530 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1531
1532 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1533
1534 /* Re-enable SD Clock */
8213af3b 1535 sdhci_update_clock(host);
d6d50a15 1536 }
49c468fc 1537
49c468fc
AN		 1538
1539 /* Reset SD Clock Enable */
1540 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1541 clk &= ~SDHCI_CLOCK_CARD_EN;
1542 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1543
6322cdd0
PR		 1544 if (host->ops->set_uhs_signaling)
1545 host->ops->set_uhs_signaling(host, ios->timing);
1546 else {
1547 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1548 /* Select Bus Speed Mode for host */
1549 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
59911568
GC		 1550 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1551 (ios->timing == MMC_TIMING_UHS_SDR104))
1552 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
069c9f14 1553 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1554 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1555 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1556 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1557 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1558 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
bb8175a8
SJ		 1559 else if ((ios->timing == MMC_TIMING_UHS_DDR50) ||
1560 (ios->timing == MMC_TIMING_MMC_DDR52))
6322cdd0
PR		 1561 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1562 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1563 }
49c468fc 1564
52983382
KL		 1565 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1566 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1567 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1568 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1569 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1570 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1571 u16 preset;
1572
1573 sdhci_enable_preset_value(host, true);
1574 preset = sdhci_get_preset_value(host);
1575 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1576 >> SDHCI_PRESET_DRV_SHIFT;
1577 }
1578
49c468fc 1579 /* Re-enable SD Clock */
8213af3b 1580 sdhci_update_clock(host);
758535c4
AN		 1581 } else
1582 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1583
b8352260
LD		 1584 /*
1585 * Some (ENE) controllers go apeshit on some ios operation,
1586 * signalling timeout and CRC errors even on CMD0. Resetting
1587 * it on each ios seems to solve the problem.
1588 */
b8c86fc5 1589 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1590 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1591
5f25a66f 1592 mmiowb();
d129bceb
PO		 1593 spin_unlock_irqrestore(&host->lock, flags);
1594}
1595
66fd8ad5
AH		 1596static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1597{
1598 struct sdhci_host *host = mmc_priv(mmc);
1599
1600 sdhci_runtime_pm_get(host);
1601 sdhci_do_set_ios(host, ios);
1602 sdhci_runtime_pm_put(host);
1603}
1604
94144a46
KL		 1605static int sdhci_do_get_cd(struct sdhci_host *host)
1606{
1607 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1608
1609 if (host->flags & SDHCI_DEVICE_DEAD)
1610 return 0;
1611
1612 /* If polling/nonremovable, assume that the card is always present. */
1613 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1614 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1615 return 1;
1616
1617 /* Try slot gpio detect */
1618 if (!IS_ERR_VALUE(gpio_cd))
1619 return !!gpio_cd;
1620
1621 /* Host native card detect */
1622 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1623}
1624
1625static int sdhci_get_cd(struct mmc_host *mmc)
1626{
1627 struct sdhci_host *host = mmc_priv(mmc);
1628 int ret;
1629
1630 sdhci_runtime_pm_get(host);
1631 ret = sdhci_do_get_cd(host);
1632 sdhci_runtime_pm_put(host);
1633 return ret;
1634}
1635
66fd8ad5 1636static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1637{
d129bceb 1638 unsigned long flags;
2dfb579c 1639 int is_readonly;
d129bceb 1640
d129bceb
PO		 1641 spin_lock_irqsave(&host->lock, flags);
1642
1e72859e 1643 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1644 is_readonly = 0;
1645 else if (host->ops->get_ro)
1646 is_readonly = host->ops->get_ro(host);
1e72859e 1647 else
2dfb579c
WS		 1648 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1649 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1650
1651 spin_unlock_irqrestore(&host->lock, flags);
1652
2dfb579c
WS		 1653 /* This quirk needs to be replaced by a callback-function later */
1654 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1655 !is_readonly : is_readonly;
d129bceb
PO		 1656}
1657
82b0e23a
TI		 1658#define SAMPLE_COUNT 5
1659
66fd8ad5 1660static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1661{
82b0e23a
TI		 1662 int i, ro_count;
1663
82b0e23a 1664 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1665 return sdhci_check_ro(host);
82b0e23a
TI		 1666
1667 ro_count = 0;
1668 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1669 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1670 if (++ro_count > SAMPLE_COUNT / 2)
1671 return 1;
1672 }
1673 msleep(30);
1674 }
1675 return 0;
1676}
1677
20758b66
AH		 1678static void sdhci_hw_reset(struct mmc_host *mmc)
1679{
1680 struct sdhci_host *host = mmc_priv(mmc);
1681
1682 if (host->ops && host->ops->hw_reset)
1683 host->ops->hw_reset(host);
1684}
1685
66fd8ad5 1686static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1687{
66fd8ad5
AH		 1688 struct sdhci_host *host = mmc_priv(mmc);
1689 int ret;
f75979b7 1690
66fd8ad5
AH		 1691 sdhci_runtime_pm_get(host);
1692 ret = sdhci_do_get_ro(host);
1693 sdhci_runtime_pm_put(host);
1694 return ret;
1695}
f75979b7 1696
66fd8ad5
AH		 1697static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1698{
be138554 1699 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1700 if (enable)
b537f94c 1701 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1702 else
b537f94c
RK		 1703 host->ier &= ~SDHCI_INT_CARD_INT;
1704
1705 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1706 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1707 mmiowb();
1708 }
66fd8ad5
AH		 1709}
1710
1711static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1712{
1713 struct sdhci_host *host = mmc_priv(mmc);
1714 unsigned long flags;
f75979b7 1715
ef104333
RK		 1716 sdhci_runtime_pm_get(host);
1717
66fd8ad5 1718 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1719 if (enable)
1720 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1721 else
1722 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1723
66fd8ad5 1724 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1725 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1726
1727 sdhci_runtime_pm_put(host);
f75979b7
PO		 1728}
1729
20b92a30 1730static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1731 struct mmc_ios *ios)
f2119df6 1732{
20b92a30 1733 u16 ctrl;
6231f3de 1734 int ret;
f2119df6 1735
20b92a30
KL		 1736 /*
1737 * Signal Voltage Switching is only applicable for Host Controllers
1738 * v3.00 and above.
1739 */
1740 if (host->version < SDHCI_SPEC_300)
1741 return 0;
6231f3de 1742
f2119df6 1743 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1744
21f5998f 1745 switch (ios->signal_voltage) {
20b92a30
KL		 1746 case MMC_SIGNAL_VOLTAGE_330:
1747 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1748 ctrl &= ~SDHCI_CTRL_VDD_180;
1749 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1750
20b92a30
KL		 1751 if (host->vqmmc) {
1752 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1753 if (ret) {
1754 pr_warning("%s: Switching to 3.3V signalling voltage "
1755 " failed\n", mmc_hostname(host->mmc));
1756 return -EIO;
1757 }
1758 }
1759 /* Wait for 5ms */
1760 usleep_range(5000, 5500);
f2119df6 1761
20b92a30
KL		 1762 /* 3.3V regulator output should be stable within 5 ms */
1763 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1764 if (!(ctrl & SDHCI_CTRL_VDD_180))
1765 return 0;
6231f3de 1766
20b92a30
KL		 1767 pr_warning("%s: 3.3V regulator output did not became stable\n",
1768 mmc_hostname(host->mmc));
1769
1770 return -EAGAIN;
1771 case MMC_SIGNAL_VOLTAGE_180:
1772 if (host->vqmmc) {
1773 ret = regulator_set_voltage(host->vqmmc,
1774 1700000, 1950000);
1775 if (ret) {
1776 pr_warning("%s: Switching to 1.8V signalling voltage "
1777 " failed\n", mmc_hostname(host->mmc));
1778 return -EIO;
1779 }
1780 }
6231f3de 1781
6231f3de
PR		 1782 /*
1783 * Enable 1.8V Signal Enable in the Host Control2
1784 * register
1785 */
20b92a30
KL		 1786 ctrl |= SDHCI_CTRL_VDD_180;
1787 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1788
20b92a30
KL		 1789 /* Wait for 5ms */
1790 usleep_range(5000, 5500);
f2119df6 1791
20b92a30
KL		 1792 /* 1.8V regulator output should be stable within 5 ms */
1793 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1794 if (ctrl & SDHCI_CTRL_VDD_180)
1795 return 0;
f2119df6 1796
20b92a30
KL		 1797 pr_warning("%s: 1.8V regulator output did not became stable\n",
1798 mmc_hostname(host->mmc));
f2119df6 1799
20b92a30
KL		 1800 return -EAGAIN;
1801 case MMC_SIGNAL_VOLTAGE_120:
1802 if (host->vqmmc) {
1803 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1804 if (ret) {
1805 pr_warning("%s: Switching to 1.2V signalling voltage "
1806 " failed\n", mmc_hostname(host->mmc));
1807 return -EIO;
f2119df6
AN		 1808 }
1809 }
6231f3de 1810 return 0;
20b92a30 1811 default:
f2119df6
AN		 1812 /* No signal voltage switch required */
1813 return 0;
20b92a30 1814 }
f2119df6
AN		 1815}
1816
66fd8ad5 1817static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1818 struct mmc_ios *ios)
66fd8ad5
AH		 1819{
1820 struct sdhci_host *host = mmc_priv(mmc);
1821 int err;
1822
1823 if (host->version < SDHCI_SPEC_300)
1824 return 0;
1825 sdhci_runtime_pm_get(host);
21f5998f 1826 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1827 sdhci_runtime_pm_put(host);
1828 return err;
1829}
1830
20b92a30
KL		 1831static int sdhci_card_busy(struct mmc_host *mmc)
1832{
1833 struct sdhci_host *host = mmc_priv(mmc);
1834 u32 present_state;
1835
1836 sdhci_runtime_pm_get(host);
1837 /* Check whether DAT[3:0] is 0000 */
1838 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1839 sdhci_runtime_pm_put(host);
1840
1841 return !(present_state & SDHCI_DATA_LVL_MASK);
1842}
1843
069c9f14 1844static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1845{
1846 struct sdhci_host *host;
1847 u16 ctrl;
b513ea25
AN		 1848 int tuning_loop_counter = MAX_TUNING_LOOP;
1849 unsigned long timeout;
1850 int err = 0;
069c9f14 1851 bool requires_tuning_nonuhs = false;
2b35bd83 1852 unsigned long flags;
b513ea25
AN		 1853
1854 host = mmc_priv(mmc);
1855
66fd8ad5 1856 sdhci_runtime_pm_get(host);
2b35bd83 1857 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1858
1859 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1860
1861 /*
069c9f14
G		 1862 * The Host Controller needs tuning only in case of SDR104 mode
1863 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1864 * Capabilities register.
069c9f14
G		 1865 * If the Host Controller supports the HS200 mode then the
1866 * tuning function has to be executed.
b513ea25 1867 */
069c9f14
G		 1868 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1869 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
156e14b1 1870 host->flags & SDHCI_SDR104_NEEDS_TUNING))
069c9f14
G		 1871 requires_tuning_nonuhs = true;
1872
b513ea25 1873 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1874 requires_tuning_nonuhs)
b513ea25
AN		 1875 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1876 else {
2b35bd83 1877 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1878 sdhci_runtime_pm_put(host);
b513ea25
AN		 1879 return 0;
1880 }
1881
45251812 1882 if (host->ops->platform_execute_tuning) {
2b35bd83 1883 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1884 err = host->ops->platform_execute_tuning(host, opcode);
1885 sdhci_runtime_pm_put(host);
1886 return err;
1887 }
1888
b513ea25
AN		 1889 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1890
1891 /*
1892 * As per the Host Controller spec v3.00, tuning command
1893 * generates Buffer Read Ready interrupt, so enable that.
1894 *
1895 * Note: The spec clearly says that when tuning sequence
1896 * is being performed, the controller does not generate
1897 * interrupts other than Buffer Read Ready interrupt. But
1898 * to make sure we don't hit a controller bug, we _only_
1899 * enable Buffer Read Ready interrupt here.
1900 */
b537f94c
RK		 1901 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1902 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1903
1904 /*
1905 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1906 * of loops reaches 40 times or a timeout of 150ms occurs.
1907 */
1908 timeout = 150;
1909 do {
1910 struct mmc_command cmd = {0};
66fd8ad5 1911 struct mmc_request mrq = {NULL};
b513ea25
AN		 1912
1913 if (!tuning_loop_counter && !timeout)
1914 break;
1915
069c9f14 1916 cmd.opcode = opcode;
b513ea25
AN		 1917 cmd.arg = 0;
1918 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1919 cmd.retries = 0;
1920 cmd.data = NULL;
1921 cmd.error = 0;
1922
1923 mrq.cmd = &cmd;
1924 host->mrq = &mrq;
1925
1926 /*
1927 * In response to CMD19, the card sends 64 bytes of tuning
1928 * block to the Host Controller. So we set the block size
1929 * to 64 here.
1930 */
069c9f14
G		 1931 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1932 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1933 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1934 SDHCI_BLOCK_SIZE);
1935 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1936 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1937 SDHCI_BLOCK_SIZE);
1938 } else {
1939 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1940 SDHCI_BLOCK_SIZE);
1941 }
b513ea25
AN		 1942
1943 /*
1944 * The tuning block is sent by the card to the host controller.
1945 * So we set the TRNS_READ bit in the Transfer Mode register.
1946 * This also takes care of setting DMA Enable and Multi Block
1947 * Select in the same register to 0.
1948 */
1949 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1950
1951 sdhci_send_command(host, &cmd);
1952
1953 host->cmd = NULL;
1954 host->mrq = NULL;
1955
2b35bd83 1956 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1957 /* Wait for Buffer Read Ready interrupt */
1958 wait_event_interruptible_timeout(host->buf_ready_int,
1959 (host->tuning_done == 1),
1960 msecs_to_jiffies(50));
2b35bd83 1961 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1962
1963 if (!host->tuning_done) {
a3c76eb9 1964 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1965 "Buffer Read Ready interrupt during tuning "
1966 "procedure, falling back to fixed sampling "
1967 "clock\n");
1968 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1969 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1970 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1971 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1972
1973 err = -EIO;
1974 goto out;
1975 }
1976
1977 host->tuning_done = 0;
1978
1979 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1980 tuning_loop_counter--;
1981 timeout--;
197160d5
NS		 1982
1983 /* eMMC spec does not require a delay between tuning cycles */
1984 if (opcode == MMC_SEND_TUNING_BLOCK)
1985 mdelay(1);
b513ea25
AN		 1986 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1987
1988 /*
1989 * The Host Driver has exhausted the maximum number of loops allowed,
1990 * so use fixed sampling frequency.
1991 */
1992 if (!tuning_loop_counter || !timeout) {
1993 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1994 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
114f2bf6 1995 err = -EIO;
b513ea25
AN		 1996 } else {
1997 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1998 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1999 " failed, falling back to fixed sampling"
2000 " clock\n");
2001 err = -EIO;
2002 }
2003 }
2004
2005out:
cf2b5eea
AN		 2006 /*
2007 * If this is the very first time we are here, we start the retuning
2008 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2009 * flag won't be set, we check this condition before actually starting
2010 * the timer.
2011 */
2012 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2013 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 2014 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 2015 mod_timer(&host->tuning_timer, jiffies +
2016 host->tuning_count * HZ);
2017 /* Tuning mode 1 limits the maximum data length to 4MB */
2018 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 2019 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 2020 host->flags &= ~SDHCI_NEEDS_RETUNING;
2021 /* Reload the new initial value for timer */
2bc02485
AS		 2022 mod_timer(&host->tuning_timer, jiffies +
2023 host->tuning_count * HZ);
cf2b5eea
AN		 2024 }
2025
2026 /*
2027 * In case tuning fails, host controllers which support re-tuning can
2028 * try tuning again at a later time, when the re-tuning timer expires.
2029 * So for these controllers, we return 0. Since there might be other
2030 * controllers who do not have this capability, we return error for
973905fe
AL		 2031 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2032 * a retuning timer to do the retuning for the card.
cf2b5eea 2033 */
973905fe 2034 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2035 err = 0;
2036
b537f94c
RK		 2037 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2038 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2b35bd83 2039 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2040 sdhci_runtime_pm_put(host);
b513ea25
AN		 2041
2042 return err;
2043}
2044
52983382
KL		 2045
2046static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2047{
4d55c5a1 2048 u16 ctrl;
4d55c5a1 2049
4d55c5a1
AN		 2050 /* Host Controller v3.00 defines preset value registers */
2051 if (host->version < SDHCI_SPEC_300)
2052 return;
2053
4d55c5a1
AN		 2054 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2055
2056 /*
2057 * We only enable or disable Preset Value if they are not already
2058 * enabled or disabled respectively. Otherwise, we bail out.
2059 */
2060 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2061 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2062 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2063 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2064 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2065 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2066 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2067 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2068 }
66fd8ad5
AH		 2069}
2070
71e69211 2071static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2072{
71e69211 2073 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2074 unsigned long flags;
2075
722e1280
CD		 2076 /* First check if client has provided their own card event */
2077 if (host->ops->card_event)
2078 host->ops->card_event(host);
2079
d129bceb
PO		 2080 spin_lock_irqsave(&host->lock, flags);
2081
66fd8ad5 2082 /* Check host->mrq first in case we are runtime suspended */
9668d765 2083 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2084 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2085 mmc_hostname(host->mmc));
a3c76eb9 2086 pr_err("%s: Resetting controller.\n",
66fd8ad5 2087 mmc_hostname(host->mmc));
d129bceb 2088
66fd8ad5
AH		 2089 sdhci_reset(host, SDHCI_RESET_CMD);
2090 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 2091
66fd8ad5
AH		 2092 host->mrq->cmd->error = -ENOMEDIUM;
2093 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2094 }
2095
2096 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2097}
2098
2099static const struct mmc_host_ops sdhci_ops = {
2100 .request = sdhci_request,
2101 .set_ios = sdhci_set_ios,
94144a46 2102 .get_cd = sdhci_get_cd,
71e69211
GL		 2103 .get_ro = sdhci_get_ro,
2104 .hw_reset = sdhci_hw_reset,
2105 .enable_sdio_irq = sdhci_enable_sdio_irq,
2106 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2107 .execute_tuning = sdhci_execute_tuning,
71e69211 2108 .card_event = sdhci_card_event,
20b92a30 2109 .card_busy = sdhci_card_busy,
71e69211
GL		 2110};
2111
2112/*****************************************************************************\
2113 * *
2114 * Tasklets *
2115 * *
2116\*****************************************************************************/
2117
d129bceb
PO		 2118static void sdhci_tasklet_finish(unsigned long param)
2119{
2120 struct sdhci_host *host;
2121 unsigned long flags;
2122 struct mmc_request *mrq;
2123
2124 host = (struct sdhci_host*)param;
2125
66fd8ad5
AH		 2126 spin_lock_irqsave(&host->lock, flags);
2127
0c9c99a7
CB		 2128 /*
2129 * If this tasklet gets rescheduled while running, it will
2130 * be run again afterwards but without any active request.
2131 */
66fd8ad5
AH		 2132 if (!host->mrq) {
2133 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2134 return;
66fd8ad5 2135 }
d129bceb
PO		 2136
2137 del_timer(&host->timer);
2138
2139 mrq = host->mrq;
2140
d129bceb
PO		 2141 /*
2142 * The controller needs a reset of internal state machines
2143 * upon error conditions.
2144 */
1e72859e 2145 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2146 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2147 (mrq->data && (mrq->data->error ||
2148 (mrq->data->stop && mrq->data->stop->error))) ||
2149 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2150
2151 /* Some controllers need this kick or reset won't work here */
8213af3b 2152 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2153 /* This is to force an update */
8213af3b 2154 sdhci_update_clock(host);
645289dc
PO		 2155
2156 /* Spec says we should do both at the same time, but Ricoh
2157 controllers do not like that. */
d129bceb
PO		 2158 sdhci_reset(host, SDHCI_RESET_CMD);
2159 sdhci_reset(host, SDHCI_RESET_DATA);
2160 }
2161
2162 host->mrq = NULL;
2163 host->cmd = NULL;
2164 host->data = NULL;
2165
f9134319 2166#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2167 sdhci_deactivate_led(host);
2f730fec 2168#endif
d129bceb 2169
5f25a66f 2170 mmiowb();
d129bceb
PO		 2171 spin_unlock_irqrestore(&host->lock, flags);
2172
2173 mmc_request_done(host->mmc, mrq);
66fd8ad5 2174 sdhci_runtime_pm_put(host);
d129bceb
PO		 2175}
2176
2177static void sdhci_timeout_timer(unsigned long data)
2178{
2179 struct sdhci_host *host;
2180 unsigned long flags;
2181
2182 host = (struct sdhci_host*)data;
2183
2184 spin_lock_irqsave(&host->lock, flags);
2185
2186 if (host->mrq) {
a3c76eb9 2187 pr_err("%s: Timeout waiting for hardware "
acf1da45 2188 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2189 sdhci_dumpregs(host);
2190
2191 if (host->data) {
17b0429d 2192 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2193 sdhci_finish_data(host);
2194 } else {
2195 if (host->cmd)
17b0429d 2196 host->cmd->error = -ETIMEDOUT;
d129bceb 2197 else
17b0429d 2198 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2199
2200 tasklet_schedule(&host->finish_tasklet);
2201 }
2202 }
2203
5f25a66f 2204 mmiowb();
d129bceb
PO		 2205 spin_unlock_irqrestore(&host->lock, flags);
2206}
2207
cf2b5eea
AN		 2208static void sdhci_tuning_timer(unsigned long data)
2209{
2210 struct sdhci_host *host;
2211 unsigned long flags;
2212
2213 host = (struct sdhci_host *)data;
2214
2215 spin_lock_irqsave(&host->lock, flags);
2216
2217 host->flags |= SDHCI_NEEDS_RETUNING;
2218
2219 spin_unlock_irqrestore(&host->lock, flags);
2220}
2221
d129bceb
PO		 2222/*****************************************************************************\
2223 * *
2224 * Interrupt handling *
2225 * *
2226\*****************************************************************************/
2227
2228static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2229{
2230 BUG_ON(intmask == 0);
2231
2232 if (!host->cmd) {
a3c76eb9 2233 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2234 "though no command operation was in progress.\n",
2235 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2236 sdhci_dumpregs(host);
2237 return;
2238 }
2239
43b58b36 2240 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2241 host->cmd->error = -ETIMEDOUT;
2242 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2243 SDHCI_INT_INDEX))
2244 host->cmd->error = -EILSEQ;
43b58b36 2245
e809517f 2246 if (host->cmd->error) {
d129bceb 2247 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2248 return;
2249 }
2250
2251 /*
2252 * The host can send and interrupt when the busy state has
2253 * ended, allowing us to wait without wasting CPU cycles.
2254 * Unfortunately this is overloaded on the "data complete"
2255 * interrupt, so we need to take some care when handling
2256 * it.
2257 *
2258 * Note: The 1.0 specification is a bit ambiguous about this
2259 * feature so there might be some problems with older
2260 * controllers.
2261 */
2262 if (host->cmd->flags & MMC_RSP_BUSY) {
2263 if (host->cmd->data)
2264 DBG("Cannot wait for busy signal when also "
2265 "doing a data transfer");
f945405c 2266 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2267 return;
f945405c
BD		 2268
2269 /* The controller does not support the end-of-busy IRQ,
2270 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2271 }
2272
2273 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2274 sdhci_finish_command(host);
d129bceb
PO		 2275}
2276
0957c333 2277#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2278static void sdhci_show_adma_error(struct sdhci_host *host)
2279{
2280 const char *name = mmc_hostname(host->mmc);
2281 u8 *desc = host->adma_desc;
2282 __le32 *dma;
2283 __le16 *len;
2284 u8 attr;
2285
2286 sdhci_dumpregs(host);
2287
2288 while (true) {
2289 dma = (__le32 *)(desc + 4);
2290 len = (__le16 *)(desc + 2);
2291 attr = *desc;
2292
2293 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2294 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2295
2296 desc += 8;
2297
2298 if (attr & 2)
2299 break;
2300 }
2301}
2302#else
2303static void sdhci_show_adma_error(struct sdhci_host *host) { }
2304#endif
2305
d129bceb
PO		 2306static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2307{
069c9f14 2308 u32 command;
d129bceb
PO		 2309 BUG_ON(intmask == 0);
2310
b513ea25
AN		 2311 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2312 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2313 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2314 if (command == MMC_SEND_TUNING_BLOCK ||
2315 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2316 host->tuning_done = 1;
2317 wake_up(&host->buf_ready_int);
2318 return;
2319 }
2320 }
2321
d129bceb
PO		 2322 if (!host->data) {
2323 /*
e809517f
PO		 2324 * The "data complete" interrupt is also used to
2325 * indicate that a busy state has ended. See comment
2326 * above in sdhci_cmd_irq().
d129bceb 2327 */
e809517f
PO		 2328 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2329 if (intmask & SDHCI_INT_DATA_END) {
2330 sdhci_finish_command(host);
2331 return;
2332 }
2333 }
d129bceb 2334
a3c76eb9 2335 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2336 "though no data operation was in progress.\n",
2337 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2338 sdhci_dumpregs(host);
2339
2340 return;
2341 }
2342
2343 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2344 host->data->error = -ETIMEDOUT;
22113efd
AL		 2345 else if (intmask & SDHCI_INT_DATA_END_BIT)
2346 host->data->error = -EILSEQ;
2347 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2348 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2349 != MMC_BUS_TEST_R)
17b0429d 2350 host->data->error = -EILSEQ;
6882a8c0 2351 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2352 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2353 sdhci_show_adma_error(host);
2134a922 2354 host->data->error = -EIO;
a4071fbb
HZ		 2355 if (host->ops->adma_workaround)
2356 host->ops->adma_workaround(host, intmask);
6882a8c0 2357 }
d129bceb 2358
17b0429d 2359 if (host->data->error)
d129bceb
PO		 2360 sdhci_finish_data(host);
2361 else {
a406f5a3 2362 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2363 sdhci_transfer_pio(host);
2364
6ba736a1
PO		 2365 /*
2366 * We currently don't do anything fancy with DMA
2367 * boundaries, but as we can't disable the feature
2368 * we need to at least restart the transfer.
f6a03cbf
MV		 2369 *
2370 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2371 * should return a valid address to continue from, but as
2372 * some controllers are faulty, don't trust them.
6ba736a1 2373 */
f6a03cbf
MV		 2374 if (intmask & SDHCI_INT_DMA_END) {
2375 u32 dmastart, dmanow;
2376 dmastart = sg_dma_address(host->data->sg);
2377 dmanow = dmastart + host->data->bytes_xfered;
2378 /*
2379 * Force update to the next DMA block boundary.
2380 */
2381 dmanow = (dmanow &
2382 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2383 SDHCI_DEFAULT_BOUNDARY_SIZE;
2384 host->data->bytes_xfered = dmanow - dmastart;
2385 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2386 " next 0x%08x\n",
2387 mmc_hostname(host->mmc), dmastart,
2388 host->data->bytes_xfered, dmanow);
2389 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2390 }
6ba736a1 2391
e538fbe8
PO		 2392 if (intmask & SDHCI_INT_DATA_END) {
2393 if (host->cmd) {
2394 /*
2395 * Data managed to finish before the
2396 * command completed. Make sure we do
2397 * things in the proper order.
2398 */
2399 host->data_early = 1;
2400 } else {
2401 sdhci_finish_data(host);
2402 }
2403 }
d129bceb
PO		 2404 }
2405}
2406
7d12e780 2407static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2408{
781e989c 2409 irqreturn_t result = IRQ_NONE;
66fd8ad5 2410 struct sdhci_host *host = dev_id;
41005003 2411 u32 intmask, mask, unexpected = 0;
781e989c 2412 int max_loops = 16;
d129bceb
PO		 2413
2414 spin_lock(&host->lock);
2415
be138554 2416 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2417 spin_unlock(&host->lock);
655bca76 2418 return IRQ_NONE;
66fd8ad5
AH		 2419 }
2420
4e4141a5 2421 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2422 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2423 result = IRQ_NONE;
2424 goto out;
2425 }
2426
41005003
RK		 2427 do {
2428 /* Clear selected interrupts. */
2429 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2430 SDHCI_INT_BUS_POWER);
2431 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2432
41005003
RK		 2433 DBG("*** %s got interrupt: 0x%08x\n",
2434 mmc_hostname(host->mmc), intmask);
d129bceb 2435
41005003
RK		 2436 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2437 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2438 SDHCI_CARD_PRESENT;
d129bceb 2439
41005003
RK		 2440 /*
2441 * There is a observation on i.mx esdhc. INSERT
2442 * bit will be immediately set again when it gets
2443 * cleared, if a card is inserted. We have to mask
2444 * the irq to prevent interrupt storm which will
2445 * freeze the system. And the REMOVE gets the
2446 * same situation.
2447 *
2448 * More testing are needed here to ensure it works
2449 * for other platforms though.
2450 */
b537f94c
RK		 2451 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2452 SDHCI_INT_CARD_REMOVE);
2453 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2454 SDHCI_INT_CARD_INSERT;
2455 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2456 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2457
2458 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2459 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2460
2461 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2462 SDHCI_INT_CARD_REMOVE);
2463 result = IRQ_WAKE_THREAD;
41005003 2464 }
d129bceb 2465
41005003
RK		 2466 if (intmask & SDHCI_INT_CMD_MASK)
2467 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2468
41005003
RK		 2469 if (intmask & SDHCI_INT_DATA_MASK)
2470 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2471
41005003
RK		 2472 if (intmask & SDHCI_INT_BUS_POWER)
2473 pr_err("%s: Card is consuming too much power!\n",
2474 mmc_hostname(host->mmc));
3192a28f 2475
781e989c
RK		 2476 if (intmask & SDHCI_INT_CARD_INT) {
2477 sdhci_enable_sdio_irq_nolock(host, false);
2478 host->thread_isr |= SDHCI_INT_CARD_INT;
2479 result = IRQ_WAKE_THREAD;
2480 }
f75979b7 2481
41005003
RK		 2482 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2483 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2484 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2485 SDHCI_INT_CARD_INT);
f75979b7 2486
41005003
RK		 2487 if (intmask) {
2488 unexpected |= intmask;
2489 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2490 }
d129bceb 2491
781e989c
RK		 2492 if (result == IRQ_NONE)
2493 result = IRQ_HANDLED;
d129bceb 2494
41005003 2495 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2496 } while (intmask && --max_loops);
d129bceb
PO		 2497out:
2498 spin_unlock(&host->lock);
2499
6379b237
AS		 2500 if (unexpected) {
2501 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2502 mmc_hostname(host->mmc), unexpected);
2503 sdhci_dumpregs(host);
2504 }
f75979b7 2505
d129bceb
PO		 2506 return result;
2507}
2508
781e989c
RK		 2509static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2510{
2511 struct sdhci_host *host = dev_id;
2512 unsigned long flags;
2513 u32 isr;
2514
2515 spin_lock_irqsave(&host->lock, flags);
2516 isr = host->thread_isr;
2517 host->thread_isr = 0;
2518 spin_unlock_irqrestore(&host->lock, flags);
2519
3560db8e
RK		 2520 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2521 sdhci_card_event(host->mmc);
2522 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2523 }
2524
781e989c
RK		 2525 if (isr & SDHCI_INT_CARD_INT) {
2526 sdio_run_irqs(host->mmc);
2527
2528 spin_lock_irqsave(&host->lock, flags);
2529 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2530 sdhci_enable_sdio_irq_nolock(host, true);
2531 spin_unlock_irqrestore(&host->lock, flags);
2532 }
2533
2534 return isr ? IRQ_HANDLED : IRQ_NONE;
2535}
2536
d129bceb
PO		 2537/*****************************************************************************\
2538 * *
2539 * Suspend/resume *
2540 * *
2541\*****************************************************************************/
2542
2543#ifdef CONFIG_PM
ad080d79
KL		 2544void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2545{
2546 u8 val;
2547 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2548 | SDHCI_WAKE_ON_INT;
2549
2550 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2551 val |= mask ;
2552 /* Avoid fake wake up */
2553 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2554 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2555 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2556}
2557EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2558
2559void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2560{
2561 u8 val;
2562 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2563 | SDHCI_WAKE_ON_INT;
2564
2565 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2566 val &= ~mask;
2567 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2568}
2569EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2570
29495aa0 2571int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2572{
a1b13b4e
CB		 2573 if (host->ops->platform_suspend)
2574 host->ops->platform_suspend(host);
2575
7260cf5e
AV		 2576 sdhci_disable_card_detection(host);
2577
cf2b5eea 2578 /* Disable tuning since we are suspending */
973905fe 2579 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2580 del_timer_sync(&host->tuning_timer);
cf2b5eea 2581 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2582 }
2583
ad080d79 2584 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2585 host->ier = 0;
2586 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2587 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2588 free_irq(host->irq, host);
2589 } else {
2590 sdhci_enable_irq_wakeups(host);
2591 enable_irq_wake(host->irq);
2592 }
4ee14ec6 2593 return 0;
d129bceb
PO		 2594}
2595
b8c86fc5 2596EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2597
b8c86fc5
PO		 2598int sdhci_resume_host(struct sdhci_host *host)
2599{
4ee14ec6 2600 int ret = 0;
d129bceb 2601
a13abc7b 2602 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2603 if (host->ops->enable_dma)
2604 host->ops->enable_dma(host);
2605 }
d129bceb 2606
ad080d79 2607 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2608 ret = request_threaded_irq(host->irq, sdhci_irq,
2609 sdhci_thread_irq, IRQF_SHARED,
2610 mmc_hostname(host->mmc), host);
ad080d79
KL		 2611 if (ret)
2612 return ret;
2613 } else {
2614 sdhci_disable_irq_wakeups(host);
2615 disable_irq_wake(host->irq);
2616 }
d129bceb 2617
6308d290
AH		 2618 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2619 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2620 /* Card keeps power but host controller does not */
2621 sdhci_init(host, 0);
2622 host->pwr = 0;
2623 host->clock = 0;
2624 sdhci_do_set_ios(host, &host->mmc->ios);
2625 } else {
2626 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2627 mmiowb();
2628 }
b8c86fc5 2629
7260cf5e
AV		 2630 sdhci_enable_card_detection(host);
2631
a1b13b4e
CB		 2632 if (host->ops->platform_resume)
2633 host->ops->platform_resume(host);
2634
cf2b5eea 2635 /* Set the re-tuning expiration flag */
973905fe 2636 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2637 host->flags |= SDHCI_NEEDS_RETUNING;
2638
2f4cbb3d 2639 return ret;
d129bceb
PO		 2640}
2641
b8c86fc5 2642EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2643#endif /* CONFIG_PM */
2644
66fd8ad5
AH		 2645#ifdef CONFIG_PM_RUNTIME
2646
2647static int sdhci_runtime_pm_get(struct sdhci_host *host)
2648{
2649 return pm_runtime_get_sync(host->mmc->parent);
2650}
2651
2652static int sdhci_runtime_pm_put(struct sdhci_host *host)
2653{
2654 pm_runtime_mark_last_busy(host->mmc->parent);
2655 return pm_runtime_put_autosuspend(host->mmc->parent);
2656}
2657
f0710a55
AH		 2658static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2659{
2660 if (host->runtime_suspended || host->bus_on)
2661 return;
2662 host->bus_on = true;
2663 pm_runtime_get_noresume(host->mmc->parent);
2664}
2665
2666static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2667{
2668 if (host->runtime_suspended || !host->bus_on)
2669 return;
2670 host->bus_on = false;
2671 pm_runtime_put_noidle(host->mmc->parent);
2672}
2673
66fd8ad5
AH		 2674int sdhci_runtime_suspend_host(struct sdhci_host *host)
2675{
2676 unsigned long flags;
2677 int ret = 0;
2678
2679 /* Disable tuning since we are suspending */
973905fe 2680 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2681 del_timer_sync(&host->tuning_timer);
2682 host->flags &= ~SDHCI_NEEDS_RETUNING;
2683 }
2684
2685 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2686 host->ier &= SDHCI_INT_CARD_INT;
2687 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2688 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2689 spin_unlock_irqrestore(&host->lock, flags);
2690
781e989c 2691 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2692
2693 spin_lock_irqsave(&host->lock, flags);
2694 host->runtime_suspended = true;
2695 spin_unlock_irqrestore(&host->lock, flags);
2696
2697 return ret;
2698}
2699EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2700
2701int sdhci_runtime_resume_host(struct sdhci_host *host)
2702{
2703 unsigned long flags;
2704 int ret = 0, host_flags = host->flags;
2705
2706 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2707 if (host->ops->enable_dma)
2708 host->ops->enable_dma(host);
2709 }
2710
2711 sdhci_init(host, 0);
2712
2713 /* Force clock and power re-program */
2714 host->pwr = 0;
2715 host->clock = 0;
2716 sdhci_do_set_ios(host, &host->mmc->ios);
2717
2718 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2719 if ((host_flags & SDHCI_PV_ENABLED) &&
2720 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2721 spin_lock_irqsave(&host->lock, flags);
2722 sdhci_enable_preset_value(host, true);
2723 spin_unlock_irqrestore(&host->lock, flags);
2724 }
66fd8ad5
AH		 2725
2726 /* Set the re-tuning expiration flag */
973905fe 2727 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2728 host->flags |= SDHCI_NEEDS_RETUNING;
2729
2730 spin_lock_irqsave(&host->lock, flags);
2731
2732 host->runtime_suspended = false;
2733
2734 /* Enable SDIO IRQ */
ef104333 2735 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2736 sdhci_enable_sdio_irq_nolock(host, true);
2737
2738 /* Enable Card Detection */
2739 sdhci_enable_card_detection(host);
2740
2741 spin_unlock_irqrestore(&host->lock, flags);
2742
2743 return ret;
2744}
2745EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2746
2747#endif
2748
d129bceb
PO		 2749/*****************************************************************************\
2750 * *
b8c86fc5 2751 * Device allocation/registration *
d129bceb
PO		 2752 * *
2753\*****************************************************************************/
2754
b8c86fc5
PO		 2755struct sdhci_host *sdhci_alloc_host(struct device *dev,
2756 size_t priv_size)
d129bceb 2757{
d129bceb
PO		 2758 struct mmc_host *mmc;
2759 struct sdhci_host *host;
2760
b8c86fc5 2761 WARN_ON(dev == NULL);
d129bceb 2762
b8c86fc5 2763 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2764 if (!mmc)
b8c86fc5 2765 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2766
2767 host = mmc_priv(mmc);
2768 host->mmc = mmc;
2769
b8c86fc5
PO		 2770 return host;
2771}
8a4da143 2772
b8c86fc5 2773EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2774
b8c86fc5
PO		 2775int sdhci_add_host(struct sdhci_host *host)
2776{
2777 struct mmc_host *mmc;
bd6a8c30 2778 u32 caps[2] = {0, 0};
f2119df6
AN		 2779 u32 max_current_caps;
2780 unsigned int ocr_avail;
b8c86fc5 2781 int ret;
d129bceb 2782
b8c86fc5
PO		 2783 WARN_ON(host == NULL);
2784 if (host == NULL)
2785 return -EINVAL;
d129bceb 2786
b8c86fc5 2787 mmc = host->mmc;
d129bceb 2788
b8c86fc5
PO		 2789 if (debug_quirks)
2790 host->quirks = debug_quirks;
66fd8ad5
AH		 2791 if (debug_quirks2)
2792 host->quirks2 = debug_quirks2;
d129bceb 2793
d96649ed
PO		 2794 sdhci_reset(host, SDHCI_RESET_ALL);
2795
4e4141a5 2796 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2797 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2798 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2799 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2800 pr_err("%s: Unknown controller version (%d). "
b69c9058 2801 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2802 host->version);
4a965505
PO		 2803 }
2804
f2119df6 2805 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2806 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2807
bd6a8c30
PR		 2808 if (host->version >= SDHCI_SPEC_300)
2809 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2810 host->caps1 :
2811 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2812
b8c86fc5 2813 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2814 host->flags |= SDHCI_USE_SDMA;
f2119df6 2815 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2816 DBG("Controller doesn't have SDMA capability\n");
67435274 2817 else
a13abc7b 2818 host->flags |= SDHCI_USE_SDMA;
d129bceb 2819
b8c86fc5 2820 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2821 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2822 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2823 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2824 }
2825
f2119df6
AN		 2826 if ((host->version >= SDHCI_SPEC_200) &&
2827 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2828 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2829
2830 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2831 (host->flags & SDHCI_USE_ADMA)) {
2832 DBG("Disabling ADMA as it is marked broken\n");
2833 host->flags &= ~SDHCI_USE_ADMA;
2834 }
2835
a13abc7b 2836 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2837 if (host->ops->enable_dma) {
2838 if (host->ops->enable_dma(host)) {
a3c76eb9 2839 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2840 "available. Falling back to PIO.\n",
2841 mmc_hostname(mmc));
a13abc7b
RR		 2842 host->flags &=
2843 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2844 }
d129bceb
PO		 2845 }
2846 }
2847
2134a922
PO		 2848 if (host->flags & SDHCI_USE_ADMA) {
2849 /*
2850 * We need to allocate descriptors for all sg entries
2851 * (128) and potentially one alignment transfer for
2852 * each of those entries.
2853 */
2854 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2855 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2856 if (!host->adma_desc || !host->align_buffer) {
2857 kfree(host->adma_desc);
2858 kfree(host->align_buffer);
a3c76eb9 2859 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2860 "buffers. Falling back to standard DMA.\n",
2861 mmc_hostname(mmc));
2862 host->flags &= ~SDHCI_USE_ADMA;
2863 }
2864 }
2865
7659150c
PO		 2866 /*
2867 * If we use DMA, then it's up to the caller to set the DMA
2868 * mask, but PIO does not need the hw shim so we set a new
2869 * mask here in that case.
2870 */
a13abc7b 2871 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2872 host->dma_mask = DMA_BIT_MASK(64);
2873 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2874 }
d129bceb 2875
c4687d5f 2876 if (host->version >= SDHCI_SPEC_300)
f2119df6 2877 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2878 >> SDHCI_CLOCK_BASE_SHIFT;
2879 else
f2119df6 2880 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2881 >> SDHCI_CLOCK_BASE_SHIFT;
2882
4240ff0a 2883 host->max_clk *= 1000000;
f27f47ef
AV		 2884 if (host->max_clk == 0 || host->quirks &
2885 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2886 if (!host->ops->get_max_clock) {
a3c76eb9 2887 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2888 "frequency.\n", mmc_hostname(mmc));
2889 return -ENODEV;
2890 }
2891 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2892 }
d129bceb 2893
c3ed3877
AN		 2894 /*
2895 * In case of Host Controller v3.00, find out whether clock
2896 * multiplier is supported.
2897 */
2898 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2899 SDHCI_CLOCK_MUL_SHIFT;
2900
2901 /*
2902 * In case the value in Clock Multiplier is 0, then programmable
2903 * clock mode is not supported, otherwise the actual clock
2904 * multiplier is one more than the value of Clock Multiplier
2905 * in the Capabilities Register.
2906 */
2907 if (host->clk_mul)
2908 host->clk_mul += 1;
2909
d129bceb
PO		 2910 /*
2911 * Set host parameters.
2912 */
2913 mmc->ops = &sdhci_ops;
c3ed3877 2914 mmc->f_max = host->max_clk;
ce5f036b 2915 if (host->ops->get_min_clock)
a9e58f25 2916 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2917 else if (host->version >= SDHCI_SPEC_300) {
2918 if (host->clk_mul) {
2919 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2920 mmc->f_max = host->max_clk * host->clk_mul;
2921 } else
2922 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2923 } else
0397526d 2924 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2925
272308ca
AS		 2926 host->timeout_clk =
2927 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2928 if (host->timeout_clk == 0) {
2929 if (host->ops->get_timeout_clock) {
2930 host->timeout_clk = host->ops->get_timeout_clock(host);
2931 } else if (!(host->quirks &
2932 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2933 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2934 "frequency.\n", mmc_hostname(mmc));
2935 return -ENODEV;
2936 }
2937 }
2938 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2939 host->timeout_clk *= 1000;
2940
2941 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2942 host->timeout_clk = mmc->f_max / 1000;
272308ca 2943
68eb80e0 2944 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
58d1246d 2945
e89d456f 2946 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 2947 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 2948
2949 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2950 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2951
8edf6371 2952 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2953 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2954 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2955 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2956 host->flags |= SDHCI_AUTO_CMD23;
2957 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2958 } else {
2959 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2960 }
2961
15ec4461
PR		 2962 /*
2963 * A controller may support 8-bit width, but the board itself
2964 * might not have the pins brought out. Boards that support
2965 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2966 * their platform code before calling sdhci_add_host(), and we
2967 * won't assume 8-bit width for hosts without that CAP.
2968 */
5fe23c7f 2969 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2970 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2971
63ef5d8c
JH		 2972 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2973 mmc->caps &= ~MMC_CAP_CMD23;
2974
f2119df6 2975 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2976 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2977
176d1ed4 2978 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2979 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2980 mmc->caps |= MMC_CAP_NEEDS_POLL;
2981
6231f3de 2982 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
462849aa 2983 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2984 if (IS_ERR_OR_NULL(host->vqmmc)) {
2985 if (PTR_ERR(host->vqmmc) < 0) {
2986 pr_info("%s: no vqmmc regulator found\n",
2987 mmc_hostname(mmc));
2988 host->vqmmc = NULL;
2989 }
8363c374 2990 } else {
a3361aba 2991 ret = regulator_enable(host->vqmmc);
cec2e216
KL		 2992 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2993 1950000))
8363c374
KL		 2994 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2995 SDHCI_SUPPORT_SDR50 |
2996 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 2997 if (ret) {
2998 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2999 mmc_hostname(mmc), ret);
3000 host->vqmmc = NULL;
3001 }
8363c374 3002 }
6231f3de 3003
6a66180a
DD		 3004 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3005 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3006 SDHCI_SUPPORT_DDR50);
3007
4188bba0
AC		 3008 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3009 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3010 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3011 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3012
3013 /* SDR104 supports also implies SDR50 support */
156e14b1 3014 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3015 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3016 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3017 * field can be promoted to support HS200.
3018 */
13868bf2
DC		 3019 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3020 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3021 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3022 mmc->caps |= MMC_CAP_UHS_SDR50;
3023
9107ebbf
MC		 3024 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3025 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3026 mmc->caps |= MMC_CAP_UHS_DDR50;
3027
069c9f14 3028 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3029 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3030 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3031
156e14b1 3032 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3033 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3034 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3035
d6d50a15
AN		 3036 /* Driver Type(s) (A, C, D) supported by the host */
3037 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3038 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3039 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3040 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3041 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3042 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3043
cf2b5eea
AN		 3044 /* Initial value for re-tuning timer count */
3045 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3046 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3047
3048 /*
3049 * In case Re-tuning Timer is not disabled, the actual value of
3050 * re-tuning timer will be 2 ^ (n - 1).
3051 */
3052 if (host->tuning_count)
3053 host->tuning_count = 1 << (host->tuning_count - 1);
3054
3055 /* Re-tuning mode supported by the Host Controller */
3056 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3057 SDHCI_RETUNING_MODE_SHIFT;
3058
8f230f45 3059 ocr_avail = 0;
bad37e1a 3060
462849aa 3061 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
657d5982
KL		 3062 if (IS_ERR_OR_NULL(host->vmmc)) {
3063 if (PTR_ERR(host->vmmc) < 0) {
3064 pr_info("%s: no vmmc regulator found\n",
3065 mmc_hostname(mmc));
3066 host->vmmc = NULL;
3067 }
8363c374 3068 }
bad37e1a 3069
68737043 3070#ifdef CONFIG_REGULATOR
a4f8f257
MS		 3071 /*
3072 * Voltage range check makes sense only if regulator reports
3073 * any voltage value.
3074 */
3075 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 3076 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3077 3600000);
68737043
PR		 3078 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3079 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 3080 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3081 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 3082 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3083 1950000);
68737043
PR		 3084 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3085 caps[0] &= ~SDHCI_CAN_VDD_180;
3086 }
3087#endif /* CONFIG_REGULATOR */
3088
f2119df6
AN		 3089 /*
3090 * According to SD Host Controller spec v3.00, if the Host System
3091 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3092 * the value is meaningful only if Voltage Support in the Capabilities
3093 * register is set. The actual current value is 4 times the register
3094 * value.
3095 */
3096 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3097 if (!max_current_caps && host->vmmc) {
3098 u32 curr = regulator_get_current_limit(host->vmmc);
3099 if (curr > 0) {
3100
3101 /* convert to SDHCI_MAX_CURRENT format */
3102 curr = curr/1000; /* convert to mA */
3103 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3104
3105 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3106 max_current_caps =
3107 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3108 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3109 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3110 }
3111 }
f2119df6
AN		 3112
3113 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3114 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3115
55c4665e 3116 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3117 SDHCI_MAX_CURRENT_330_MASK) >>
3118 SDHCI_MAX_CURRENT_330_SHIFT) *
3119 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3120 }
3121 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3122 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3123
55c4665e 3124 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3125 SDHCI_MAX_CURRENT_300_MASK) >>
3126 SDHCI_MAX_CURRENT_300_SHIFT) *
3127 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3128 }
3129 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3130 ocr_avail |= MMC_VDD_165_195;
3131
55c4665e 3132 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3133 SDHCI_MAX_CURRENT_180_MASK) >>
3134 SDHCI_MAX_CURRENT_180_SHIFT) *
3135 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3136 }
3137
c0b887b6
HZ		 3138 if (host->ocr_mask)
3139 ocr_avail = host->ocr_mask;
3140
8f230f45
TI		 3141 mmc->ocr_avail = ocr_avail;
3142 mmc->ocr_avail_sdio = ocr_avail;
3143 if (host->ocr_avail_sdio)
3144 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3145 mmc->ocr_avail_sd = ocr_avail;
3146 if (host->ocr_avail_sd)
3147 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3148 else /* normal SD controllers don't support 1.8V */
3149 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3150 mmc->ocr_avail_mmc = ocr_avail;
3151 if (host->ocr_avail_mmc)
3152 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3153
3154 if (mmc->ocr_avail == 0) {
a3c76eb9 3155 pr_err("%s: Hardware doesn't report any "
b69c9058 3156 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3157 return -ENODEV;
146ad66e
PO		 3158 }
3159
d129bceb
PO		 3160 spin_lock_init(&host->lock);
3161
3162 /*
2134a922
PO		 3163 * Maximum number of segments. Depends on if the hardware
3164 * can do scatter/gather or not.
d129bceb 3165 */
2134a922 3166 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3167 mmc->max_segs = 128;
a13abc7b 3168 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3169 mmc->max_segs = 1;
2134a922 3170 else /* PIO */
a36274e0 3171 mmc->max_segs = 128;
d129bceb
PO		 3172
3173 /*
bab76961 3174 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3175 * size (512KiB).
d129bceb 3176 */
55db890a 3177 mmc->max_req_size = 524288;
d129bceb
PO		 3178
3179 /*
3180 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3181 * of bytes. When doing hardware scatter/gather, each entry cannot
3182 * be larger than 64 KiB though.
d129bceb 3183 */
30652aa3
OJ		 3184 if (host->flags & SDHCI_USE_ADMA) {
3185 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3186 mmc->max_seg_size = 65535;
3187 else
3188 mmc->max_seg_size = 65536;
3189 } else {
2134a922 3190 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3191 }
d129bceb 3192
fe4a3c7a
PO		 3193 /*
3194 * Maximum block size. This varies from controller to controller and
3195 * is specified in the capabilities register.
3196 */
0633f654
AV		 3197 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3198 mmc->max_blk_size = 2;
3199 } else {
f2119df6 3200 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3201 SDHCI_MAX_BLOCK_SHIFT;
3202 if (mmc->max_blk_size >= 3) {
a3c76eb9 3203 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3204 "assuming 512 bytes\n", mmc_hostname(mmc));
3205 mmc->max_blk_size = 0;
3206 }
3207 }
3208
3209 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3210
55db890a
PO		 3211 /*
3212 * Maximum block count.
3213 */
1388eefd 3214 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3215
d129bceb
PO		 3216 /*
3217 * Init tasklets.
3218 */
d129bceb
PO		 3219 tasklet_init(&host->finish_tasklet,
3220 sdhci_tasklet_finish, (unsigned long)host);
3221
e4cad1b5 3222 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3223
cf2b5eea 3224 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3225 init_waitqueue_head(&host->buf_ready_int);
3226
cf2b5eea
AN		 3227 /* Initialize re-tuning timer */
3228 init_timer(&host->tuning_timer);
3229 host->tuning_timer.data = (unsigned long)host;
3230 host->tuning_timer.function = sdhci_tuning_timer;
3231 }
3232
2af502ca
SG		 3233 sdhci_init(host, 0);
3234
781e989c
RK		 3235 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3236 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3237 if (ret) {
3238 pr_err("%s: Failed to request IRQ %d: %d\n",
3239 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3240 goto untasklet;
0fc81ee3 3241 }
d129bceb 3242
d129bceb
PO		 3243#ifdef CONFIG_MMC_DEBUG
3244 sdhci_dumpregs(host);
3245#endif
3246
f9134319 3247#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3248 snprintf(host->led_name, sizeof(host->led_name),
3249 "%s::", mmc_hostname(mmc));
3250 host->led.name = host->led_name;
2f730fec
PO		 3251 host->led.brightness = LED_OFF;
3252 host->led.default_trigger = mmc_hostname(mmc);
3253 host->led.brightness_set = sdhci_led_control;
3254
b8c86fc5 3255 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3256 if (ret) {
3257 pr_err("%s: Failed to register LED device: %d\n",
3258 mmc_hostname(mmc), ret);
2f730fec 3259 goto reset;
0fc81ee3 3260 }
2f730fec
PO		 3261#endif
3262
5f25a66f
PO		 3263 mmiowb();
3264
d129bceb
PO		 3265 mmc_add_host(mmc);
3266
a3c76eb9 3267 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3268 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3269 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3270 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3271
7260cf5e
AV		 3272 sdhci_enable_card_detection(host);
3273
d129bceb
PO		 3274 return 0;
3275
f9134319 3276#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3277reset:
3278 sdhci_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3279 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3280 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3281 free_irq(host->irq, host);
3282#endif
8ef1a143 3283untasklet:
d129bceb 3284 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3285
3286 return ret;
3287}
3288
b8c86fc5 3289EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3290
1e72859e 3291void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3292{
1e72859e
PO		 3293 unsigned long flags;
3294
3295 if (dead) {
3296 spin_lock_irqsave(&host->lock, flags);
3297
3298 host->flags |= SDHCI_DEVICE_DEAD;
3299
3300 if (host->mrq) {
a3c76eb9 3301 pr_err("%s: Controller removed during "
1e72859e
PO		 3302 " transfer!\n", mmc_hostname(host->mmc));
3303
3304 host->mrq->cmd->error = -ENOMEDIUM;
3305 tasklet_schedule(&host->finish_tasklet);
3306 }
3307
3308 spin_unlock_irqrestore(&host->lock, flags);
3309 }
3310
7260cf5e
AV		 3311 sdhci_disable_card_detection(host);
3312
b8c86fc5 3313 mmc_remove_host(host->mmc);
d129bceb 3314
f9134319 3315#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3316 led_classdev_unregister(&host->led);
3317#endif
3318
1e72859e
PO		 3319 if (!dead)
3320 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 3321
b537f94c
RK		 3322 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3323 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3324 free_irq(host->irq, host);
3325
3326 del_timer_sync(&host->timer);
3327
d129bceb 3328 tasklet_kill(&host->finish_tasklet);
2134a922 3329
77dcb3f4
PR		 3330 if (host->vmmc) {
3331 regulator_disable(host->vmmc);
9bea3c85 3332 regulator_put(host->vmmc);
77dcb3f4 3333 }
9bea3c85 3334
6231f3de
PR		 3335 if (host->vqmmc) {
3336 regulator_disable(host->vqmmc);
3337 regulator_put(host->vqmmc);
3338 }
3339
2134a922
PO		 3340 kfree(host->adma_desc);
3341 kfree(host->align_buffer);
3342
3343 host->adma_desc = NULL;
3344 host->align_buffer = NULL;
d129bceb
PO		 3345}
3346
b8c86fc5 3347EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3348
b8c86fc5 3349void sdhci_free_host(struct sdhci_host *host)
d129bceb 3350{
b8c86fc5 3351 mmc_free_host(host->mmc);
d129bceb
PO		 3352}
3353
b8c86fc5 3354EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3355
3356/*****************************************************************************\
3357 * *
3358 * Driver init/exit *
3359 * *
3360\*****************************************************************************/
3361
3362static int __init sdhci_drv_init(void)
3363{
a3c76eb9 3364 pr_info(DRIVER_NAME
52fbf9c9 3365 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3366 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3367
b8c86fc5 3368 return 0;
d129bceb
PO		 3369}
3370
3371static void __exit sdhci_drv_exit(void)
3372{
d129bceb
PO		 3373}
3374
3375module_init(sdhci_drv_init);
3376module_exit(sdhci_drv_exit);
3377
df673b22 3378module_param(debug_quirks, uint, 0444);
66fd8ad5 3379module_param(debug_quirks2, uint, 0444);
67435274 3380
32710e8f 3381MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3382MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3383MODULE_LICENSE("GPL");
67435274 3384
df673b22 3385MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3386MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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