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mmc: queue: let host controllers specify maximum discard timeout
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
9bea3c85 22#include <linux/regulator/consumer.h>
d129bceb 23
2f730fec
PO		 24#include <linux/leds.h>
25
22113efd 26#include <linux/mmc/mmc.h>
d129bceb 27#include <linux/mmc/host.h>
d129bceb 28
d129bceb
PO		 29#include "sdhci.h"
30
31#define DRIVER_NAME "sdhci"
d129bceb 32
d129bceb 33#define DBG(f, x...) \
c6563178 34 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 35
f9134319
PO		 36#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
37 defined(CONFIG_MMC_SDHCI_MODULE))
38#define SDHCI_USE_LEDS_CLASS
39#endif
40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
67435274 44
d129bceb
PO		 45static void sdhci_finish_data(struct sdhci_host *);
46
47static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
48static void sdhci_finish_command(struct sdhci_host *);
cf2b5eea
AN		 49static int sdhci_execute_tuning(struct mmc_host *mmc);
50static void sdhci_tuning_timer(unsigned long data);
d129bceb
PO		 51
52static void sdhci_dumpregs(struct sdhci_host *host)
53{
412ab659
PR		 54 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
55 mmc_hostname(host->mmc));
d129bceb
PO		 56
57 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 58 sdhci_readl(host, SDHCI_DMA_ADDRESS),
59 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 60 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 61 sdhci_readw(host, SDHCI_BLOCK_SIZE),
62 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 63 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 64 sdhci_readl(host, SDHCI_ARGUMENT),
65 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 66 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 67 sdhci_readl(host, SDHCI_PRESENT_STATE),
68 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 69 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 70 sdhci_readb(host, SDHCI_POWER_CONTROL),
71 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 72 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 73 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
74 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 75 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 76 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
77 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 78 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 79 sdhci_readl(host, SDHCI_INT_ENABLE),
80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 81 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 82 sdhci_readw(host, SDHCI_ACMD12_ERR),
83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
e8120ad1 84 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 85 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1
PR		 86 sdhci_readl(host, SDHCI_CAPABILITIES_1));
87 printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
88 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 89 sdhci_readl(host, SDHCI_MAX_CURRENT));
f2119df6
AN		 90 printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
91 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 92
be3f4ae0
BD		 93 if (host->flags & SDHCI_USE_ADMA)
94 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
95 readl(host->ioaddr + SDHCI_ADMA_ERROR),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
97
d129bceb
PO		 98 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
99}
100
101/*****************************************************************************\
102 * *
103 * Low level functions *
104 * *
105\*****************************************************************************/
106
7260cf5e
AV		 107static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
108{
109 u32 ier;
110
111 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
112 ier &= ~clear;
113 ier |= set;
114 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
115 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
116}
117
118static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
119{
120 sdhci_clear_set_irqs(host, 0, irqs);
121}
122
123static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
124{
125 sdhci_clear_set_irqs(host, irqs, 0);
126}
127
128static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
129{
d25928d1 130 u32 present, irqs;
7260cf5e 131
68d1fb7e
AV		 132 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
133 return;
134
d25928d1
SG		 135 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
136 SDHCI_CARD_PRESENT;
137 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
138
7260cf5e
AV		 139 if (enable)
140 sdhci_unmask_irqs(host, irqs);
141 else
142 sdhci_mask_irqs(host, irqs);
143}
144
145static void sdhci_enable_card_detection(struct sdhci_host *host)
146{
147 sdhci_set_card_detection(host, true);
148}
149
150static void sdhci_disable_card_detection(struct sdhci_host *host)
151{
152 sdhci_set_card_detection(host, false);
153}
154
d129bceb
PO		 155static void sdhci_reset(struct sdhci_host *host, u8 mask)
156{
e16514d8 157 unsigned long timeout;
063a9dbb 158 u32 uninitialized_var(ier);
e16514d8 159
b8c86fc5 160 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 161 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 162 SDHCI_CARD_PRESENT))
163 return;
164 }
165
063a9dbb
AV		 166 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
167 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
168
393c1a34
PR		 169 if (host->ops->platform_reset_enter)
170 host->ops->platform_reset_enter(host, mask);
171
4e4141a5 172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 173
e16514d8 174 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 175 host->clock = 0;
176
e16514d8
PO		 177 /* Wait max 100 ms */
178 timeout = 100;
179
180 /* hw clears the bit when it's done */
4e4141a5 181 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 182 if (timeout == 0) {
acf1da45 183 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 184 mmc_hostname(host->mmc), (int)mask);
185 sdhci_dumpregs(host);
186 return;
187 }
188 timeout--;
189 mdelay(1);
d129bceb 190 }
063a9dbb 191
393c1a34
PR		 192 if (host->ops->platform_reset_exit)
193 host->ops->platform_reset_exit(host, mask);
194
063a9dbb
AV		 195 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
196 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 197}
198
2f4cbb3d
NP		 199static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
200
201static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 202{
2f4cbb3d
NP		 203 if (soft)
204 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
205 else
206 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 207
7260cf5e
AV		 208 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
209 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 210 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
211 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 212 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 213
214 if (soft) {
215 /* force clock reconfiguration */
216 host->clock = 0;
217 sdhci_set_ios(host->mmc, &host->mmc->ios);
218 }
7260cf5e 219}
d129bceb 220
7260cf5e
AV		 221static void sdhci_reinit(struct sdhci_host *host)
222{
2f4cbb3d 223 sdhci_init(host, 0);
7260cf5e 224 sdhci_enable_card_detection(host);
d129bceb
PO		 225}
226
227static void sdhci_activate_led(struct sdhci_host *host)
228{
229 u8 ctrl;
230
4e4141a5 231 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 232 ctrl |= SDHCI_CTRL_LED;
4e4141a5 233 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 234}
235
236static void sdhci_deactivate_led(struct sdhci_host *host)
237{
238 u8 ctrl;
239
4e4141a5 240 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 241 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 242 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 243}
244
f9134319 245#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 246static void sdhci_led_control(struct led_classdev *led,
247 enum led_brightness brightness)
248{
249 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
250 unsigned long flags;
251
252 spin_lock_irqsave(&host->lock, flags);
253
254 if (brightness == LED_OFF)
255 sdhci_deactivate_led(host);
256 else
257 sdhci_activate_led(host);
258
259 spin_unlock_irqrestore(&host->lock, flags);
260}
261#endif
262
d129bceb
PO		 263/*****************************************************************************\
264 * *
265 * Core functions *
266 * *
267\*****************************************************************************/
268
a406f5a3 269static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 270{
7659150c
PO		 271 unsigned long flags;
272 size_t blksize, len, chunk;
7244b85b 273 u32 uninitialized_var(scratch);
7659150c 274 u8 *buf;
d129bceb 275
a406f5a3 276 DBG("PIO reading\n");
d129bceb 277
a406f5a3 278 blksize = host->data->blksz;
7659150c 279 chunk = 0;
d129bceb 280
7659150c 281 local_irq_save(flags);
d129bceb 282
a406f5a3 283 while (blksize) {
7659150c
PO		 284 if (!sg_miter_next(&host->sg_miter))
285 BUG();
d129bceb 286
7659150c 287 len = min(host->sg_miter.length, blksize);
d129bceb 288
7659150c
PO		 289 blksize -= len;
290 host->sg_miter.consumed = len;
14d836e7 291
7659150c 292 buf = host->sg_miter.addr;
d129bceb 293
7659150c
PO		 294 while (len) {
295 if (chunk == 0) {
4e4141a5 296 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 297 chunk = 4;
a406f5a3 298 }
7659150c
PO		 299
300 *buf = scratch & 0xFF;
301
302 buf++;
303 scratch >>= 8;
304 chunk--;
305 len--;
d129bceb 306 }
a406f5a3 307 }
7659150c
PO		 308
309 sg_miter_stop(&host->sg_miter);
310
311 local_irq_restore(flags);
a406f5a3 312}
d129bceb 313
a406f5a3
PO		 314static void sdhci_write_block_pio(struct sdhci_host *host)
315{
7659150c
PO		 316 unsigned long flags;
317 size_t blksize, len, chunk;
318 u32 scratch;
319 u8 *buf;
d129bceb 320
a406f5a3
PO		 321 DBG("PIO writing\n");
322
323 blksize = host->data->blksz;
7659150c
PO		 324 chunk = 0;
325 scratch = 0;
d129bceb 326
7659150c 327 local_irq_save(flags);
d129bceb 328
a406f5a3 329 while (blksize) {
7659150c
PO		 330 if (!sg_miter_next(&host->sg_miter))
331 BUG();
a406f5a3 332
7659150c
PO		 333 len = min(host->sg_miter.length, blksize);
334
335 blksize -= len;
336 host->sg_miter.consumed = len;
337
338 buf = host->sg_miter.addr;
d129bceb 339
7659150c
PO		 340 while (len) {
341 scratch |= (u32)*buf << (chunk * 8);
342
343 buf++;
344 chunk++;
345 len--;
346
347 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 348 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 349 chunk = 0;
350 scratch = 0;
d129bceb 351 }
d129bceb
PO		 352 }
353 }
7659150c
PO		 354
355 sg_miter_stop(&host->sg_miter);
356
357 local_irq_restore(flags);
a406f5a3
PO		 358}
359
360static void sdhci_transfer_pio(struct sdhci_host *host)
361{
362 u32 mask;
363
364 BUG_ON(!host->data);
365
7659150c 366 if (host->blocks == 0)
a406f5a3
PO		 367 return;
368
369 if (host->data->flags & MMC_DATA_READ)
370 mask = SDHCI_DATA_AVAILABLE;
371 else
372 mask = SDHCI_SPACE_AVAILABLE;
373
4a3cba32
PO		 374 /*
375 * Some controllers (JMicron JMB38x) mess up the buffer bits
376 * for transfers < 4 bytes. As long as it is just one block,
377 * we can ignore the bits.
378 */
379 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
380 (host->data->blocks == 1))
381 mask = ~0;
382
4e4141a5 383 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 384 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
385 udelay(100);
386
a406f5a3
PO		 387 if (host->data->flags & MMC_DATA_READ)
388 sdhci_read_block_pio(host);
389 else
390 sdhci_write_block_pio(host);
d129bceb 391
7659150c
PO		 392 host->blocks--;
393 if (host->blocks == 0)
a406f5a3 394 break;
a406f5a3 395 }
d129bceb 396
a406f5a3 397 DBG("PIO transfer complete.\n");
d129bceb
PO		 398}
399
2134a922
PO		 400static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
401{
402 local_irq_save(*flags);
403 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
404}
405
406static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
407{
408 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
409 local_irq_restore(*flags);
410}
411
118cd17d
BD		 412static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
413{
9e506f35
BD		 414 __le32 *dataddr = (__le32 __force *)(desc + 4);
415 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 416
9e506f35
BD		 417 /* SDHCI specification says ADMA descriptors should be 4 byte
418 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 419
9e506f35
BD		 420 cmdlen[0] = cpu_to_le16(cmd);
421 cmdlen[1] = cpu_to_le16(len);
422
423 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 424}
425
8f1934ce 426static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 427 struct mmc_data *data)
428{
429 int direction;
430
431 u8 *desc;
432 u8 *align;
433 dma_addr_t addr;
434 dma_addr_t align_addr;
435 int len, offset;
436
437 struct scatterlist *sg;
438 int i;
439 char *buffer;
440 unsigned long flags;
441
442 /*
443 * The spec does not specify endianness of descriptor table.
444 * We currently guess that it is LE.
445 */
446
447 if (data->flags & MMC_DATA_READ)
448 direction = DMA_FROM_DEVICE;
449 else
450 direction = DMA_TO_DEVICE;
451
452 /*
453 * The ADMA descriptor table is mapped further down as we
454 * need to fill it with data first.
455 */
456
457 host->align_addr = dma_map_single(mmc_dev(host->mmc),
458 host->align_buffer, 128 * 4, direction);
8d8bb39b 459 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 460 goto fail;
2134a922
PO		 461 BUG_ON(host->align_addr & 0x3);
462
463 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
464 data->sg, data->sg_len, direction);
8f1934ce
PO		 465 if (host->sg_count == 0)
466 goto unmap_align;
2134a922
PO		 467
468 desc = host->adma_desc;
469 align = host->align_buffer;
470
471 align_addr = host->align_addr;
472
473 for_each_sg(data->sg, sg, host->sg_count, i) {
474 addr = sg_dma_address(sg);
475 len = sg_dma_len(sg);
476
477 /*
478 * The SDHCI specification states that ADMA
479 * addresses must be 32-bit aligned. If they
480 * aren't, then we use a bounce buffer for
481 * the (up to three) bytes that screw up the
482 * alignment.
483 */
484 offset = (4 - (addr & 0x3)) & 0x3;
485 if (offset) {
486 if (data->flags & MMC_DATA_WRITE) {
487 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 488 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 489 memcpy(align, buffer, offset);
490 sdhci_kunmap_atomic(buffer, &flags);
491 }
492
118cd17d
BD		 493 /* tran, valid */
494 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 495
496 BUG_ON(offset > 65536);
497
2134a922
PO		 498 align += 4;
499 align_addr += 4;
500
501 desc += 8;
502
503 addr += offset;
504 len -= offset;
505 }
506
2134a922
PO		 507 BUG_ON(len > 65536);
508
118cd17d
BD		 509 /* tran, valid */
510 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 511 desc += 8;
512
513 /*
514 * If this triggers then we have a calculation bug
515 * somewhere. :/
516 */
517 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
518 }
519
70764a90
TA		 520 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
521 /*
522 * Mark the last descriptor as the terminating descriptor
523 */
524 if (desc != host->adma_desc) {
525 desc -= 8;
526 desc[0] |= 0x2; /* end */
527 }
528 } else {
529 /*
530 * Add a terminating entry.
531 */
2134a922 532
70764a90
TA		 533 /* nop, end, valid */
534 sdhci_set_adma_desc(desc, 0, 0, 0x3);
535 }
2134a922
PO		 536
537 /*
538 * Resync align buffer as we might have changed it.
539 */
540 if (data->flags & MMC_DATA_WRITE) {
541 dma_sync_single_for_device(mmc_dev(host->mmc),
542 host->align_addr, 128 * 4, direction);
543 }
544
545 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
546 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 547 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 548 goto unmap_entries;
2134a922 549 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 550
551 return 0;
552
553unmap_entries:
554 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
555 data->sg_len, direction);
556unmap_align:
557 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
558 128 * 4, direction);
559fail:
560 return -EINVAL;
2134a922
PO		 561}
562
563static void sdhci_adma_table_post(struct sdhci_host *host,
564 struct mmc_data *data)
565{
566 int direction;
567
568 struct scatterlist *sg;
569 int i, size;
570 u8 *align;
571 char *buffer;
572 unsigned long flags;
573
574 if (data->flags & MMC_DATA_READ)
575 direction = DMA_FROM_DEVICE;
576 else
577 direction = DMA_TO_DEVICE;
578
579 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
580 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
581
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
583 128 * 4, direction);
584
585 if (data->flags & MMC_DATA_READ) {
586 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
587 data->sg_len, direction);
588
589 align = host->align_buffer;
590
591 for_each_sg(data->sg, sg, host->sg_count, i) {
592 if (sg_dma_address(sg) & 0x3) {
593 size = 4 - (sg_dma_address(sg) & 0x3);
594
595 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 596 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 597 memcpy(buffer, align, size);
598 sdhci_kunmap_atomic(buffer, &flags);
599
600 align += 4;
601 }
602 }
603 }
604
605 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
606 data->sg_len, direction);
607}
608
a3c7778f 609static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 610{
1c8cde92 611 u8 count;
a3c7778f 612 struct mmc_data *data = cmd->data;
1c8cde92 613 unsigned target_timeout, current_timeout;
d129bceb 614
ee53ab5d
PO		 615 /*
616 * If the host controller provides us with an incorrect timeout
617 * value, just skip the check and use 0xE. The hardware may take
618 * longer to time out, but that's much better than having a too-short
619 * timeout value.
620 */
11a2f1b7 621 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 622 return 0xE;
e538fbe8 623
a3c7778f
AW		 624 /* Unspecified timeout, assume max */
625 if (!data && !cmd->cmd_timeout_ms)
626 return 0xE;
d129bceb 627
a3c7778f
AW		 628 /* timeout in us */
629 if (!data)
630 target_timeout = cmd->cmd_timeout_ms * 1000;
631 else
632 target_timeout = data->timeout_ns / 1000 +
633 data->timeout_clks / host->clock;
81b39802 634
4b01681c
MB		 635 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
636 host->timeout_clk = host->clock / 1000;
637
1c8cde92
PO		 638 /*
639 * Figure out needed cycles.
640 * We do this in steps in order to fit inside a 32 bit int.
641 * The first step is the minimum timeout, which will have a
642 * minimum resolution of 6 bits:
643 * (1) 2^13*1000 > 2^22,
644 * (2) host->timeout_clk < 2^16
645 * =>
646 * (1) / (2) > 2^6
647 */
4b01681c 648 BUG_ON(!host->timeout_clk);
1c8cde92
PO		 649 count = 0;
650 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
651 while (current_timeout < target_timeout) {
652 count++;
653 current_timeout <<= 1;
654 if (count >= 0xF)
655 break;
656 }
657
658 if (count >= 0xF) {
a3c7778f
AW		 659 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
660 mmc_hostname(host->mmc), cmd->opcode);
1c8cde92
PO		 661 count = 0xE;
662 }
663
ee53ab5d
PO		 664 return count;
665}
666
6aa943ab
AV		 667static void sdhci_set_transfer_irqs(struct sdhci_host *host)
668{
669 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
670 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
671
672 if (host->flags & SDHCI_REQ_USE_DMA)
673 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
674 else
675 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
676}
677
a3c7778f 678static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 679{
680 u8 count;
2134a922 681 u8 ctrl;
a3c7778f 682 struct mmc_data *data = cmd->data;
8f1934ce 683 int ret;
ee53ab5d
PO		 684
685 WARN_ON(host->data);
686
a3c7778f
AW		 687 if (data || (cmd->flags & MMC_RSP_BUSY)) {
688 count = sdhci_calc_timeout(host, cmd);
689 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
690 }
691
692 if (!data)
ee53ab5d
PO		 693 return;
694
695 /* Sanity checks */
696 BUG_ON(data->blksz * data->blocks > 524288);
697 BUG_ON(data->blksz > host->mmc->max_blk_size);
698 BUG_ON(data->blocks > 65535);
699
700 host->data = data;
701 host->data_early = 0;
f6a03cbf 702 host->data->bytes_xfered = 0;
ee53ab5d 703
a13abc7b 704 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 705 host->flags |= SDHCI_REQ_USE_DMA;
706
2134a922
PO		 707 /*
708 * FIXME: This doesn't account for merging when mapping the
709 * scatterlist.
710 */
711 if (host->flags & SDHCI_REQ_USE_DMA) {
712 int broken, i;
713 struct scatterlist *sg;
714
715 broken = 0;
716 if (host->flags & SDHCI_USE_ADMA) {
717 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
718 broken = 1;
719 } else {
720 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
721 broken = 1;
722 }
723
724 if (unlikely(broken)) {
725 for_each_sg(data->sg, sg, data->sg_len, i) {
726 if (sg->length & 0x3) {
727 DBG("Reverting to PIO because of "
728 "transfer size (%d)\n",
729 sg->length);
730 host->flags &= ~SDHCI_REQ_USE_DMA;
731 break;
732 }
733 }
734 }
c9fddbc4
PO		 735 }
736
737 /*
738 * The assumption here being that alignment is the same after
739 * translation to device address space.
740 */
2134a922
PO		 741 if (host->flags & SDHCI_REQ_USE_DMA) {
742 int broken, i;
743 struct scatterlist *sg;
744
745 broken = 0;
746 if (host->flags & SDHCI_USE_ADMA) {
747 /*
748 * As we use 3 byte chunks to work around
749 * alignment problems, we need to check this
750 * quirk.
751 */
752 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
753 broken = 1;
754 } else {
755 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
756 broken = 1;
757 }
758
759 if (unlikely(broken)) {
760 for_each_sg(data->sg, sg, data->sg_len, i) {
761 if (sg->offset & 0x3) {
762 DBG("Reverting to PIO because of "
763 "bad alignment\n");
764 host->flags &= ~SDHCI_REQ_USE_DMA;
765 break;
766 }
767 }
768 }
769 }
770
8f1934ce
PO		 771 if (host->flags & SDHCI_REQ_USE_DMA) {
772 if (host->flags & SDHCI_USE_ADMA) {
773 ret = sdhci_adma_table_pre(host, data);
774 if (ret) {
775 /*
776 * This only happens when someone fed
777 * us an invalid request.
778 */
779 WARN_ON(1);
ebd6d357 780 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 781 } else {
4e4141a5
AV		 782 sdhci_writel(host, host->adma_addr,
783 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 784 }
785 } else {
c8b3e02e 786 int sg_cnt;
8f1934ce 787
c8b3e02e 788 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 789 data->sg, data->sg_len,
790 (data->flags & MMC_DATA_READ) ?
791 DMA_FROM_DEVICE :
792 DMA_TO_DEVICE);
c8b3e02e 793 if (sg_cnt == 0) {
8f1934ce
PO		 794 /*
795 * This only happens when someone fed
796 * us an invalid request.
797 */
798 WARN_ON(1);
ebd6d357 799 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 800 } else {
719a61b4 801 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 802 sdhci_writel(host, sg_dma_address(data->sg),
803 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 804 }
805 }
806 }
807
2134a922
PO		 808 /*
809 * Always adjust the DMA selection as some controllers
810 * (e.g. JMicron) can't do PIO properly when the selection
811 * is ADMA.
812 */
813 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 814 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 815 ctrl &= ~SDHCI_CTRL_DMA_MASK;
816 if ((host->flags & SDHCI_REQ_USE_DMA) &&
817 (host->flags & SDHCI_USE_ADMA))
818 ctrl |= SDHCI_CTRL_ADMA32;
819 else
820 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 821 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 822 }
823
8f1934ce 824 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 825 int flags;
826
827 flags = SG_MITER_ATOMIC;
828 if (host->data->flags & MMC_DATA_READ)
829 flags |= SG_MITER_TO_SG;
830 else
831 flags |= SG_MITER_FROM_SG;
832 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 833 host->blocks = data->blocks;
d129bceb 834 }
c7fa9963 835
6aa943ab
AV		 836 sdhci_set_transfer_irqs(host);
837
f6a03cbf
MV		 838 /* Set the DMA boundary value and block size */
839 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
840 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 841 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 842}
843
844static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 845 struct mmc_command *cmd)
c7fa9963
PO		 846{
847 u16 mode;
e89d456f 848 struct mmc_data *data = cmd->data;
c7fa9963 849
c7fa9963
PO		 850 if (data == NULL)
851 return;
852
e538fbe8
PO		 853 WARN_ON(!host->data);
854
c7fa9963 855 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 856 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
857 mode |= SDHCI_TRNS_MULTI;
858 /*
859 * If we are sending CMD23, CMD12 never gets sent
860 * on successful completion (so no Auto-CMD12).
861 */
862 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
863 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 864 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
865 mode |= SDHCI_TRNS_AUTO_CMD23;
866 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
867 }
c4512f79 868 }
8edf6371 869
c7fa9963
PO		 870 if (data->flags & MMC_DATA_READ)
871 mode |= SDHCI_TRNS_READ;
c9fddbc4 872 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 873 mode |= SDHCI_TRNS_DMA;
874
4e4141a5 875 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 876}
877
878static void sdhci_finish_data(struct sdhci_host *host)
879{
880 struct mmc_data *data;
d129bceb
PO		 881
882 BUG_ON(!host->data);
883
884 data = host->data;
885 host->data = NULL;
886
c9fddbc4 887 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 888 if (host->flags & SDHCI_USE_ADMA)
889 sdhci_adma_table_post(host, data);
890 else {
891 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
892 data->sg_len, (data->flags & MMC_DATA_READ) ?
893 DMA_FROM_DEVICE : DMA_TO_DEVICE);
894 }
d129bceb
PO		 895 }
896
897 /*
c9b74c5b
PO		 898 * The specification states that the block count register must
899 * be updated, but it does not specify at what point in the
900 * data flow. That makes the register entirely useless to read
901 * back so we have to assume that nothing made it to the card
902 * in the event of an error.
d129bceb 903 */
c9b74c5b
PO		 904 if (data->error)
905 data->bytes_xfered = 0;
d129bceb 906 else
c9b74c5b 907 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 908
e89d456f
AW		 909 /*
910 * Need to send CMD12 if -
911 * a) open-ended multiblock transfer (no CMD23)
912 * b) error in multiblock transfer
913 */
914 if (data->stop &&
915 (data->error ||
916 !host->mrq->sbc)) {
917
d129bceb
PO		 918 /*
919 * The controller needs a reset of internal state machines
920 * upon error conditions.
921 */
17b0429d 922 if (data->error) {
d129bceb
PO		 923 sdhci_reset(host, SDHCI_RESET_CMD);
924 sdhci_reset(host, SDHCI_RESET_DATA);
925 }
926
927 sdhci_send_command(host, data->stop);
928 } else
929 tasklet_schedule(&host->finish_tasklet);
930}
931
932static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
933{
934 int flags;
fd2208d7 935 u32 mask;
7cb2c76f 936 unsigned long timeout;
d129bceb
PO		 937
938 WARN_ON(host->cmd);
939
d129bceb 940 /* Wait max 10 ms */
7cb2c76f 941 timeout = 10;
fd2208d7
PO		 942
943 mask = SDHCI_CMD_INHIBIT;
944 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
945 mask |= SDHCI_DATA_INHIBIT;
946
947 /* We shouldn't wait for data inihibit for stop commands, even
948 though they might use busy signaling */
949 if (host->mrq->data && (cmd == host->mrq->data->stop))
950 mask &= ~SDHCI_DATA_INHIBIT;
951
4e4141a5 952 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 953 if (timeout == 0) {
d129bceb 954 printk(KERN_ERR "%s: Controller never released "
acf1da45 955 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 956 sdhci_dumpregs(host);
17b0429d 957 cmd->error = -EIO;
d129bceb
PO		 958 tasklet_schedule(&host->finish_tasklet);
959 return;
960 }
7cb2c76f
PO		 961 timeout--;
962 mdelay(1);
963 }
d129bceb
PO		 964
965 mod_timer(&host->timer, jiffies + 10 * HZ);
966
967 host->cmd = cmd;
968
a3c7778f 969 sdhci_prepare_data(host, cmd);
d129bceb 970
4e4141a5 971 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 972
e89d456f 973 sdhci_set_transfer_mode(host, cmd);
c7fa9963 974
d129bceb 975 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 976 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 977 mmc_hostname(host->mmc));
17b0429d 978 cmd->error = -EINVAL;
d129bceb
PO		 979 tasklet_schedule(&host->finish_tasklet);
980 return;
981 }
982
983 if (!(cmd->flags & MMC_RSP_PRESENT))
984 flags = SDHCI_CMD_RESP_NONE;
985 else if (cmd->flags & MMC_RSP_136)
986 flags = SDHCI_CMD_RESP_LONG;
987 else if (cmd->flags & MMC_RSP_BUSY)
988 flags = SDHCI_CMD_RESP_SHORT_BUSY;
989 else
990 flags = SDHCI_CMD_RESP_SHORT;
991
992 if (cmd->flags & MMC_RSP_CRC)
993 flags |= SDHCI_CMD_CRC;
994 if (cmd->flags & MMC_RSP_OPCODE)
995 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 996
997 /* CMD19 is special in that the Data Present Select should be set */
998 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
d129bceb
PO		 999 flags |= SDHCI_CMD_DATA;
1000
4e4141a5 1001 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1002}
1003
1004static void sdhci_finish_command(struct sdhci_host *host)
1005{
1006 int i;
1007
1008 BUG_ON(host->cmd == NULL);
1009
1010 if (host->cmd->flags & MMC_RSP_PRESENT) {
1011 if (host->cmd->flags & MMC_RSP_136) {
1012 /* CRC is stripped so we need to do some shifting. */
1013 for (i = 0;i < 4;i++) {
4e4141a5 1014 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1015 SDHCI_RESPONSE + (3-i)*4) << 8;
1016 if (i != 3)
1017 host->cmd->resp[i] |=
4e4141a5 1018 sdhci_readb(host,
d129bceb
PO		 1019 SDHCI_RESPONSE + (3-i)*4-1);
1020 }
1021 } else {
4e4141a5 1022 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1023 }
1024 }
1025
17b0429d 1026 host->cmd->error = 0;
d129bceb 1027
e89d456f
AW		 1028 /* Finished CMD23, now send actual command. */
1029 if (host->cmd == host->mrq->sbc) {
1030 host->cmd = NULL;
1031 sdhci_send_command(host, host->mrq->cmd);
1032 } else {
e538fbe8 1033
e89d456f
AW		 1034 /* Processed actual command. */
1035 if (host->data && host->data_early)
1036 sdhci_finish_data(host);
d129bceb 1037
e89d456f
AW		 1038 if (!host->cmd->data)
1039 tasklet_schedule(&host->finish_tasklet);
1040
1041 host->cmd = NULL;
1042 }
d129bceb
PO		 1043}
1044
1045static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1046{
c3ed3877
AN		 1047 int div = 0; /* Initialized for compiler warning */
1048 u16 clk = 0;
7cb2c76f 1049 unsigned long timeout;
d129bceb
PO		 1050
1051 if (clock == host->clock)
1052 return;
1053
8114634c
AV		 1054 if (host->ops->set_clock) {
1055 host->ops->set_clock(host, clock);
1056 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1057 return;
1058 }
1059
4e4141a5 1060 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1061
1062 if (clock == 0)
1063 goto out;
1064
85105c53 1065 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1066 /*
1067 * Check if the Host Controller supports Programmable Clock
1068 * Mode.
1069 */
1070 if (host->clk_mul) {
1071 u16 ctrl;
1072
1073 /*
1074 * We need to figure out whether the Host Driver needs
1075 * to select Programmable Clock Mode, or the value can
1076 * be set automatically by the Host Controller based on
1077 * the Preset Value registers.
1078 */
1079 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1080 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1081 for (div = 1; div <= 1024; div++) {
1082 if (((host->max_clk * host->clk_mul) /
1083 div) <= clock)
1084 break;
1085 }
1086 /*
1087 * Set Programmable Clock Mode in the Clock
1088 * Control register.
1089 */
1090 clk = SDHCI_PROG_CLOCK_MODE;
1091 div--;
1092 }
1093 } else {
1094 /* Version 3.00 divisors must be a multiple of 2. */
1095 if (host->max_clk <= clock)
1096 div = 1;
1097 else {
1098 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1099 div += 2) {
1100 if ((host->max_clk / div) <= clock)
1101 break;
1102 }
85105c53 1103 }
c3ed3877 1104 div >>= 1;
85105c53
ZG		 1105 }
1106 } else {
1107 /* Version 2.00 divisors must be a power of 2. */
0397526d 1108 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1109 if ((host->max_clk / div) <= clock)
1110 break;
1111 }
c3ed3877 1112 div >>= 1;
d129bceb 1113 }
d129bceb 1114
c3ed3877 1115 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1116 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1117 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1118 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1119 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1120
27f6cb16
CB		 1121 /* Wait max 20 ms */
1122 timeout = 20;
4e4141a5 1123 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1124 & SDHCI_CLOCK_INT_STABLE)) {
1125 if (timeout == 0) {
acf1da45
PO		 1126 printk(KERN_ERR "%s: Internal clock never "
1127 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1128 sdhci_dumpregs(host);
1129 return;
1130 }
7cb2c76f
PO		 1131 timeout--;
1132 mdelay(1);
1133 }
d129bceb
PO		 1134
1135 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1136 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1137
1138out:
1139 host->clock = clock;
1140}
1141
146ad66e
PO		 1142static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1143{
8364248a 1144 u8 pwr = 0;
146ad66e 1145
8364248a 1146 if (power != (unsigned short)-1) {
ae628903
PO		 1147 switch (1 << power) {
1148 case MMC_VDD_165_195:
1149 pwr = SDHCI_POWER_180;
1150 break;
1151 case MMC_VDD_29_30:
1152 case MMC_VDD_30_31:
1153 pwr = SDHCI_POWER_300;
1154 break;
1155 case MMC_VDD_32_33:
1156 case MMC_VDD_33_34:
1157 pwr = SDHCI_POWER_330;
1158 break;
1159 default:
1160 BUG();
1161 }
1162 }
1163
1164 if (host->pwr == pwr)
146ad66e
PO		 1165 return;
1166
ae628903
PO		 1167 host->pwr = pwr;
1168
1169 if (pwr == 0) {
4e4141a5 1170 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1171 return;
9e9dc5f2
DS		 1172 }
1173
1174 /*
1175 * Spec says that we should clear the power reg before setting
1176 * a new value. Some controllers don't seem to like this though.
1177 */
b8c86fc5 1178 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1179 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1180
e08c1694 1181 /*
c71f6512 1182 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1183 * and set turn on power at the same time, so set the voltage first.
1184 */
11a2f1b7 1185 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1186 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1187
ae628903 1188 pwr |= SDHCI_POWER_ON;
146ad66e 1189
ae628903 1190 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1191
1192 /*
1193 * Some controllers need an extra 10ms delay of 10ms before they
1194 * can apply clock after applying power
1195 */
11a2f1b7 1196 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1197 mdelay(10);
146ad66e
PO		 1198}
1199
d129bceb
PO		 1200/*****************************************************************************\
1201 * *
1202 * MMC callbacks *
1203 * *
1204\*****************************************************************************/
1205
1206static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1207{
1208 struct sdhci_host *host;
68d1fb7e 1209 bool present;
d129bceb
PO		 1210 unsigned long flags;
1211
1212 host = mmc_priv(mmc);
1213
1214 spin_lock_irqsave(&host->lock, flags);
1215
1216 WARN_ON(host->mrq != NULL);
1217
f9134319 1218#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1219 sdhci_activate_led(host);
2f730fec 1220#endif
e89d456f
AW		 1221
1222 /*
1223 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1224 * requests if Auto-CMD12 is enabled.
1225 */
1226 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1227 if (mrq->stop) {
1228 mrq->data->stop = NULL;
1229 mrq->stop = NULL;
1230 }
1231 }
d129bceb
PO		 1232
1233 host->mrq = mrq;
1234
68d1fb7e
AV		 1235 /* If polling, assume that the card is always present. */
1236 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1237 present = true;
1238 else
1239 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1240 SDHCI_CARD_PRESENT;
1241
1242 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1243 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1244 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1245 } else {
1246 u32 present_state;
1247
1248 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1249 /*
1250 * Check if the re-tuning timer has already expired and there
1251 * is no on-going data transfer. If so, we need to execute
1252 * tuning procedure before sending command.
1253 */
1254 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1255 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1256 spin_unlock_irqrestore(&host->lock, flags);
1257 sdhci_execute_tuning(mmc);
1258 spin_lock_irqsave(&host->lock, flags);
1259
1260 /* Restore original mmc_request structure */
1261 host->mrq = mrq;
1262 }
1263
8edf6371 1264 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1265 sdhci_send_command(host, mrq->sbc);
1266 else
1267 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1268 }
d129bceb 1269
5f25a66f 1270 mmiowb();
d129bceb
PO		 1271 spin_unlock_irqrestore(&host->lock, flags);
1272}
1273
1274static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1275{
1276 struct sdhci_host *host;
1277 unsigned long flags;
1278 u8 ctrl;
1279
1280 host = mmc_priv(mmc);
1281
1282 spin_lock_irqsave(&host->lock, flags);
1283
1e72859e
PO		 1284 if (host->flags & SDHCI_DEVICE_DEAD)
1285 goto out;
1286
d129bceb
PO		 1287 /*
1288 * Reset the chip on each power off.
1289 * Should clear out any weird states.
1290 */
1291 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1292 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1293 sdhci_reinit(host);
d129bceb
PO		 1294 }
1295
1296 sdhci_set_clock(host, ios->clock);
1297
1298 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1299 sdhci_set_power(host, -1);
d129bceb 1300 else
146ad66e 1301 sdhci_set_power(host, ios->vdd);
d129bceb 1302
643a81ff
PR		 1303 if (host->ops->platform_send_init_74_clocks)
1304 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1305
15ec4461
PR		 1306 /*
1307 * If your platform has 8-bit width support but is not a v3 controller,
1308 * or if it requires special setup code, you should implement that in
1309 * platform_8bit_width().
1310 */
1311 if (host->ops->platform_8bit_width)
1312 host->ops->platform_8bit_width(host, ios->bus_width);
1313 else {
1314 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1315 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1316 ctrl &= ~SDHCI_CTRL_4BITBUS;
1317 if (host->version >= SDHCI_SPEC_300)
1318 ctrl |= SDHCI_CTRL_8BITBUS;
1319 } else {
1320 if (host->version >= SDHCI_SPEC_300)
1321 ctrl &= ~SDHCI_CTRL_8BITBUS;
1322 if (ios->bus_width == MMC_BUS_WIDTH_4)
1323 ctrl |= SDHCI_CTRL_4BITBUS;
1324 else
1325 ctrl &= ~SDHCI_CTRL_4BITBUS;
1326 }
1327 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1328 }
ae6d6c92 1329
15ec4461 1330 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1331
3ab9c8da
PR		 1332 if ((ios->timing == MMC_TIMING_SD_HS ||
1333 ios->timing == MMC_TIMING_MMC_HS)
1334 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1335 ctrl |= SDHCI_CTRL_HISPD;
1336 else
1337 ctrl &= ~SDHCI_CTRL_HISPD;
1338
d6d50a15 1339 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1340 u16 clk, ctrl_2;
1341 unsigned int clock;
1342
1343 /* In case of UHS-I modes, set High Speed Enable */
1344 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1345 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1346 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1347 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1348 (ios->timing == MMC_TIMING_UHS_SDR12))
1349 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1350
1351 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1352 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1353 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1354 /*
1355 * We only need to set Driver Strength if the
1356 * preset value enable is not set.
1357 */
1358 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1359 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1360 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1361 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1362 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1363
1364 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1365 } else {
1366 /*
1367 * According to SDHC Spec v3.00, if the Preset Value
1368 * Enable in the Host Control 2 register is set, we
1369 * need to reset SD Clock Enable before changing High
1370 * Speed Enable to avoid generating clock gliches.
1371 */
758535c4
AN		 1372
1373 /* Reset SD Clock Enable */
1374 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1375 clk &= ~SDHCI_CLOCK_CARD_EN;
1376 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1377
1378 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1379
1380 /* Re-enable SD Clock */
1381 clock = host->clock;
1382 host->clock = 0;
1383 sdhci_set_clock(host, clock);
d6d50a15 1384 }
49c468fc 1385
49c468fc
AN		 1386
1387 /* Reset SD Clock Enable */
1388 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1389 clk &= ~SDHCI_CLOCK_CARD_EN;
1390 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1391
6322cdd0
PR		 1392 if (host->ops->set_uhs_signaling)
1393 host->ops->set_uhs_signaling(host, ios->timing);
1394 else {
1395 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1396 /* Select Bus Speed Mode for host */
1397 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1398 if (ios->timing == MMC_TIMING_UHS_SDR12)
1399 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1400 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1401 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1402 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1403 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1404 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1405 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1406 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1407 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1408 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1409 }
49c468fc
AN		 1410
1411 /* Re-enable SD Clock */
1412 clock = host->clock;
1413 host->clock = 0;
1414 sdhci_set_clock(host, clock);
758535c4
AN		 1415 } else
1416 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1417
b8352260
LD		 1418 /*
1419 * Some (ENE) controllers go apeshit on some ios operation,
1420 * signalling timeout and CRC errors even on CMD0. Resetting
1421 * it on each ios seems to solve the problem.
1422 */
b8c86fc5 1423 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1424 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1425
1e72859e 1426out:
5f25a66f 1427 mmiowb();
d129bceb
PO		 1428 spin_unlock_irqrestore(&host->lock, flags);
1429}
1430
82b0e23a 1431static int check_ro(struct sdhci_host *host)
d129bceb 1432{
d129bceb 1433 unsigned long flags;
2dfb579c 1434 int is_readonly;
d129bceb 1435
d129bceb
PO		 1436 spin_lock_irqsave(&host->lock, flags);
1437
1e72859e 1438 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1439 is_readonly = 0;
1440 else if (host->ops->get_ro)
1441 is_readonly = host->ops->get_ro(host);
1e72859e 1442 else
2dfb579c
WS		 1443 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1444 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1445
1446 spin_unlock_irqrestore(&host->lock, flags);
1447
2dfb579c
WS		 1448 /* This quirk needs to be replaced by a callback-function later */
1449 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1450 !is_readonly : is_readonly;
d129bceb
PO		 1451}
1452
82b0e23a
TI		 1453#define SAMPLE_COUNT 5
1454
1455static int sdhci_get_ro(struct mmc_host *mmc)
1456{
1457 struct sdhci_host *host;
1458 int i, ro_count;
1459
1460 host = mmc_priv(mmc);
1461
1462 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1463 return check_ro(host);
1464
1465 ro_count = 0;
1466 for (i = 0; i < SAMPLE_COUNT; i++) {
1467 if (check_ro(host)) {
1468 if (++ro_count > SAMPLE_COUNT / 2)
1469 return 1;
1470 }
1471 msleep(30);
1472 }
1473 return 0;
1474}
1475
f75979b7
PO		 1476static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1477{
1478 struct sdhci_host *host;
1479 unsigned long flags;
f75979b7
PO		 1480
1481 host = mmc_priv(mmc);
1482
1483 spin_lock_irqsave(&host->lock, flags);
1484
1e72859e
PO		 1485 if (host->flags & SDHCI_DEVICE_DEAD)
1486 goto out;
1487
f75979b7 1488 if (enable)
7260cf5e
AV		 1489 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1490 else
1491 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1492out:
f75979b7
PO		 1493 mmiowb();
1494
1495 spin_unlock_irqrestore(&host->lock, flags);
1496}
1497
f2119df6
AN		 1498static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1499 struct mmc_ios *ios)
1500{
1501 struct sdhci_host *host;
1502 u8 pwr;
1503 u16 clk, ctrl;
1504 u32 present_state;
1505
1506 host = mmc_priv(mmc);
1507
1508 /*
1509 * Signal Voltage Switching is only applicable for Host Controllers
1510 * v3.00 and above.
1511 */
1512 if (host->version < SDHCI_SPEC_300)
1513 return 0;
1514
1515 /*
1516 * We first check whether the request is to set signalling voltage
1517 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1518 */
1519 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1520 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1521 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1522 ctrl &= ~SDHCI_CTRL_VDD_180;
1523 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1524
1525 /* Wait for 5ms */
1526 usleep_range(5000, 5500);
1527
1528 /* 3.3V regulator output should be stable within 5 ms */
1529 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1530 if (!(ctrl & SDHCI_CTRL_VDD_180))
1531 return 0;
1532 else {
1533 printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1534 "signalling voltage failed\n");
1535 return -EIO;
1536 }
1537 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1538 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1539 /* Stop SDCLK */
1540 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1541 clk &= ~SDHCI_CLOCK_CARD_EN;
1542 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1543
1544 /* Check whether DAT[3:0] is 0000 */
1545 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1546 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1547 SDHCI_DATA_LVL_SHIFT)) {
1548 /*
1549 * Enable 1.8V Signal Enable in the Host Control2
1550 * register
1551 */
1552 ctrl |= SDHCI_CTRL_VDD_180;
1553 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1554
1555 /* Wait for 5ms */
1556 usleep_range(5000, 5500);
1557
1558 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1559 if (ctrl & SDHCI_CTRL_VDD_180) {
1560 /* Provide SDCLK again and wait for 1ms*/
1561 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1562 clk |= SDHCI_CLOCK_CARD_EN;
1563 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1564 usleep_range(1000, 1500);
1565
1566 /*
1567 * If DAT[3:0] level is 1111b, then the card
1568 * was successfully switched to 1.8V signaling.
1569 */
1570 present_state = sdhci_readl(host,
1571 SDHCI_PRESENT_STATE);
1572 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1573 SDHCI_DATA_LVL_MASK)
1574 return 0;
1575 }
1576 }
1577
1578 /*
1579 * If we are here, that means the switch to 1.8V signaling
1580 * failed. We power cycle the card, and retry initialization
1581 * sequence by setting S18R to 0.
1582 */
1583 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1584 pwr &= ~SDHCI_POWER_ON;
1585 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1586
1587 /* Wait for 1ms as per the spec */
1588 usleep_range(1000, 1500);
1589 pwr |= SDHCI_POWER_ON;
1590 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1591
1592 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1593 "voltage failed, retrying with S18R set to 0\n");
1594 return -EAGAIN;
1595 } else
1596 /* No signal voltage switch required */
1597 return 0;
1598}
1599
b513ea25
AN		 1600static int sdhci_execute_tuning(struct mmc_host *mmc)
1601{
1602 struct sdhci_host *host;
1603 u16 ctrl;
1604 u32 ier;
1605 int tuning_loop_counter = MAX_TUNING_LOOP;
1606 unsigned long timeout;
1607 int err = 0;
1608
1609 host = mmc_priv(mmc);
1610
1611 disable_irq(host->irq);
1612 spin_lock(&host->lock);
1613
1614 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1615
1616 /*
1617 * Host Controller needs tuning only in case of SDR104 mode
1618 * and for SDR50 mode when Use Tuning for SDR50 is set in
1619 * Capabilities register.
1620 */
1621 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1622 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1623 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1624 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1625 else {
1626 spin_unlock(&host->lock);
1627 enable_irq(host->irq);
1628 return 0;
1629 }
1630
1631 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1632
1633 /*
1634 * As per the Host Controller spec v3.00, tuning command
1635 * generates Buffer Read Ready interrupt, so enable that.
1636 *
1637 * Note: The spec clearly says that when tuning sequence
1638 * is being performed, the controller does not generate
1639 * interrupts other than Buffer Read Ready interrupt. But
1640 * to make sure we don't hit a controller bug, we _only_
1641 * enable Buffer Read Ready interrupt here.
1642 */
1643 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1644 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1645
1646 /*
1647 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1648 * of loops reaches 40 times or a timeout of 150ms occurs.
1649 */
1650 timeout = 150;
1651 do {
1652 struct mmc_command cmd = {0};
1653 struct mmc_request mrq = {0};
1654
1655 if (!tuning_loop_counter && !timeout)
1656 break;
1657
1658 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1659 cmd.arg = 0;
1660 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1661 cmd.retries = 0;
1662 cmd.data = NULL;
1663 cmd.error = 0;
1664
1665 mrq.cmd = &cmd;
1666 host->mrq = &mrq;
1667
1668 /*
1669 * In response to CMD19, the card sends 64 bytes of tuning
1670 * block to the Host Controller. So we set the block size
1671 * to 64 here.
1672 */
1673 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1674
1675 /*
1676 * The tuning block is sent by the card to the host controller.
1677 * So we set the TRNS_READ bit in the Transfer Mode register.
1678 * This also takes care of setting DMA Enable and Multi Block
1679 * Select in the same register to 0.
1680 */
1681 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1682
1683 sdhci_send_command(host, &cmd);
1684
1685 host->cmd = NULL;
1686 host->mrq = NULL;
1687
1688 spin_unlock(&host->lock);
1689 enable_irq(host->irq);
1690
1691 /* Wait for Buffer Read Ready interrupt */
1692 wait_event_interruptible_timeout(host->buf_ready_int,
1693 (host->tuning_done == 1),
1694 msecs_to_jiffies(50));
1695 disable_irq(host->irq);
1696 spin_lock(&host->lock);
1697
1698 if (!host->tuning_done) {
1699 printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1700 "Buffer Read Ready interrupt during tuning "
1701 "procedure, falling back to fixed sampling "
1702 "clock\n");
1703 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1704 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1705 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1706 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1707
1708 err = -EIO;
1709 goto out;
1710 }
1711
1712 host->tuning_done = 0;
1713
1714 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1715 tuning_loop_counter--;
1716 timeout--;
1717 mdelay(1);
1718 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1719
1720 /*
1721 * The Host Driver has exhausted the maximum number of loops allowed,
1722 * so use fixed sampling frequency.
1723 */
1724 if (!tuning_loop_counter || !timeout) {
1725 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1726 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1727 } else {
1728 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1729 printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1730 " failed, falling back to fixed sampling"
1731 " clock\n");
1732 err = -EIO;
1733 }
1734 }
1735
1736out:
cf2b5eea
AN		 1737 /*
1738 * If this is the very first time we are here, we start the retuning
1739 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1740 * flag won't be set, we check this condition before actually starting
1741 * the timer.
1742 */
1743 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1744 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1745 mod_timer(&host->tuning_timer, jiffies +
1746 host->tuning_count * HZ);
1747 /* Tuning mode 1 limits the maximum data length to 4MB */
1748 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1749 } else {
1750 host->flags &= ~SDHCI_NEEDS_RETUNING;
1751 /* Reload the new initial value for timer */
1752 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1753 mod_timer(&host->tuning_timer, jiffies +
1754 host->tuning_count * HZ);
1755 }
1756
1757 /*
1758 * In case tuning fails, host controllers which support re-tuning can
1759 * try tuning again at a later time, when the re-tuning timer expires.
1760 * So for these controllers, we return 0. Since there might be other
1761 * controllers who do not have this capability, we return error for
1762 * them.
1763 */
1764 if (err && host->tuning_count &&
1765 host->tuning_mode == SDHCI_TUNING_MODE_1)
1766 err = 0;
1767
b513ea25
AN		 1768 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1769 spin_unlock(&host->lock);
1770 enable_irq(host->irq);
1771
1772 return err;
1773}
1774
4d55c5a1
AN		 1775static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1776{
1777 struct sdhci_host *host;
1778 u16 ctrl;
1779 unsigned long flags;
1780
1781 host = mmc_priv(mmc);
1782
1783 /* Host Controller v3.00 defines preset value registers */
1784 if (host->version < SDHCI_SPEC_300)
1785 return;
1786
1787 spin_lock_irqsave(&host->lock, flags);
1788
1789 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1790
1791 /*
1792 * We only enable or disable Preset Value if they are not already
1793 * enabled or disabled respectively. Otherwise, we bail out.
1794 */
1795 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1796 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1797 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1798 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1799 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1800 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1801 }
1802
1803 spin_unlock_irqrestore(&host->lock, flags);
1804}
1805
ab7aefd0 1806static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1807 .request = sdhci_request,
1808 .set_ios = sdhci_set_ios,
1809 .get_ro = sdhci_get_ro,
f75979b7 1810 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1811 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1812 .execute_tuning = sdhci_execute_tuning,
4d55c5a1 1813 .enable_preset_value = sdhci_enable_preset_value,
d129bceb
PO		 1814};
1815
1816/*****************************************************************************\
1817 * *
1818 * Tasklets *
1819 * *
1820\*****************************************************************************/
1821
1822static void sdhci_tasklet_card(unsigned long param)
1823{
1824 struct sdhci_host *host;
1825 unsigned long flags;
1826
1827 host = (struct sdhci_host*)param;
1828
1829 spin_lock_irqsave(&host->lock, flags);
1830
4e4141a5 1831 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1832 if (host->mrq) {
1833 printk(KERN_ERR "%s: Card removed during transfer!\n",
1834 mmc_hostname(host->mmc));
1835 printk(KERN_ERR "%s: Resetting controller.\n",
1836 mmc_hostname(host->mmc));
1837
1838 sdhci_reset(host, SDHCI_RESET_CMD);
1839 sdhci_reset(host, SDHCI_RESET_DATA);
1840
17b0429d 1841 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1842 tasklet_schedule(&host->finish_tasklet);
1843 }
1844 }
1845
1846 spin_unlock_irqrestore(&host->lock, flags);
1847
04cf585d 1848 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1849}
1850
1851static void sdhci_tasklet_finish(unsigned long param)
1852{
1853 struct sdhci_host *host;
1854 unsigned long flags;
1855 struct mmc_request *mrq;
1856
1857 host = (struct sdhci_host*)param;
1858
0c9c99a7
CB		 1859 /*
1860 * If this tasklet gets rescheduled while running, it will
1861 * be run again afterwards but without any active request.
1862 */
1863 if (!host->mrq)
1864 return;
1865
d129bceb
PO		 1866 spin_lock_irqsave(&host->lock, flags);
1867
1868 del_timer(&host->timer);
1869
cf2b5eea
AN		 1870 if (host->version >= SDHCI_SPEC_300)
1871 del_timer(&host->tuning_timer);
1872
d129bceb
PO		 1873 mrq = host->mrq;
1874
d129bceb
PO		 1875 /*
1876 * The controller needs a reset of internal state machines
1877 * upon error conditions.
1878 */
1e72859e 1879 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1880 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1881 (mrq->data && (mrq->data->error ||
1882 (mrq->data->stop && mrq->data->stop->error))) ||
1883 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1884
1885 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1886 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1887 unsigned int clock;
1888
1889 /* This is to force an update */
1890 clock = host->clock;
1891 host->clock = 0;
1892 sdhci_set_clock(host, clock);
1893 }
1894
1895 /* Spec says we should do both at the same time, but Ricoh
1896 controllers do not like that. */
d129bceb
PO		 1897 sdhci_reset(host, SDHCI_RESET_CMD);
1898 sdhci_reset(host, SDHCI_RESET_DATA);
1899 }
1900
1901 host->mrq = NULL;
1902 host->cmd = NULL;
1903 host->data = NULL;
1904
f9134319 1905#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1906 sdhci_deactivate_led(host);
2f730fec 1907#endif
d129bceb 1908
5f25a66f 1909 mmiowb();
d129bceb
PO		 1910 spin_unlock_irqrestore(&host->lock, flags);
1911
1912 mmc_request_done(host->mmc, mrq);
1913}
1914
1915static void sdhci_timeout_timer(unsigned long data)
1916{
1917 struct sdhci_host *host;
1918 unsigned long flags;
1919
1920 host = (struct sdhci_host*)data;
1921
1922 spin_lock_irqsave(&host->lock, flags);
1923
1924 if (host->mrq) {
acf1da45
PO		 1925 printk(KERN_ERR "%s: Timeout waiting for hardware "
1926 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1927 sdhci_dumpregs(host);
1928
1929 if (host->data) {
17b0429d 1930 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1931 sdhci_finish_data(host);
1932 } else {
1933 if (host->cmd)
17b0429d 1934 host->cmd->error = -ETIMEDOUT;
d129bceb 1935 else
17b0429d 1936 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1937
1938 tasklet_schedule(&host->finish_tasklet);
1939 }
1940 }
1941
5f25a66f 1942 mmiowb();
d129bceb
PO		 1943 spin_unlock_irqrestore(&host->lock, flags);
1944}
1945
cf2b5eea
AN		 1946static void sdhci_tuning_timer(unsigned long data)
1947{
1948 struct sdhci_host *host;
1949 unsigned long flags;
1950
1951 host = (struct sdhci_host *)data;
1952
1953 spin_lock_irqsave(&host->lock, flags);
1954
1955 host->flags |= SDHCI_NEEDS_RETUNING;
1956
1957 spin_unlock_irqrestore(&host->lock, flags);
1958}
1959
d129bceb
PO		 1960/*****************************************************************************\
1961 * *
1962 * Interrupt handling *
1963 * *
1964\*****************************************************************************/
1965
1966static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1967{
1968 BUG_ON(intmask == 0);
1969
1970 if (!host->cmd) {
b67ac3f3
PO		 1971 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1972 "though no command operation was in progress.\n",
1973 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1974 sdhci_dumpregs(host);
1975 return;
1976 }
1977
43b58b36 1978 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1979 host->cmd->error = -ETIMEDOUT;
1980 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1981 SDHCI_INT_INDEX))
1982 host->cmd->error = -EILSEQ;
43b58b36 1983
e809517f 1984 if (host->cmd->error) {
d129bceb 1985 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1986 return;
1987 }
1988
1989 /*
1990 * The host can send and interrupt when the busy state has
1991 * ended, allowing us to wait without wasting CPU cycles.
1992 * Unfortunately this is overloaded on the "data complete"
1993 * interrupt, so we need to take some care when handling
1994 * it.
1995 *
1996 * Note: The 1.0 specification is a bit ambiguous about this
1997 * feature so there might be some problems with older
1998 * controllers.
1999 */
2000 if (host->cmd->flags & MMC_RSP_BUSY) {
2001 if (host->cmd->data)
2002 DBG("Cannot wait for busy signal when also "
2003 "doing a data transfer");
f945405c 2004 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2005 return;
f945405c
BD		 2006
2007 /* The controller does not support the end-of-busy IRQ,
2008 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2009 }
2010
2011 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2012 sdhci_finish_command(host);
d129bceb
PO		 2013}
2014
0957c333 2015#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2016static void sdhci_show_adma_error(struct sdhci_host *host)
2017{
2018 const char *name = mmc_hostname(host->mmc);
2019 u8 *desc = host->adma_desc;
2020 __le32 *dma;
2021 __le16 *len;
2022 u8 attr;
2023
2024 sdhci_dumpregs(host);
2025
2026 while (true) {
2027 dma = (__le32 *)(desc + 4);
2028 len = (__le16 *)(desc + 2);
2029 attr = *desc;
2030
2031 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2032 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2033
2034 desc += 8;
2035
2036 if (attr & 2)
2037 break;
2038 }
2039}
2040#else
2041static void sdhci_show_adma_error(struct sdhci_host *host) { }
2042#endif
2043
d129bceb
PO		 2044static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2045{
2046 BUG_ON(intmask == 0);
2047
b513ea25
AN		 2048 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2049 if (intmask & SDHCI_INT_DATA_AVAIL) {
2050 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2051 MMC_SEND_TUNING_BLOCK) {
2052 host->tuning_done = 1;
2053 wake_up(&host->buf_ready_int);
2054 return;
2055 }
2056 }
2057
d129bceb
PO		 2058 if (!host->data) {
2059 /*
e809517f
PO		 2060 * The "data complete" interrupt is also used to
2061 * indicate that a busy state has ended. See comment
2062 * above in sdhci_cmd_irq().
d129bceb 2063 */
e809517f
PO		 2064 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2065 if (intmask & SDHCI_INT_DATA_END) {
2066 sdhci_finish_command(host);
2067 return;
2068 }
2069 }
d129bceb 2070
b67ac3f3
PO		 2071 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2072 "though no data operation was in progress.\n",
2073 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2074 sdhci_dumpregs(host);
2075
2076 return;
2077 }
2078
2079 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2080 host->data->error = -ETIMEDOUT;
22113efd
AL		 2081 else if (intmask & SDHCI_INT_DATA_END_BIT)
2082 host->data->error = -EILSEQ;
2083 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2084 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2085 != MMC_BUS_TEST_R)
17b0429d 2086 host->data->error = -EILSEQ;
6882a8c0
BD		 2087 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2088 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2089 sdhci_show_adma_error(host);
2134a922 2090 host->data->error = -EIO;
6882a8c0 2091 }
d129bceb 2092
17b0429d 2093 if (host->data->error)
d129bceb
PO		 2094 sdhci_finish_data(host);
2095 else {
a406f5a3 2096 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2097 sdhci_transfer_pio(host);
2098
6ba736a1
PO		 2099 /*
2100 * We currently don't do anything fancy with DMA
2101 * boundaries, but as we can't disable the feature
2102 * we need to at least restart the transfer.
f6a03cbf
MV		 2103 *
2104 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2105 * should return a valid address to continue from, but as
2106 * some controllers are faulty, don't trust them.
6ba736a1 2107 */
f6a03cbf
MV		 2108 if (intmask & SDHCI_INT_DMA_END) {
2109 u32 dmastart, dmanow;
2110 dmastart = sg_dma_address(host->data->sg);
2111 dmanow = dmastart + host->data->bytes_xfered;
2112 /*
2113 * Force update to the next DMA block boundary.
2114 */
2115 dmanow = (dmanow &
2116 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2117 SDHCI_DEFAULT_BOUNDARY_SIZE;
2118 host->data->bytes_xfered = dmanow - dmastart;
2119 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2120 " next 0x%08x\n",
2121 mmc_hostname(host->mmc), dmastart,
2122 host->data->bytes_xfered, dmanow);
2123 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2124 }
6ba736a1 2125
e538fbe8
PO		 2126 if (intmask & SDHCI_INT_DATA_END) {
2127 if (host->cmd) {
2128 /*
2129 * Data managed to finish before the
2130 * command completed. Make sure we do
2131 * things in the proper order.
2132 */
2133 host->data_early = 1;
2134 } else {
2135 sdhci_finish_data(host);
2136 }
2137 }
d129bceb
PO		 2138 }
2139}
2140
7d12e780 2141static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2142{
2143 irqreturn_t result;
2144 struct sdhci_host* host = dev_id;
2145 u32 intmask;
f75979b7 2146 int cardint = 0;
d129bceb
PO		 2147
2148 spin_lock(&host->lock);
2149
4e4141a5 2150 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2151
62df67a5 2152 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2153 result = IRQ_NONE;
2154 goto out;
2155 }
2156
b69c9058
PO		 2157 DBG("*** %s got interrupt: 0x%08x\n",
2158 mmc_hostname(host->mmc), intmask);
d129bceb 2159
3192a28f 2160 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2161 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2162 SDHCI_CARD_PRESENT;
2163
2164 /*
2165 * There is a observation on i.mx esdhc. INSERT bit will be
2166 * immediately set again when it gets cleared, if a card is
2167 * inserted. We have to mask the irq to prevent interrupt
2168 * storm which will freeze the system. And the REMOVE gets
2169 * the same situation.
2170 *
2171 * More testing are needed here to ensure it works for other
2172 * platforms though.
2173 */
2174 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2175 SDHCI_INT_CARD_REMOVE);
2176 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2177 SDHCI_INT_CARD_INSERT);
2178
4e4141a5 2179 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2180 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2181 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2182 tasklet_schedule(&host->card_tasklet);
3192a28f 2183 }
d129bceb 2184
3192a28f 2185 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2186 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2187 SDHCI_INT_STATUS);
3192a28f 2188 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2189 }
2190
2191 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2192 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2193 SDHCI_INT_STATUS);
3192a28f 2194 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2195 }
2196
2197 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2198
964f9ce2
PO		 2199 intmask &= ~SDHCI_INT_ERROR;
2200
d129bceb 2201 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 2202 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 2203 mmc_hostname(host->mmc));
4e4141a5 2204 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2205 }
2206
9d26a5d3 2207 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2208
f75979b7
PO		 2209 if (intmask & SDHCI_INT_CARD_INT)
2210 cardint = 1;
2211
2212 intmask &= ~SDHCI_INT_CARD_INT;
2213
3192a28f 2214 if (intmask) {
acf1da45 2215 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 2216 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 2217 sdhci_dumpregs(host);
2218
4e4141a5 2219 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2220 }
d129bceb
PO		 2221
2222 result = IRQ_HANDLED;
2223
5f25a66f 2224 mmiowb();
d129bceb
PO		 2225out:
2226 spin_unlock(&host->lock);
2227
f75979b7
PO		 2228 /*
2229 * We have to delay this as it calls back into the driver.
2230 */
2231 if (cardint)
2232 mmc_signal_sdio_irq(host->mmc);
2233
d129bceb
PO		 2234 return result;
2235}
2236
2237/*****************************************************************************\
2238 * *
2239 * Suspend/resume *
2240 * *
2241\*****************************************************************************/
2242
2243#ifdef CONFIG_PM
2244
b8c86fc5 2245int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 2246{
b8c86fc5 2247 int ret;
a715dfc7 2248
7260cf5e
AV		 2249 sdhci_disable_card_detection(host);
2250
cf2b5eea
AN		 2251 /* Disable tuning since we are suspending */
2252 if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2253 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2254 host->flags &= ~SDHCI_NEEDS_RETUNING;
2255 mod_timer(&host->tuning_timer, jiffies +
2256 host->tuning_count * HZ);
2257 }
2258
1a13f8fa 2259 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 2260 if (ret)
2261 return ret;
a715dfc7 2262
b8c86fc5 2263 free_irq(host->irq, host);
d129bceb 2264
9bea3c85
MS		 2265 if (host->vmmc)
2266 ret = regulator_disable(host->vmmc);
2267
2268 return ret;
d129bceb
PO		 2269}
2270
b8c86fc5 2271EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2272
b8c86fc5
PO		 2273int sdhci_resume_host(struct sdhci_host *host)
2274{
2275 int ret;
d129bceb 2276
9bea3c85
MS		 2277 if (host->vmmc) {
2278 int ret = regulator_enable(host->vmmc);
2279 if (ret)
2280 return ret;
2281 }
2282
2283
a13abc7b 2284 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2285 if (host->ops->enable_dma)
2286 host->ops->enable_dma(host);
2287 }
d129bceb 2288
b8c86fc5
PO		 2289 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2290 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2291 if (ret)
2292 return ret;
d129bceb 2293
2f4cbb3d 2294 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 2295 mmiowb();
2296
2297 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2298 sdhci_enable_card_detection(host);
2299
cf2b5eea
AN		 2300 /* Set the re-tuning expiration flag */
2301 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2302 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2303 host->flags |= SDHCI_NEEDS_RETUNING;
2304
2f4cbb3d 2305 return ret;
d129bceb
PO		 2306}
2307
b8c86fc5 2308EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2309
5f619704
DD		 2310void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2311{
2312 u8 val;
2313 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2314 val |= SDHCI_WAKE_ON_INT;
2315 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2316}
2317
2318EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2319
d129bceb
PO		 2320#endif /* CONFIG_PM */
2321
2322/*****************************************************************************\
2323 * *
b8c86fc5 2324 * Device allocation/registration *
d129bceb
PO		 2325 * *
2326\*****************************************************************************/
2327
b8c86fc5
PO		 2328struct sdhci_host *sdhci_alloc_host(struct device *dev,
2329 size_t priv_size)
d129bceb 2330{
d129bceb
PO		 2331 struct mmc_host *mmc;
2332 struct sdhci_host *host;
2333
b8c86fc5 2334 WARN_ON(dev == NULL);
d129bceb 2335
b8c86fc5 2336 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2337 if (!mmc)
b8c86fc5 2338 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2339
2340 host = mmc_priv(mmc);
2341 host->mmc = mmc;
2342
b8c86fc5
PO		 2343 return host;
2344}
8a4da143 2345
b8c86fc5 2346EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2347
b8c86fc5
PO		 2348int sdhci_add_host(struct sdhci_host *host)
2349{
2350 struct mmc_host *mmc;
f2119df6
AN		 2351 u32 caps[2];
2352 u32 max_current_caps;
2353 unsigned int ocr_avail;
b8c86fc5 2354 int ret;
d129bceb 2355
b8c86fc5
PO		 2356 WARN_ON(host == NULL);
2357 if (host == NULL)
2358 return -EINVAL;
d129bceb 2359
b8c86fc5 2360 mmc = host->mmc;
d129bceb 2361
b8c86fc5
PO		 2362 if (debug_quirks)
2363 host->quirks = debug_quirks;
d129bceb 2364
d96649ed
PO		 2365 sdhci_reset(host, SDHCI_RESET_ALL);
2366
4e4141a5 2367 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2368 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2369 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2370 if (host->version > SDHCI_SPEC_300) {
4a965505 2371 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 2372 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2373 host->version);
4a965505
PO		 2374 }
2375
f2119df6 2376 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2377 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2378
f2119df6
AN		 2379 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2380 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2381
b8c86fc5 2382 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2383 host->flags |= SDHCI_USE_SDMA;
f2119df6 2384 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2385 DBG("Controller doesn't have SDMA capability\n");
67435274 2386 else
a13abc7b 2387 host->flags |= SDHCI_USE_SDMA;
d129bceb 2388
b8c86fc5 2389 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2390 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2391 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2392 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2393 }
2394
f2119df6
AN		 2395 if ((host->version >= SDHCI_SPEC_200) &&
2396 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2397 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2398
2399 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2400 (host->flags & SDHCI_USE_ADMA)) {
2401 DBG("Disabling ADMA as it is marked broken\n");
2402 host->flags &= ~SDHCI_USE_ADMA;
2403 }
2404
a13abc7b 2405 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2406 if (host->ops->enable_dma) {
2407 if (host->ops->enable_dma(host)) {
2408 printk(KERN_WARNING "%s: No suitable DMA "
2409 "available. Falling back to PIO.\n",
2410 mmc_hostname(mmc));
a13abc7b
RR		 2411 host->flags &=
2412 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2413 }
d129bceb
PO		 2414 }
2415 }
2416
2134a922
PO		 2417 if (host->flags & SDHCI_USE_ADMA) {
2418 /*
2419 * We need to allocate descriptors for all sg entries
2420 * (128) and potentially one alignment transfer for
2421 * each of those entries.
2422 */
2423 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2424 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2425 if (!host->adma_desc || !host->align_buffer) {
2426 kfree(host->adma_desc);
2427 kfree(host->align_buffer);
2428 printk(KERN_WARNING "%s: Unable to allocate ADMA "
2429 "buffers. Falling back to standard DMA.\n",
2430 mmc_hostname(mmc));
2431 host->flags &= ~SDHCI_USE_ADMA;
2432 }
2433 }
2434
7659150c
PO		 2435 /*
2436 * If we use DMA, then it's up to the caller to set the DMA
2437 * mask, but PIO does not need the hw shim so we set a new
2438 * mask here in that case.
2439 */
a13abc7b 2440 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2441 host->dma_mask = DMA_BIT_MASK(64);
2442 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2443 }
d129bceb 2444
c4687d5f 2445 if (host->version >= SDHCI_SPEC_300)
f2119df6 2446 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2447 >> SDHCI_CLOCK_BASE_SHIFT;
2448 else
f2119df6 2449 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2450 >> SDHCI_CLOCK_BASE_SHIFT;
2451
4240ff0a 2452 host->max_clk *= 1000000;
f27f47ef
AV		 2453 if (host->max_clk == 0 || host->quirks &
2454 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a
BD		 2455 if (!host->ops->get_max_clock) {
2456 printk(KERN_ERR
2457 "%s: Hardware doesn't specify base clock "
2458 "frequency.\n", mmc_hostname(mmc));
2459 return -ENODEV;
2460 }
2461 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2462 }
d129bceb 2463
1c8cde92 2464 host->timeout_clk =
f2119df6 2465 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1c8cde92 2466 if (host->timeout_clk == 0) {
81b39802
AV		 2467 if (host->ops->get_timeout_clock) {
2468 host->timeout_clk = host->ops->get_timeout_clock(host);
2469 } else if (!(host->quirks &
2470 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4240ff0a
BD		 2471 printk(KERN_ERR
2472 "%s: Hardware doesn't specify timeout clock "
2473 "frequency.\n", mmc_hostname(mmc));
2474 return -ENODEV;
2475 }
1c8cde92 2476 }
f2119df6 2477 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
1c8cde92 2478 host->timeout_clk *= 1000;
d129bceb 2479
c3ed3877
AN		 2480 /*
2481 * In case of Host Controller v3.00, find out whether clock
2482 * multiplier is supported.
2483 */
2484 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2485 SDHCI_CLOCK_MUL_SHIFT;
2486
2487 /*
2488 * In case the value in Clock Multiplier is 0, then programmable
2489 * clock mode is not supported, otherwise the actual clock
2490 * multiplier is one more than the value of Clock Multiplier
2491 * in the Capabilities Register.
2492 */
2493 if (host->clk_mul)
2494 host->clk_mul += 1;
2495
d129bceb
PO		 2496 /*
2497 * Set host parameters.
2498 */
2499 mmc->ops = &sdhci_ops;
c3ed3877 2500 mmc->f_max = host->max_clk;
ce5f036b 2501 if (host->ops->get_min_clock)
a9e58f25 2502 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2503 else if (host->version >= SDHCI_SPEC_300) {
2504 if (host->clk_mul) {
2505 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2506 mmc->f_max = host->max_clk * host->clk_mul;
2507 } else
2508 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2509 } else
0397526d 2510 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2511
e89d456f
AW		 2512 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2513
2514 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2515 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2516
8edf6371 2517 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2518 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2519 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2520 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2521 host->flags |= SDHCI_AUTO_CMD23;
2522 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2523 } else {
2524 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2525 }
2526
15ec4461
PR		 2527 /*
2528 * A controller may support 8-bit width, but the board itself
2529 * might not have the pins brought out. Boards that support
2530 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2531 * their platform code before calling sdhci_add_host(), and we
2532 * won't assume 8-bit width for hosts without that CAP.
2533 */
5fe23c7f 2534 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2535 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2536
f2119df6 2537 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2538 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2539
176d1ed4
JC		 2540 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2541 mmc_card_is_removable(mmc))
68d1fb7e
AV		 2542 mmc->caps |= MMC_CAP_NEEDS_POLL;
2543
f2119df6
AN		 2544 /* UHS-I mode(s) supported by the host controller. */
2545 if (host->version >= SDHCI_SPEC_300)
2546 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2547
2548 /* SDR104 supports also implies SDR50 support */
2549 if (caps[1] & SDHCI_SUPPORT_SDR104)
2550 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2551 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2552 mmc->caps |= MMC_CAP_UHS_SDR50;
2553
2554 if (caps[1] & SDHCI_SUPPORT_DDR50)
2555 mmc->caps |= MMC_CAP_UHS_DDR50;
2556
b513ea25
AN		 2557 /* Does the host needs tuning for SDR50? */
2558 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2559 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2560
d6d50a15
AN		 2561 /* Driver Type(s) (A, C, D) supported by the host */
2562 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2563 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2564 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2565 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2566 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2567 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2568
cf2b5eea
AN		 2569 /* Initial value for re-tuning timer count */
2570 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2571 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2572
2573 /*
2574 * In case Re-tuning Timer is not disabled, the actual value of
2575 * re-tuning timer will be 2 ^ (n - 1).
2576 */
2577 if (host->tuning_count)
2578 host->tuning_count = 1 << (host->tuning_count - 1);
2579
2580 /* Re-tuning mode supported by the Host Controller */
2581 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2582 SDHCI_RETUNING_MODE_SHIFT;
2583
8f230f45 2584 ocr_avail = 0;
f2119df6
AN		 2585 /*
2586 * According to SD Host Controller spec v3.00, if the Host System
2587 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2588 * the value is meaningful only if Voltage Support in the Capabilities
2589 * register is set. The actual current value is 4 times the register
2590 * value.
2591 */
2592 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2593
2594 if (caps[0] & SDHCI_CAN_VDD_330) {
2595 int max_current_330;
2596
8f230f45 2597 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6
AN		 2598
2599 max_current_330 = ((max_current_caps &
2600 SDHCI_MAX_CURRENT_330_MASK) >>
2601 SDHCI_MAX_CURRENT_330_SHIFT) *
2602 SDHCI_MAX_CURRENT_MULTIPLIER;
2603
2604 if (max_current_330 > 150)
2605 mmc->caps |= MMC_CAP_SET_XPC_330;
2606 }
2607 if (caps[0] & SDHCI_CAN_VDD_300) {
2608 int max_current_300;
2609
8f230f45 2610 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6
AN		 2611
2612 max_current_300 = ((max_current_caps &
2613 SDHCI_MAX_CURRENT_300_MASK) >>
2614 SDHCI_MAX_CURRENT_300_SHIFT) *
2615 SDHCI_MAX_CURRENT_MULTIPLIER;
2616
2617 if (max_current_300 > 150)
2618 mmc->caps |= MMC_CAP_SET_XPC_300;
2619 }
2620 if (caps[0] & SDHCI_CAN_VDD_180) {
2621 int max_current_180;
2622
8f230f45
TI		 2623 ocr_avail |= MMC_VDD_165_195;
2624
f2119df6
AN		 2625 max_current_180 = ((max_current_caps &
2626 SDHCI_MAX_CURRENT_180_MASK) >>
2627 SDHCI_MAX_CURRENT_180_SHIFT) *
2628 SDHCI_MAX_CURRENT_MULTIPLIER;
2629
2630 if (max_current_180 > 150)
2631 mmc->caps |= MMC_CAP_SET_XPC_180;
5371c927
AN		 2632
2633 /* Maximum current capabilities of the host at 1.8V */
2634 if (max_current_180 >= 800)
2635 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2636 else if (max_current_180 >= 600)
2637 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2638 else if (max_current_180 >= 400)
2639 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2640 else
2641 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
f2119df6
AN		 2642 }
2643
8f230f45
TI		 2644 mmc->ocr_avail = ocr_avail;
2645 mmc->ocr_avail_sdio = ocr_avail;
2646 if (host->ocr_avail_sdio)
2647 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2648 mmc->ocr_avail_sd = ocr_avail;
2649 if (host->ocr_avail_sd)
2650 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2651 else /* normal SD controllers don't support 1.8V */
2652 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2653 mmc->ocr_avail_mmc = ocr_avail;
2654 if (host->ocr_avail_mmc)
2655 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2656
2657 if (mmc->ocr_avail == 0) {
2658 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 2659 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2660 return -ENODEV;
146ad66e
PO		 2661 }
2662
d129bceb
PO		 2663 spin_lock_init(&host->lock);
2664
2665 /*
2134a922
PO		 2666 * Maximum number of segments. Depends on if the hardware
2667 * can do scatter/gather or not.
d129bceb 2668 */
2134a922 2669 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2670 mmc->max_segs = 128;
a13abc7b 2671 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2672 mmc->max_segs = 1;
2134a922 2673 else /* PIO */
a36274e0 2674 mmc->max_segs = 128;
d129bceb
PO		 2675
2676 /*
bab76961 2677 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2678 * size (512KiB).
d129bceb 2679 */
55db890a 2680 mmc->max_req_size = 524288;
d129bceb
PO		 2681
2682 /*
2683 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2684 * of bytes. When doing hardware scatter/gather, each entry cannot
2685 * be larger than 64 KiB though.
d129bceb 2686 */
30652aa3
OJ		 2687 if (host->flags & SDHCI_USE_ADMA) {
2688 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2689 mmc->max_seg_size = 65535;
2690 else
2691 mmc->max_seg_size = 65536;
2692 } else {
2134a922 2693 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2694 }
d129bceb 2695
fe4a3c7a
PO		 2696 /*
2697 * Maximum block size. This varies from controller to controller and
2698 * is specified in the capabilities register.
2699 */
0633f654
AV		 2700 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2701 mmc->max_blk_size = 2;
2702 } else {
f2119df6 2703 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2704 SDHCI_MAX_BLOCK_SHIFT;
2705 if (mmc->max_blk_size >= 3) {
2706 printk(KERN_WARNING "%s: Invalid maximum block size, "
2707 "assuming 512 bytes\n", mmc_hostname(mmc));
2708 mmc->max_blk_size = 0;
2709 }
2710 }
2711
2712 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 2713
55db890a
PO		 2714 /*
2715 * Maximum block count.
2716 */
1388eefd 2717 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 2718
d129bceb
PO		 2719 /*
2720 * Init tasklets.
2721 */
2722 tasklet_init(&host->card_tasklet,
2723 sdhci_tasklet_card, (unsigned long)host);
2724 tasklet_init(&host->finish_tasklet,
2725 sdhci_tasklet_finish, (unsigned long)host);
2726
e4cad1b5 2727 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2728
cf2b5eea 2729 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 2730 init_waitqueue_head(&host->buf_ready_int);
2731
cf2b5eea
AN		 2732 /* Initialize re-tuning timer */
2733 init_timer(&host->tuning_timer);
2734 host->tuning_timer.data = (unsigned long)host;
2735 host->tuning_timer.function = sdhci_tuning_timer;
2736 }
2737
dace1453 2738 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2739 mmc_hostname(mmc), host);
d129bceb 2740 if (ret)
8ef1a143 2741 goto untasklet;
d129bceb 2742
9bea3c85
MS		 2743 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2744 if (IS_ERR(host->vmmc)) {
2745 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2746 host->vmmc = NULL;
2747 } else {
2748 regulator_enable(host->vmmc);
2749 }
2750
2f4cbb3d 2751 sdhci_init(host, 0);
d129bceb
PO		 2752
2753#ifdef CONFIG_MMC_DEBUG
2754 sdhci_dumpregs(host);
2755#endif
2756
f9134319 2757#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2758 snprintf(host->led_name, sizeof(host->led_name),
2759 "%s::", mmc_hostname(mmc));
2760 host->led.name = host->led_name;
2f730fec
PO		 2761 host->led.brightness = LED_OFF;
2762 host->led.default_trigger = mmc_hostname(mmc);
2763 host->led.brightness_set = sdhci_led_control;
2764
b8c86fc5 2765 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2766 if (ret)
2767 goto reset;
2768#endif
2769
5f25a66f
PO		 2770 mmiowb();
2771
d129bceb
PO		 2772 mmc_add_host(mmc);
2773
a13abc7b 2774 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2775 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2776 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2777 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2778
7260cf5e
AV		 2779 sdhci_enable_card_detection(host);
2780
d129bceb
PO		 2781 return 0;
2782
f9134319 2783#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2784reset:
2785 sdhci_reset(host, SDHCI_RESET_ALL);
2786 free_irq(host->irq, host);
2787#endif
8ef1a143 2788untasklet:
d129bceb
PO		 2789 tasklet_kill(&host->card_tasklet);
2790 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2791
2792 return ret;
2793}
2794
b8c86fc5 2795EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2796
1e72859e 2797void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2798{
1e72859e
PO		 2799 unsigned long flags;
2800
2801 if (dead) {
2802 spin_lock_irqsave(&host->lock, flags);
2803
2804 host->flags |= SDHCI_DEVICE_DEAD;
2805
2806 if (host->mrq) {
2807 printk(KERN_ERR "%s: Controller removed during "
2808 " transfer!\n", mmc_hostname(host->mmc));
2809
2810 host->mrq->cmd->error = -ENOMEDIUM;
2811 tasklet_schedule(&host->finish_tasklet);
2812 }
2813
2814 spin_unlock_irqrestore(&host->lock, flags);
2815 }
2816
7260cf5e
AV		 2817 sdhci_disable_card_detection(host);
2818
b8c86fc5 2819 mmc_remove_host(host->mmc);
d129bceb 2820
f9134319 2821#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2822 led_classdev_unregister(&host->led);
2823#endif
2824
1e72859e
PO		 2825 if (!dead)
2826 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 2827
2828 free_irq(host->irq, host);
2829
2830 del_timer_sync(&host->timer);
cf2b5eea
AN		 2831 if (host->version >= SDHCI_SPEC_300)
2832 del_timer_sync(&host->tuning_timer);
d129bceb
PO		 2833
2834 tasklet_kill(&host->card_tasklet);
2835 tasklet_kill(&host->finish_tasklet);
2134a922 2836
9bea3c85
MS		 2837 if (host->vmmc) {
2838 regulator_disable(host->vmmc);
2839 regulator_put(host->vmmc);
2840 }
2841
2134a922
PO		 2842 kfree(host->adma_desc);
2843 kfree(host->align_buffer);
2844
2845 host->adma_desc = NULL;
2846 host->align_buffer = NULL;
d129bceb
PO		 2847}
2848
b8c86fc5 2849EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 2850
b8c86fc5 2851void sdhci_free_host(struct sdhci_host *host)
d129bceb 2852{
b8c86fc5 2853 mmc_free_host(host->mmc);
d129bceb
PO		 2854}
2855
b8c86fc5 2856EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 2857
2858/*****************************************************************************\
2859 * *
2860 * Driver init/exit *
2861 * *
2862\*****************************************************************************/
2863
2864static int __init sdhci_drv_init(void)
2865{
2866 printk(KERN_INFO DRIVER_NAME
52fbf9c9 2867 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 2868 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2869
b8c86fc5 2870 return 0;
d129bceb
PO		 2871}
2872
2873static void __exit sdhci_drv_exit(void)
2874{
d129bceb
PO		 2875}
2876
2877module_init(sdhci_drv_init);
2878module_exit(sdhci_drv_exit);
2879
df673b22 2880module_param(debug_quirks, uint, 0444);
67435274 2881
32710e8f 2882MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 2883MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 2884MODULE_LICENSE("GPL");
67435274 2885
df673b22 2886MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux kernel - Deliverables
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