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mmc: core: Block CMD23 support for UHS104/SDXC cards.
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
9bea3c85 22#include <linux/regulator/consumer.h>
d129bceb 23
2f730fec
PO		 24#include <linux/leds.h>
25
22113efd 26#include <linux/mmc/mmc.h>
d129bceb 27#include <linux/mmc/host.h>
d129bceb 28
d129bceb
PO		 29#include "sdhci.h"
30
31#define DRIVER_NAME "sdhci"
d129bceb 32
d129bceb 33#define DBG(f, x...) \
c6563178 34 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 35
f9134319
PO		 36#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
37 defined(CONFIG_MMC_SDHCI_MODULE))
38#define SDHCI_USE_LEDS_CLASS
39#endif
40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
67435274 44
d129bceb
PO		 45static void sdhci_finish_data(struct sdhci_host *);
46
47static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
48static void sdhci_finish_command(struct sdhci_host *);
cf2b5eea
AN		 49static int sdhci_execute_tuning(struct mmc_host *mmc);
50static void sdhci_tuning_timer(unsigned long data);
d129bceb
PO		 51
52static void sdhci_dumpregs(struct sdhci_host *host)
53{
412ab659
PR		 54 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
55 mmc_hostname(host->mmc));
d129bceb
PO		 56
57 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 58 sdhci_readl(host, SDHCI_DMA_ADDRESS),
59 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 60 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 61 sdhci_readw(host, SDHCI_BLOCK_SIZE),
62 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 63 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 64 sdhci_readl(host, SDHCI_ARGUMENT),
65 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 66 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 67 sdhci_readl(host, SDHCI_PRESENT_STATE),
68 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 69 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 70 sdhci_readb(host, SDHCI_POWER_CONTROL),
71 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 72 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 73 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
74 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 75 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 76 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
77 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 78 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 79 sdhci_readl(host, SDHCI_INT_ENABLE),
80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 81 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 82 sdhci_readw(host, SDHCI_ACMD12_ERR),
83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
e8120ad1 84 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 85 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1
PR		 86 sdhci_readl(host, SDHCI_CAPABILITIES_1));
87 printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
88 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 89 sdhci_readl(host, SDHCI_MAX_CURRENT));
f2119df6
AN		 90 printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
91 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 92
be3f4ae0
BD		 93 if (host->flags & SDHCI_USE_ADMA)
94 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
95 readl(host->ioaddr + SDHCI_ADMA_ERROR),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
97
d129bceb
PO		 98 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
99}
100
101/*****************************************************************************\
102 * *
103 * Low level functions *
104 * *
105\*****************************************************************************/
106
7260cf5e
AV		 107static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
108{
109 u32 ier;
110
111 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
112 ier &= ~clear;
113 ier |= set;
114 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
115 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
116}
117
118static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
119{
120 sdhci_clear_set_irqs(host, 0, irqs);
121}
122
123static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
124{
125 sdhci_clear_set_irqs(host, irqs, 0);
126}
127
128static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
129{
130 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
131
68d1fb7e
AV		 132 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
133 return;
134
7260cf5e
AV		 135 if (enable)
136 sdhci_unmask_irqs(host, irqs);
137 else
138 sdhci_mask_irqs(host, irqs);
139}
140
141static void sdhci_enable_card_detection(struct sdhci_host *host)
142{
143 sdhci_set_card_detection(host, true);
144}
145
146static void sdhci_disable_card_detection(struct sdhci_host *host)
147{
148 sdhci_set_card_detection(host, false);
149}
150
d129bceb
PO		 151static void sdhci_reset(struct sdhci_host *host, u8 mask)
152{
e16514d8 153 unsigned long timeout;
063a9dbb 154 u32 uninitialized_var(ier);
e16514d8 155
b8c86fc5 156 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 157 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 158 SDHCI_CARD_PRESENT))
159 return;
160 }
161
063a9dbb
AV		 162 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
163 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
164
393c1a34
PR		 165 if (host->ops->platform_reset_enter)
166 host->ops->platform_reset_enter(host, mask);
167
4e4141a5 168 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 169
e16514d8 170 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 171 host->clock = 0;
172
e16514d8
PO		 173 /* Wait max 100 ms */
174 timeout = 100;
175
176 /* hw clears the bit when it's done */
4e4141a5 177 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 178 if (timeout == 0) {
acf1da45 179 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 180 mmc_hostname(host->mmc), (int)mask);
181 sdhci_dumpregs(host);
182 return;
183 }
184 timeout--;
185 mdelay(1);
d129bceb 186 }
063a9dbb 187
393c1a34
PR		 188 if (host->ops->platform_reset_exit)
189 host->ops->platform_reset_exit(host, mask);
190
063a9dbb
AV		 191 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
192 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 193}
194
2f4cbb3d
NP		 195static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
196
197static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 198{
2f4cbb3d
NP		 199 if (soft)
200 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
201 else
202 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 203
7260cf5e
AV		 204 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
205 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 206 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
207 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 208 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 209
210 if (soft) {
211 /* force clock reconfiguration */
212 host->clock = 0;
213 sdhci_set_ios(host->mmc, &host->mmc->ios);
214 }
7260cf5e 215}
d129bceb 216
7260cf5e
AV		 217static void sdhci_reinit(struct sdhci_host *host)
218{
2f4cbb3d 219 sdhci_init(host, 0);
7260cf5e 220 sdhci_enable_card_detection(host);
d129bceb
PO		 221}
222
223static void sdhci_activate_led(struct sdhci_host *host)
224{
225 u8 ctrl;
226
4e4141a5 227 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 228 ctrl |= SDHCI_CTRL_LED;
4e4141a5 229 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 230}
231
232static void sdhci_deactivate_led(struct sdhci_host *host)
233{
234 u8 ctrl;
235
4e4141a5 236 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 237 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 238 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 239}
240
f9134319 241#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 242static void sdhci_led_control(struct led_classdev *led,
243 enum led_brightness brightness)
244{
245 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
246 unsigned long flags;
247
248 spin_lock_irqsave(&host->lock, flags);
249
250 if (brightness == LED_OFF)
251 sdhci_deactivate_led(host);
252 else
253 sdhci_activate_led(host);
254
255 spin_unlock_irqrestore(&host->lock, flags);
256}
257#endif
258
d129bceb
PO		 259/*****************************************************************************\
260 * *
261 * Core functions *
262 * *
263\*****************************************************************************/
264
a406f5a3 265static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 266{
7659150c
PO		 267 unsigned long flags;
268 size_t blksize, len, chunk;
7244b85b 269 u32 uninitialized_var(scratch);
7659150c 270 u8 *buf;
d129bceb 271
a406f5a3 272 DBG("PIO reading\n");
d129bceb 273
a406f5a3 274 blksize = host->data->blksz;
7659150c 275 chunk = 0;
d129bceb 276
7659150c 277 local_irq_save(flags);
d129bceb 278
a406f5a3 279 while (blksize) {
7659150c
PO		 280 if (!sg_miter_next(&host->sg_miter))
281 BUG();
d129bceb 282
7659150c 283 len = min(host->sg_miter.length, blksize);
d129bceb 284
7659150c
PO		 285 blksize -= len;
286 host->sg_miter.consumed = len;
14d836e7 287
7659150c 288 buf = host->sg_miter.addr;
d129bceb 289
7659150c
PO		 290 while (len) {
291 if (chunk == 0) {
4e4141a5 292 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 293 chunk = 4;
a406f5a3 294 }
7659150c
PO		 295
296 *buf = scratch & 0xFF;
297
298 buf++;
299 scratch >>= 8;
300 chunk--;
301 len--;
d129bceb 302 }
a406f5a3 303 }
7659150c
PO		 304
305 sg_miter_stop(&host->sg_miter);
306
307 local_irq_restore(flags);
a406f5a3 308}
d129bceb 309
a406f5a3
PO		 310static void sdhci_write_block_pio(struct sdhci_host *host)
311{
7659150c
PO		 312 unsigned long flags;
313 size_t blksize, len, chunk;
314 u32 scratch;
315 u8 *buf;
d129bceb 316
a406f5a3
PO		 317 DBG("PIO writing\n");
318
319 blksize = host->data->blksz;
7659150c
PO		 320 chunk = 0;
321 scratch = 0;
d129bceb 322
7659150c 323 local_irq_save(flags);
d129bceb 324
a406f5a3 325 while (blksize) {
7659150c
PO		 326 if (!sg_miter_next(&host->sg_miter))
327 BUG();
a406f5a3 328
7659150c
PO		 329 len = min(host->sg_miter.length, blksize);
330
331 blksize -= len;
332 host->sg_miter.consumed = len;
333
334 buf = host->sg_miter.addr;
d129bceb 335
7659150c
PO		 336 while (len) {
337 scratch |= (u32)*buf << (chunk * 8);
338
339 buf++;
340 chunk++;
341 len--;
342
343 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 344 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 345 chunk = 0;
346 scratch = 0;
d129bceb 347 }
d129bceb
PO		 348 }
349 }
7659150c
PO		 350
351 sg_miter_stop(&host->sg_miter);
352
353 local_irq_restore(flags);
a406f5a3
PO		 354}
355
356static void sdhci_transfer_pio(struct sdhci_host *host)
357{
358 u32 mask;
359
360 BUG_ON(!host->data);
361
7659150c 362 if (host->blocks == 0)
a406f5a3
PO		 363 return;
364
365 if (host->data->flags & MMC_DATA_READ)
366 mask = SDHCI_DATA_AVAILABLE;
367 else
368 mask = SDHCI_SPACE_AVAILABLE;
369
4a3cba32
PO		 370 /*
371 * Some controllers (JMicron JMB38x) mess up the buffer bits
372 * for transfers < 4 bytes. As long as it is just one block,
373 * we can ignore the bits.
374 */
375 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
376 (host->data->blocks == 1))
377 mask = ~0;
378
4e4141a5 379 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 380 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
381 udelay(100);
382
a406f5a3
PO		 383 if (host->data->flags & MMC_DATA_READ)
384 sdhci_read_block_pio(host);
385 else
386 sdhci_write_block_pio(host);
d129bceb 387
7659150c
PO		 388 host->blocks--;
389 if (host->blocks == 0)
a406f5a3 390 break;
a406f5a3 391 }
d129bceb 392
a406f5a3 393 DBG("PIO transfer complete.\n");
d129bceb
PO		 394}
395
2134a922
PO		 396static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
397{
398 local_irq_save(*flags);
399 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
400}
401
402static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
403{
404 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
405 local_irq_restore(*flags);
406}
407
118cd17d
BD		 408static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
409{
9e506f35
BD		 410 __le32 *dataddr = (__le32 __force *)(desc + 4);
411 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 412
9e506f35
BD		 413 /* SDHCI specification says ADMA descriptors should be 4 byte
414 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 415
9e506f35
BD		 416 cmdlen[0] = cpu_to_le16(cmd);
417 cmdlen[1] = cpu_to_le16(len);
418
419 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 420}
421
8f1934ce 422static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 423 struct mmc_data *data)
424{
425 int direction;
426
427 u8 *desc;
428 u8 *align;
429 dma_addr_t addr;
430 dma_addr_t align_addr;
431 int len, offset;
432
433 struct scatterlist *sg;
434 int i;
435 char *buffer;
436 unsigned long flags;
437
438 /*
439 * The spec does not specify endianness of descriptor table.
440 * We currently guess that it is LE.
441 */
442
443 if (data->flags & MMC_DATA_READ)
444 direction = DMA_FROM_DEVICE;
445 else
446 direction = DMA_TO_DEVICE;
447
448 /*
449 * The ADMA descriptor table is mapped further down as we
450 * need to fill it with data first.
451 */
452
453 host->align_addr = dma_map_single(mmc_dev(host->mmc),
454 host->align_buffer, 128 * 4, direction);
8d8bb39b 455 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 456 goto fail;
2134a922
PO		 457 BUG_ON(host->align_addr & 0x3);
458
459 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
460 data->sg, data->sg_len, direction);
8f1934ce
PO		 461 if (host->sg_count == 0)
462 goto unmap_align;
2134a922
PO		 463
464 desc = host->adma_desc;
465 align = host->align_buffer;
466
467 align_addr = host->align_addr;
468
469 for_each_sg(data->sg, sg, host->sg_count, i) {
470 addr = sg_dma_address(sg);
471 len = sg_dma_len(sg);
472
473 /*
474 * The SDHCI specification states that ADMA
475 * addresses must be 32-bit aligned. If they
476 * aren't, then we use a bounce buffer for
477 * the (up to three) bytes that screw up the
478 * alignment.
479 */
480 offset = (4 - (addr & 0x3)) & 0x3;
481 if (offset) {
482 if (data->flags & MMC_DATA_WRITE) {
483 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 484 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 485 memcpy(align, buffer, offset);
486 sdhci_kunmap_atomic(buffer, &flags);
487 }
488
118cd17d
BD		 489 /* tran, valid */
490 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 491
492 BUG_ON(offset > 65536);
493
2134a922
PO		 494 align += 4;
495 align_addr += 4;
496
497 desc += 8;
498
499 addr += offset;
500 len -= offset;
501 }
502
2134a922
PO		 503 BUG_ON(len > 65536);
504
118cd17d
BD		 505 /* tran, valid */
506 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 507 desc += 8;
508
509 /*
510 * If this triggers then we have a calculation bug
511 * somewhere. :/
512 */
513 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
514 }
515
70764a90
TA		 516 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
517 /*
518 * Mark the last descriptor as the terminating descriptor
519 */
520 if (desc != host->adma_desc) {
521 desc -= 8;
522 desc[0] |= 0x2; /* end */
523 }
524 } else {
525 /*
526 * Add a terminating entry.
527 */
2134a922 528
70764a90
TA		 529 /* nop, end, valid */
530 sdhci_set_adma_desc(desc, 0, 0, 0x3);
531 }
2134a922
PO		 532
533 /*
534 * Resync align buffer as we might have changed it.
535 */
536 if (data->flags & MMC_DATA_WRITE) {
537 dma_sync_single_for_device(mmc_dev(host->mmc),
538 host->align_addr, 128 * 4, direction);
539 }
540
541 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
542 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 543 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 544 goto unmap_entries;
2134a922 545 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 546
547 return 0;
548
549unmap_entries:
550 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
551 data->sg_len, direction);
552unmap_align:
553 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
554 128 * 4, direction);
555fail:
556 return -EINVAL;
2134a922
PO		 557}
558
559static void sdhci_adma_table_post(struct sdhci_host *host,
560 struct mmc_data *data)
561{
562 int direction;
563
564 struct scatterlist *sg;
565 int i, size;
566 u8 *align;
567 char *buffer;
568 unsigned long flags;
569
570 if (data->flags & MMC_DATA_READ)
571 direction = DMA_FROM_DEVICE;
572 else
573 direction = DMA_TO_DEVICE;
574
575 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
576 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
577
578 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
579 128 * 4, direction);
580
581 if (data->flags & MMC_DATA_READ) {
582 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
583 data->sg_len, direction);
584
585 align = host->align_buffer;
586
587 for_each_sg(data->sg, sg, host->sg_count, i) {
588 if (sg_dma_address(sg) & 0x3) {
589 size = 4 - (sg_dma_address(sg) & 0x3);
590
591 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 592 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 593 memcpy(buffer, align, size);
594 sdhci_kunmap_atomic(buffer, &flags);
595
596 align += 4;
597 }
598 }
599 }
600
601 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
602 data->sg_len, direction);
603}
604
a3c7778f 605static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 606{
1c8cde92 607 u8 count;
a3c7778f 608 struct mmc_data *data = cmd->data;
1c8cde92 609 unsigned target_timeout, current_timeout;
d129bceb 610
ee53ab5d
PO		 611 /*
612 * If the host controller provides us with an incorrect timeout
613 * value, just skip the check and use 0xE. The hardware may take
614 * longer to time out, but that's much better than having a too-short
615 * timeout value.
616 */
11a2f1b7 617 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 618 return 0xE;
e538fbe8 619
a3c7778f
AW		 620 /* Unspecified timeout, assume max */
621 if (!data && !cmd->cmd_timeout_ms)
622 return 0xE;
d129bceb 623
a3c7778f
AW		 624 /* timeout in us */
625 if (!data)
626 target_timeout = cmd->cmd_timeout_ms * 1000;
627 else
628 target_timeout = data->timeout_ns / 1000 +
629 data->timeout_clks / host->clock;
81b39802 630
4b01681c
MB		 631 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
632 host->timeout_clk = host->clock / 1000;
633
1c8cde92
PO		 634 /*
635 * Figure out needed cycles.
636 * We do this in steps in order to fit inside a 32 bit int.
637 * The first step is the minimum timeout, which will have a
638 * minimum resolution of 6 bits:
639 * (1) 2^13*1000 > 2^22,
640 * (2) host->timeout_clk < 2^16
641 * =>
642 * (1) / (2) > 2^6
643 */
4b01681c 644 BUG_ON(!host->timeout_clk);
1c8cde92
PO		 645 count = 0;
646 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
647 while (current_timeout < target_timeout) {
648 count++;
649 current_timeout <<= 1;
650 if (count >= 0xF)
651 break;
652 }
653
654 if (count >= 0xF) {
a3c7778f
AW		 655 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
656 mmc_hostname(host->mmc), cmd->opcode);
1c8cde92
PO		 657 count = 0xE;
658 }
659
ee53ab5d
PO		 660 return count;
661}
662
6aa943ab
AV		 663static void sdhci_set_transfer_irqs(struct sdhci_host *host)
664{
665 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
666 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
667
668 if (host->flags & SDHCI_REQ_USE_DMA)
669 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
670 else
671 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
672}
673
a3c7778f 674static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 675{
676 u8 count;
2134a922 677 u8 ctrl;
a3c7778f 678 struct mmc_data *data = cmd->data;
8f1934ce 679 int ret;
ee53ab5d
PO		 680
681 WARN_ON(host->data);
682
a3c7778f
AW		 683 if (data || (cmd->flags & MMC_RSP_BUSY)) {
684 count = sdhci_calc_timeout(host, cmd);
685 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
686 }
687
688 if (!data)
ee53ab5d
PO		 689 return;
690
691 /* Sanity checks */
692 BUG_ON(data->blksz * data->blocks > 524288);
693 BUG_ON(data->blksz > host->mmc->max_blk_size);
694 BUG_ON(data->blocks > 65535);
695
696 host->data = data;
697 host->data_early = 0;
f6a03cbf 698 host->data->bytes_xfered = 0;
ee53ab5d 699
a13abc7b 700 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 701 host->flags |= SDHCI_REQ_USE_DMA;
702
2134a922
PO		 703 /*
704 * FIXME: This doesn't account for merging when mapping the
705 * scatterlist.
706 */
707 if (host->flags & SDHCI_REQ_USE_DMA) {
708 int broken, i;
709 struct scatterlist *sg;
710
711 broken = 0;
712 if (host->flags & SDHCI_USE_ADMA) {
713 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
714 broken = 1;
715 } else {
716 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
717 broken = 1;
718 }
719
720 if (unlikely(broken)) {
721 for_each_sg(data->sg, sg, data->sg_len, i) {
722 if (sg->length & 0x3) {
723 DBG("Reverting to PIO because of "
724 "transfer size (%d)\n",
725 sg->length);
726 host->flags &= ~SDHCI_REQ_USE_DMA;
727 break;
728 }
729 }
730 }
c9fddbc4
PO		 731 }
732
733 /*
734 * The assumption here being that alignment is the same after
735 * translation to device address space.
736 */
2134a922
PO		 737 if (host->flags & SDHCI_REQ_USE_DMA) {
738 int broken, i;
739 struct scatterlist *sg;
740
741 broken = 0;
742 if (host->flags & SDHCI_USE_ADMA) {
743 /*
744 * As we use 3 byte chunks to work around
745 * alignment problems, we need to check this
746 * quirk.
747 */
748 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
749 broken = 1;
750 } else {
751 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
752 broken = 1;
753 }
754
755 if (unlikely(broken)) {
756 for_each_sg(data->sg, sg, data->sg_len, i) {
757 if (sg->offset & 0x3) {
758 DBG("Reverting to PIO because of "
759 "bad alignment\n");
760 host->flags &= ~SDHCI_REQ_USE_DMA;
761 break;
762 }
763 }
764 }
765 }
766
8f1934ce
PO		 767 if (host->flags & SDHCI_REQ_USE_DMA) {
768 if (host->flags & SDHCI_USE_ADMA) {
769 ret = sdhci_adma_table_pre(host, data);
770 if (ret) {
771 /*
772 * This only happens when someone fed
773 * us an invalid request.
774 */
775 WARN_ON(1);
ebd6d357 776 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 777 } else {
4e4141a5
AV		 778 sdhci_writel(host, host->adma_addr,
779 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 780 }
781 } else {
c8b3e02e 782 int sg_cnt;
8f1934ce 783
c8b3e02e 784 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 785 data->sg, data->sg_len,
786 (data->flags & MMC_DATA_READ) ?
787 DMA_FROM_DEVICE :
788 DMA_TO_DEVICE);
c8b3e02e 789 if (sg_cnt == 0) {
8f1934ce
PO		 790 /*
791 * This only happens when someone fed
792 * us an invalid request.
793 */
794 WARN_ON(1);
ebd6d357 795 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 796 } else {
719a61b4 797 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 798 sdhci_writel(host, sg_dma_address(data->sg),
799 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 800 }
801 }
802 }
803
2134a922
PO		 804 /*
805 * Always adjust the DMA selection as some controllers
806 * (e.g. JMicron) can't do PIO properly when the selection
807 * is ADMA.
808 */
809 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 810 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 811 ctrl &= ~SDHCI_CTRL_DMA_MASK;
812 if ((host->flags & SDHCI_REQ_USE_DMA) &&
813 (host->flags & SDHCI_USE_ADMA))
814 ctrl |= SDHCI_CTRL_ADMA32;
815 else
816 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 817 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 818 }
819
8f1934ce 820 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 821 int flags;
822
823 flags = SG_MITER_ATOMIC;
824 if (host->data->flags & MMC_DATA_READ)
825 flags |= SG_MITER_TO_SG;
826 else
827 flags |= SG_MITER_FROM_SG;
828 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 829 host->blocks = data->blocks;
d129bceb 830 }
c7fa9963 831
6aa943ab
AV		 832 sdhci_set_transfer_irqs(host);
833
f6a03cbf
MV		 834 /* Set the DMA boundary value and block size */
835 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
836 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 837 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 838}
839
840static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 841 struct mmc_command *cmd)
c7fa9963
PO		 842{
843 u16 mode;
e89d456f 844 struct mmc_data *data = cmd->data;
c7fa9963 845
c7fa9963
PO		 846 if (data == NULL)
847 return;
848
e538fbe8
PO		 849 WARN_ON(!host->data);
850
c7fa9963 851 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 852 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
853 mode |= SDHCI_TRNS_MULTI;
854 /*
855 * If we are sending CMD23, CMD12 never gets sent
856 * on successful completion (so no Auto-CMD12).
857 */
858 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
859 mode |= SDHCI_TRNS_AUTO_CMD12;
c4512f79 860 }
c7fa9963
PO		 861 if (data->flags & MMC_DATA_READ)
862 mode |= SDHCI_TRNS_READ;
c9fddbc4 863 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 864 mode |= SDHCI_TRNS_DMA;
865
4e4141a5 866 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 867}
868
869static void sdhci_finish_data(struct sdhci_host *host)
870{
871 struct mmc_data *data;
d129bceb
PO		 872
873 BUG_ON(!host->data);
874
875 data = host->data;
876 host->data = NULL;
877
c9fddbc4 878 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 879 if (host->flags & SDHCI_USE_ADMA)
880 sdhci_adma_table_post(host, data);
881 else {
882 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
883 data->sg_len, (data->flags & MMC_DATA_READ) ?
884 DMA_FROM_DEVICE : DMA_TO_DEVICE);
885 }
d129bceb
PO		 886 }
887
888 /*
c9b74c5b
PO		 889 * The specification states that the block count register must
890 * be updated, but it does not specify at what point in the
891 * data flow. That makes the register entirely useless to read
892 * back so we have to assume that nothing made it to the card
893 * in the event of an error.
d129bceb 894 */
c9b74c5b
PO		 895 if (data->error)
896 data->bytes_xfered = 0;
d129bceb 897 else
c9b74c5b 898 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 899
e89d456f
AW		 900 /*
901 * Need to send CMD12 if -
902 * a) open-ended multiblock transfer (no CMD23)
903 * b) error in multiblock transfer
904 */
905 if (data->stop &&
906 (data->error ||
907 !host->mrq->sbc)) {
908
d129bceb
PO		 909 /*
910 * The controller needs a reset of internal state machines
911 * upon error conditions.
912 */
17b0429d 913 if (data->error) {
d129bceb
PO		 914 sdhci_reset(host, SDHCI_RESET_CMD);
915 sdhci_reset(host, SDHCI_RESET_DATA);
916 }
917
918 sdhci_send_command(host, data->stop);
919 } else
920 tasklet_schedule(&host->finish_tasklet);
921}
922
923static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
924{
925 int flags;
fd2208d7 926 u32 mask;
7cb2c76f 927 unsigned long timeout;
d129bceb
PO		 928
929 WARN_ON(host->cmd);
930
d129bceb 931 /* Wait max 10 ms */
7cb2c76f 932 timeout = 10;
fd2208d7
PO		 933
934 mask = SDHCI_CMD_INHIBIT;
935 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
936 mask |= SDHCI_DATA_INHIBIT;
937
938 /* We shouldn't wait for data inihibit for stop commands, even
939 though they might use busy signaling */
940 if (host->mrq->data && (cmd == host->mrq->data->stop))
941 mask &= ~SDHCI_DATA_INHIBIT;
942
4e4141a5 943 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 944 if (timeout == 0) {
d129bceb 945 printk(KERN_ERR "%s: Controller never released "
acf1da45 946 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 947 sdhci_dumpregs(host);
17b0429d 948 cmd->error = -EIO;
d129bceb
PO		 949 tasklet_schedule(&host->finish_tasklet);
950 return;
951 }
7cb2c76f
PO		 952 timeout--;
953 mdelay(1);
954 }
d129bceb
PO		 955
956 mod_timer(&host->timer, jiffies + 10 * HZ);
957
958 host->cmd = cmd;
959
a3c7778f 960 sdhci_prepare_data(host, cmd);
d129bceb 961
4e4141a5 962 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 963
e89d456f 964 sdhci_set_transfer_mode(host, cmd);
c7fa9963 965
d129bceb 966 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 967 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 968 mmc_hostname(host->mmc));
17b0429d 969 cmd->error = -EINVAL;
d129bceb
PO		 970 tasklet_schedule(&host->finish_tasklet);
971 return;
972 }
973
974 if (!(cmd->flags & MMC_RSP_PRESENT))
975 flags = SDHCI_CMD_RESP_NONE;
976 else if (cmd->flags & MMC_RSP_136)
977 flags = SDHCI_CMD_RESP_LONG;
978 else if (cmd->flags & MMC_RSP_BUSY)
979 flags = SDHCI_CMD_RESP_SHORT_BUSY;
980 else
981 flags = SDHCI_CMD_RESP_SHORT;
982
983 if (cmd->flags & MMC_RSP_CRC)
984 flags |= SDHCI_CMD_CRC;
985 if (cmd->flags & MMC_RSP_OPCODE)
986 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 987
988 /* CMD19 is special in that the Data Present Select should be set */
989 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
d129bceb
PO		 990 flags |= SDHCI_CMD_DATA;
991
4e4141a5 992 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 993}
994
995static void sdhci_finish_command(struct sdhci_host *host)
996{
997 int i;
998
999 BUG_ON(host->cmd == NULL);
1000
1001 if (host->cmd->flags & MMC_RSP_PRESENT) {
1002 if (host->cmd->flags & MMC_RSP_136) {
1003 /* CRC is stripped so we need to do some shifting. */
1004 for (i = 0;i < 4;i++) {
4e4141a5 1005 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1006 SDHCI_RESPONSE + (3-i)*4) << 8;
1007 if (i != 3)
1008 host->cmd->resp[i] |=
4e4141a5 1009 sdhci_readb(host,
d129bceb
PO		 1010 SDHCI_RESPONSE + (3-i)*4-1);
1011 }
1012 } else {
4e4141a5 1013 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1014 }
1015 }
1016
17b0429d 1017 host->cmd->error = 0;
d129bceb 1018
e89d456f
AW		 1019 /* Finished CMD23, now send actual command. */
1020 if (host->cmd == host->mrq->sbc) {
1021 host->cmd = NULL;
1022 sdhci_send_command(host, host->mrq->cmd);
1023 } else {
e538fbe8 1024
e89d456f
AW		 1025 /* Processed actual command. */
1026 if (host->data && host->data_early)
1027 sdhci_finish_data(host);
d129bceb 1028
e89d456f
AW		 1029 if (!host->cmd->data)
1030 tasklet_schedule(&host->finish_tasklet);
1031
1032 host->cmd = NULL;
1033 }
d129bceb
PO		 1034}
1035
1036static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1037{
c3ed3877
AN		 1038 int div = 0; /* Initialized for compiler warning */
1039 u16 clk = 0;
7cb2c76f 1040 unsigned long timeout;
d129bceb
PO		 1041
1042 if (clock == host->clock)
1043 return;
1044
8114634c
AV		 1045 if (host->ops->set_clock) {
1046 host->ops->set_clock(host, clock);
1047 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1048 return;
1049 }
1050
4e4141a5 1051 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1052
1053 if (clock == 0)
1054 goto out;
1055
85105c53 1056 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1057 /*
1058 * Check if the Host Controller supports Programmable Clock
1059 * Mode.
1060 */
1061 if (host->clk_mul) {
1062 u16 ctrl;
1063
1064 /*
1065 * We need to figure out whether the Host Driver needs
1066 * to select Programmable Clock Mode, or the value can
1067 * be set automatically by the Host Controller based on
1068 * the Preset Value registers.
1069 */
1070 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1071 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1072 for (div = 1; div <= 1024; div++) {
1073 if (((host->max_clk * host->clk_mul) /
1074 div) <= clock)
1075 break;
1076 }
1077 /*
1078 * Set Programmable Clock Mode in the Clock
1079 * Control register.
1080 */
1081 clk = SDHCI_PROG_CLOCK_MODE;
1082 div--;
1083 }
1084 } else {
1085 /* Version 3.00 divisors must be a multiple of 2. */
1086 if (host->max_clk <= clock)
1087 div = 1;
1088 else {
1089 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1090 div += 2) {
1091 if ((host->max_clk / div) <= clock)
1092 break;
1093 }
85105c53 1094 }
c3ed3877 1095 div >>= 1;
85105c53
ZG		 1096 }
1097 } else {
1098 /* Version 2.00 divisors must be a power of 2. */
0397526d 1099 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1100 if ((host->max_clk / div) <= clock)
1101 break;
1102 }
c3ed3877 1103 div >>= 1;
d129bceb 1104 }
d129bceb 1105
c3ed3877 1106 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1107 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1108 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1109 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1110 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1111
27f6cb16
CB		 1112 /* Wait max 20 ms */
1113 timeout = 20;
4e4141a5 1114 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1115 & SDHCI_CLOCK_INT_STABLE)) {
1116 if (timeout == 0) {
acf1da45
PO		 1117 printk(KERN_ERR "%s: Internal clock never "
1118 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1119 sdhci_dumpregs(host);
1120 return;
1121 }
7cb2c76f
PO		 1122 timeout--;
1123 mdelay(1);
1124 }
d129bceb
PO		 1125
1126 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1127 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1128
1129out:
1130 host->clock = clock;
1131}
1132
146ad66e
PO		 1133static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1134{
8364248a 1135 u8 pwr = 0;
146ad66e 1136
8364248a 1137 if (power != (unsigned short)-1) {
ae628903
PO		 1138 switch (1 << power) {
1139 case MMC_VDD_165_195:
1140 pwr = SDHCI_POWER_180;
1141 break;
1142 case MMC_VDD_29_30:
1143 case MMC_VDD_30_31:
1144 pwr = SDHCI_POWER_300;
1145 break;
1146 case MMC_VDD_32_33:
1147 case MMC_VDD_33_34:
1148 pwr = SDHCI_POWER_330;
1149 break;
1150 default:
1151 BUG();
1152 }
1153 }
1154
1155 if (host->pwr == pwr)
146ad66e
PO		 1156 return;
1157
ae628903
PO		 1158 host->pwr = pwr;
1159
1160 if (pwr == 0) {
4e4141a5 1161 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1162 return;
9e9dc5f2
DS		 1163 }
1164
1165 /*
1166 * Spec says that we should clear the power reg before setting
1167 * a new value. Some controllers don't seem to like this though.
1168 */
b8c86fc5 1169 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1170 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1171
e08c1694 1172 /*
c71f6512 1173 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1174 * and set turn on power at the same time, so set the voltage first.
1175 */
11a2f1b7 1176 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1177 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1178
ae628903 1179 pwr |= SDHCI_POWER_ON;
146ad66e 1180
ae628903 1181 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1182
1183 /*
1184 * Some controllers need an extra 10ms delay of 10ms before they
1185 * can apply clock after applying power
1186 */
11a2f1b7 1187 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1188 mdelay(10);
146ad66e
PO		 1189}
1190
d129bceb
PO		 1191/*****************************************************************************\
1192 * *
1193 * MMC callbacks *
1194 * *
1195\*****************************************************************************/
1196
1197static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1198{
1199 struct sdhci_host *host;
68d1fb7e 1200 bool present;
d129bceb
PO		 1201 unsigned long flags;
1202
1203 host = mmc_priv(mmc);
1204
1205 spin_lock_irqsave(&host->lock, flags);
1206
1207 WARN_ON(host->mrq != NULL);
1208
f9134319 1209#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1210 sdhci_activate_led(host);
2f730fec 1211#endif
e89d456f
AW		 1212
1213 /*
1214 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1215 * requests if Auto-CMD12 is enabled.
1216 */
1217 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1218 if (mrq->stop) {
1219 mrq->data->stop = NULL;
1220 mrq->stop = NULL;
1221 }
1222 }
d129bceb
PO		 1223
1224 host->mrq = mrq;
1225
68d1fb7e
AV		 1226 /* If polling, assume that the card is always present. */
1227 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1228 present = true;
1229 else
1230 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1231 SDHCI_CARD_PRESENT;
1232
1233 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1234 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1235 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1236 } else {
1237 u32 present_state;
1238
1239 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1240 /*
1241 * Check if the re-tuning timer has already expired and there
1242 * is no on-going data transfer. If so, we need to execute
1243 * tuning procedure before sending command.
1244 */
1245 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1246 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1247 spin_unlock_irqrestore(&host->lock, flags);
1248 sdhci_execute_tuning(mmc);
1249 spin_lock_irqsave(&host->lock, flags);
1250
1251 /* Restore original mmc_request structure */
1252 host->mrq = mrq;
1253 }
1254
e89d456f
AW		 1255 if (mrq->sbc)
1256 sdhci_send_command(host, mrq->sbc);
1257 else
1258 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1259 }
d129bceb 1260
5f25a66f 1261 mmiowb();
d129bceb
PO		 1262 spin_unlock_irqrestore(&host->lock, flags);
1263}
1264
1265static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1266{
1267 struct sdhci_host *host;
1268 unsigned long flags;
1269 u8 ctrl;
1270
1271 host = mmc_priv(mmc);
1272
1273 spin_lock_irqsave(&host->lock, flags);
1274
1e72859e
PO		 1275 if (host->flags & SDHCI_DEVICE_DEAD)
1276 goto out;
1277
d129bceb
PO		 1278 /*
1279 * Reset the chip on each power off.
1280 * Should clear out any weird states.
1281 */
1282 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1283 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1284 sdhci_reinit(host);
d129bceb
PO		 1285 }
1286
1287 sdhci_set_clock(host, ios->clock);
1288
1289 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1290 sdhci_set_power(host, -1);
d129bceb 1291 else
146ad66e 1292 sdhci_set_power(host, ios->vdd);
d129bceb 1293
643a81ff
PR		 1294 if (host->ops->platform_send_init_74_clocks)
1295 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1296
15ec4461
PR		 1297 /*
1298 * If your platform has 8-bit width support but is not a v3 controller,
1299 * or if it requires special setup code, you should implement that in
1300 * platform_8bit_width().
1301 */
1302 if (host->ops->platform_8bit_width)
1303 host->ops->platform_8bit_width(host, ios->bus_width);
1304 else {
1305 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1306 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1307 ctrl &= ~SDHCI_CTRL_4BITBUS;
1308 if (host->version >= SDHCI_SPEC_300)
1309 ctrl |= SDHCI_CTRL_8BITBUS;
1310 } else {
1311 if (host->version >= SDHCI_SPEC_300)
1312 ctrl &= ~SDHCI_CTRL_8BITBUS;
1313 if (ios->bus_width == MMC_BUS_WIDTH_4)
1314 ctrl |= SDHCI_CTRL_4BITBUS;
1315 else
1316 ctrl &= ~SDHCI_CTRL_4BITBUS;
1317 }
1318 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1319 }
ae6d6c92 1320
15ec4461 1321 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1322
3ab9c8da
PR		 1323 if ((ios->timing == MMC_TIMING_SD_HS ||
1324 ios->timing == MMC_TIMING_MMC_HS)
1325 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1326 ctrl |= SDHCI_CTRL_HISPD;
1327 else
1328 ctrl &= ~SDHCI_CTRL_HISPD;
1329
d6d50a15 1330 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1331 u16 clk, ctrl_2;
1332 unsigned int clock;
1333
1334 /* In case of UHS-I modes, set High Speed Enable */
1335 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1336 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1337 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1338 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1339 (ios->timing == MMC_TIMING_UHS_SDR12))
1340 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1341
1342 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1343 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1344 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1345 /*
1346 * We only need to set Driver Strength if the
1347 * preset value enable is not set.
1348 */
1349 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1350 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1351 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1352 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1353 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1354
1355 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1356 } else {
1357 /*
1358 * According to SDHC Spec v3.00, if the Preset Value
1359 * Enable in the Host Control 2 register is set, we
1360 * need to reset SD Clock Enable before changing High
1361 * Speed Enable to avoid generating clock gliches.
1362 */
758535c4
AN		 1363
1364 /* Reset SD Clock Enable */
1365 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1366 clk &= ~SDHCI_CLOCK_CARD_EN;
1367 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1368
1369 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1370
1371 /* Re-enable SD Clock */
1372 clock = host->clock;
1373 host->clock = 0;
1374 sdhci_set_clock(host, clock);
d6d50a15 1375 }
49c468fc 1376
49c468fc
AN		 1377
1378 /* Reset SD Clock Enable */
1379 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1380 clk &= ~SDHCI_CLOCK_CARD_EN;
1381 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1382
6322cdd0
PR		 1383 if (host->ops->set_uhs_signaling)
1384 host->ops->set_uhs_signaling(host, ios->timing);
1385 else {
1386 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1387 /* Select Bus Speed Mode for host */
1388 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1389 if (ios->timing == MMC_TIMING_UHS_SDR12)
1390 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1391 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1392 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1393 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1394 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1395 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1396 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1397 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1398 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1399 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1400 }
49c468fc
AN		 1401
1402 /* Re-enable SD Clock */
1403 clock = host->clock;
1404 host->clock = 0;
1405 sdhci_set_clock(host, clock);
758535c4
AN		 1406 } else
1407 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1408
b8352260
LD		 1409 /*
1410 * Some (ENE) controllers go apeshit on some ios operation,
1411 * signalling timeout and CRC errors even on CMD0. Resetting
1412 * it on each ios seems to solve the problem.
1413 */
b8c86fc5 1414 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1415 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1416
1e72859e 1417out:
5f25a66f 1418 mmiowb();
d129bceb
PO		 1419 spin_unlock_irqrestore(&host->lock, flags);
1420}
1421
82b0e23a 1422static int check_ro(struct sdhci_host *host)
d129bceb 1423{
d129bceb 1424 unsigned long flags;
2dfb579c 1425 int is_readonly;
d129bceb 1426
d129bceb
PO		 1427 spin_lock_irqsave(&host->lock, flags);
1428
1e72859e 1429 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1430 is_readonly = 0;
1431 else if (host->ops->get_ro)
1432 is_readonly = host->ops->get_ro(host);
1e72859e 1433 else
2dfb579c
WS		 1434 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1435 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1436
1437 spin_unlock_irqrestore(&host->lock, flags);
1438
2dfb579c
WS		 1439 /* This quirk needs to be replaced by a callback-function later */
1440 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1441 !is_readonly : is_readonly;
d129bceb
PO		 1442}
1443
82b0e23a
TI		 1444#define SAMPLE_COUNT 5
1445
1446static int sdhci_get_ro(struct mmc_host *mmc)
1447{
1448 struct sdhci_host *host;
1449 int i, ro_count;
1450
1451 host = mmc_priv(mmc);
1452
1453 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1454 return check_ro(host);
1455
1456 ro_count = 0;
1457 for (i = 0; i < SAMPLE_COUNT; i++) {
1458 if (check_ro(host)) {
1459 if (++ro_count > SAMPLE_COUNT / 2)
1460 return 1;
1461 }
1462 msleep(30);
1463 }
1464 return 0;
1465}
1466
f75979b7
PO		 1467static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1468{
1469 struct sdhci_host *host;
1470 unsigned long flags;
f75979b7
PO		 1471
1472 host = mmc_priv(mmc);
1473
1474 spin_lock_irqsave(&host->lock, flags);
1475
1e72859e
PO		 1476 if (host->flags & SDHCI_DEVICE_DEAD)
1477 goto out;
1478
f75979b7 1479 if (enable)
7260cf5e
AV		 1480 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1481 else
1482 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1483out:
f75979b7
PO		 1484 mmiowb();
1485
1486 spin_unlock_irqrestore(&host->lock, flags);
1487}
1488
f2119df6
AN		 1489static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1490 struct mmc_ios *ios)
1491{
1492 struct sdhci_host *host;
1493 u8 pwr;
1494 u16 clk, ctrl;
1495 u32 present_state;
1496
1497 host = mmc_priv(mmc);
1498
1499 /*
1500 * Signal Voltage Switching is only applicable for Host Controllers
1501 * v3.00 and above.
1502 */
1503 if (host->version < SDHCI_SPEC_300)
1504 return 0;
1505
1506 /*
1507 * We first check whether the request is to set signalling voltage
1508 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1509 */
1510 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1511 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1512 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1513 ctrl &= ~SDHCI_CTRL_VDD_180;
1514 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1515
1516 /* Wait for 5ms */
1517 usleep_range(5000, 5500);
1518
1519 /* 3.3V regulator output should be stable within 5 ms */
1520 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1521 if (!(ctrl & SDHCI_CTRL_VDD_180))
1522 return 0;
1523 else {
1524 printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1525 "signalling voltage failed\n");
1526 return -EIO;
1527 }
1528 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1529 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1530 /* Stop SDCLK */
1531 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1532 clk &= ~SDHCI_CLOCK_CARD_EN;
1533 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1534
1535 /* Check whether DAT[3:0] is 0000 */
1536 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1537 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1538 SDHCI_DATA_LVL_SHIFT)) {
1539 /*
1540 * Enable 1.8V Signal Enable in the Host Control2
1541 * register
1542 */
1543 ctrl |= SDHCI_CTRL_VDD_180;
1544 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1545
1546 /* Wait for 5ms */
1547 usleep_range(5000, 5500);
1548
1549 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1550 if (ctrl & SDHCI_CTRL_VDD_180) {
1551 /* Provide SDCLK again and wait for 1ms*/
1552 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1553 clk |= SDHCI_CLOCK_CARD_EN;
1554 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1555 usleep_range(1000, 1500);
1556
1557 /*
1558 * If DAT[3:0] level is 1111b, then the card
1559 * was successfully switched to 1.8V signaling.
1560 */
1561 present_state = sdhci_readl(host,
1562 SDHCI_PRESENT_STATE);
1563 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1564 SDHCI_DATA_LVL_MASK)
1565 return 0;
1566 }
1567 }
1568
1569 /*
1570 * If we are here, that means the switch to 1.8V signaling
1571 * failed. We power cycle the card, and retry initialization
1572 * sequence by setting S18R to 0.
1573 */
1574 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1575 pwr &= ~SDHCI_POWER_ON;
1576 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1577
1578 /* Wait for 1ms as per the spec */
1579 usleep_range(1000, 1500);
1580 pwr |= SDHCI_POWER_ON;
1581 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1582
1583 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1584 "voltage failed, retrying with S18R set to 0\n");
1585 return -EAGAIN;
1586 } else
1587 /* No signal voltage switch required */
1588 return 0;
1589}
1590
b513ea25
AN		 1591static int sdhci_execute_tuning(struct mmc_host *mmc)
1592{
1593 struct sdhci_host *host;
1594 u16 ctrl;
1595 u32 ier;
1596 int tuning_loop_counter = MAX_TUNING_LOOP;
1597 unsigned long timeout;
1598 int err = 0;
1599
1600 host = mmc_priv(mmc);
1601
1602 disable_irq(host->irq);
1603 spin_lock(&host->lock);
1604
1605 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1606
1607 /*
1608 * Host Controller needs tuning only in case of SDR104 mode
1609 * and for SDR50 mode when Use Tuning for SDR50 is set in
1610 * Capabilities register.
1611 */
1612 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1613 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1614 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1615 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1616 else {
1617 spin_unlock(&host->lock);
1618 enable_irq(host->irq);
1619 return 0;
1620 }
1621
1622 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1623
1624 /*
1625 * As per the Host Controller spec v3.00, tuning command
1626 * generates Buffer Read Ready interrupt, so enable that.
1627 *
1628 * Note: The spec clearly says that when tuning sequence
1629 * is being performed, the controller does not generate
1630 * interrupts other than Buffer Read Ready interrupt. But
1631 * to make sure we don't hit a controller bug, we _only_
1632 * enable Buffer Read Ready interrupt here.
1633 */
1634 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1635 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1636
1637 /*
1638 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1639 * of loops reaches 40 times or a timeout of 150ms occurs.
1640 */
1641 timeout = 150;
1642 do {
1643 struct mmc_command cmd = {0};
1644 struct mmc_request mrq = {0};
1645
1646 if (!tuning_loop_counter && !timeout)
1647 break;
1648
1649 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1650 cmd.arg = 0;
1651 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1652 cmd.retries = 0;
1653 cmd.data = NULL;
1654 cmd.error = 0;
1655
1656 mrq.cmd = &cmd;
1657 host->mrq = &mrq;
1658
1659 /*
1660 * In response to CMD19, the card sends 64 bytes of tuning
1661 * block to the Host Controller. So we set the block size
1662 * to 64 here.
1663 */
1664 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1665
1666 /*
1667 * The tuning block is sent by the card to the host controller.
1668 * So we set the TRNS_READ bit in the Transfer Mode register.
1669 * This also takes care of setting DMA Enable and Multi Block
1670 * Select in the same register to 0.
1671 */
1672 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1673
1674 sdhci_send_command(host, &cmd);
1675
1676 host->cmd = NULL;
1677 host->mrq = NULL;
1678
1679 spin_unlock(&host->lock);
1680 enable_irq(host->irq);
1681
1682 /* Wait for Buffer Read Ready interrupt */
1683 wait_event_interruptible_timeout(host->buf_ready_int,
1684 (host->tuning_done == 1),
1685 msecs_to_jiffies(50));
1686 disable_irq(host->irq);
1687 spin_lock(&host->lock);
1688
1689 if (!host->tuning_done) {
1690 printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1691 "Buffer Read Ready interrupt during tuning "
1692 "procedure, falling back to fixed sampling "
1693 "clock\n");
1694 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1695 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1696 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1697 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1698
1699 err = -EIO;
1700 goto out;
1701 }
1702
1703 host->tuning_done = 0;
1704
1705 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1706 tuning_loop_counter--;
1707 timeout--;
1708 mdelay(1);
1709 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1710
1711 /*
1712 * The Host Driver has exhausted the maximum number of loops allowed,
1713 * so use fixed sampling frequency.
1714 */
1715 if (!tuning_loop_counter || !timeout) {
1716 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1717 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1718 } else {
1719 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1720 printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1721 " failed, falling back to fixed sampling"
1722 " clock\n");
1723 err = -EIO;
1724 }
1725 }
1726
1727out:
cf2b5eea
AN		 1728 /*
1729 * If this is the very first time we are here, we start the retuning
1730 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1731 * flag won't be set, we check this condition before actually starting
1732 * the timer.
1733 */
1734 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1735 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1736 mod_timer(&host->tuning_timer, jiffies +
1737 host->tuning_count * HZ);
1738 /* Tuning mode 1 limits the maximum data length to 4MB */
1739 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1740 } else {
1741 host->flags &= ~SDHCI_NEEDS_RETUNING;
1742 /* Reload the new initial value for timer */
1743 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1744 mod_timer(&host->tuning_timer, jiffies +
1745 host->tuning_count * HZ);
1746 }
1747
1748 /*
1749 * In case tuning fails, host controllers which support re-tuning can
1750 * try tuning again at a later time, when the re-tuning timer expires.
1751 * So for these controllers, we return 0. Since there might be other
1752 * controllers who do not have this capability, we return error for
1753 * them.
1754 */
1755 if (err && host->tuning_count &&
1756 host->tuning_mode == SDHCI_TUNING_MODE_1)
1757 err = 0;
1758
b513ea25
AN		 1759 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1760 spin_unlock(&host->lock);
1761 enable_irq(host->irq);
1762
1763 return err;
1764}
1765
4d55c5a1
AN		 1766static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1767{
1768 struct sdhci_host *host;
1769 u16 ctrl;
1770 unsigned long flags;
1771
1772 host = mmc_priv(mmc);
1773
1774 /* Host Controller v3.00 defines preset value registers */
1775 if (host->version < SDHCI_SPEC_300)
1776 return;
1777
1778 spin_lock_irqsave(&host->lock, flags);
1779
1780 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1781
1782 /*
1783 * We only enable or disable Preset Value if they are not already
1784 * enabled or disabled respectively. Otherwise, we bail out.
1785 */
1786 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1787 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1788 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1789 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1790 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1791 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1792 }
1793
1794 spin_unlock_irqrestore(&host->lock, flags);
1795}
1796
ab7aefd0 1797static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1798 .request = sdhci_request,
1799 .set_ios = sdhci_set_ios,
1800 .get_ro = sdhci_get_ro,
f75979b7 1801 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1802 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1803 .execute_tuning = sdhci_execute_tuning,
4d55c5a1 1804 .enable_preset_value = sdhci_enable_preset_value,
d129bceb
PO		 1805};
1806
1807/*****************************************************************************\
1808 * *
1809 * Tasklets *
1810 * *
1811\*****************************************************************************/
1812
1813static void sdhci_tasklet_card(unsigned long param)
1814{
1815 struct sdhci_host *host;
1816 unsigned long flags;
1817
1818 host = (struct sdhci_host*)param;
1819
1820 spin_lock_irqsave(&host->lock, flags);
1821
4e4141a5 1822 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1823 if (host->mrq) {
1824 printk(KERN_ERR "%s: Card removed during transfer!\n",
1825 mmc_hostname(host->mmc));
1826 printk(KERN_ERR "%s: Resetting controller.\n",
1827 mmc_hostname(host->mmc));
1828
1829 sdhci_reset(host, SDHCI_RESET_CMD);
1830 sdhci_reset(host, SDHCI_RESET_DATA);
1831
17b0429d 1832 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1833 tasklet_schedule(&host->finish_tasklet);
1834 }
1835 }
1836
1837 spin_unlock_irqrestore(&host->lock, flags);
1838
04cf585d 1839 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1840}
1841
1842static void sdhci_tasklet_finish(unsigned long param)
1843{
1844 struct sdhci_host *host;
1845 unsigned long flags;
1846 struct mmc_request *mrq;
1847
1848 host = (struct sdhci_host*)param;
1849
0c9c99a7
CB		 1850 /*
1851 * If this tasklet gets rescheduled while running, it will
1852 * be run again afterwards but without any active request.
1853 */
1854 if (!host->mrq)
1855 return;
1856
d129bceb
PO		 1857 spin_lock_irqsave(&host->lock, flags);
1858
1859 del_timer(&host->timer);
1860
cf2b5eea
AN		 1861 if (host->version >= SDHCI_SPEC_300)
1862 del_timer(&host->tuning_timer);
1863
d129bceb
PO		 1864 mrq = host->mrq;
1865
d129bceb
PO		 1866 /*
1867 * The controller needs a reset of internal state machines
1868 * upon error conditions.
1869 */
1e72859e 1870 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1871 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1872 (mrq->data && (mrq->data->error ||
1873 (mrq->data->stop && mrq->data->stop->error))) ||
1874 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1875
1876 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1877 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1878 unsigned int clock;
1879
1880 /* This is to force an update */
1881 clock = host->clock;
1882 host->clock = 0;
1883 sdhci_set_clock(host, clock);
1884 }
1885
1886 /* Spec says we should do both at the same time, but Ricoh
1887 controllers do not like that. */
d129bceb
PO		 1888 sdhci_reset(host, SDHCI_RESET_CMD);
1889 sdhci_reset(host, SDHCI_RESET_DATA);
1890 }
1891
1892 host->mrq = NULL;
1893 host->cmd = NULL;
1894 host->data = NULL;
1895
f9134319 1896#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1897 sdhci_deactivate_led(host);
2f730fec 1898#endif
d129bceb 1899
5f25a66f 1900 mmiowb();
d129bceb
PO		 1901 spin_unlock_irqrestore(&host->lock, flags);
1902
1903 mmc_request_done(host->mmc, mrq);
1904}
1905
1906static void sdhci_timeout_timer(unsigned long data)
1907{
1908 struct sdhci_host *host;
1909 unsigned long flags;
1910
1911 host = (struct sdhci_host*)data;
1912
1913 spin_lock_irqsave(&host->lock, flags);
1914
1915 if (host->mrq) {
acf1da45
PO		 1916 printk(KERN_ERR "%s: Timeout waiting for hardware "
1917 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1918 sdhci_dumpregs(host);
1919
1920 if (host->data) {
17b0429d 1921 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1922 sdhci_finish_data(host);
1923 } else {
1924 if (host->cmd)
17b0429d 1925 host->cmd->error = -ETIMEDOUT;
d129bceb 1926 else
17b0429d 1927 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1928
1929 tasklet_schedule(&host->finish_tasklet);
1930 }
1931 }
1932
5f25a66f 1933 mmiowb();
d129bceb
PO		 1934 spin_unlock_irqrestore(&host->lock, flags);
1935}
1936
cf2b5eea
AN		 1937static void sdhci_tuning_timer(unsigned long data)
1938{
1939 struct sdhci_host *host;
1940 unsigned long flags;
1941
1942 host = (struct sdhci_host *)data;
1943
1944 spin_lock_irqsave(&host->lock, flags);
1945
1946 host->flags |= SDHCI_NEEDS_RETUNING;
1947
1948 spin_unlock_irqrestore(&host->lock, flags);
1949}
1950
d129bceb
PO		 1951/*****************************************************************************\
1952 * *
1953 * Interrupt handling *
1954 * *
1955\*****************************************************************************/
1956
1957static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1958{
1959 BUG_ON(intmask == 0);
1960
1961 if (!host->cmd) {
b67ac3f3
PO		 1962 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1963 "though no command operation was in progress.\n",
1964 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1965 sdhci_dumpregs(host);
1966 return;
1967 }
1968
43b58b36 1969 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1970 host->cmd->error = -ETIMEDOUT;
1971 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1972 SDHCI_INT_INDEX))
1973 host->cmd->error = -EILSEQ;
43b58b36 1974
e809517f 1975 if (host->cmd->error) {
d129bceb 1976 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1977 return;
1978 }
1979
1980 /*
1981 * The host can send and interrupt when the busy state has
1982 * ended, allowing us to wait without wasting CPU cycles.
1983 * Unfortunately this is overloaded on the "data complete"
1984 * interrupt, so we need to take some care when handling
1985 * it.
1986 *
1987 * Note: The 1.0 specification is a bit ambiguous about this
1988 * feature so there might be some problems with older
1989 * controllers.
1990 */
1991 if (host->cmd->flags & MMC_RSP_BUSY) {
1992 if (host->cmd->data)
1993 DBG("Cannot wait for busy signal when also "
1994 "doing a data transfer");
f945405c 1995 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1996 return;
f945405c
BD		 1997
1998 /* The controller does not support the end-of-busy IRQ,
1999 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2000 }
2001
2002 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2003 sdhci_finish_command(host);
d129bceb
PO		 2004}
2005
0957c333 2006#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2007static void sdhci_show_adma_error(struct sdhci_host *host)
2008{
2009 const char *name = mmc_hostname(host->mmc);
2010 u8 *desc = host->adma_desc;
2011 __le32 *dma;
2012 __le16 *len;
2013 u8 attr;
2014
2015 sdhci_dumpregs(host);
2016
2017 while (true) {
2018 dma = (__le32 *)(desc + 4);
2019 len = (__le16 *)(desc + 2);
2020 attr = *desc;
2021
2022 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2023 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2024
2025 desc += 8;
2026
2027 if (attr & 2)
2028 break;
2029 }
2030}
2031#else
2032static void sdhci_show_adma_error(struct sdhci_host *host) { }
2033#endif
2034
d129bceb
PO		 2035static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2036{
2037 BUG_ON(intmask == 0);
2038
b513ea25
AN		 2039 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2040 if (intmask & SDHCI_INT_DATA_AVAIL) {
2041 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2042 MMC_SEND_TUNING_BLOCK) {
2043 host->tuning_done = 1;
2044 wake_up(&host->buf_ready_int);
2045 return;
2046 }
2047 }
2048
d129bceb
PO		 2049 if (!host->data) {
2050 /*
e809517f
PO		 2051 * The "data complete" interrupt is also used to
2052 * indicate that a busy state has ended. See comment
2053 * above in sdhci_cmd_irq().
d129bceb 2054 */
e809517f
PO		 2055 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2056 if (intmask & SDHCI_INT_DATA_END) {
2057 sdhci_finish_command(host);
2058 return;
2059 }
2060 }
d129bceb 2061
b67ac3f3
PO		 2062 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2063 "though no data operation was in progress.\n",
2064 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2065 sdhci_dumpregs(host);
2066
2067 return;
2068 }
2069
2070 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2071 host->data->error = -ETIMEDOUT;
22113efd
AL		 2072 else if (intmask & SDHCI_INT_DATA_END_BIT)
2073 host->data->error = -EILSEQ;
2074 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2075 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2076 != MMC_BUS_TEST_R)
17b0429d 2077 host->data->error = -EILSEQ;
6882a8c0
BD		 2078 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2079 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2080 sdhci_show_adma_error(host);
2134a922 2081 host->data->error = -EIO;
6882a8c0 2082 }
d129bceb 2083
17b0429d 2084 if (host->data->error)
d129bceb
PO		 2085 sdhci_finish_data(host);
2086 else {
a406f5a3 2087 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2088 sdhci_transfer_pio(host);
2089
6ba736a1
PO		 2090 /*
2091 * We currently don't do anything fancy with DMA
2092 * boundaries, but as we can't disable the feature
2093 * we need to at least restart the transfer.
f6a03cbf
MV		 2094 *
2095 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2096 * should return a valid address to continue from, but as
2097 * some controllers are faulty, don't trust them.
6ba736a1 2098 */
f6a03cbf
MV		 2099 if (intmask & SDHCI_INT_DMA_END) {
2100 u32 dmastart, dmanow;
2101 dmastart = sg_dma_address(host->data->sg);
2102 dmanow = dmastart + host->data->bytes_xfered;
2103 /*
2104 * Force update to the next DMA block boundary.
2105 */
2106 dmanow = (dmanow &
2107 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2108 SDHCI_DEFAULT_BOUNDARY_SIZE;
2109 host->data->bytes_xfered = dmanow - dmastart;
2110 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2111 " next 0x%08x\n",
2112 mmc_hostname(host->mmc), dmastart,
2113 host->data->bytes_xfered, dmanow);
2114 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2115 }
6ba736a1 2116
e538fbe8
PO		 2117 if (intmask & SDHCI_INT_DATA_END) {
2118 if (host->cmd) {
2119 /*
2120 * Data managed to finish before the
2121 * command completed. Make sure we do
2122 * things in the proper order.
2123 */
2124 host->data_early = 1;
2125 } else {
2126 sdhci_finish_data(host);
2127 }
2128 }
d129bceb
PO		 2129 }
2130}
2131
7d12e780 2132static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2133{
2134 irqreturn_t result;
2135 struct sdhci_host* host = dev_id;
2136 u32 intmask;
f75979b7 2137 int cardint = 0;
d129bceb
PO		 2138
2139 spin_lock(&host->lock);
2140
4e4141a5 2141 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2142
62df67a5 2143 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2144 result = IRQ_NONE;
2145 goto out;
2146 }
2147
b69c9058
PO		 2148 DBG("*** %s got interrupt: 0x%08x\n",
2149 mmc_hostname(host->mmc), intmask);
d129bceb 2150
3192a28f 2151 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
4e4141a5
AV		 2152 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2153 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
d129bceb 2154 tasklet_schedule(&host->card_tasklet);
3192a28f 2155 }
d129bceb 2156
3192a28f 2157 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2158
3192a28f 2159 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2160 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2161 SDHCI_INT_STATUS);
3192a28f 2162 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2163 }
2164
2165 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2166 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2167 SDHCI_INT_STATUS);
3192a28f 2168 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2169 }
2170
2171 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2172
964f9ce2
PO		 2173 intmask &= ~SDHCI_INT_ERROR;
2174
d129bceb 2175 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 2176 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 2177 mmc_hostname(host->mmc));
4e4141a5 2178 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2179 }
2180
9d26a5d3 2181 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2182
f75979b7
PO		 2183 if (intmask & SDHCI_INT_CARD_INT)
2184 cardint = 1;
2185
2186 intmask &= ~SDHCI_INT_CARD_INT;
2187
3192a28f 2188 if (intmask) {
acf1da45 2189 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 2190 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 2191 sdhci_dumpregs(host);
2192
4e4141a5 2193 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2194 }
d129bceb
PO		 2195
2196 result = IRQ_HANDLED;
2197
5f25a66f 2198 mmiowb();
d129bceb
PO		 2199out:
2200 spin_unlock(&host->lock);
2201
f75979b7
PO		 2202 /*
2203 * We have to delay this as it calls back into the driver.
2204 */
2205 if (cardint)
2206 mmc_signal_sdio_irq(host->mmc);
2207
d129bceb
PO		 2208 return result;
2209}
2210
2211/*****************************************************************************\
2212 * *
2213 * Suspend/resume *
2214 * *
2215\*****************************************************************************/
2216
2217#ifdef CONFIG_PM
2218
b8c86fc5 2219int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 2220{
b8c86fc5 2221 int ret;
a715dfc7 2222
7260cf5e
AV		 2223 sdhci_disable_card_detection(host);
2224
cf2b5eea
AN		 2225 /* Disable tuning since we are suspending */
2226 if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2227 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2228 host->flags &= ~SDHCI_NEEDS_RETUNING;
2229 mod_timer(&host->tuning_timer, jiffies +
2230 host->tuning_count * HZ);
2231 }
2232
1a13f8fa 2233 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 2234 if (ret)
2235 return ret;
a715dfc7 2236
b8c86fc5 2237 free_irq(host->irq, host);
d129bceb 2238
9bea3c85
MS		 2239 if (host->vmmc)
2240 ret = regulator_disable(host->vmmc);
2241
2242 return ret;
d129bceb
PO		 2243}
2244
b8c86fc5 2245EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2246
b8c86fc5
PO		 2247int sdhci_resume_host(struct sdhci_host *host)
2248{
2249 int ret;
d129bceb 2250
9bea3c85
MS		 2251 if (host->vmmc) {
2252 int ret = regulator_enable(host->vmmc);
2253 if (ret)
2254 return ret;
2255 }
2256
2257
a13abc7b 2258 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2259 if (host->ops->enable_dma)
2260 host->ops->enable_dma(host);
2261 }
d129bceb 2262
b8c86fc5
PO		 2263 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2264 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2265 if (ret)
2266 return ret;
d129bceb 2267
2f4cbb3d 2268 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 2269 mmiowb();
2270
2271 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2272 sdhci_enable_card_detection(host);
2273
cf2b5eea
AN		 2274 /* Set the re-tuning expiration flag */
2275 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2276 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2277 host->flags |= SDHCI_NEEDS_RETUNING;
2278
2f4cbb3d 2279 return ret;
d129bceb
PO		 2280}
2281
b8c86fc5 2282EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2283
5f619704
DD		 2284void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2285{
2286 u8 val;
2287 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2288 val |= SDHCI_WAKE_ON_INT;
2289 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2290}
2291
2292EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2293
d129bceb
PO		 2294#endif /* CONFIG_PM */
2295
2296/*****************************************************************************\
2297 * *
b8c86fc5 2298 * Device allocation/registration *
d129bceb
PO		 2299 * *
2300\*****************************************************************************/
2301
b8c86fc5
PO		 2302struct sdhci_host *sdhci_alloc_host(struct device *dev,
2303 size_t priv_size)
d129bceb 2304{
d129bceb
PO		 2305 struct mmc_host *mmc;
2306 struct sdhci_host *host;
2307
b8c86fc5 2308 WARN_ON(dev == NULL);
d129bceb 2309
b8c86fc5 2310 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2311 if (!mmc)
b8c86fc5 2312 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2313
2314 host = mmc_priv(mmc);
2315 host->mmc = mmc;
2316
b8c86fc5
PO		 2317 return host;
2318}
8a4da143 2319
b8c86fc5 2320EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2321
b8c86fc5
PO		 2322int sdhci_add_host(struct sdhci_host *host)
2323{
2324 struct mmc_host *mmc;
f2119df6
AN		 2325 u32 caps[2];
2326 u32 max_current_caps;
2327 unsigned int ocr_avail;
b8c86fc5 2328 int ret;
d129bceb 2329
b8c86fc5
PO		 2330 WARN_ON(host == NULL);
2331 if (host == NULL)
2332 return -EINVAL;
d129bceb 2333
b8c86fc5 2334 mmc = host->mmc;
d129bceb 2335
b8c86fc5
PO		 2336 if (debug_quirks)
2337 host->quirks = debug_quirks;
d129bceb 2338
d96649ed
PO		 2339 sdhci_reset(host, SDHCI_RESET_ALL);
2340
4e4141a5 2341 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2342 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2343 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2344 if (host->version > SDHCI_SPEC_300) {
4a965505 2345 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 2346 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2347 host->version);
4a965505
PO		 2348 }
2349
f2119df6 2350 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2351 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2352
f2119df6
AN		 2353 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2354 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2355
b8c86fc5 2356 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2357 host->flags |= SDHCI_USE_SDMA;
f2119df6 2358 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2359 DBG("Controller doesn't have SDMA capability\n");
67435274 2360 else
a13abc7b 2361 host->flags |= SDHCI_USE_SDMA;
d129bceb 2362
b8c86fc5 2363 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2364 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2365 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2366 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2367 }
2368
f2119df6
AN		 2369 if ((host->version >= SDHCI_SPEC_200) &&
2370 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2371 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2372
2373 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2374 (host->flags & SDHCI_USE_ADMA)) {
2375 DBG("Disabling ADMA as it is marked broken\n");
2376 host->flags &= ~SDHCI_USE_ADMA;
2377 }
2378
a13abc7b 2379 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2380 if (host->ops->enable_dma) {
2381 if (host->ops->enable_dma(host)) {
2382 printk(KERN_WARNING "%s: No suitable DMA "
2383 "available. Falling back to PIO.\n",
2384 mmc_hostname(mmc));
a13abc7b
RR		 2385 host->flags &=
2386 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2387 }
d129bceb
PO		 2388 }
2389 }
2390
2134a922
PO		 2391 if (host->flags & SDHCI_USE_ADMA) {
2392 /*
2393 * We need to allocate descriptors for all sg entries
2394 * (128) and potentially one alignment transfer for
2395 * each of those entries.
2396 */
2397 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2398 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2399 if (!host->adma_desc || !host->align_buffer) {
2400 kfree(host->adma_desc);
2401 kfree(host->align_buffer);
2402 printk(KERN_WARNING "%s: Unable to allocate ADMA "
2403 "buffers. Falling back to standard DMA.\n",
2404 mmc_hostname(mmc));
2405 host->flags &= ~SDHCI_USE_ADMA;
2406 }
2407 }
2408
7659150c
PO		 2409 /*
2410 * If we use DMA, then it's up to the caller to set the DMA
2411 * mask, but PIO does not need the hw shim so we set a new
2412 * mask here in that case.
2413 */
a13abc7b 2414 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2415 host->dma_mask = DMA_BIT_MASK(64);
2416 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2417 }
d129bceb 2418
c4687d5f 2419 if (host->version >= SDHCI_SPEC_300)
f2119df6 2420 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2421 >> SDHCI_CLOCK_BASE_SHIFT;
2422 else
f2119df6 2423 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2424 >> SDHCI_CLOCK_BASE_SHIFT;
2425
4240ff0a 2426 host->max_clk *= 1000000;
f27f47ef
AV		 2427 if (host->max_clk == 0 || host->quirks &
2428 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a
BD		 2429 if (!host->ops->get_max_clock) {
2430 printk(KERN_ERR
2431 "%s: Hardware doesn't specify base clock "
2432 "frequency.\n", mmc_hostname(mmc));
2433 return -ENODEV;
2434 }
2435 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2436 }
d129bceb 2437
1c8cde92 2438 host->timeout_clk =
f2119df6 2439 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1c8cde92 2440 if (host->timeout_clk == 0) {
81b39802
AV		 2441 if (host->ops->get_timeout_clock) {
2442 host->timeout_clk = host->ops->get_timeout_clock(host);
2443 } else if (!(host->quirks &
2444 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4240ff0a
BD		 2445 printk(KERN_ERR
2446 "%s: Hardware doesn't specify timeout clock "
2447 "frequency.\n", mmc_hostname(mmc));
2448 return -ENODEV;
2449 }
1c8cde92 2450 }
f2119df6 2451 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
1c8cde92 2452 host->timeout_clk *= 1000;
d129bceb 2453
c3ed3877
AN		 2454 /*
2455 * In case of Host Controller v3.00, find out whether clock
2456 * multiplier is supported.
2457 */
2458 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2459 SDHCI_CLOCK_MUL_SHIFT;
2460
2461 /*
2462 * In case the value in Clock Multiplier is 0, then programmable
2463 * clock mode is not supported, otherwise the actual clock
2464 * multiplier is one more than the value of Clock Multiplier
2465 * in the Capabilities Register.
2466 */
2467 if (host->clk_mul)
2468 host->clk_mul += 1;
2469
d129bceb
PO		 2470 /*
2471 * Set host parameters.
2472 */
2473 mmc->ops = &sdhci_ops;
c3ed3877 2474 mmc->f_max = host->max_clk;
ce5f036b 2475 if (host->ops->get_min_clock)
a9e58f25 2476 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2477 else if (host->version >= SDHCI_SPEC_300) {
2478 if (host->clk_mul) {
2479 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2480 mmc->f_max = host->max_clk * host->clk_mul;
2481 } else
2482 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2483 } else
0397526d 2484 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2485
e89d456f
AW		 2486 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2487
2488 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2489 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2490
15ec4461
PR		 2491 /*
2492 * A controller may support 8-bit width, but the board itself
2493 * might not have the pins brought out. Boards that support
2494 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2495 * their platform code before calling sdhci_add_host(), and we
2496 * won't assume 8-bit width for hosts without that CAP.
2497 */
5fe23c7f 2498 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2499 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2500
f2119df6 2501 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2502 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2503
176d1ed4
JC		 2504 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2505 mmc_card_is_removable(mmc))
68d1fb7e
AV		 2506 mmc->caps |= MMC_CAP_NEEDS_POLL;
2507
f2119df6
AN		 2508 /* UHS-I mode(s) supported by the host controller. */
2509 if (host->version >= SDHCI_SPEC_300)
2510 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2511
2512 /* SDR104 supports also implies SDR50 support */
2513 if (caps[1] & SDHCI_SUPPORT_SDR104)
2514 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2515 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2516 mmc->caps |= MMC_CAP_UHS_SDR50;
2517
2518 if (caps[1] & SDHCI_SUPPORT_DDR50)
2519 mmc->caps |= MMC_CAP_UHS_DDR50;
2520
b513ea25
AN		 2521 /* Does the host needs tuning for SDR50? */
2522 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2523 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2524
d6d50a15
AN		 2525 /* Driver Type(s) (A, C, D) supported by the host */
2526 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2527 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2528 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2529 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2530 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2531 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2532
cf2b5eea
AN		 2533 /* Initial value for re-tuning timer count */
2534 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2535 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2536
2537 /*
2538 * In case Re-tuning Timer is not disabled, the actual value of
2539 * re-tuning timer will be 2 ^ (n - 1).
2540 */
2541 if (host->tuning_count)
2542 host->tuning_count = 1 << (host->tuning_count - 1);
2543
2544 /* Re-tuning mode supported by the Host Controller */
2545 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2546 SDHCI_RETUNING_MODE_SHIFT;
2547
8f230f45 2548 ocr_avail = 0;
f2119df6
AN		 2549 /*
2550 * According to SD Host Controller spec v3.00, if the Host System
2551 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2552 * the value is meaningful only if Voltage Support in the Capabilities
2553 * register is set. The actual current value is 4 times the register
2554 * value.
2555 */
2556 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2557
2558 if (caps[0] & SDHCI_CAN_VDD_330) {
2559 int max_current_330;
2560
8f230f45 2561 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6
AN		 2562
2563 max_current_330 = ((max_current_caps &
2564 SDHCI_MAX_CURRENT_330_MASK) >>
2565 SDHCI_MAX_CURRENT_330_SHIFT) *
2566 SDHCI_MAX_CURRENT_MULTIPLIER;
2567
2568 if (max_current_330 > 150)
2569 mmc->caps |= MMC_CAP_SET_XPC_330;
2570 }
2571 if (caps[0] & SDHCI_CAN_VDD_300) {
2572 int max_current_300;
2573
8f230f45 2574 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6
AN		 2575
2576 max_current_300 = ((max_current_caps &
2577 SDHCI_MAX_CURRENT_300_MASK) >>
2578 SDHCI_MAX_CURRENT_300_SHIFT) *
2579 SDHCI_MAX_CURRENT_MULTIPLIER;
2580
2581 if (max_current_300 > 150)
2582 mmc->caps |= MMC_CAP_SET_XPC_300;
2583 }
2584 if (caps[0] & SDHCI_CAN_VDD_180) {
2585 int max_current_180;
2586
8f230f45
TI		 2587 ocr_avail |= MMC_VDD_165_195;
2588
f2119df6
AN		 2589 max_current_180 = ((max_current_caps &
2590 SDHCI_MAX_CURRENT_180_MASK) >>
2591 SDHCI_MAX_CURRENT_180_SHIFT) *
2592 SDHCI_MAX_CURRENT_MULTIPLIER;
2593
2594 if (max_current_180 > 150)
2595 mmc->caps |= MMC_CAP_SET_XPC_180;
5371c927
AN		 2596
2597 /* Maximum current capabilities of the host at 1.8V */
2598 if (max_current_180 >= 800)
2599 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2600 else if (max_current_180 >= 600)
2601 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2602 else if (max_current_180 >= 400)
2603 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2604 else
2605 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
f2119df6
AN		 2606 }
2607
8f230f45
TI		 2608 mmc->ocr_avail = ocr_avail;
2609 mmc->ocr_avail_sdio = ocr_avail;
2610 if (host->ocr_avail_sdio)
2611 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2612 mmc->ocr_avail_sd = ocr_avail;
2613 if (host->ocr_avail_sd)
2614 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2615 else /* normal SD controllers don't support 1.8V */
2616 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2617 mmc->ocr_avail_mmc = ocr_avail;
2618 if (host->ocr_avail_mmc)
2619 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2620
2621 if (mmc->ocr_avail == 0) {
2622 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 2623 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2624 return -ENODEV;
146ad66e
PO		 2625 }
2626
d129bceb
PO		 2627 spin_lock_init(&host->lock);
2628
2629 /*
2134a922
PO		 2630 * Maximum number of segments. Depends on if the hardware
2631 * can do scatter/gather or not.
d129bceb 2632 */
2134a922 2633 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2634 mmc->max_segs = 128;
a13abc7b 2635 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2636 mmc->max_segs = 1;
2134a922 2637 else /* PIO */
a36274e0 2638 mmc->max_segs = 128;
d129bceb
PO		 2639
2640 /*
bab76961 2641 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2642 * size (512KiB).
d129bceb 2643 */
55db890a 2644 mmc->max_req_size = 524288;
d129bceb
PO		 2645
2646 /*
2647 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2648 * of bytes. When doing hardware scatter/gather, each entry cannot
2649 * be larger than 64 KiB though.
d129bceb 2650 */
30652aa3
OJ		 2651 if (host->flags & SDHCI_USE_ADMA) {
2652 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2653 mmc->max_seg_size = 65535;
2654 else
2655 mmc->max_seg_size = 65536;
2656 } else {
2134a922 2657 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2658 }
d129bceb 2659
fe4a3c7a
PO		 2660 /*
2661 * Maximum block size. This varies from controller to controller and
2662 * is specified in the capabilities register.
2663 */
0633f654
AV		 2664 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2665 mmc->max_blk_size = 2;
2666 } else {
f2119df6 2667 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2668 SDHCI_MAX_BLOCK_SHIFT;
2669 if (mmc->max_blk_size >= 3) {
2670 printk(KERN_WARNING "%s: Invalid maximum block size, "
2671 "assuming 512 bytes\n", mmc_hostname(mmc));
2672 mmc->max_blk_size = 0;
2673 }
2674 }
2675
2676 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 2677
55db890a
PO		 2678 /*
2679 * Maximum block count.
2680 */
1388eefd 2681 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 2682
d129bceb
PO		 2683 /*
2684 * Init tasklets.
2685 */
2686 tasklet_init(&host->card_tasklet,
2687 sdhci_tasklet_card, (unsigned long)host);
2688 tasklet_init(&host->finish_tasklet,
2689 sdhci_tasklet_finish, (unsigned long)host);
2690
e4cad1b5 2691 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2692
cf2b5eea 2693 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 2694 init_waitqueue_head(&host->buf_ready_int);
2695
cf2b5eea
AN		 2696 /* Initialize re-tuning timer */
2697 init_timer(&host->tuning_timer);
2698 host->tuning_timer.data = (unsigned long)host;
2699 host->tuning_timer.function = sdhci_tuning_timer;
2700 }
2701
dace1453 2702 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2703 mmc_hostname(mmc), host);
d129bceb 2704 if (ret)
8ef1a143 2705 goto untasklet;
d129bceb 2706
9bea3c85
MS		 2707 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2708 if (IS_ERR(host->vmmc)) {
2709 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2710 host->vmmc = NULL;
2711 } else {
2712 regulator_enable(host->vmmc);
2713 }
2714
2f4cbb3d 2715 sdhci_init(host, 0);
d129bceb
PO		 2716
2717#ifdef CONFIG_MMC_DEBUG
2718 sdhci_dumpregs(host);
2719#endif
2720
f9134319 2721#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2722 snprintf(host->led_name, sizeof(host->led_name),
2723 "%s::", mmc_hostname(mmc));
2724 host->led.name = host->led_name;
2f730fec
PO		 2725 host->led.brightness = LED_OFF;
2726 host->led.default_trigger = mmc_hostname(mmc);
2727 host->led.brightness_set = sdhci_led_control;
2728
b8c86fc5 2729 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2730 if (ret)
2731 goto reset;
2732#endif
2733
5f25a66f
PO		 2734 mmiowb();
2735
d129bceb
PO		 2736 mmc_add_host(mmc);
2737
a13abc7b 2738 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2739 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2740 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2741 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2742
7260cf5e
AV		 2743 sdhci_enable_card_detection(host);
2744
d129bceb
PO		 2745 return 0;
2746
f9134319 2747#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2748reset:
2749 sdhci_reset(host, SDHCI_RESET_ALL);
2750 free_irq(host->irq, host);
2751#endif
8ef1a143 2752untasklet:
d129bceb
PO		 2753 tasklet_kill(&host->card_tasklet);
2754 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2755
2756 return ret;
2757}
2758
b8c86fc5 2759EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2760
1e72859e 2761void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2762{
1e72859e
PO		 2763 unsigned long flags;
2764
2765 if (dead) {
2766 spin_lock_irqsave(&host->lock, flags);
2767
2768 host->flags |= SDHCI_DEVICE_DEAD;
2769
2770 if (host->mrq) {
2771 printk(KERN_ERR "%s: Controller removed during "
2772 " transfer!\n", mmc_hostname(host->mmc));
2773
2774 host->mrq->cmd->error = -ENOMEDIUM;
2775 tasklet_schedule(&host->finish_tasklet);
2776 }
2777
2778 spin_unlock_irqrestore(&host->lock, flags);
2779 }
2780
7260cf5e
AV		 2781 sdhci_disable_card_detection(host);
2782
b8c86fc5 2783 mmc_remove_host(host->mmc);
d129bceb 2784
f9134319 2785#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2786 led_classdev_unregister(&host->led);
2787#endif
2788
1e72859e
PO		 2789 if (!dead)
2790 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 2791
2792 free_irq(host->irq, host);
2793
2794 del_timer_sync(&host->timer);
cf2b5eea
AN		 2795 if (host->version >= SDHCI_SPEC_300)
2796 del_timer_sync(&host->tuning_timer);
d129bceb
PO		 2797
2798 tasklet_kill(&host->card_tasklet);
2799 tasklet_kill(&host->finish_tasklet);
2134a922 2800
9bea3c85
MS		 2801 if (host->vmmc) {
2802 regulator_disable(host->vmmc);
2803 regulator_put(host->vmmc);
2804 }
2805
2134a922
PO		 2806 kfree(host->adma_desc);
2807 kfree(host->align_buffer);
2808
2809 host->adma_desc = NULL;
2810 host->align_buffer = NULL;
d129bceb
PO		 2811}
2812
b8c86fc5 2813EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 2814
b8c86fc5 2815void sdhci_free_host(struct sdhci_host *host)
d129bceb 2816{
b8c86fc5 2817 mmc_free_host(host->mmc);
d129bceb
PO		 2818}
2819
b8c86fc5 2820EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 2821
2822/*****************************************************************************\
2823 * *
2824 * Driver init/exit *
2825 * *
2826\*****************************************************************************/
2827
2828static int __init sdhci_drv_init(void)
2829{
2830 printk(KERN_INFO DRIVER_NAME
52fbf9c9 2831 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 2832 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2833
b8c86fc5 2834 return 0;
d129bceb
PO		 2835}
2836
2837static void __exit sdhci_drv_exit(void)
2838{
d129bceb
PO		 2839}
2840
2841module_init(sdhci_drv_init);
2842module_exit(sdhci_drv_exit);
2843
df673b22 2844module_param(debug_quirks, uint, 0444);
67435274 2845
32710e8f 2846MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 2847MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 2848MODULE_LICENSE("GPL");
67435274 2849
df673b22 2850MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux kernel - Deliverables
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