[deliverable/linux.git] / drivers / mmc / host / sdhci.h

/*
 *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
 *
 * Header file for Host Controller registers and I/O accessors.
 *
 *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */
#ifndef __SDHCI_HW_H
#define __SDHCI_HW_H

#include <linux/scatterlist.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/io.h>

#include <linux/mmc/sdhci.h>

/*
 * Controller registers
 */

#define SDHCI_DMA_ADDRESS	0x00
#define SDHCI_ARGUMENT2		SDHCI_DMA_ADDRESS

#define SDHCI_BLOCK_SIZE	0x04
#define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))

#define SDHCI_BLOCK_COUNT	0x06

#define SDHCI_ARGUMENT		0x08

#define SDHCI_TRANSFER_MODE	0x0C
#define  SDHCI_TRNS_DMA		0x01
#define  SDHCI_TRNS_BLK_CNT_EN	0x02
#define  SDHCI_TRNS_AUTO_CMD12	0x04
#define  SDHCI_TRNS_AUTO_CMD23	0x08
#define  SDHCI_TRNS_READ	0x10
#define  SDHCI_TRNS_MULTI	0x20

#define SDHCI_COMMAND		0x0E
#define  SDHCI_CMD_RESP_MASK	0x03
#define  SDHCI_CMD_CRC		0x08
#define  SDHCI_CMD_INDEX	0x10
#define  SDHCI_CMD_DATA		0x20
#define  SDHCI_CMD_ABORTCMD	0xC0

#define  SDHCI_CMD_RESP_NONE	0x00
#define  SDHCI_CMD_RESP_LONG	0x01
#define  SDHCI_CMD_RESP_SHORT	0x02
#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03

#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)

#define SDHCI_RESPONSE		0x10

#define SDHCI_BUFFER		0x20

#define SDHCI_PRESENT_STATE	0x24
#define  SDHCI_CMD_INHIBIT	0x00000001
#define  SDHCI_DATA_INHIBIT	0x00000002
#define  SDHCI_DOING_WRITE	0x00000100
#define  SDHCI_DOING_READ	0x00000200
#define  SDHCI_SPACE_AVAILABLE	0x00000400
#define  SDHCI_DATA_AVAILABLE	0x00000800
#define  SDHCI_CARD_PRESENT	0x00010000
#define  SDHCI_WRITE_PROTECT	0x00080000
#define  SDHCI_DATA_LVL_MASK	0x00F00000
#define   SDHCI_DATA_LVL_SHIFT	20

#define SDHCI_HOST_CONTROL	0x28
#define  SDHCI_CTRL_LED		0x01
#define  SDHCI_CTRL_4BITBUS	0x02
#define  SDHCI_CTRL_HISPD	0x04
#define  SDHCI_CTRL_DMA_MASK	0x18
#define   SDHCI_CTRL_SDMA	0x00
#define   SDHCI_CTRL_ADMA1	0x08
#define   SDHCI_CTRL_ADMA32	0x10
#define   SDHCI_CTRL_ADMA64	0x18
#define   SDHCI_CTRL_8BITBUS	0x20

#define SDHCI_POWER_CONTROL	0x29
#define  SDHCI_POWER_ON		0x01
#define  SDHCI_POWER_180	0x0A
#define  SDHCI_POWER_300	0x0C
#define  SDHCI_POWER_330	0x0E

#define SDHCI_BLOCK_GAP_CONTROL	0x2A

#define SDHCI_WAKE_UP_CONTROL	0x2B
#define  SDHCI_WAKE_ON_INT	0x01
#define  SDHCI_WAKE_ON_INSERT	0x02
#define  SDHCI_WAKE_ON_REMOVE	0x04

#define SDHCI_CLOCK_CONTROL	0x2C
#define  SDHCI_DIVIDER_SHIFT	8
#define  SDHCI_DIVIDER_HI_SHIFT	6
#define  SDHCI_DIV_MASK	0xFF
#define  SDHCI_DIV_MASK_LEN	8
#define  SDHCI_DIV_HI_MASK	0x300
#define  SDHCI_PROG_CLOCK_MODE	0x0020
#define  SDHCI_CLOCK_CARD_EN	0x0004
#define  SDHCI_CLOCK_INT_STABLE	0x0002
#define  SDHCI_CLOCK_INT_EN	0x0001

#define SDHCI_TIMEOUT_CONTROL	0x2E

#define SDHCI_SOFTWARE_RESET	0x2F
#define  SDHCI_RESET_ALL	0x01
#define  SDHCI_RESET_CMD	0x02
#define  SDHCI_RESET_DATA	0x04

#define SDHCI_INT_STATUS	0x30
#define SDHCI_INT_ENABLE	0x34
#define SDHCI_SIGNAL_ENABLE	0x38
#define  SDHCI_INT_RESPONSE	0x00000001
#define  SDHCI_INT_DATA_END	0x00000002
#define  SDHCI_INT_DMA_END	0x00000008
#define  SDHCI_INT_SPACE_AVAIL	0x00000010
#define  SDHCI_INT_DATA_AVAIL	0x00000020
#define  SDHCI_INT_CARD_INSERT	0x00000040
#define  SDHCI_INT_CARD_REMOVE	0x00000080
#define  SDHCI_INT_CARD_INT	0x00000100
#define  SDHCI_INT_ERROR	0x00008000
#define  SDHCI_INT_TIMEOUT	0x00010000
#define  SDHCI_INT_CRC		0x00020000
#define  SDHCI_INT_END_BIT	0x00040000
#define  SDHCI_INT_INDEX	0x00080000
#define  SDHCI_INT_DATA_TIMEOUT	0x00100000
#define  SDHCI_INT_DATA_CRC	0x00200000
#define  SDHCI_INT_DATA_END_BIT	0x00400000
#define  SDHCI_INT_BUS_POWER	0x00800000
#define  SDHCI_INT_ACMD12ERR	0x01000000
#define  SDHCI_INT_ADMA_ERROR	0x02000000

#define  SDHCI_INT_NORMAL_MASK	0x00007FFF
#define  SDHCI_INT_ERROR_MASK	0xFFFF8000

#define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
#define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
#define SDHCI_INT_ALL_MASK	((unsigned int)-1)

#define SDHCI_ACMD12_ERR	0x3C

#define SDHCI_HOST_CONTROL2		0x3E
#define  SDHCI_CTRL_UHS_MASK		0x0007
#define   SDHCI_CTRL_UHS_SDR12		0x0000
#define   SDHCI_CTRL_UHS_SDR25		0x0001
#define   SDHCI_CTRL_UHS_SDR50		0x0002
#define   SDHCI_CTRL_UHS_SDR104		0x0003
#define   SDHCI_CTRL_UHS_DDR50		0x0004
#define  SDHCI_CTRL_VDD_180		0x0008
#define  SDHCI_CTRL_DRV_TYPE_MASK	0x0030
#define   SDHCI_CTRL_DRV_TYPE_B		0x0000
#define   SDHCI_CTRL_DRV_TYPE_A		0x0010
#define   SDHCI_CTRL_DRV_TYPE_C		0x0020
#define   SDHCI_CTRL_DRV_TYPE_D		0x0030
#define  SDHCI_CTRL_EXEC_TUNING		0x0040
#define  SDHCI_CTRL_TUNED_CLK		0x0080
#define  SDHCI_CTRL_PRESET_VAL_ENABLE	0x8000

#define SDHCI_CAPABILITIES	0x40
#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
#define  SDHCI_TIMEOUT_CLK_SHIFT 0
#define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
#define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
#define  SDHCI_CLOCK_BASE_SHIFT	8
#define  SDHCI_MAX_BLOCK_MASK	0x00030000
#define  SDHCI_MAX_BLOCK_SHIFT  16
#define  SDHCI_CAN_DO_8BIT	0x00040000
#define  SDHCI_CAN_DO_ADMA2	0x00080000
#define  SDHCI_CAN_DO_ADMA1	0x00100000
#define  SDHCI_CAN_DO_HISPD	0x00200000
#define  SDHCI_CAN_DO_SDMA	0x00400000
#define  SDHCI_CAN_VDD_330	0x01000000
#define  SDHCI_CAN_VDD_300	0x02000000
#define  SDHCI_CAN_VDD_180	0x04000000
#define  SDHCI_CAN_64BIT	0x10000000

#define  SDHCI_SUPPORT_SDR50	0x00000001
#define  SDHCI_SUPPORT_SDR104	0x00000002
#define  SDHCI_SUPPORT_DDR50	0x00000004
#define  SDHCI_DRIVER_TYPE_A	0x00000010
#define  SDHCI_DRIVER_TYPE_C	0x00000020
#define  SDHCI_DRIVER_TYPE_D	0x00000040
#define  SDHCI_RETUNING_TIMER_COUNT_MASK	0x00000F00
#define  SDHCI_RETUNING_TIMER_COUNT_SHIFT	8
#define  SDHCI_USE_SDR50_TUNING			0x00002000
#define  SDHCI_RETUNING_MODE_MASK		0x0000C000
#define  SDHCI_RETUNING_MODE_SHIFT		14
#define  SDHCI_CLOCK_MUL_MASK	0x00FF0000
#define  SDHCI_CLOCK_MUL_SHIFT	16

#define SDHCI_CAPABILITIES_1	0x44

#define SDHCI_MAX_CURRENT		0x48
#define  SDHCI_MAX_CURRENT_330_MASK	0x0000FF
#define  SDHCI_MAX_CURRENT_330_SHIFT	0
#define  SDHCI_MAX_CURRENT_300_MASK	0x00FF00
#define  SDHCI_MAX_CURRENT_300_SHIFT	8
#define  SDHCI_MAX_CURRENT_180_MASK	0xFF0000
#define  SDHCI_MAX_CURRENT_180_SHIFT	16
#define   SDHCI_MAX_CURRENT_MULTIPLIER	4

/* 4C-4F reserved for more max current */

#define SDHCI_SET_ACMD12_ERROR	0x50
#define SDHCI_SET_INT_ERROR	0x52

#define SDHCI_ADMA_ERROR	0x54

/* 55-57 reserved */

#define SDHCI_ADMA_ADDRESS	0x58

/* 60-FB reserved */

#define SDHCI_SLOT_INT_STATUS	0xFC

#define SDHCI_HOST_VERSION	0xFE
#define  SDHCI_VENDOR_VER_MASK	0xFF00
#define  SDHCI_VENDOR_VER_SHIFT	8
#define  SDHCI_SPEC_VER_MASK	0x00FF
#define  SDHCI_SPEC_VER_SHIFT	0
#define   SDHCI_SPEC_100	0
#define   SDHCI_SPEC_200	1
#define   SDHCI_SPEC_300	2

/*
 * End of controller registers.
 */

#define SDHCI_MAX_DIV_SPEC_200	256
#define SDHCI_MAX_DIV_SPEC_300	2046

/*
 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
 */
#define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
#define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)

struct sdhci_ops {
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	u32		(*read_l)(struct sdhci_host *host, int reg);
	u16		(*read_w)(struct sdhci_host *host, int reg);
	u8		(*read_b)(struct sdhci_host *host, int reg);
	void		(*write_l)(struct sdhci_host *host, u32 val, int reg);
	void		(*write_w)(struct sdhci_host *host, u16 val, int reg);
	void		(*write_b)(struct sdhci_host *host, u8 val, int reg);
#endif

	void	(*set_clock)(struct sdhci_host *host, unsigned int clock);

	int		(*enable_dma)(struct sdhci_host *host);
	unsigned int	(*get_max_clock)(struct sdhci_host *host);
	unsigned int	(*get_min_clock)(struct sdhci_host *host);
	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
	int		(*platform_8bit_width)(struct sdhci_host *host,
					       int width);
	void (*platform_send_init_74_clocks)(struct sdhci_host *host,
					     u8 power_mode);
	unsigned int    (*get_ro)(struct sdhci_host *host);
	void	(*platform_reset_enter)(struct sdhci_host *host, u8 mask);
	void	(*platform_reset_exit)(struct sdhci_host *host, u8 mask);
	int	(*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
	void	(*hw_reset)(struct sdhci_host *host);
};

#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS

static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	if (unlikely(host->ops->write_l))
		host->ops->write_l(host, val, reg);
	else
		writel(val, host->ioaddr + reg);
}

static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	if (unlikely(host->ops->write_w))
		host->ops->write_w(host, val, reg);
	else
		writew(val, host->ioaddr + reg);
}

static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
	if (unlikely(host->ops->write_b))
		host->ops->write_b(host, val, reg);
	else
		writeb(val, host->ioaddr + reg);
}

static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_l))
		return host->ops->read_l(host, reg);
	else
		return readl(host->ioaddr + reg);
}

static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_w))
		return host->ops->read_w(host, reg);
	else
		return readw(host->ioaddr + reg);
}

static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_b))
		return host->ops->read_b(host, reg);
	else
		return readb(host->ioaddr + reg);
}

#else

static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	writel(val, host->ioaddr + reg);
}

static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	writew(val, host->ioaddr + reg);
}

static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
	writeb(val, host->ioaddr + reg);
}

static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
	return readl(host->ioaddr + reg);
}

static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
	return readw(host->ioaddr + reg);
}

static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
	return readb(host->ioaddr + reg);
}

#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */

extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
	size_t priv_size);
extern void sdhci_free_host(struct sdhci_host *host);

static inline void *sdhci_priv(struct sdhci_host *host)
{
	return (void *)host->private;
}

extern void sdhci_card_detect(struct sdhci_host *host);
extern int sdhci_add_host(struct sdhci_host *host);
extern void sdhci_remove_host(struct sdhci_host *host, int dead);

#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
extern int sdhci_resume_host(struct sdhci_host *host);
extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
#endif

#ifdef CONFIG_PM_RUNTIME
extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
extern int sdhci_runtime_resume_host(struct sdhci_host *host);
#endif

#endif /* __SDHCI_HW_H */
Commit	Line	Data
d129bceb	1	/*
70f10482	2	* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
d129bceb	3	*
1978fda8 GC	4	* Header file for Host Controller registers and I/O accessors.
1978fda8 GC	5	*
b69c9058	6	* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb PO	7	*
d129bceb PO	8	* This program is free software; you can redistribute it and/or modify
643f720c PO	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or (at
	11	* your option) any later version.
d129bceb	12	*/
1978fda8 GC	13	#ifndef __SDHCI_HW_H
1978fda8 GC	14	#define __SDHCI_HW_H
d129bceb	15
0c7ad106	16	#include <linux/scatterlist.h>
4e4141a5 AV	17	#include <linux/compiler.h>
	18	#include <linux/types.h>
	19	#include <linux/io.h>
0c7ad106	20
1978fda8 GC	21	#include <linux/mmc/sdhci.h>
1978fda8 GC	22
d129bceb PO	23	/*
	24	* Controller registers
	25	*/
	26
	27	#define SDHCI_DMA_ADDRESS 0x00
8edf6371	28	#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
d129bceb PO	29
d129bceb PO	30	#define SDHCI_BLOCK_SIZE 0x04
bab76961	31	#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) \| (blksz & 0xFFF))
d129bceb PO	32
	33	#define SDHCI_BLOCK_COUNT 0x06
	34
	35	#define SDHCI_ARGUMENT 0x08
	36
	37	#define SDHCI_TRANSFER_MODE 0x0C
	38	#define SDHCI_TRNS_DMA 0x01
	39	#define SDHCI_TRNS_BLK_CNT_EN 0x02
e89d456f	40	#define SDHCI_TRNS_AUTO_CMD12 0x04
8edf6371	41	#define SDHCI_TRNS_AUTO_CMD23 0x08
d129bceb PO	42	#define SDHCI_TRNS_READ 0x10
	43	#define SDHCI_TRNS_MULTI 0x20
	44
	45	#define SDHCI_COMMAND 0x0E
	46	#define SDHCI_CMD_RESP_MASK 0x03
	47	#define SDHCI_CMD_CRC 0x08
	48	#define SDHCI_CMD_INDEX 0x10
	49	#define SDHCI_CMD_DATA 0x20
574e3f56	50	#define SDHCI_CMD_ABORTCMD 0xC0
d129bceb PO	51
	52	#define SDHCI_CMD_RESP_NONE 0x00
	53	#define SDHCI_CMD_RESP_LONG 0x01
	54	#define SDHCI_CMD_RESP_SHORT 0x02
	55	#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
	56
	57	#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) \| (f & 0xff))
22113efd	58	#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
d129bceb PO	59
	60	#define SDHCI_RESPONSE 0x10
	61
	62	#define SDHCI_BUFFER 0x20
	63
	64	#define SDHCI_PRESENT_STATE 0x24
	65	#define SDHCI_CMD_INHIBIT 0x00000001
	66	#define SDHCI_DATA_INHIBIT 0x00000002
	67	#define SDHCI_DOING_WRITE 0x00000100
	68	#define SDHCI_DOING_READ 0x00000200
	69	#define SDHCI_SPACE_AVAILABLE 0x00000400
	70	#define SDHCI_DATA_AVAILABLE 0x00000800
	71	#define SDHCI_CARD_PRESENT 0x00010000
	72	#define SDHCI_WRITE_PROTECT 0x00080000
f2119df6 AN	73	#define SDHCI_DATA_LVL_MASK 0x00F00000
f2119df6 AN	74	#define SDHCI_DATA_LVL_SHIFT 20
d129bceb	75
d6d50a15	76	#define SDHCI_HOST_CONTROL 0x28
d129bceb PO	77	#define SDHCI_CTRL_LED 0x01
d129bceb PO	78	#define SDHCI_CTRL_4BITBUS 0x02
077df884	79	#define SDHCI_CTRL_HISPD 0x04
2134a922 PO	80	#define SDHCI_CTRL_DMA_MASK 0x18
	81	#define SDHCI_CTRL_SDMA 0x00
	82	#define SDHCI_CTRL_ADMA1 0x08
	83	#define SDHCI_CTRL_ADMA32 0x10
	84	#define SDHCI_CTRL_ADMA64 0x18
15ec4461	85	#define SDHCI_CTRL_8BITBUS 0x20
d129bceb PO	86
d129bceb PO	87	#define SDHCI_POWER_CONTROL 0x29
146ad66e PO	88	#define SDHCI_POWER_ON 0x01
	89	#define SDHCI_POWER_180 0x0A
	90	#define SDHCI_POWER_300 0x0C
	91	#define SDHCI_POWER_330 0x0E
d129bceb PO	92
	93	#define SDHCI_BLOCK_GAP_CONTROL 0x2A
	94
2df3b71b	95	#define SDHCI_WAKE_UP_CONTROL 0x2B
5f619704 DD	96	#define SDHCI_WAKE_ON_INT 0x01
	97	#define SDHCI_WAKE_ON_INSERT 0x02
	98	#define SDHCI_WAKE_ON_REMOVE 0x04
d129bceb PO	99
	100	#define SDHCI_CLOCK_CONTROL 0x2C
	101	#define SDHCI_DIVIDER_SHIFT 8
85105c53 ZG	102	#define SDHCI_DIVIDER_HI_SHIFT 6
	103	#define SDHCI_DIV_MASK 0xFF
	104	#define SDHCI_DIV_MASK_LEN 8
	105	#define SDHCI_DIV_HI_MASK 0x300
c3ed3877	106	#define SDHCI_PROG_CLOCK_MODE 0x0020
d129bceb PO	107	#define SDHCI_CLOCK_CARD_EN 0x0004
	108	#define SDHCI_CLOCK_INT_STABLE 0x0002
	109	#define SDHCI_CLOCK_INT_EN 0x0001
	110
	111	#define SDHCI_TIMEOUT_CONTROL 0x2E
	112
	113	#define SDHCI_SOFTWARE_RESET 0x2F
	114	#define SDHCI_RESET_ALL 0x01
	115	#define SDHCI_RESET_CMD 0x02
	116	#define SDHCI_RESET_DATA 0x04
	117
	118	#define SDHCI_INT_STATUS 0x30
	119	#define SDHCI_INT_ENABLE 0x34
	120	#define SDHCI_SIGNAL_ENABLE 0x38
	121	#define SDHCI_INT_RESPONSE 0x00000001
	122	#define SDHCI_INT_DATA_END 0x00000002
	123	#define SDHCI_INT_DMA_END 0x00000008
a406f5a3 PO	124	#define SDHCI_INT_SPACE_AVAIL 0x00000010
a406f5a3 PO	125	#define SDHCI_INT_DATA_AVAIL 0x00000020
d129bceb PO	126	#define SDHCI_INT_CARD_INSERT 0x00000040
	127	#define SDHCI_INT_CARD_REMOVE 0x00000080
	128	#define SDHCI_INT_CARD_INT 0x00000100
964f9ce2	129	#define SDHCI_INT_ERROR 0x00008000
d129bceb PO	130	#define SDHCI_INT_TIMEOUT 0x00010000
	131	#define SDHCI_INT_CRC 0x00020000
	132	#define SDHCI_INT_END_BIT 0x00040000
	133	#define SDHCI_INT_INDEX 0x00080000
	134	#define SDHCI_INT_DATA_TIMEOUT 0x00100000
	135	#define SDHCI_INT_DATA_CRC 0x00200000
	136	#define SDHCI_INT_DATA_END_BIT 0x00400000
	137	#define SDHCI_INT_BUS_POWER 0x00800000
	138	#define SDHCI_INT_ACMD12ERR 0x01000000
2134a922	139	#define SDHCI_INT_ADMA_ERROR 0x02000000
d129bceb PO	140
	141	#define SDHCI_INT_NORMAL_MASK 0x00007FFF
	142	#define SDHCI_INT_ERROR_MASK 0xFFFF8000
	143
	144	#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE \| SDHCI_INT_TIMEOUT \| \
	145	SDHCI_INT_CRC \| SDHCI_INT_END_BIT \| SDHCI_INT_INDEX)
	146	#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END \| SDHCI_INT_DMA_END \| \
a406f5a3	147	SDHCI_INT_DATA_AVAIL \| SDHCI_INT_SPACE_AVAIL \| \
d129bceb	148	SDHCI_INT_DATA_TIMEOUT \| SDHCI_INT_DATA_CRC \| \
a751a7d6	149	SDHCI_INT_DATA_END_BIT \| SDHCI_INT_ADMA_ERROR)
7260cf5e	150	#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
d129bceb PO	151
	152	#define SDHCI_ACMD12_ERR 0x3C
	153
f2119df6	154	#define SDHCI_HOST_CONTROL2 0x3E
49c468fc AN	155	#define SDHCI_CTRL_UHS_MASK 0x0007
	156	#define SDHCI_CTRL_UHS_SDR12 0x0000
	157	#define SDHCI_CTRL_UHS_SDR25 0x0001
	158	#define SDHCI_CTRL_UHS_SDR50 0x0002
	159	#define SDHCI_CTRL_UHS_SDR104 0x0003
	160	#define SDHCI_CTRL_UHS_DDR50 0x0004
f2119df6	161	#define SDHCI_CTRL_VDD_180 0x0008
d6d50a15 AN	162	#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
	163	#define SDHCI_CTRL_DRV_TYPE_B 0x0000
	164	#define SDHCI_CTRL_DRV_TYPE_A 0x0010
	165	#define SDHCI_CTRL_DRV_TYPE_C 0x0020
	166	#define SDHCI_CTRL_DRV_TYPE_D 0x0030
b513ea25 AN	167	#define SDHCI_CTRL_EXEC_TUNING 0x0040
b513ea25 AN	168	#define SDHCI_CTRL_TUNED_CLK 0x0080
d6d50a15	169	#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
d129bceb PO	170
d129bceb PO	171	#define SDHCI_CAPABILITIES 0x40
1c8cde92 PO	172	#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
	173	#define SDHCI_TIMEOUT_CLK_SHIFT 0
	174	#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
d129bceb	175	#define SDHCI_CLOCK_BASE_MASK 0x00003F00
c4687d5f	176	#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
d129bceb	177	#define SDHCI_CLOCK_BASE_SHIFT 8
1d676e02 PO	178	#define SDHCI_MAX_BLOCK_MASK 0x00030000
1d676e02 PO	179	#define SDHCI_MAX_BLOCK_SHIFT 16
15ec4461	180	#define SDHCI_CAN_DO_8BIT 0x00040000
2134a922 PO	181	#define SDHCI_CAN_DO_ADMA2 0x00080000
2134a922 PO	182	#define SDHCI_CAN_DO_ADMA1 0x00100000
077df884	183	#define SDHCI_CAN_DO_HISPD 0x00200000
a13abc7b	184	#define SDHCI_CAN_DO_SDMA 0x00400000
146ad66e PO	185	#define SDHCI_CAN_VDD_330 0x01000000
	186	#define SDHCI_CAN_VDD_300 0x02000000
	187	#define SDHCI_CAN_VDD_180 0x04000000
2134a922	188	#define SDHCI_CAN_64BIT 0x10000000
d129bceb	189
f2119df6 AN	190	#define SDHCI_SUPPORT_SDR50 0x00000001
	191	#define SDHCI_SUPPORT_SDR104 0x00000002
	192	#define SDHCI_SUPPORT_DDR50 0x00000004
d6d50a15 AN	193	#define SDHCI_DRIVER_TYPE_A 0x00000010
	194	#define SDHCI_DRIVER_TYPE_C 0x00000020
	195	#define SDHCI_DRIVER_TYPE_D 0x00000040
cf2b5eea AN	196	#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
	197	#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
	198	#define SDHCI_USE_SDR50_TUNING 0x00002000
	199	#define SDHCI_RETUNING_MODE_MASK 0x0000C000
	200	#define SDHCI_RETUNING_MODE_SHIFT 14
c3ed3877 AN	201	#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
c3ed3877 AN	202	#define SDHCI_CLOCK_MUL_SHIFT 16
f2119df6	203
e8120ad1	204	#define SDHCI_CAPABILITIES_1 0x44
d129bceb	205
f2119df6 AN	206	#define SDHCI_MAX_CURRENT 0x48
	207	#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
	208	#define SDHCI_MAX_CURRENT_330_SHIFT 0
	209	#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00
	210	#define SDHCI_MAX_CURRENT_300_SHIFT 8
	211	#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
	212	#define SDHCI_MAX_CURRENT_180_SHIFT 16
	213	#define SDHCI_MAX_CURRENT_MULTIPLIER 4
d129bceb PO	214
	215	/* 4C-4F reserved for more max current */
	216
2134a922 PO	217	#define SDHCI_SET_ACMD12_ERROR 0x50
	218	#define SDHCI_SET_INT_ERROR 0x52
	219
	220	#define SDHCI_ADMA_ERROR 0x54
	221
	222	/* 55-57 reserved */
	223
	224	#define SDHCI_ADMA_ADDRESS 0x58
	225
	226	/* 60-FB reserved */
d129bceb PO	227
	228	#define SDHCI_SLOT_INT_STATUS 0xFC
	229
	230	#define SDHCI_HOST_VERSION 0xFE
4a965505 PO	231	#define SDHCI_VENDOR_VER_MASK 0xFF00
	232	#define SDHCI_VENDOR_VER_SHIFT 8
	233	#define SDHCI_SPEC_VER_MASK 0x00FF
	234	#define SDHCI_SPEC_VER_SHIFT 0
2134a922 PO	235	#define SDHCI_SPEC_100 0
2134a922 PO	236	#define SDHCI_SPEC_200 1
85105c53	237	#define SDHCI_SPEC_300 2
d129bceb	238
0397526d ZG	239	/*
	240	* End of controller registers.
	241	*/
	242
	243	#define SDHCI_MAX_DIV_SPEC_200 256
	244	#define SDHCI_MAX_DIV_SPEC_300 2046
	245
f6a03cbf MV	246	/*
	247	* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
	248	*/
	249	#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
	250	#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
	251
b8c86fc5	252	struct sdhci_ops {
4e4141a5	253	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
dc297c92 MF	254	u32 (read_l)(struct sdhci_host host, int reg);
	255	u16 (read_w)(struct sdhci_host host, int reg);
	256	u8 (read_b)(struct sdhci_host host, int reg);
	257	void (write_l)(struct sdhci_host host, u32 val, int reg);
	258	void (write_w)(struct sdhci_host host, u16 val, int reg);
	259	void (write_b)(struct sdhci_host host, u8 val, int reg);
4e4141a5 AV	260	#endif
4e4141a5 AV	261
8114634c AV	262	void (set_clock)(struct sdhci_host host, unsigned int clock);
8114634c AV	263
b8c86fc5	264	int (enable_dma)(struct sdhci_host host);
4240ff0a	265	unsigned int (get_max_clock)(struct sdhci_host host);
a9e58f25	266	unsigned int (get_min_clock)(struct sdhci_host host);
4240ff0a	267	unsigned int (get_timeout_clock)(struct sdhci_host host);
15ec4461 PR	268	int (platform_8bit_width)(struct sdhci_host host,
15ec4461 PR	269	int width);
643a81ff PR	270	void (platform_send_init_74_clocks)(struct sdhci_host host,
643a81ff PR	271	u8 power_mode);
2dfb579c	272	unsigned int (get_ro)(struct sdhci_host host);
393c1a34 PR	273	void (platform_reset_enter)(struct sdhci_host host, u8 mask);
393c1a34 PR	274	void (platform_reset_exit)(struct sdhci_host host, u8 mask);
6322cdd0	275	int (set_uhs_signaling)(struct sdhci_host host, unsigned int uhs);
20758b66	276	void (hw_reset)(struct sdhci_host host);
d129bceb	277	};
b8c86fc5	278
4e4141a5 AV	279	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	280
	281	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	282	{
dc297c92 MF	283	if (unlikely(host->ops->write_l))
dc297c92 MF	284	host->ops->write_l(host, val, reg);
4e4141a5 AV	285	else
	286	writel(val, host->ioaddr + reg);
	287	}
	288
	289	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	290	{
dc297c92 MF	291	if (unlikely(host->ops->write_w))
dc297c92 MF	292	host->ops->write_w(host, val, reg);
4e4141a5 AV	293	else
	294	writew(val, host->ioaddr + reg);
	295	}
	296
	297	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
	298	{
dc297c92 MF	299	if (unlikely(host->ops->write_b))
dc297c92 MF	300	host->ops->write_b(host, val, reg);
4e4141a5 AV	301	else
	302	writeb(val, host->ioaddr + reg);
	303	}
	304
	305	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
	306	{
dc297c92 MF	307	if (unlikely(host->ops->read_l))
dc297c92 MF	308	return host->ops->read_l(host, reg);
4e4141a5 AV	309	else
	310	return readl(host->ioaddr + reg);
	311	}
	312
	313	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
	314	{
dc297c92 MF	315	if (unlikely(host->ops->read_w))
dc297c92 MF	316	return host->ops->read_w(host, reg);
4e4141a5 AV	317	else
	318	return readw(host->ioaddr + reg);
	319	}
	320
	321	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
	322	{
dc297c92 MF	323	if (unlikely(host->ops->read_b))
dc297c92 MF	324	return host->ops->read_b(host, reg);
4e4141a5 AV	325	else
	326	return readb(host->ioaddr + reg);
	327	}
	328
	329	#else
	330
	331	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	332	{
	333	writel(val, host->ioaddr + reg);
	334	}
	335
	336	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	337	{
	338	writew(val, host->ioaddr + reg);
	339	}
	340
	341	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
	342	{
	343	writeb(val, host->ioaddr + reg);
	344	}
	345
	346	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
	347	{
	348	return readl(host->ioaddr + reg);
	349	}
	350
	351	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
	352	{
	353	return readw(host->ioaddr + reg);
	354	}
	355
	356	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
	357	{
	358	return readb(host->ioaddr + reg);
	359	}
	360
	361	#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
b8c86fc5 PO	362
	363	extern struct sdhci_host sdhci_alloc_host(struct device dev,
	364	size_t priv_size);
	365	extern void sdhci_free_host(struct sdhci_host *host);
	366
	367	static inline void sdhci_priv(struct sdhci_host host)
	368	{
	369	return (void *)host->private;
	370	}
	371
17866e14	372	extern void sdhci_card_detect(struct sdhci_host *host);
b8c86fc5	373	extern int sdhci_add_host(struct sdhci_host *host);
1e72859e	374	extern void sdhci_remove_host(struct sdhci_host *host, int dead);
b8c86fc5 PO	375
	376	#ifdef CONFIG_PM
	377	extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
	378	extern int sdhci_resume_host(struct sdhci_host *host);
5f619704	379	extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
b8c86fc5	380	#endif
c0bba0d2	381
66fd8ad5 AH	382	#ifdef CONFIG_PM_RUNTIME
	383	extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
	384	extern int sdhci_runtime_resume_host(struct sdhci_host *host);
	385	#endif
	386
1978fda8	387	#endif /* __SDHCI_HW_H */