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fdc50a94 YG |
1 | /* |
2 | * MMCIF eMMC driver. | |
3 | * | |
4 | * Copyright (C) 2010 Renesas Solutions Corp. | |
5 | * Yusuke Goda <yusuke.goda.sx@renesas.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License. | |
10 | * | |
11 | * | |
12 | * TODO | |
13 | * 1. DMA | |
14 | * 2. Power management | |
15 | * 3. Handle MMC errors better | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/dma-mapping.h> | |
20 | #include <linux/mmc/host.h> | |
21 | #include <linux/mmc/card.h> | |
22 | #include <linux/mmc/core.h> | |
23 | #include <linux/mmc/mmc.h> | |
24 | #include <linux/mmc/sdio.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/mmc/sh_mmcif.h> | |
29 | ||
30 | #define DRIVER_NAME "sh_mmcif" | |
31 | #define DRIVER_VERSION "2010-04-28" | |
32 | ||
33 | #define MMCIF_CE_CMD_SET 0x00000000 | |
34 | #define MMCIF_CE_ARG 0x00000008 | |
35 | #define MMCIF_CE_ARG_CMD12 0x0000000C | |
36 | #define MMCIF_CE_CMD_CTRL 0x00000010 | |
37 | #define MMCIF_CE_BLOCK_SET 0x00000014 | |
38 | #define MMCIF_CE_CLK_CTRL 0x00000018 | |
39 | #define MMCIF_CE_BUF_ACC 0x0000001C | |
40 | #define MMCIF_CE_RESP3 0x00000020 | |
41 | #define MMCIF_CE_RESP2 0x00000024 | |
42 | #define MMCIF_CE_RESP1 0x00000028 | |
43 | #define MMCIF_CE_RESP0 0x0000002C | |
44 | #define MMCIF_CE_RESP_CMD12 0x00000030 | |
45 | #define MMCIF_CE_DATA 0x00000034 | |
46 | #define MMCIF_CE_INT 0x00000040 | |
47 | #define MMCIF_CE_INT_MASK 0x00000044 | |
48 | #define MMCIF_CE_HOST_STS1 0x00000048 | |
49 | #define MMCIF_CE_HOST_STS2 0x0000004C | |
50 | #define MMCIF_CE_VERSION 0x0000007C | |
51 | ||
52 | /* CE_CMD_SET */ | |
53 | #define CMD_MASK 0x3f000000 | |
54 | #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) | |
55 | #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ | |
56 | #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ | |
57 | #define CMD_SET_RBSY (1 << 21) /* R1b */ | |
58 | #define CMD_SET_CCSEN (1 << 20) | |
59 | #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ | |
60 | #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ | |
61 | #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ | |
62 | #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ | |
63 | #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ | |
64 | #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ | |
65 | #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ | |
66 | #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ | |
67 | #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ | |
68 | #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ | |
69 | #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ | |
70 | #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ | |
71 | #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ | |
72 | #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ | |
73 | #define CMD_SET_CCSH (1 << 5) | |
74 | #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ | |
75 | #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ | |
76 | #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ | |
77 | ||
78 | /* CE_CMD_CTRL */ | |
79 | #define CMD_CTRL_BREAK (1 << 0) | |
80 | ||
81 | /* CE_BLOCK_SET */ | |
82 | #define BLOCK_SIZE_MASK 0x0000ffff | |
83 | ||
84 | /* CE_CLK_CTRL */ | |
85 | #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */ | |
86 | #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) | |
87 | #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) | |
88 | #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */ | |
89 | #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \ | |
90 | (1 << 9) | (1 << 8)) /* resp busy timeout */ | |
91 | #define SRWDTO_29 ((1 << 7) | (1 << 6) | \ | |
92 | (1 << 5) | (1 << 4)) /* read/write timeout */ | |
93 | #define SCCSTO_29 ((1 << 3) | (1 << 2) | \ | |
94 | (1 << 1) | (1 << 0)) /* ccs timeout */ | |
95 | ||
96 | /* CE_BUF_ACC */ | |
97 | #define BUF_ACC_DMAWEN (1 << 25) | |
98 | #define BUF_ACC_DMAREN (1 << 24) | |
99 | #define BUF_ACC_BUSW_32 (0 << 17) | |
100 | #define BUF_ACC_BUSW_16 (1 << 17) | |
101 | #define BUF_ACC_ATYP (1 << 16) | |
102 | ||
103 | /* CE_INT */ | |
104 | #define INT_CCSDE (1 << 29) | |
105 | #define INT_CMD12DRE (1 << 26) | |
106 | #define INT_CMD12RBE (1 << 25) | |
107 | #define INT_CMD12CRE (1 << 24) | |
108 | #define INT_DTRANE (1 << 23) | |
109 | #define INT_BUFRE (1 << 22) | |
110 | #define INT_BUFWEN (1 << 21) | |
111 | #define INT_BUFREN (1 << 20) | |
112 | #define INT_CCSRCV (1 << 19) | |
113 | #define INT_RBSYE (1 << 17) | |
114 | #define INT_CRSPE (1 << 16) | |
115 | #define INT_CMDVIO (1 << 15) | |
116 | #define INT_BUFVIO (1 << 14) | |
117 | #define INT_WDATERR (1 << 11) | |
118 | #define INT_RDATERR (1 << 10) | |
119 | #define INT_RIDXERR (1 << 9) | |
120 | #define INT_RSPERR (1 << 8) | |
121 | #define INT_CCSTO (1 << 5) | |
122 | #define INT_CRCSTO (1 << 4) | |
123 | #define INT_WDATTO (1 << 3) | |
124 | #define INT_RDATTO (1 << 2) | |
125 | #define INT_RBSYTO (1 << 1) | |
126 | #define INT_RSPTO (1 << 0) | |
127 | #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ | |
128 | INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ | |
129 | INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ | |
130 | INT_RDATTO | INT_RBSYTO | INT_RSPTO) | |
131 | ||
132 | /* CE_INT_MASK */ | |
133 | #define MASK_ALL 0x00000000 | |
134 | #define MASK_MCCSDE (1 << 29) | |
135 | #define MASK_MCMD12DRE (1 << 26) | |
136 | #define MASK_MCMD12RBE (1 << 25) | |
137 | #define MASK_MCMD12CRE (1 << 24) | |
138 | #define MASK_MDTRANE (1 << 23) | |
139 | #define MASK_MBUFRE (1 << 22) | |
140 | #define MASK_MBUFWEN (1 << 21) | |
141 | #define MASK_MBUFREN (1 << 20) | |
142 | #define MASK_MCCSRCV (1 << 19) | |
143 | #define MASK_MRBSYE (1 << 17) | |
144 | #define MASK_MCRSPE (1 << 16) | |
145 | #define MASK_MCMDVIO (1 << 15) | |
146 | #define MASK_MBUFVIO (1 << 14) | |
147 | #define MASK_MWDATERR (1 << 11) | |
148 | #define MASK_MRDATERR (1 << 10) | |
149 | #define MASK_MRIDXERR (1 << 9) | |
150 | #define MASK_MRSPERR (1 << 8) | |
151 | #define MASK_MCCSTO (1 << 5) | |
152 | #define MASK_MCRCSTO (1 << 4) | |
153 | #define MASK_MWDATTO (1 << 3) | |
154 | #define MASK_MRDATTO (1 << 2) | |
155 | #define MASK_MRBSYTO (1 << 1) | |
156 | #define MASK_MRSPTO (1 << 0) | |
157 | ||
158 | /* CE_HOST_STS1 */ | |
159 | #define STS1_CMDSEQ (1 << 31) | |
160 | ||
161 | /* CE_HOST_STS2 */ | |
162 | #define STS2_CRCSTE (1 << 31) | |
163 | #define STS2_CRC16E (1 << 30) | |
164 | #define STS2_AC12CRCE (1 << 29) | |
165 | #define STS2_RSPCRC7E (1 << 28) | |
166 | #define STS2_CRCSTEBE (1 << 27) | |
167 | #define STS2_RDATEBE (1 << 26) | |
168 | #define STS2_AC12REBE (1 << 25) | |
169 | #define STS2_RSPEBE (1 << 24) | |
170 | #define STS2_AC12IDXE (1 << 23) | |
171 | #define STS2_RSPIDXE (1 << 22) | |
172 | #define STS2_CCSTO (1 << 15) | |
173 | #define STS2_RDATTO (1 << 14) | |
174 | #define STS2_DATBSYTO (1 << 13) | |
175 | #define STS2_CRCSTTO (1 << 12) | |
176 | #define STS2_AC12BSYTO (1 << 11) | |
177 | #define STS2_RSPBSYTO (1 << 10) | |
178 | #define STS2_AC12RSPTO (1 << 9) | |
179 | #define STS2_RSPTO (1 << 8) | |
180 | #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ | |
181 | STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) | |
182 | #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ | |
183 | STS2_DATBSYTO | STS2_CRCSTTO | \ | |
184 | STS2_AC12BSYTO | STS2_RSPBSYTO | \ | |
185 | STS2_AC12RSPTO | STS2_RSPTO) | |
186 | ||
187 | /* CE_VERSION */ | |
188 | #define SOFT_RST_ON (1 << 31) | |
189 | #define SOFT_RST_OFF (0 << 31) | |
190 | ||
191 | #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ | |
192 | #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ | |
193 | #define CLKDEV_INIT 400000 /* 400 KHz */ | |
194 | ||
195 | struct sh_mmcif_host { | |
196 | struct mmc_host *mmc; | |
197 | struct mmc_data *data; | |
198 | struct mmc_command *cmd; | |
199 | struct platform_device *pd; | |
200 | struct clk *hclk; | |
201 | unsigned int clk; | |
202 | int bus_width; | |
203 | u16 wait_int; | |
204 | u16 sd_error; | |
205 | long timeout; | |
206 | void __iomem *addr; | |
207 | wait_queue_head_t intr_wait; | |
208 | }; | |
209 | ||
210 | static inline u32 sh_mmcif_readl(struct sh_mmcif_host *host, unsigned int reg) | |
211 | { | |
212 | return readl(host->addr + reg); | |
213 | } | |
214 | ||
215 | static inline void sh_mmcif_writel(struct sh_mmcif_host *host, | |
216 | unsigned int reg, u32 val) | |
217 | { | |
218 | writel(val, host->addr + reg); | |
219 | } | |
220 | ||
221 | static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, | |
222 | unsigned int reg, u32 val) | |
223 | { | |
224 | writel(val | sh_mmcif_readl(host, reg), host->addr + reg); | |
225 | } | |
226 | ||
227 | static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, | |
228 | unsigned int reg, u32 val) | |
229 | { | |
230 | writel(~val & sh_mmcif_readl(host, reg), host->addr + reg); | |
231 | } | |
232 | ||
233 | ||
234 | static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) | |
235 | { | |
236 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; | |
237 | ||
238 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
239 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); | |
240 | ||
241 | if (!clk) | |
242 | return; | |
243 | if (p->sup_pclk && clk == host->clk) | |
244 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); | |
245 | else | |
246 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & | |
247 | (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16)); | |
248 | ||
249 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
250 | } | |
251 | ||
252 | static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) | |
253 | { | |
254 | u32 tmp; | |
255 | ||
256 | tmp = 0x010f0000 & sh_mmcif_readl(host, MMCIF_CE_CLK_CTRL); | |
257 | ||
258 | sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_ON); | |
259 | sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_OFF); | |
260 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | | |
261 | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); | |
262 | /* byte swap on */ | |
263 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); | |
264 | } | |
265 | ||
266 | static int sh_mmcif_error_manage(struct sh_mmcif_host *host) | |
267 | { | |
268 | u32 state1, state2; | |
269 | int ret, timeout = 10000000; | |
270 | ||
271 | host->sd_error = 0; | |
272 | host->wait_int = 0; | |
273 | ||
274 | state1 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS1); | |
275 | state2 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS2); | |
276 | pr_debug("%s: ERR HOST_STS1 = %08x\n", \ | |
277 | DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS1)); | |
278 | pr_debug("%s: ERR HOST_STS2 = %08x\n", \ | |
279 | DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS2)); | |
280 | ||
281 | if (state1 & STS1_CMDSEQ) { | |
282 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); | |
283 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); | |
284 | while (1) { | |
285 | timeout--; | |
286 | if (timeout < 0) { | |
287 | pr_err(DRIVER_NAME": Forceed end of " \ | |
288 | "command sequence timeout err\n"); | |
289 | return -EIO; | |
290 | } | |
291 | if (!(sh_mmcif_readl(host, MMCIF_CE_HOST_STS1) | |
292 | & STS1_CMDSEQ)) | |
293 | break; | |
294 | mdelay(1); | |
295 | } | |
296 | sh_mmcif_sync_reset(host); | |
297 | pr_debug(DRIVER_NAME": Forced end of command sequence\n"); | |
298 | return -EIO; | |
299 | } | |
300 | ||
301 | if (state2 & STS2_CRC_ERR) { | |
302 | pr_debug(DRIVER_NAME": Happened CRC error\n"); | |
303 | ret = -EIO; | |
304 | } else if (state2 & STS2_TIMEOUT_ERR) { | |
305 | pr_debug(DRIVER_NAME": Happened Timeout error\n"); | |
306 | ret = -ETIMEDOUT; | |
307 | } else { | |
308 | pr_debug(DRIVER_NAME": Happened End/Index error\n"); | |
309 | ret = -EIO; | |
310 | } | |
311 | return ret; | |
312 | } | |
313 | ||
314 | static int sh_mmcif_single_read(struct sh_mmcif_host *host, | |
315 | struct mmc_request *mrq) | |
316 | { | |
317 | struct mmc_data *data = mrq->data; | |
318 | long time; | |
319 | u32 blocksize, i, *p = sg_virt(data->sg); | |
320 | ||
321 | host->wait_int = 0; | |
322 | ||
323 | /* buf read enable */ | |
324 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
325 | time = wait_event_interruptible_timeout(host->intr_wait, | |
326 | host->wait_int == 1 || | |
327 | host->sd_error == 1, host->timeout); | |
328 | if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) | |
329 | return sh_mmcif_error_manage(host); | |
330 | ||
331 | host->wait_int = 0; | |
332 | blocksize = (BLOCK_SIZE_MASK & | |
333 | sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3; | |
334 | for (i = 0; i < blocksize / 4; i++) | |
335 | *p++ = sh_mmcif_readl(host, MMCIF_CE_DATA); | |
336 | ||
337 | /* buffer read end */ | |
338 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); | |
339 | time = wait_event_interruptible_timeout(host->intr_wait, | |
340 | host->wait_int == 1 || | |
341 | host->sd_error == 1, host->timeout); | |
342 | if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) | |
343 | return sh_mmcif_error_manage(host); | |
344 | ||
345 | host->wait_int = 0; | |
346 | return 0; | |
347 | } | |
348 | ||
349 | static int sh_mmcif_multi_read(struct sh_mmcif_host *host, | |
350 | struct mmc_request *mrq) | |
351 | { | |
352 | struct mmc_data *data = mrq->data; | |
353 | long time; | |
354 | u32 blocksize, i, j, sec, *p; | |
355 | ||
356 | blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET); | |
357 | for (j = 0; j < data->sg_len; j++) { | |
358 | p = sg_virt(data->sg); | |
359 | host->wait_int = 0; | |
360 | for (sec = 0; sec < data->sg->length / blocksize; sec++) { | |
361 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
362 | /* buf read enable */ | |
363 | time = wait_event_interruptible_timeout(host->intr_wait, | |
364 | host->wait_int == 1 || | |
365 | host->sd_error == 1, host->timeout); | |
366 | ||
367 | if (host->wait_int != 1 && | |
368 | (time == 0 || host->sd_error != 0)) | |
369 | return sh_mmcif_error_manage(host); | |
370 | ||
371 | host->wait_int = 0; | |
372 | for (i = 0; i < blocksize / 4; i++) | |
373 | *p++ = sh_mmcif_readl(host, MMCIF_CE_DATA); | |
374 | } | |
375 | if (j < data->sg_len - 1) | |
376 | data->sg++; | |
377 | } | |
378 | return 0; | |
379 | } | |
380 | ||
381 | static int sh_mmcif_single_write(struct sh_mmcif_host *host, | |
382 | struct mmc_request *mrq) | |
383 | { | |
384 | struct mmc_data *data = mrq->data; | |
385 | long time; | |
386 | u32 blocksize, i, *p = sg_virt(data->sg); | |
387 | ||
388 | host->wait_int = 0; | |
389 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); | |
390 | ||
391 | /* buf write enable */ | |
392 | time = wait_event_interruptible_timeout(host->intr_wait, | |
393 | host->wait_int == 1 || | |
394 | host->sd_error == 1, host->timeout); | |
395 | if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) | |
396 | return sh_mmcif_error_manage(host); | |
397 | ||
398 | host->wait_int = 0; | |
399 | blocksize = (BLOCK_SIZE_MASK & | |
400 | sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3; | |
401 | for (i = 0; i < blocksize / 4; i++) | |
402 | sh_mmcif_writel(host, MMCIF_CE_DATA, *p++); | |
403 | ||
404 | /* buffer write end */ | |
405 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); | |
406 | ||
407 | time = wait_event_interruptible_timeout(host->intr_wait, | |
408 | host->wait_int == 1 || | |
409 | host->sd_error == 1, host->timeout); | |
410 | if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) | |
411 | return sh_mmcif_error_manage(host); | |
412 | ||
413 | host->wait_int = 0; | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static int sh_mmcif_multi_write(struct sh_mmcif_host *host, | |
418 | struct mmc_request *mrq) | |
419 | { | |
420 | struct mmc_data *data = mrq->data; | |
421 | long time; | |
422 | u32 i, sec, j, blocksize, *p; | |
423 | ||
424 | blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET); | |
425 | ||
426 | for (j = 0; j < data->sg_len; j++) { | |
427 | p = sg_virt(data->sg); | |
428 | host->wait_int = 0; | |
429 | for (sec = 0; sec < data->sg->length / blocksize; sec++) { | |
430 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); | |
431 | /* buf write enable*/ | |
432 | time = wait_event_interruptible_timeout(host->intr_wait, | |
433 | host->wait_int == 1 || | |
434 | host->sd_error == 1, host->timeout); | |
435 | ||
436 | if (host->wait_int != 1 && | |
437 | (time == 0 || host->sd_error != 0)) | |
438 | return sh_mmcif_error_manage(host); | |
439 | ||
440 | host->wait_int = 0; | |
441 | for (i = 0; i < blocksize / 4; i++) | |
442 | sh_mmcif_writel(host, MMCIF_CE_DATA, *p++); | |
443 | } | |
444 | if (j < data->sg_len - 1) | |
445 | data->sg++; | |
446 | } | |
447 | return 0; | |
448 | } | |
449 | ||
450 | static void sh_mmcif_get_response(struct sh_mmcif_host *host, | |
451 | struct mmc_command *cmd) | |
452 | { | |
453 | if (cmd->flags & MMC_RSP_136) { | |
454 | cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP3); | |
455 | cmd->resp[1] = sh_mmcif_readl(host, MMCIF_CE_RESP2); | |
456 | cmd->resp[2] = sh_mmcif_readl(host, MMCIF_CE_RESP1); | |
457 | cmd->resp[3] = sh_mmcif_readl(host, MMCIF_CE_RESP0); | |
458 | } else | |
459 | cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP0); | |
460 | } | |
461 | ||
462 | static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, | |
463 | struct mmc_command *cmd) | |
464 | { | |
465 | cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP_CMD12); | |
466 | } | |
467 | ||
468 | static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, | |
469 | struct mmc_request *mrq, struct mmc_command *cmd, u32 opc) | |
470 | { | |
471 | u32 tmp = 0; | |
472 | ||
473 | /* Response Type check */ | |
474 | switch (mmc_resp_type(cmd)) { | |
475 | case MMC_RSP_NONE: | |
476 | tmp |= CMD_SET_RTYP_NO; | |
477 | break; | |
478 | case MMC_RSP_R1: | |
479 | case MMC_RSP_R1B: | |
480 | case MMC_RSP_R3: | |
481 | tmp |= CMD_SET_RTYP_6B; | |
482 | break; | |
483 | case MMC_RSP_R2: | |
484 | tmp |= CMD_SET_RTYP_17B; | |
485 | break; | |
486 | default: | |
487 | pr_err(DRIVER_NAME": Not support type response.\n"); | |
488 | break; | |
489 | } | |
490 | switch (opc) { | |
491 | /* RBSY */ | |
492 | case MMC_SWITCH: | |
493 | case MMC_STOP_TRANSMISSION: | |
494 | case MMC_SET_WRITE_PROT: | |
495 | case MMC_CLR_WRITE_PROT: | |
496 | case MMC_ERASE: | |
497 | case MMC_GEN_CMD: | |
498 | tmp |= CMD_SET_RBSY; | |
499 | break; | |
500 | } | |
501 | /* WDAT / DATW */ | |
502 | if (host->data) { | |
503 | tmp |= CMD_SET_WDAT; | |
504 | switch (host->bus_width) { | |
505 | case MMC_BUS_WIDTH_1: | |
506 | tmp |= CMD_SET_DATW_1; | |
507 | break; | |
508 | case MMC_BUS_WIDTH_4: | |
509 | tmp |= CMD_SET_DATW_4; | |
510 | break; | |
511 | case MMC_BUS_WIDTH_8: | |
512 | tmp |= CMD_SET_DATW_8; | |
513 | break; | |
514 | default: | |
515 | pr_err(DRIVER_NAME": Not support bus width.\n"); | |
516 | break; | |
517 | } | |
518 | } | |
519 | /* DWEN */ | |
520 | if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) | |
521 | tmp |= CMD_SET_DWEN; | |
522 | /* CMLTE/CMD12EN */ | |
523 | if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { | |
524 | tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; | |
525 | sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, | |
526 | mrq->data->blocks << 16); | |
527 | } | |
528 | /* RIDXC[1:0] check bits */ | |
529 | if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || | |
530 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
531 | tmp |= CMD_SET_RIDXC_BITS; | |
532 | /* RCRC7C[1:0] check bits */ | |
533 | if (opc == MMC_SEND_OP_COND) | |
534 | tmp |= CMD_SET_CRC7C_BITS; | |
535 | /* RCRC7C[1:0] internal CRC7 */ | |
536 | if (opc == MMC_ALL_SEND_CID || | |
537 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
538 | tmp |= CMD_SET_CRC7C_INTERNAL; | |
539 | ||
540 | return opc = ((opc << 24) | tmp); | |
541 | } | |
542 | ||
543 | static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host, | |
544 | struct mmc_request *mrq, u32 opc) | |
545 | { | |
546 | u32 ret; | |
547 | ||
548 | switch (opc) { | |
549 | case MMC_READ_MULTIPLE_BLOCK: | |
550 | ret = sh_mmcif_multi_read(host, mrq); | |
551 | break; | |
552 | case MMC_WRITE_MULTIPLE_BLOCK: | |
553 | ret = sh_mmcif_multi_write(host, mrq); | |
554 | break; | |
555 | case MMC_WRITE_BLOCK: | |
556 | ret = sh_mmcif_single_write(host, mrq); | |
557 | break; | |
558 | case MMC_READ_SINGLE_BLOCK: | |
559 | case MMC_SEND_EXT_CSD: | |
560 | ret = sh_mmcif_single_read(host, mrq); | |
561 | break; | |
562 | default: | |
563 | pr_err(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc); | |
564 | ret = -EINVAL; | |
565 | break; | |
566 | } | |
567 | return ret; | |
568 | } | |
569 | ||
570 | static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, | |
571 | struct mmc_request *mrq, struct mmc_command *cmd) | |
572 | { | |
573 | long time; | |
574 | int ret = 0, mask = 0; | |
575 | u32 opc = cmd->opcode; | |
576 | ||
577 | host->cmd = cmd; | |
578 | ||
579 | switch (opc) { | |
580 | /* respons busy check */ | |
581 | case MMC_SWITCH: | |
582 | case MMC_STOP_TRANSMISSION: | |
583 | case MMC_SET_WRITE_PROT: | |
584 | case MMC_CLR_WRITE_PROT: | |
585 | case MMC_ERASE: | |
586 | case MMC_GEN_CMD: | |
587 | mask = MASK_MRBSYE; | |
588 | break; | |
589 | default: | |
590 | mask = MASK_MCRSPE; | |
591 | break; | |
592 | } | |
593 | mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | | |
594 | MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | | |
595 | MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | | |
596 | MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; | |
597 | ||
598 | if (host->data) { | |
599 | sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, 0); | |
600 | sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, mrq->data->blksz); | |
601 | } | |
602 | opc = sh_mmcif_set_cmd(host, mrq, cmd, opc); | |
603 | ||
604 | sh_mmcif_writel(host, MMCIF_CE_INT, 0xD80430C0); | |
605 | sh_mmcif_writel(host, MMCIF_CE_INT_MASK, mask); | |
606 | /* set arg */ | |
607 | sh_mmcif_writel(host, MMCIF_CE_ARG, cmd->arg); | |
608 | host->wait_int = 0; | |
609 | /* set cmd */ | |
610 | sh_mmcif_writel(host, MMCIF_CE_CMD_SET, opc); | |
611 | ||
612 | time = wait_event_interruptible_timeout(host->intr_wait, | |
613 | host->wait_int == 1 || host->sd_error == 1, host->timeout); | |
614 | if (host->wait_int != 1 && time == 0) { | |
615 | cmd->error = sh_mmcif_error_manage(host); | |
616 | return; | |
617 | } | |
618 | if (host->sd_error) { | |
619 | switch (cmd->opcode) { | |
620 | case MMC_ALL_SEND_CID: | |
621 | case MMC_SELECT_CARD: | |
622 | case MMC_APP_CMD: | |
623 | cmd->error = -ETIMEDOUT; | |
624 | break; | |
625 | default: | |
626 | pr_debug("%s: Cmd(d'%d) err\n", | |
627 | DRIVER_NAME, cmd->opcode); | |
628 | cmd->error = sh_mmcif_error_manage(host); | |
629 | break; | |
630 | } | |
631 | host->sd_error = 0; | |
632 | host->wait_int = 0; | |
633 | return; | |
634 | } | |
635 | if (!(cmd->flags & MMC_RSP_PRESENT)) { | |
636 | cmd->error = ret; | |
637 | host->wait_int = 0; | |
638 | return; | |
639 | } | |
640 | if (host->wait_int == 1) { | |
641 | sh_mmcif_get_response(host, cmd); | |
642 | host->wait_int = 0; | |
643 | } | |
644 | if (host->data) { | |
645 | ret = sh_mmcif_data_trans(host, mrq, cmd->opcode); | |
646 | if (ret < 0) | |
647 | mrq->data->bytes_xfered = 0; | |
648 | else | |
649 | mrq->data->bytes_xfered = | |
650 | mrq->data->blocks * mrq->data->blksz; | |
651 | } | |
652 | cmd->error = ret; | |
653 | } | |
654 | ||
655 | static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, | |
656 | struct mmc_request *mrq, struct mmc_command *cmd) | |
657 | { | |
658 | long time; | |
659 | ||
660 | if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) | |
661 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); | |
662 | else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) | |
663 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); | |
664 | else { | |
665 | pr_err(DRIVER_NAME": not support stop cmd\n"); | |
666 | cmd->error = sh_mmcif_error_manage(host); | |
667 | return; | |
668 | } | |
669 | ||
670 | time = wait_event_interruptible_timeout(host->intr_wait, | |
671 | host->wait_int == 1 || | |
672 | host->sd_error == 1, host->timeout); | |
673 | if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) { | |
674 | cmd->error = sh_mmcif_error_manage(host); | |
675 | return; | |
676 | } | |
677 | sh_mmcif_get_cmd12response(host, cmd); | |
678 | host->wait_int = 0; | |
679 | cmd->error = 0; | |
680 | } | |
681 | ||
682 | static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
683 | { | |
684 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
685 | ||
686 | switch (mrq->cmd->opcode) { | |
687 | /* MMCIF does not support SD/SDIO command */ | |
688 | case SD_IO_SEND_OP_COND: | |
689 | case MMC_APP_CMD: | |
690 | mrq->cmd->error = -ETIMEDOUT; | |
691 | mmc_request_done(mmc, mrq); | |
692 | return; | |
693 | case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ | |
694 | if (!mrq->data) { | |
695 | /* send_if_cond cmd (not support) */ | |
696 | mrq->cmd->error = -ETIMEDOUT; | |
697 | mmc_request_done(mmc, mrq); | |
698 | return; | |
699 | } | |
700 | break; | |
701 | default: | |
702 | break; | |
703 | } | |
704 | host->data = mrq->data; | |
705 | sh_mmcif_start_cmd(host, mrq, mrq->cmd); | |
706 | host->data = NULL; | |
707 | ||
708 | if (mrq->cmd->error != 0) { | |
709 | mmc_request_done(mmc, mrq); | |
710 | return; | |
711 | } | |
712 | if (mrq->stop) | |
713 | sh_mmcif_stop_cmd(host, mrq, mrq->stop); | |
714 | mmc_request_done(mmc, mrq); | |
715 | } | |
716 | ||
717 | static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
718 | { | |
719 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
720 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; | |
721 | ||
722 | if (ios->power_mode == MMC_POWER_OFF) { | |
723 | /* clock stop */ | |
724 | sh_mmcif_clock_control(host, 0); | |
725 | if (p->down_pwr) | |
726 | p->down_pwr(host->pd); | |
727 | return; | |
728 | } else if (ios->power_mode == MMC_POWER_UP) { | |
729 | if (p->set_pwr) | |
730 | p->set_pwr(host->pd, ios->power_mode); | |
731 | } | |
732 | ||
733 | if (ios->clock) | |
734 | sh_mmcif_clock_control(host, ios->clock); | |
735 | ||
736 | host->bus_width = ios->bus_width; | |
737 | } | |
738 | ||
739 | static struct mmc_host_ops sh_mmcif_ops = { | |
740 | .request = sh_mmcif_request, | |
741 | .set_ios = sh_mmcif_set_ios, | |
742 | }; | |
743 | ||
744 | static void sh_mmcif_detect(struct mmc_host *mmc) | |
745 | { | |
746 | mmc_detect_change(mmc, 0); | |
747 | } | |
748 | ||
749 | static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) | |
750 | { | |
751 | struct sh_mmcif_host *host = dev_id; | |
752 | u32 state = 0; | |
753 | int err = 0; | |
754 | ||
755 | state = sh_mmcif_readl(host, MMCIF_CE_INT); | |
756 | ||
757 | if (state & INT_RBSYE) { | |
758 | sh_mmcif_writel(host, MMCIF_CE_INT, ~(INT_RBSYE | INT_CRSPE)); | |
759 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); | |
760 | } else if (state & INT_CRSPE) { | |
761 | sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_CRSPE); | |
762 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); | |
763 | } else if (state & INT_BUFREN) { | |
764 | sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFREN); | |
765 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
766 | } else if (state & INT_BUFWEN) { | |
767 | sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFWEN); | |
768 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); | |
769 | } else if (state & INT_CMD12DRE) { | |
770 | sh_mmcif_writel(host, MMCIF_CE_INT, | |
771 | ~(INT_CMD12DRE | INT_CMD12RBE | | |
772 | INT_CMD12CRE | INT_BUFRE)); | |
773 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); | |
774 | } else if (state & INT_BUFRE) { | |
775 | sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFRE); | |
776 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); | |
777 | } else if (state & INT_DTRANE) { | |
778 | sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_DTRANE); | |
779 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); | |
780 | } else if (state & INT_CMD12RBE) { | |
781 | sh_mmcif_writel(host, MMCIF_CE_INT, | |
782 | ~(INT_CMD12RBE | INT_CMD12CRE)); | |
783 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); | |
784 | } else if (state & INT_ERR_STS) { | |
785 | /* err interrupts */ | |
786 | sh_mmcif_writel(host, MMCIF_CE_INT, ~state); | |
787 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); | |
788 | err = 1; | |
789 | } else { | |
790 | pr_debug("%s: Not support int\n", DRIVER_NAME); | |
791 | sh_mmcif_writel(host, MMCIF_CE_INT, ~state); | |
792 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); | |
793 | err = 1; | |
794 | } | |
795 | if (err) { | |
796 | host->sd_error = 1; | |
797 | pr_debug("%s: int err state = %08x\n", DRIVER_NAME, state); | |
798 | } | |
799 | host->wait_int = 1; | |
800 | wake_up(&host->intr_wait); | |
801 | ||
802 | return IRQ_HANDLED; | |
803 | } | |
804 | ||
805 | static int __devinit sh_mmcif_probe(struct platform_device *pdev) | |
806 | { | |
807 | int ret = 0, irq[2]; | |
808 | struct mmc_host *mmc; | |
809 | struct sh_mmcif_host *host = NULL; | |
810 | struct sh_mmcif_plat_data *pd = NULL; | |
811 | struct resource *res; | |
812 | void __iomem *reg; | |
813 | char clk_name[8]; | |
814 | ||
815 | irq[0] = platform_get_irq(pdev, 0); | |
816 | irq[1] = platform_get_irq(pdev, 1); | |
817 | if (irq[0] < 0 || irq[1] < 0) { | |
818 | pr_err(DRIVER_NAME": Get irq error\n"); | |
819 | return -ENXIO; | |
820 | } | |
821 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
822 | if (!res) { | |
823 | dev_err(&pdev->dev, "platform_get_resource error.\n"); | |
824 | return -ENXIO; | |
825 | } | |
826 | reg = ioremap(res->start, resource_size(res)); | |
827 | if (!reg) { | |
828 | dev_err(&pdev->dev, "ioremap error.\n"); | |
829 | return -ENOMEM; | |
830 | } | |
831 | pd = (struct sh_mmcif_plat_data *)(pdev->dev.platform_data); | |
832 | if (!pd) { | |
833 | dev_err(&pdev->dev, "sh_mmcif plat data error.\n"); | |
834 | ret = -ENXIO; | |
835 | goto clean_up; | |
836 | } | |
837 | mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); | |
838 | if (!mmc) { | |
839 | ret = -ENOMEM; | |
840 | goto clean_up; | |
841 | } | |
842 | host = mmc_priv(mmc); | |
843 | host->mmc = mmc; | |
844 | host->addr = reg; | |
845 | host->timeout = 1000; | |
846 | ||
847 | snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id); | |
848 | host->hclk = clk_get(&pdev->dev, clk_name); | |
849 | if (IS_ERR(host->hclk)) { | |
850 | dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); | |
851 | ret = PTR_ERR(host->hclk); | |
852 | goto clean_up1; | |
853 | } | |
854 | clk_enable(host->hclk); | |
855 | host->clk = clk_get_rate(host->hclk); | |
856 | host->pd = pdev; | |
857 | ||
858 | init_waitqueue_head(&host->intr_wait); | |
859 | ||
860 | mmc->ops = &sh_mmcif_ops; | |
861 | mmc->f_max = host->clk; | |
862 | /* close to 400KHz */ | |
863 | if (mmc->f_max < 51200000) | |
864 | mmc->f_min = mmc->f_max / 128; | |
865 | else if (mmc->f_max < 102400000) | |
866 | mmc->f_min = mmc->f_max / 256; | |
867 | else | |
868 | mmc->f_min = mmc->f_max / 512; | |
869 | if (pd->ocr) | |
870 | mmc->ocr_avail = pd->ocr; | |
871 | mmc->caps = MMC_CAP_MMC_HIGHSPEED; | |
872 | if (pd->caps) | |
873 | mmc->caps |= pd->caps; | |
874 | mmc->max_phys_segs = 128; | |
875 | mmc->max_hw_segs = 128; | |
876 | mmc->max_blk_size = 512; | |
877 | mmc->max_blk_count = 65535; | |
878 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
879 | mmc->max_seg_size = mmc->max_req_size; | |
880 | ||
881 | sh_mmcif_sync_reset(host); | |
882 | platform_set_drvdata(pdev, host); | |
883 | mmc_add_host(mmc); | |
884 | ||
885 | ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host); | |
886 | if (ret) { | |
887 | pr_err(DRIVER_NAME": request_irq error (sh_mmc:error)\n"); | |
888 | goto clean_up2; | |
889 | } | |
890 | ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host); | |
891 | if (ret) { | |
892 | free_irq(irq[0], host); | |
893 | pr_err(DRIVER_NAME": request_irq error (sh_mmc:int)\n"); | |
894 | goto clean_up2; | |
895 | } | |
896 | ||
897 | sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL); | |
898 | sh_mmcif_detect(host->mmc); | |
899 | ||
900 | pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION); | |
901 | pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME, | |
902 | sh_mmcif_readl(host, MMCIF_CE_VERSION) & 0x0000ffff); | |
903 | return ret; | |
904 | ||
905 | clean_up2: | |
906 | clk_disable(host->hclk); | |
907 | clean_up1: | |
908 | mmc_free_host(mmc); | |
909 | clean_up: | |
910 | if (reg) | |
911 | iounmap(reg); | |
912 | return ret; | |
913 | } | |
914 | ||
915 | static int __devexit sh_mmcif_remove(struct platform_device *pdev) | |
916 | { | |
917 | struct sh_mmcif_host *host = platform_get_drvdata(pdev); | |
918 | int irq[2]; | |
919 | ||
920 | sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL); | |
921 | ||
922 | irq[0] = platform_get_irq(pdev, 0); | |
923 | irq[1] = platform_get_irq(pdev, 1); | |
924 | ||
925 | if (host->addr) | |
926 | iounmap(host->addr); | |
927 | ||
928 | platform_set_drvdata(pdev, NULL); | |
929 | mmc_remove_host(host->mmc); | |
930 | ||
931 | free_irq(irq[0], host); | |
932 | free_irq(irq[1], host); | |
933 | ||
934 | clk_disable(host->hclk); | |
935 | mmc_free_host(host->mmc); | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | static struct platform_driver sh_mmcif_driver = { | |
941 | .probe = sh_mmcif_probe, | |
942 | .remove = sh_mmcif_remove, | |
943 | .driver = { | |
944 | .name = DRIVER_NAME, | |
945 | }, | |
946 | }; | |
947 | ||
948 | static int __init sh_mmcif_init(void) | |
949 | { | |
950 | return platform_driver_register(&sh_mmcif_driver); | |
951 | } | |
952 | ||
953 | static void __exit sh_mmcif_exit(void) | |
954 | { | |
955 | platform_driver_unregister(&sh_mmcif_driver); | |
956 | } | |
957 | ||
958 | module_init(sh_mmcif_init); | |
959 | module_exit(sh_mmcif_exit); | |
960 | ||
961 | ||
962 | MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); | |
963 | MODULE_LICENSE("GPL"); | |
964 | MODULE_ALIAS(DRIVER_NAME); | |
965 | MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); |