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mmc: simplify mmc_cd_gpio_request() by removing two parameters
[deliverable/linux.git] / drivers / mmc / host / tmio_mmc_pio.c
CommitLineData
b6147490
GL		 1/*
2 * linux/drivers/mmc/host/tmio_mmc_pio.c
3 *
4 * Copyright (C) 2011 Guennadi Liakhovetski
5 * Copyright (C) 2007 Ian Molton
6 * Copyright (C) 2004 Ian Molton
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Driver for the MMC / SD / SDIO IP found in:
13 *
14 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
15 *
16 * This driver draws mainly on scattered spec sheets, Reverse engineering
17 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
18 * support). (Further 4 bit support from a later datasheet).
19 *
20 * TODO:
21 * Investigate using a workqueue for PIO transfers
22 * Eliminate FIXMEs
23 * SDIO support
24 * Better Power management
25 * Handle MMC errors better
26 * double buffer support
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/highmem.h>
33#include <linux/interrupt.h>
34#include <linux/io.h>
35#include <linux/irq.h>
36#include <linux/mfd/tmio.h>
37#include <linux/mmc/host.h>
cba179ae 38#include <linux/mmc/tmio.h>
b6147490
GL		 39#include <linux/module.h>
40#include <linux/pagemap.h>
41#include <linux/platform_device.h>
c419e611 42#include <linux/pm_qos.h>
e6ee7182 43#include <linux/pm_runtime.h>
b6147490 44#include <linux/scatterlist.h>
b6147490 45#include <linux/spinlock.h>
e3de2be7 46#include <linux/workqueue.h>
b6147490
GL		 47
48#include "tmio_mmc.h"
49
b6147490
GL		 50void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
51{
54680fe7
SH		 52 host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
53 sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 54}
55
56void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
57{
54680fe7
SH		 58 host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ);
59 sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 60}
61
62static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
63{
64 sd_ctrl_write32(host, CTL_STATUS, ~i);
65}
66
67static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
68{
69 host->sg_len = data->sg_len;
70 host->sg_ptr = data->sg;
71 host->sg_orig = data->sg;
72 host->sg_off = 0;
73}
74
75static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
76{
77 host->sg_ptr = sg_next(host->sg_ptr);
78 host->sg_off = 0;
79 return --host->sg_len;
80}
81
82#ifdef CONFIG_MMC_DEBUG
83
84#define STATUS_TO_TEXT(a, status, i) \
85 do { \
86 if (status & TMIO_STAT_##a) { \
87 if (i++) \
88 printk(" | "); \
89 printk(#a); \
90 } \
91 } while (0)
92
93static void pr_debug_status(u32 status)
94{
95 int i = 0;
a3c76eb9 96 pr_debug("status: %08x = ", status);
b6147490
GL		 97 STATUS_TO_TEXT(CARD_REMOVE, status, i);
98 STATUS_TO_TEXT(CARD_INSERT, status, i);
99 STATUS_TO_TEXT(SIGSTATE, status, i);
100 STATUS_TO_TEXT(WRPROTECT, status, i);
101 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
102 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
103 STATUS_TO_TEXT(SIGSTATE_A, status, i);
104 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
105 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
106 STATUS_TO_TEXT(ILL_FUNC, status, i);
107 STATUS_TO_TEXT(CMD_BUSY, status, i);
108 STATUS_TO_TEXT(CMDRESPEND, status, i);
109 STATUS_TO_TEXT(DATAEND, status, i);
110 STATUS_TO_TEXT(CRCFAIL, status, i);
111 STATUS_TO_TEXT(DATATIMEOUT, status, i);
112 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
113 STATUS_TO_TEXT(RXOVERFLOW, status, i);
114 STATUS_TO_TEXT(TXUNDERRUN, status, i);
115 STATUS_TO_TEXT(RXRDY, status, i);
116 STATUS_TO_TEXT(TXRQ, status, i);
117 STATUS_TO_TEXT(ILL_ACCESS, status, i);
118 printk("\n");
119}
120
121#else
122#define pr_debug_status(s) do { } while (0)
123#endif
124
125static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
126{
127 struct tmio_mmc_host *host = mmc_priv(mmc);
128
129 if (enable) {
130 host->sdio_irq_enabled = 1;
54680fe7
SH		 131 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL &
132 ~TMIO_SDIO_STAT_IOIRQ;
b6147490 133 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
54680fe7 134 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
b6147490 135 } else {
54680fe7
SH		 136 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
137 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
b6147490
GL		 138 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
139 host->sdio_irq_enabled = 0;
140 }
141}
142
143static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
144{
145 u32 clk = 0, clock;
146
147 if (new_clock) {
148 for (clock = host->mmc->f_min, clk = 0x80000080;
149 new_clock >= (clock<<1); clk >>= 1)
150 clock <<= 1;
151 clk |= 0x100;
152 }
153
154 if (host->set_clk_div)
155 host->set_clk_div(host->pdev, (clk>>22) & 1);
156
157 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
158}
159
160static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
161{
69d1fe18 162 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
b6147490 163
69d1fe18
GL		 164 /* implicit BUG_ON(!res) */
165 if (resource_size(res) > 0x100) {
166 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
167 msleep(10);
168 }
d9b03421 169
b6147490
GL		 170 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
171 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
172 msleep(10);
173}
174
175static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
176{
69d1fe18 177 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
b6147490
GL		 178
179 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
180 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
181 msleep(10);
d9b03421 182
69d1fe18
GL		 183 /* implicit BUG_ON(!res) */
184 if (resource_size(res) > 0x100) {
185 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
186 msleep(10);
187 }
b6147490
GL		 188}
189
190static void tmio_mmc_reset(struct tmio_mmc_host *host)
191{
69d1fe18
GL		 192 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
193
b6147490
GL		 194 /* FIXME - should we set stop clock reg here */
195 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
69d1fe18
GL		 196 /* implicit BUG_ON(!res) */
197 if (resource_size(res) > 0x100)
198 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
b6147490
GL		 199 msleep(10);
200 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
69d1fe18
GL		 201 if (resource_size(res) > 0x100)
202 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
b6147490
GL		 203 msleep(10);
204}
205
206static void tmio_mmc_reset_work(struct work_struct *work)
207{
208 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
209 delayed_reset_work.work);
210 struct mmc_request *mrq;
211 unsigned long flags;
212
213 spin_lock_irqsave(&host->lock, flags);
214 mrq = host->mrq;
215
df3ef2d3
GL		 216 /*
217 * is request already finished? Since we use a non-blocking
218 * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
219 * us, so, have to check for IS_ERR(host->mrq)
220 */
221 if (IS_ERR_OR_NULL(mrq)
b6147490
GL		 222 || time_is_after_jiffies(host->last_req_ts +
223 msecs_to_jiffies(2000))) {
224 spin_unlock_irqrestore(&host->lock, flags);
225 return;
226 }
227
228 dev_warn(&host->pdev->dev,
229 "timeout waiting for hardware interrupt (CMD%u)\n",
230 mrq->cmd->opcode);
231
232 if (host->data)
233 host->data->error = -ETIMEDOUT;
234 else if (host->cmd)
235 host->cmd->error = -ETIMEDOUT;
236 else
237 mrq->cmd->error = -ETIMEDOUT;
238
239 host->cmd = NULL;
240 host->data = NULL;
b6147490
GL		 241 host->force_pio = false;
242
243 spin_unlock_irqrestore(&host->lock, flags);
244
245 tmio_mmc_reset(host);
246
df3ef2d3
GL		 247 /* Ready for new calls */
248 host->mrq = NULL;
249
e3de2be7 250 tmio_mmc_abort_dma(host);
b6147490
GL		 251 mmc_request_done(host->mmc, mrq);
252}
253
df3ef2d3 254/* called with host->lock held, interrupts disabled */
b6147490
GL		 255static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
256{
b9269fdd
GL		 257 struct mmc_request *mrq;
258 unsigned long flags;
b6147490 259
b9269fdd
GL		 260 spin_lock_irqsave(&host->lock, flags);
261
262 mrq = host->mrq;
263 if (IS_ERR_OR_NULL(mrq)) {
264 spin_unlock_irqrestore(&host->lock, flags);
b6147490 265 return;
b9269fdd 266 }
b6147490 267
b6147490
GL		 268 host->cmd = NULL;
269 host->data = NULL;
270 host->force_pio = false;
271
272 cancel_delayed_work(&host->delayed_reset_work);
273
df3ef2d3 274 host->mrq = NULL;
b9269fdd 275 spin_unlock_irqrestore(&host->lock, flags);
df3ef2d3 276
e3de2be7
GL		 277 if (mrq->cmd->error || (mrq->data && mrq->data->error))
278 tmio_mmc_abort_dma(host);
279
b6147490
GL		 280 mmc_request_done(host->mmc, mrq);
281}
282
b9269fdd
GL		 283static void tmio_mmc_done_work(struct work_struct *work)
284{
285 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
286 done);
287 tmio_mmc_finish_request(host);
288}
289
b6147490
GL		 290/* These are the bitmasks the tmio chip requires to implement the MMC response
291 * types. Note that R1 and R6 are the same in this scheme. */
292#define APP_CMD 0x0040
293#define RESP_NONE 0x0300
294#define RESP_R1 0x0400
295#define RESP_R1B 0x0500
296#define RESP_R2 0x0600
297#define RESP_R3 0x0700
298#define DATA_PRESENT 0x0800
299#define TRANSFER_READ 0x1000
300#define TRANSFER_MULTI 0x2000
301#define SECURITY_CMD 0x4000
302
303static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
304{
305 struct mmc_data *data = host->data;
306 int c = cmd->opcode;
e23cd53c 307 u32 irq_mask = TMIO_MASK_CMD;
b6147490
GL		 308
309 /* Command 12 is handled by hardware */
310 if (cmd->opcode == 12 && !cmd->arg) {
311 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
312 return 0;
313 }
314
315 switch (mmc_resp_type(cmd)) {
316 case MMC_RSP_NONE: c |= RESP_NONE; break;
317 case MMC_RSP_R1: c |= RESP_R1; break;
318 case MMC_RSP_R1B: c |= RESP_R1B; break;
319 case MMC_RSP_R2: c |= RESP_R2; break;
320 case MMC_RSP_R3: c |= RESP_R3; break;
321 default:
322 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
323 return -EINVAL;
324 }
325
326 host->cmd = cmd;
327
328/* FIXME - this seems to be ok commented out but the spec suggest this bit
329 * should be set when issuing app commands.
330 * if(cmd->flags & MMC_FLAG_ACMD)
331 * c |= APP_CMD;
332 */
333 if (data) {
334 c |= DATA_PRESENT;
335 if (data->blocks > 1) {
336 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
337 c |= TRANSFER_MULTI;
338 }
339 if (data->flags & MMC_DATA_READ)
340 c |= TRANSFER_READ;
341 }
342
e23cd53c
GL		 343 if (!host->native_hotplug)
344 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
345 tmio_mmc_enable_mmc_irqs(host, irq_mask);
b6147490
GL		 346
347 /* Fire off the command */
348 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
349 sd_ctrl_write16(host, CTL_SD_CMD, c);
350
351 return 0;
352}
353
354/*
355 * This chip always returns (at least?) as much data as you ask for.
356 * I'm unsure what happens if you ask for less than a block. This should be
25985edc 357 * looked into to ensure that a funny length read doesn't hose the controller.
b6147490
GL		 358 */
359static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
360{
361 struct mmc_data *data = host->data;
362 void *sg_virt;
363 unsigned short *buf;
364 unsigned int count;
365 unsigned long flags;
366
367 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
368 pr_err("PIO IRQ in DMA mode!\n");
369 return;
370 } else if (!data) {
371 pr_debug("Spurious PIO IRQ\n");
372 return;
373 }
374
375 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
376 buf = (unsigned short *)(sg_virt + host->sg_off);
377
378 count = host->sg_ptr->length - host->sg_off;
379 if (count > data->blksz)
380 count = data->blksz;
381
382 pr_debug("count: %08x offset: %08x flags %08x\n",
383 count, host->sg_off, data->flags);
384
385 /* Transfer the data */
386 if (data->flags & MMC_DATA_READ)
387 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
388 else
389 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
390
391 host->sg_off += count;
392
393 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
394
395 if (host->sg_off == host->sg_ptr->length)
396 tmio_mmc_next_sg(host);
397
398 return;
399}
400
401static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
402{
403 if (host->sg_ptr == &host->bounce_sg) {
404 unsigned long flags;
405 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
406 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
407 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
408 }
409}
410
411/* needs to be called with host->lock held */
412void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
413{
414 struct mmc_data *data = host->data;
415 struct mmc_command *stop;
416
417 host->data = NULL;
418
419 if (!data) {
420 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
421 return;
422 }
423 stop = data->stop;
424
425 /* FIXME - return correct transfer count on errors */
426 if (!data->error)
427 data->bytes_xfered = data->blocks * data->blksz;
428 else
429 data->bytes_xfered = 0;
430
431 pr_debug("Completed data request\n");
432
433 /*
434 * FIXME: other drivers allow an optional stop command of any given type
435 * which we dont do, as the chip can auto generate them.
436 * Perhaps we can be smarter about when to use auto CMD12 and
437 * only issue the auto request when we know this is the desired
438 * stop command, allowing fallback to the stop command the
439 * upper layers expect. For now, we do what works.
440 */
441
442 if (data->flags & MMC_DATA_READ) {
443 if (host->chan_rx && !host->force_pio)
444 tmio_mmc_check_bounce_buffer(host);
445 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
446 host->mrq);
447 } else {
448 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
449 host->mrq);
450 }
451
452 if (stop) {
453 if (stop->opcode == 12 && !stop->arg)
454 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
455 else
456 BUG();
457 }
458
b9269fdd 459 schedule_work(&host->done);
b6147490
GL		 460}
461
462static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
463{
464 struct mmc_data *data;
465 spin_lock(&host->lock);
466 data = host->data;
467
468 if (!data)
469 goto out;
470
471 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
472 /*
473 * Has all data been written out yet? Testing on SuperH showed,
474 * that in most cases the first interrupt comes already with the
475 * BUSY status bit clear, but on some operations, like mount or
476 * in the beginning of a write / sync / umount, there is one
477 * DATAEND interrupt with the BUSY bit set, in this cases
478 * waiting for one more interrupt fixes the problem.
479 */
480 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
481 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
482 tasklet_schedule(&host->dma_complete);
483 }
484 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
485 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
486 tasklet_schedule(&host->dma_complete);
487 } else {
488 tmio_mmc_do_data_irq(host);
489 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
490 }
491out:
492 spin_unlock(&host->lock);
493}
494
495static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
496 unsigned int stat)
497{
498 struct mmc_command *cmd = host->cmd;
499 int i, addr;
500
501 spin_lock(&host->lock);
502
503 if (!host->cmd) {
504 pr_debug("Spurious CMD irq\n");
505 goto out;
506 }
507
508 host->cmd = NULL;
509
510 /* This controller is sicker than the PXA one. Not only do we need to
511 * drop the top 8 bits of the first response word, we also need to
512 * modify the order of the response for short response command types.
513 */
514
515 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
516 cmd->resp[i] = sd_ctrl_read32(host, addr);
517
518 if (cmd->flags & MMC_RSP_136) {
519 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
520 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
521 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
522 cmd->resp[3] <<= 8;
523 } else if (cmd->flags & MMC_RSP_R3) {
524 cmd->resp[0] = cmd->resp[3];
525 }
526
527 if (stat & TMIO_STAT_CMDTIMEOUT)
528 cmd->error = -ETIMEDOUT;
529 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
530 cmd->error = -EILSEQ;
531
532 /* If there is data to handle we enable data IRQs here, and
533 * we will ultimatley finish the request in the data_end handler.
534 * If theres no data or we encountered an error, finish now.
535 */
536 if (host->data && !cmd->error) {
537 if (host->data->flags & MMC_DATA_READ) {
538 if (host->force_pio || !host->chan_rx)
539 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
540 else
541 tasklet_schedule(&host->dma_issue);
542 } else {
543 if (host->force_pio || !host->chan_tx)
544 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
545 else
546 tasklet_schedule(&host->dma_issue);
547 }
548 } else {
b9269fdd 549 schedule_work(&host->done);
b6147490
GL		 550 }
551
552out:
553 spin_unlock(&host->lock);
554}
555
7729c7a2
SH		 556static void tmio_mmc_card_irq_status(struct tmio_mmc_host *host,
557 int *ireg, int *status)
b6147490 558{
7729c7a2
SH		 559 *status = sd_ctrl_read32(host, CTL_STATUS);
560 *ireg = *status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;
b6147490 561
7729c7a2
SH		 562 pr_debug_status(*status);
563 pr_debug_status(*ireg);
564}
b6147490 565
7729c7a2
SH		 566static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host,
567 int ireg, int status)
568{
569 struct mmc_host *mmc = host->mmc;
b6147490 570
e312eb1e
PP		 571 /* Card insert / remove attempts */
572 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
573 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
574 TMIO_STAT_CARD_REMOVE);
71d111cd
GL		 575 if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) ||
576 ((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) &&
577 !work_pending(&mmc->detect.work))
b9269fdd 578 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
7729c7a2 579 return true;
b6147490
GL		 580 }
581
7729c7a2
SH		 582 return false;
583}
584
585irqreturn_t tmio_mmc_card_detect_irq(int irq, void *devid)
586{
587 unsigned int ireg, status;
588 struct tmio_mmc_host *host = devid;
b6147490 589
7729c7a2
SH		 590 tmio_mmc_card_irq_status(host, &ireg, &status);
591 __tmio_mmc_card_detect_irq(host, ireg, status);
592
593 return IRQ_HANDLED;
594}
595EXPORT_SYMBOL(tmio_mmc_card_detect_irq);
596
597static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host,
598 int ireg, int status)
599{
e312eb1e
PP		 600 /* Command completion */
601 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
602 tmio_mmc_ack_mmc_irqs(host,
603 TMIO_STAT_CMDRESPEND |
604 TMIO_STAT_CMDTIMEOUT);
605 tmio_mmc_cmd_irq(host, status);
7729c7a2 606 return true;
e312eb1e 607 }
b6147490 608
e312eb1e
PP		 609 /* Data transfer */
610 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
611 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
612 tmio_mmc_pio_irq(host);
7729c7a2 613 return true;
e312eb1e 614 }
b6147490 615
e312eb1e
PP		 616 /* Data transfer completion */
617 if (ireg & TMIO_STAT_DATAEND) {
618 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
619 tmio_mmc_data_irq(host);
7729c7a2 620 return true;
b6147490 621 }
e312eb1e 622
7729c7a2
SH		 623 return false;
624}
625
626irqreturn_t tmio_mmc_sdcard_irq(int irq, void *devid)
627{
628 unsigned int ireg, status;
629 struct tmio_mmc_host *host = devid;
630
631 tmio_mmc_card_irq_status(host, &ireg, &status);
632 __tmio_mmc_sdcard_irq(host, ireg, status);
633
634 return IRQ_HANDLED;
635}
636EXPORT_SYMBOL(tmio_mmc_sdcard_irq);
637
638irqreturn_t tmio_mmc_sdio_irq(int irq, void *devid)
639{
640 struct tmio_mmc_host *host = devid;
641 struct mmc_host *mmc = host->mmc;
642 struct tmio_mmc_data *pdata = host->pdata;
643 unsigned int ireg, status;
644
645 if (!(pdata->flags & TMIO_MMC_SDIO_IRQ))
646 return IRQ_HANDLED;
647
648 status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
649 ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdcard_irq_mask;
650
651 sd_ctrl_write16(host, CTL_SDIO_STATUS, status & ~TMIO_SDIO_MASK_ALL);
652
653 if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ)
654 mmc_signal_sdio_irq(mmc);
655
656 return IRQ_HANDLED;
657}
658EXPORT_SYMBOL(tmio_mmc_sdio_irq);
659
660irqreturn_t tmio_mmc_irq(int irq, void *devid)
661{
662 struct tmio_mmc_host *host = devid;
663 unsigned int ireg, status;
664
665 pr_debug("MMC IRQ begin\n");
666
667 tmio_mmc_card_irq_status(host, &ireg, &status);
668 if (__tmio_mmc_card_detect_irq(host, ireg, status))
669 return IRQ_HANDLED;
670 if (__tmio_mmc_sdcard_irq(host, ireg, status))
671 return IRQ_HANDLED;
672
673 tmio_mmc_sdio_irq(irq, devid);
b6147490 674
b6147490
GL		 675 return IRQ_HANDLED;
676}
8e7bfdb3 677EXPORT_SYMBOL(tmio_mmc_irq);
b6147490
GL		 678
679static int tmio_mmc_start_data(struct tmio_mmc_host *host,
680 struct mmc_data *data)
681{
682 struct tmio_mmc_data *pdata = host->pdata;
683
684 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
685 data->blksz, data->blocks);
686
687 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
688 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
689 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
690
691 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
692 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
693 mmc_hostname(host->mmc), data->blksz);
694 return -EINVAL;
695 }
696 }
697
698 tmio_mmc_init_sg(host, data);
699 host->data = data;
700
701 /* Set transfer length / blocksize */
702 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
703 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
704
705 tmio_mmc_start_dma(host, data);
706
707 return 0;
708}
709
710/* Process requests from the MMC layer */
711static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
712{
713 struct tmio_mmc_host *host = mmc_priv(mmc);
df3ef2d3 714 unsigned long flags;
b6147490
GL		 715 int ret;
716
df3ef2d3
GL		 717 spin_lock_irqsave(&host->lock, flags);
718
719 if (host->mrq) {
b6147490 720 pr_debug("request not null\n");
df3ef2d3
GL		 721 if (IS_ERR(host->mrq)) {
722 spin_unlock_irqrestore(&host->lock, flags);
723 mrq->cmd->error = -EAGAIN;
724 mmc_request_done(mmc, mrq);
725 return;
726 }
727 }
b6147490
GL		 728
729 host->last_req_ts = jiffies;
730 wmb();
731 host->mrq = mrq;
732
df3ef2d3
GL		 733 spin_unlock_irqrestore(&host->lock, flags);
734
b6147490
GL		 735 if (mrq->data) {
736 ret = tmio_mmc_start_data(host, mrq->data);
737 if (ret)
738 goto fail;
739 }
740
741 ret = tmio_mmc_start_command(host, mrq->cmd);
742 if (!ret) {
743 schedule_delayed_work(&host->delayed_reset_work,
744 msecs_to_jiffies(2000));
745 return;
746 }
747
748fail:
b6147490 749 host->force_pio = false;
df3ef2d3 750 host->mrq = NULL;
b6147490
GL		 751 mrq->cmd->error = ret;
752 mmc_request_done(mmc, mrq);
753}
754
755/* Set MMC clock / power.
756 * Note: This controller uses a simple divider scheme therefore it cannot
757 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
758 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
759 * slowest setting.
760 */
761static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
762{
763 struct tmio_mmc_host *host = mmc_priv(mmc);
7311bef0 764 struct tmio_mmc_data *pdata = host->pdata;
df3ef2d3
GL		 765 unsigned long flags;
766
b9269fdd
GL		 767 mutex_lock(&host->ios_lock);
768
df3ef2d3
GL		 769 spin_lock_irqsave(&host->lock, flags);
770 if (host->mrq) {
771 if (IS_ERR(host->mrq)) {
772 dev_dbg(&host->pdev->dev,
773 "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
774 current->comm, task_pid_nr(current),
775 ios->clock, ios->power_mode);
776 host->mrq = ERR_PTR(-EINTR);
777 } else {
778 dev_dbg(&host->pdev->dev,
779 "%s.%d: CMD%u active since %lu, now %lu!\n",
780 current->comm, task_pid_nr(current),
781 host->mrq->cmd->opcode, host->last_req_ts, jiffies);
782 }
783 spin_unlock_irqrestore(&host->lock, flags);
b9269fdd
GL		 784
785 mutex_unlock(&host->ios_lock);
df3ef2d3
GL		 786 return;
787 }
788
789 host->mrq = ERR_PTR(-EBUSY);
790
791 spin_unlock_irqrestore(&host->lock, flags);
b6147490 792
71d111cd
GL		 793 /*
794 * pdata->power == false only if COLD_CD is available, otherwise only
795 * in short time intervals during probing or resuming
796 */
797 if (ios->power_mode == MMC_POWER_ON && ios->clock) {
798 if (!pdata->power) {
7311bef0
GL		 799 pm_runtime_get_sync(&host->pdev->dev);
800 pdata->power = true;
801 }
71d111cd 802 tmio_mmc_set_clock(host, ios->clock);
c919c2a0
GL		 803 /* power up SD bus */
804 if (host->set_pwr)
805 host->set_pwr(host->pdev, 1);
5fd01579
GL		 806 /* start bus clock */
807 tmio_mmc_clk_start(host);
71d111cd 808 } else if (ios->power_mode != MMC_POWER_UP) {
f6b8b52c 809 if (host->set_pwr && ios->power_mode == MMC_POWER_OFF)
71d111cd 810 host->set_pwr(host->pdev, 0);
cbb18b30 811 if (pdata->power) {
71d111cd
GL		 812 pdata->power = false;
813 pm_runtime_put(&host->pdev->dev);
814 }
815 tmio_mmc_clk_stop(host);
b6147490
GL		 816 }
817
818 switch (ios->bus_width) {
819 case MMC_BUS_WIDTH_1:
820 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
821 break;
822 case MMC_BUS_WIDTH_4:
823 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
824 break;
825 }
826
827 /* Let things settle. delay taken from winCE driver */
828 udelay(140);
df3ef2d3
GL		 829 if (PTR_ERR(host->mrq) == -EINTR)
830 dev_dbg(&host->pdev->dev,
831 "%s.%d: IOS interrupted: clk %u, mode %u",
832 current->comm, task_pid_nr(current),
833 ios->clock, ios->power_mode);
834 host->mrq = NULL;
b9269fdd
GL		 835
836 mutex_unlock(&host->ios_lock);
b6147490
GL		 837}
838
839static int tmio_mmc_get_ro(struct mmc_host *mmc)
840{
841 struct tmio_mmc_host *host = mmc_priv(mmc);
842 struct tmio_mmc_data *pdata = host->pdata;
843
7d8b4c2a
GL		 844 return !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
845 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
b6147490
GL		 846}
847
848static int tmio_mmc_get_cd(struct mmc_host *mmc)
849{
850 struct tmio_mmc_host *host = mmc_priv(mmc);
851 struct tmio_mmc_data *pdata = host->pdata;
852
853 if (!pdata->get_cd)
854 return -ENOSYS;
855 else
856 return pdata->get_cd(host->pdev);
857}
858
859static const struct mmc_host_ops tmio_mmc_ops = {
860 .request = tmio_mmc_request,
861 .set_ios = tmio_mmc_set_ios,
862 .get_ro = tmio_mmc_get_ro,
863 .get_cd = tmio_mmc_get_cd,
864 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
865};
866
867int __devinit tmio_mmc_host_probe(struct tmio_mmc_host **host,
868 struct platform_device *pdev,
869 struct tmio_mmc_data *pdata)
870{
871 struct tmio_mmc_host *_host;
872 struct mmc_host *mmc;
873 struct resource *res_ctl;
874 int ret;
875 u32 irq_mask = TMIO_MASK_CMD;
876
877 res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
878 if (!res_ctl)
879 return -EINVAL;
880
881 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
882 if (!mmc)
883 return -ENOMEM;
884
7311bef0 885 pdata->dev = &pdev->dev;
b6147490
GL		 886 _host = mmc_priv(mmc);
887 _host->pdata = pdata;
888 _host->mmc = mmc;
889 _host->pdev = pdev;
890 platform_set_drvdata(pdev, mmc);
891
892 _host->set_pwr = pdata->set_pwr;
893 _host->set_clk_div = pdata->set_clk_div;
894
895 /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
896 _host->bus_shift = resource_size(res_ctl) >> 10;
897
898 _host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
899 if (!_host->ctl) {
900 ret = -ENOMEM;
901 goto host_free;
902 }
903
904 mmc->ops = &tmio_mmc_ops;
905 mmc->caps = MMC_CAP_4_BIT_DATA | pdata->capabilities;
906 mmc->f_max = pdata->hclk;
907 mmc->f_min = mmc->f_max / 512;
908 mmc->max_segs = 32;
909 mmc->max_blk_size = 512;
910 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
911 mmc->max_segs;
912 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
913 mmc->max_seg_size = mmc->max_req_size;
914 if (pdata->ocr_mask)
915 mmc->ocr_avail = pdata->ocr_mask;
916 else
917 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
918
7311bef0 919 pdata->power = false;
e6ee7182
GL		 920 pm_runtime_enable(&pdev->dev);
921 ret = pm_runtime_resume(&pdev->dev);
922 if (ret < 0)
923 goto pm_disable;
924
cbb18b30
BH		 925 /*
926 * There are 4 different scenarios for the card detection:
927 * 1) an external gpio irq handles the cd (best for power savings)
928 * 2) internal sdhi irq handles the cd
929 * 3) a worker thread polls the sdhi - indicated by MMC_CAP_NEEDS_POLL
930 * 4) the medium is non-removable - indicated by MMC_CAP_NONREMOVABLE
931 *
932 * While we increment the rtpm counter for all scenarios when the mmc
933 * core activates us by calling an appropriate set_ios(), we must
934 * additionally ensure that in case 2) the tmio mmc hardware stays
935 * powered on during runtime for the card detection to work.
936 */
937 if (!(pdata->flags & TMIO_MMC_HAS_COLD_CD
938 || mmc->caps & MMC_CAP_NEEDS_POLL
939 || mmc->caps & MMC_CAP_NONREMOVABLE))
940 pm_runtime_get_noresume(&pdev->dev);
941
b6147490
GL		 942 tmio_mmc_clk_stop(_host);
943 tmio_mmc_reset(_host);
944
54680fe7 945 _host->sdcard_irq_mask = sd_ctrl_read32(_host, CTL_IRQ_MASK);
b6147490
GL		 946 tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
947 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
948 tmio_mmc_enable_sdio_irq(mmc, 0);
949
b6147490 950 spin_lock_init(&_host->lock);
b9269fdd 951 mutex_init(&_host->ios_lock);
b6147490
GL		 952
953 /* Init delayed work for request timeouts */
954 INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
b9269fdd 955 INIT_WORK(&_host->done, tmio_mmc_done_work);
b6147490
GL		 956
957 /* See if we also get DMA */
958 tmio_mmc_request_dma(_host, pdata);
959
960 mmc_add_host(mmc);
961
c419e611
RW		 962 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
963
b6147490
GL		 964 /* Unmask the IRQs we want to know about */
965 if (!_host->chan_rx)
966 irq_mask |= TMIO_MASK_READOP;
967 if (!_host->chan_tx)
968 irq_mask |= TMIO_MASK_WRITEOP;
e23cd53c
GL		 969 if (!_host->native_hotplug)
970 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
b6147490
GL		 971
972 tmio_mmc_enable_mmc_irqs(_host, irq_mask);
973
974 *host = _host;
975
976 return 0;
977
e6ee7182
GL		 978pm_disable:
979 pm_runtime_disable(&pdev->dev);
b6147490
GL		 980 iounmap(_host->ctl);
981host_free:
982 mmc_free_host(mmc);
983
984 return ret;
985}
986EXPORT_SYMBOL(tmio_mmc_host_probe);
987
988void tmio_mmc_host_remove(struct tmio_mmc_host *host)
989{
e6ee7182
GL		 990 struct platform_device *pdev = host->pdev;
991
7311bef0
GL		 992 /*
993 * We don't have to manipulate pdata->power here: if there is a card in
994 * the slot, the runtime PM is active and our .runtime_resume() will not
995 * be run. If there is no card in the slot and the platform can suspend
996 * the controller, the runtime PM is suspended and pdata->power == false,
997 * so, our .runtime_resume() will not try to detect a card in the slot.
998 */
cbb18b30
BH		 999 if (host->pdata->flags & TMIO_MMC_HAS_COLD_CD
1000 || host->mmc->caps & MMC_CAP_NEEDS_POLL
1001 || host->mmc->caps & MMC_CAP_NONREMOVABLE)
7311bef0
GL		 1002 pm_runtime_get_sync(&pdev->dev);
1003
c419e611
RW		 1004 dev_pm_qos_hide_latency_limit(&pdev->dev);
1005
b6147490 1006 mmc_remove_host(host->mmc);
b9269fdd 1007 cancel_work_sync(&host->done);
b6147490
GL		 1008 cancel_delayed_work_sync(&host->delayed_reset_work);
1009 tmio_mmc_release_dma(host);
e6ee7182 1010
e6ee7182
GL		 1011 pm_runtime_put_sync(&pdev->dev);
1012 pm_runtime_disable(&pdev->dev);
7311bef0
GL		 1013
1014 iounmap(host->ctl);
1015 mmc_free_host(host->mmc);
b6147490
GL		 1016}
1017EXPORT_SYMBOL(tmio_mmc_host_remove);
1018
e6ee7182
GL		 1019#ifdef CONFIG_PM
1020int tmio_mmc_host_suspend(struct device *dev)
1021{
1022 struct mmc_host *mmc = dev_get_drvdata(dev);
1023 struct tmio_mmc_host *host = mmc_priv(mmc);
1024 int ret = mmc_suspend_host(mmc);
1025
1026 if (!ret)
1027 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
1028
1029 host->pm_error = pm_runtime_put_sync(dev);
1030
1031 return ret;
1032}
1033EXPORT_SYMBOL(tmio_mmc_host_suspend);
1034
1035int tmio_mmc_host_resume(struct device *dev)
1036{
1037 struct mmc_host *mmc = dev_get_drvdata(dev);
1038 struct tmio_mmc_host *host = mmc_priv(mmc);
1039
7311bef0
GL		 1040 /* The MMC core will perform the complete set up */
1041 host->pdata->power = false;
1042
71d111cd 1043 host->pm_global = true;
e6ee7182
GL		 1044 if (!host->pm_error)
1045 pm_runtime_get_sync(dev);
1046
71d111cd
GL		 1047 if (host->pm_global) {
1048 /* Runtime PM resume callback didn't run */
1049 tmio_mmc_reset(host);
162f43e3 1050 tmio_mmc_enable_dma(host, true);
71d111cd
GL		 1051 host->pm_global = false;
1052 }
e6ee7182
GL		 1053
1054 return mmc_resume_host(mmc);
1055}
1056EXPORT_SYMBOL(tmio_mmc_host_resume);
1057
1058#endif /* CONFIG_PM */
1059
7311bef0
GL		 1060int tmio_mmc_host_runtime_suspend(struct device *dev)
1061{
1062 return 0;
1063}
1064EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
1065
1066int tmio_mmc_host_runtime_resume(struct device *dev)
1067{
1068 struct mmc_host *mmc = dev_get_drvdata(dev);
1069 struct tmio_mmc_host *host = mmc_priv(mmc);
1070 struct tmio_mmc_data *pdata = host->pdata;
1071
1072 tmio_mmc_reset(host);
162f43e3 1073 tmio_mmc_enable_dma(host, true);
7311bef0
GL		 1074
1075 if (pdata->power) {
1076 /* Only entered after a card-insert interrupt */
71d111cd
GL		 1077 if (!mmc->card)
1078 tmio_mmc_set_ios(mmc, &mmc->ios);
7311bef0
GL		 1079 mmc_detect_change(mmc, msecs_to_jiffies(100));
1080 }
71d111cd 1081 host->pm_global = false;
7311bef0
GL		 1082
1083 return 0;
1084}
1085EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
1086
b6147490 1087MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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