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mmc: protect the tmio_mmc driver against a theoretical race
[deliverable/linux.git] / drivers / mmc / host / tmio_mmc_pio.c
CommitLineData
b6147490
GL		 1/*
2 * linux/drivers/mmc/host/tmio_mmc_pio.c
3 *
4 * Copyright (C) 2011 Guennadi Liakhovetski
5 * Copyright (C) 2007 Ian Molton
6 * Copyright (C) 2004 Ian Molton
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Driver for the MMC / SD / SDIO IP found in:
13 *
14 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
15 *
16 * This driver draws mainly on scattered spec sheets, Reverse engineering
17 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
18 * support). (Further 4 bit support from a later datasheet).
19 *
20 * TODO:
21 * Investigate using a workqueue for PIO transfers
22 * Eliminate FIXMEs
23 * SDIO support
24 * Better Power management
25 * Handle MMC errors better
26 * double buffer support
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/highmem.h>
33#include <linux/interrupt.h>
34#include <linux/io.h>
35#include <linux/irq.h>
36#include <linux/mfd/tmio.h>
37#include <linux/mmc/host.h>
cba179ae 38#include <linux/mmc/tmio.h>
b6147490
GL		 39#include <linux/module.h>
40#include <linux/pagemap.h>
41#include <linux/platform_device.h>
e6ee7182 42#include <linux/pm_runtime.h>
b6147490
GL		 43#include <linux/scatterlist.h>
44#include <linux/workqueue.h>
45#include <linux/spinlock.h>
46
47#include "tmio_mmc.h"
48
b6147490
GL		 49static u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
50{
51 return readw(host->ctl + (addr << host->bus_shift));
52}
53
54static void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
55 u16 *buf, int count)
56{
57 readsw(host->ctl + (addr << host->bus_shift), buf, count);
58}
59
60static u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)
61{
62 return readw(host->ctl + (addr << host->bus_shift)) |
63 readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
64}
65
66static void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
67{
68 writew(val, host->ctl + (addr << host->bus_shift));
69}
70
71static void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
72 u16 *buf, int count)
73{
74 writesw(host->ctl + (addr << host->bus_shift), buf, count);
75}
76
77static void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
78{
79 writew(val, host->ctl + (addr << host->bus_shift));
80 writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
81}
82
83void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
84{
85 u32 mask = sd_ctrl_read32(host, CTL_IRQ_MASK) & ~(i & TMIO_MASK_IRQ);
86 sd_ctrl_write32(host, CTL_IRQ_MASK, mask);
87}
88
89void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
90{
91 u32 mask = sd_ctrl_read32(host, CTL_IRQ_MASK) | (i & TMIO_MASK_IRQ);
92 sd_ctrl_write32(host, CTL_IRQ_MASK, mask);
93}
94
95static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
96{
97 sd_ctrl_write32(host, CTL_STATUS, ~i);
98}
99
100static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
101{
102 host->sg_len = data->sg_len;
103 host->sg_ptr = data->sg;
104 host->sg_orig = data->sg;
105 host->sg_off = 0;
106}
107
108static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
109{
110 host->sg_ptr = sg_next(host->sg_ptr);
111 host->sg_off = 0;
112 return --host->sg_len;
113}
114
115#ifdef CONFIG_MMC_DEBUG
116
117#define STATUS_TO_TEXT(a, status, i) \
118 do { \
119 if (status & TMIO_STAT_##a) { \
120 if (i++) \
121 printk(" | "); \
122 printk(#a); \
123 } \
124 } while (0)
125
126static void pr_debug_status(u32 status)
127{
128 int i = 0;
129 printk(KERN_DEBUG "status: %08x = ", status);
130 STATUS_TO_TEXT(CARD_REMOVE, status, i);
131 STATUS_TO_TEXT(CARD_INSERT, status, i);
132 STATUS_TO_TEXT(SIGSTATE, status, i);
133 STATUS_TO_TEXT(WRPROTECT, status, i);
134 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
135 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
136 STATUS_TO_TEXT(SIGSTATE_A, status, i);
137 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
138 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
139 STATUS_TO_TEXT(ILL_FUNC, status, i);
140 STATUS_TO_TEXT(CMD_BUSY, status, i);
141 STATUS_TO_TEXT(CMDRESPEND, status, i);
142 STATUS_TO_TEXT(DATAEND, status, i);
143 STATUS_TO_TEXT(CRCFAIL, status, i);
144 STATUS_TO_TEXT(DATATIMEOUT, status, i);
145 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
146 STATUS_TO_TEXT(RXOVERFLOW, status, i);
147 STATUS_TO_TEXT(TXUNDERRUN, status, i);
148 STATUS_TO_TEXT(RXRDY, status, i);
149 STATUS_TO_TEXT(TXRQ, status, i);
150 STATUS_TO_TEXT(ILL_ACCESS, status, i);
151 printk("\n");
152}
153
154#else
155#define pr_debug_status(s) do { } while (0)
156#endif
157
158static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
159{
160 struct tmio_mmc_host *host = mmc_priv(mmc);
161
162 if (enable) {
163 host->sdio_irq_enabled = 1;
164 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
165 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK,
166 (TMIO_SDIO_MASK_ALL & ~TMIO_SDIO_STAT_IOIRQ));
167 } else {
168 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, TMIO_SDIO_MASK_ALL);
169 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
170 host->sdio_irq_enabled = 0;
171 }
172}
173
174static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
175{
176 u32 clk = 0, clock;
177
178 if (new_clock) {
179 for (clock = host->mmc->f_min, clk = 0x80000080;
180 new_clock >= (clock<<1); clk >>= 1)
181 clock <<= 1;
182 clk |= 0x100;
183 }
184
185 if (host->set_clk_div)
186 host->set_clk_div(host->pdev, (clk>>22) & 1);
187
188 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
189}
190
191static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
192{
69d1fe18 193 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
b6147490 194
69d1fe18
GL		 195 /* implicit BUG_ON(!res) */
196 if (resource_size(res) > 0x100) {
197 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
198 msleep(10);
199 }
d9b03421 200
b6147490
GL		 201 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
202 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
203 msleep(10);
204}
205
206static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
207{
69d1fe18 208 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
b6147490
GL		 209
210 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
211 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
212 msleep(10);
d9b03421 213
69d1fe18
GL		 214 /* implicit BUG_ON(!res) */
215 if (resource_size(res) > 0x100) {
216 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
217 msleep(10);
218 }
b6147490
GL		 219}
220
221static void tmio_mmc_reset(struct tmio_mmc_host *host)
222{
69d1fe18
GL		 223 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
224
b6147490
GL		 225 /* FIXME - should we set stop clock reg here */
226 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
69d1fe18
GL		 227 /* implicit BUG_ON(!res) */
228 if (resource_size(res) > 0x100)
229 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
b6147490
GL		 230 msleep(10);
231 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
69d1fe18
GL		 232 if (resource_size(res) > 0x100)
233 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
b6147490
GL		 234 msleep(10);
235}
236
237static void tmio_mmc_reset_work(struct work_struct *work)
238{
239 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
240 delayed_reset_work.work);
241 struct mmc_request *mrq;
242 unsigned long flags;
243
244 spin_lock_irqsave(&host->lock, flags);
245 mrq = host->mrq;
246
df3ef2d3
GL		 247 /*
248 * is request already finished? Since we use a non-blocking
249 * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
250 * us, so, have to check for IS_ERR(host->mrq)
251 */
252 if (IS_ERR_OR_NULL(mrq)
b6147490
GL		 253 || time_is_after_jiffies(host->last_req_ts +
254 msecs_to_jiffies(2000))) {
255 spin_unlock_irqrestore(&host->lock, flags);
256 return;
257 }
258
259 dev_warn(&host->pdev->dev,
260 "timeout waiting for hardware interrupt (CMD%u)\n",
261 mrq->cmd->opcode);
262
263 if (host->data)
264 host->data->error = -ETIMEDOUT;
265 else if (host->cmd)
266 host->cmd->error = -ETIMEDOUT;
267 else
268 mrq->cmd->error = -ETIMEDOUT;
269
270 host->cmd = NULL;
271 host->data = NULL;
b6147490
GL		 272 host->force_pio = false;
273
274 spin_unlock_irqrestore(&host->lock, flags);
275
276 tmio_mmc_reset(host);
277
df3ef2d3
GL		 278 /* Ready for new calls */
279 host->mrq = NULL;
280
b6147490
GL		 281 mmc_request_done(host->mmc, mrq);
282}
283
df3ef2d3 284/* called with host->lock held, interrupts disabled */
b6147490
GL		 285static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
286{
287 struct mmc_request *mrq = host->mrq;
288
289 if (!mrq)
290 return;
291
b6147490
GL		 292 host->cmd = NULL;
293 host->data = NULL;
294 host->force_pio = false;
295
296 cancel_delayed_work(&host->delayed_reset_work);
297
df3ef2d3
GL		 298 host->mrq = NULL;
299
300 /* FIXME: mmc_request_done() can schedule! */
b6147490
GL		 301 mmc_request_done(host->mmc, mrq);
302}
303
304/* These are the bitmasks the tmio chip requires to implement the MMC response
305 * types. Note that R1 and R6 are the same in this scheme. */
306#define APP_CMD 0x0040
307#define RESP_NONE 0x0300
308#define RESP_R1 0x0400
309#define RESP_R1B 0x0500
310#define RESP_R2 0x0600
311#define RESP_R3 0x0700
312#define DATA_PRESENT 0x0800
313#define TRANSFER_READ 0x1000
314#define TRANSFER_MULTI 0x2000
315#define SECURITY_CMD 0x4000
316
317static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
318{
319 struct mmc_data *data = host->data;
320 int c = cmd->opcode;
321
322 /* Command 12 is handled by hardware */
323 if (cmd->opcode == 12 && !cmd->arg) {
324 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
325 return 0;
326 }
327
328 switch (mmc_resp_type(cmd)) {
329 case MMC_RSP_NONE: c |= RESP_NONE; break;
330 case MMC_RSP_R1: c |= RESP_R1; break;
331 case MMC_RSP_R1B: c |= RESP_R1B; break;
332 case MMC_RSP_R2: c |= RESP_R2; break;
333 case MMC_RSP_R3: c |= RESP_R3; break;
334 default:
335 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
336 return -EINVAL;
337 }
338
339 host->cmd = cmd;
340
341/* FIXME - this seems to be ok commented out but the spec suggest this bit
342 * should be set when issuing app commands.
343 * if(cmd->flags & MMC_FLAG_ACMD)
344 * c |= APP_CMD;
345 */
346 if (data) {
347 c |= DATA_PRESENT;
348 if (data->blocks > 1) {
349 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
350 c |= TRANSFER_MULTI;
351 }
352 if (data->flags & MMC_DATA_READ)
353 c |= TRANSFER_READ;
354 }
355
356 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_CMD);
357
358 /* Fire off the command */
359 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
360 sd_ctrl_write16(host, CTL_SD_CMD, c);
361
362 return 0;
363}
364
365/*
366 * This chip always returns (at least?) as much data as you ask for.
367 * I'm unsure what happens if you ask for less than a block. This should be
25985edc 368 * looked into to ensure that a funny length read doesn't hose the controller.
b6147490
GL		 369 */
370static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
371{
372 struct mmc_data *data = host->data;
373 void *sg_virt;
374 unsigned short *buf;
375 unsigned int count;
376 unsigned long flags;
377
378 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
379 pr_err("PIO IRQ in DMA mode!\n");
380 return;
381 } else if (!data) {
382 pr_debug("Spurious PIO IRQ\n");
383 return;
384 }
385
386 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
387 buf = (unsigned short *)(sg_virt + host->sg_off);
388
389 count = host->sg_ptr->length - host->sg_off;
390 if (count > data->blksz)
391 count = data->blksz;
392
393 pr_debug("count: %08x offset: %08x flags %08x\n",
394 count, host->sg_off, data->flags);
395
396 /* Transfer the data */
397 if (data->flags & MMC_DATA_READ)
398 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
399 else
400 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
401
402 host->sg_off += count;
403
404 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
405
406 if (host->sg_off == host->sg_ptr->length)
407 tmio_mmc_next_sg(host);
408
409 return;
410}
411
412static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
413{
414 if (host->sg_ptr == &host->bounce_sg) {
415 unsigned long flags;
416 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
417 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
418 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
419 }
420}
421
422/* needs to be called with host->lock held */
423void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
424{
425 struct mmc_data *data = host->data;
426 struct mmc_command *stop;
427
428 host->data = NULL;
429
430 if (!data) {
431 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
432 return;
433 }
434 stop = data->stop;
435
436 /* FIXME - return correct transfer count on errors */
437 if (!data->error)
438 data->bytes_xfered = data->blocks * data->blksz;
439 else
440 data->bytes_xfered = 0;
441
442 pr_debug("Completed data request\n");
443
444 /*
445 * FIXME: other drivers allow an optional stop command of any given type
446 * which we dont do, as the chip can auto generate them.
447 * Perhaps we can be smarter about when to use auto CMD12 and
448 * only issue the auto request when we know this is the desired
449 * stop command, allowing fallback to the stop command the
450 * upper layers expect. For now, we do what works.
451 */
452
453 if (data->flags & MMC_DATA_READ) {
454 if (host->chan_rx && !host->force_pio)
455 tmio_mmc_check_bounce_buffer(host);
456 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
457 host->mrq);
458 } else {
459 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
460 host->mrq);
461 }
462
463 if (stop) {
464 if (stop->opcode == 12 && !stop->arg)
465 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
466 else
467 BUG();
468 }
469
470 tmio_mmc_finish_request(host);
471}
472
473static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
474{
475 struct mmc_data *data;
476 spin_lock(&host->lock);
477 data = host->data;
478
479 if (!data)
480 goto out;
481
482 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
483 /*
484 * Has all data been written out yet? Testing on SuperH showed,
485 * that in most cases the first interrupt comes already with the
486 * BUSY status bit clear, but on some operations, like mount or
487 * in the beginning of a write / sync / umount, there is one
488 * DATAEND interrupt with the BUSY bit set, in this cases
489 * waiting for one more interrupt fixes the problem.
490 */
491 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
492 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
493 tasklet_schedule(&host->dma_complete);
494 }
495 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
496 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
497 tasklet_schedule(&host->dma_complete);
498 } else {
499 tmio_mmc_do_data_irq(host);
500 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
501 }
502out:
503 spin_unlock(&host->lock);
504}
505
506static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
507 unsigned int stat)
508{
509 struct mmc_command *cmd = host->cmd;
510 int i, addr;
511
512 spin_lock(&host->lock);
513
514 if (!host->cmd) {
515 pr_debug("Spurious CMD irq\n");
516 goto out;
517 }
518
519 host->cmd = NULL;
520
521 /* This controller is sicker than the PXA one. Not only do we need to
522 * drop the top 8 bits of the first response word, we also need to
523 * modify the order of the response for short response command types.
524 */
525
526 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
527 cmd->resp[i] = sd_ctrl_read32(host, addr);
528
529 if (cmd->flags & MMC_RSP_136) {
530 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
531 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
532 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
533 cmd->resp[3] <<= 8;
534 } else if (cmd->flags & MMC_RSP_R3) {
535 cmd->resp[0] = cmd->resp[3];
536 }
537
538 if (stat & TMIO_STAT_CMDTIMEOUT)
539 cmd->error = -ETIMEDOUT;
540 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
541 cmd->error = -EILSEQ;
542
543 /* If there is data to handle we enable data IRQs here, and
544 * we will ultimatley finish the request in the data_end handler.
545 * If theres no data or we encountered an error, finish now.
546 */
547 if (host->data && !cmd->error) {
548 if (host->data->flags & MMC_DATA_READ) {
549 if (host->force_pio || !host->chan_rx)
550 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
551 else
552 tasklet_schedule(&host->dma_issue);
553 } else {
554 if (host->force_pio || !host->chan_tx)
555 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
556 else
557 tasklet_schedule(&host->dma_issue);
558 }
559 } else {
560 tmio_mmc_finish_request(host);
561 }
562
563out:
564 spin_unlock(&host->lock);
565}
566
567static irqreturn_t tmio_mmc_irq(int irq, void *devid)
568{
569 struct tmio_mmc_host *host = devid;
570 struct tmio_mmc_data *pdata = host->pdata;
571 unsigned int ireg, irq_mask, status;
572 unsigned int sdio_ireg, sdio_irq_mask, sdio_status;
573
574 pr_debug("MMC IRQ begin\n");
575
576 status = sd_ctrl_read32(host, CTL_STATUS);
577 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
578 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
579
580 sdio_ireg = 0;
581 if (!ireg && pdata->flags & TMIO_MMC_SDIO_IRQ) {
582 sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
583 sdio_irq_mask = sd_ctrl_read16(host, CTL_SDIO_IRQ_MASK);
584 sdio_ireg = sdio_status & TMIO_SDIO_MASK_ALL & ~sdio_irq_mask;
585
586 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status & ~TMIO_SDIO_MASK_ALL);
587
588 if (sdio_ireg && !host->sdio_irq_enabled) {
589 pr_warning("tmio_mmc: Spurious SDIO IRQ, disabling! 0x%04x 0x%04x 0x%04x\n",
590 sdio_status, sdio_irq_mask, sdio_ireg);
591 tmio_mmc_enable_sdio_irq(host->mmc, 0);
592 goto out;
593 }
594
595 if (host->mmc->caps & MMC_CAP_SDIO_IRQ &&
596 sdio_ireg & TMIO_SDIO_STAT_IOIRQ)
597 mmc_signal_sdio_irq(host->mmc);
598
599 if (sdio_ireg)
600 goto out;
601 }
602
603 pr_debug_status(status);
604 pr_debug_status(ireg);
605
606 if (!ireg) {
607 tmio_mmc_disable_mmc_irqs(host, status & ~irq_mask);
608
609 pr_warning("tmio_mmc: Spurious irq, disabling! "
610 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg);
611 pr_debug_status(status);
612
613 goto out;
614 }
615
616 while (ireg) {
617 /* Card insert / remove attempts */
618 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
619 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
620 TMIO_STAT_CARD_REMOVE);
621 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
622 }
623
624 /* CRC and other errors */
625/* if (ireg & TMIO_STAT_ERR_IRQ)
626 * handled |= tmio_error_irq(host, irq, stat);
627 */
628
629 /* Command completion */
630 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
631 tmio_mmc_ack_mmc_irqs(host,
632 TMIO_STAT_CMDRESPEND |
633 TMIO_STAT_CMDTIMEOUT);
634 tmio_mmc_cmd_irq(host, status);
635 }
636
637 /* Data transfer */
638 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
639 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
640 tmio_mmc_pio_irq(host);
641 }
642
643 /* Data transfer completion */
644 if (ireg & TMIO_STAT_DATAEND) {
645 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
646 tmio_mmc_data_irq(host);
647 }
648
649 /* Check status - keep going until we've handled it all */
650 status = sd_ctrl_read32(host, CTL_STATUS);
651 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
652 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
653
654 pr_debug("Status at end of loop: %08x\n", status);
655 pr_debug_status(status);
656 }
657 pr_debug("MMC IRQ end\n");
658
659out:
660 return IRQ_HANDLED;
661}
662
663static int tmio_mmc_start_data(struct tmio_mmc_host *host,
664 struct mmc_data *data)
665{
666 struct tmio_mmc_data *pdata = host->pdata;
667
668 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
669 data->blksz, data->blocks);
670
671 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
672 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
673 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
674
675 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
676 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
677 mmc_hostname(host->mmc), data->blksz);
678 return -EINVAL;
679 }
680 }
681
682 tmio_mmc_init_sg(host, data);
683 host->data = data;
684
685 /* Set transfer length / blocksize */
686 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
687 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
688
689 tmio_mmc_start_dma(host, data);
690
691 return 0;
692}
693
694/* Process requests from the MMC layer */
695static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
696{
697 struct tmio_mmc_host *host = mmc_priv(mmc);
df3ef2d3 698 unsigned long flags;
b6147490
GL		 699 int ret;
700
df3ef2d3
GL		 701 spin_lock_irqsave(&host->lock, flags);
702
703 if (host->mrq) {
b6147490 704 pr_debug("request not null\n");
df3ef2d3
GL		 705 if (IS_ERR(host->mrq)) {
706 spin_unlock_irqrestore(&host->lock, flags);
707 mrq->cmd->error = -EAGAIN;
708 mmc_request_done(mmc, mrq);
709 return;
710 }
711 }
b6147490
GL		 712
713 host->last_req_ts = jiffies;
714 wmb();
715 host->mrq = mrq;
716
df3ef2d3
GL		 717 spin_unlock_irqrestore(&host->lock, flags);
718
b6147490
GL		 719 if (mrq->data) {
720 ret = tmio_mmc_start_data(host, mrq->data);
721 if (ret)
722 goto fail;
723 }
724
725 ret = tmio_mmc_start_command(host, mrq->cmd);
726 if (!ret) {
727 schedule_delayed_work(&host->delayed_reset_work,
728 msecs_to_jiffies(2000));
729 return;
730 }
731
732fail:
b6147490 733 host->force_pio = false;
df3ef2d3 734 host->mrq = NULL;
b6147490
GL		 735 mrq->cmd->error = ret;
736 mmc_request_done(mmc, mrq);
737}
738
739/* Set MMC clock / power.
740 * Note: This controller uses a simple divider scheme therefore it cannot
741 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
742 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
743 * slowest setting.
744 */
745static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
746{
747 struct tmio_mmc_host *host = mmc_priv(mmc);
df3ef2d3
GL		 748 unsigned long flags;
749
750 spin_lock_irqsave(&host->lock, flags);
751 if (host->mrq) {
752 if (IS_ERR(host->mrq)) {
753 dev_dbg(&host->pdev->dev,
754 "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
755 current->comm, task_pid_nr(current),
756 ios->clock, ios->power_mode);
757 host->mrq = ERR_PTR(-EINTR);
758 } else {
759 dev_dbg(&host->pdev->dev,
760 "%s.%d: CMD%u active since %lu, now %lu!\n",
761 current->comm, task_pid_nr(current),
762 host->mrq->cmd->opcode, host->last_req_ts, jiffies);
763 }
764 spin_unlock_irqrestore(&host->lock, flags);
765 return;
766 }
767
768 host->mrq = ERR_PTR(-EBUSY);
769
770 spin_unlock_irqrestore(&host->lock, flags);
b6147490
GL		 771
772 if (ios->clock)
773 tmio_mmc_set_clock(host, ios->clock);
774
a7edbe39 775 /* Power sequence - OFF -> UP -> ON */
c919c2a0
GL		 776 if (ios->power_mode == MMC_POWER_UP) {
777 /* power up SD bus */
778 if (host->set_pwr)
779 host->set_pwr(host->pdev, 1);
780 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
5fd01579
GL		 781 /* power down SD bus */
782 if (ios->power_mode == MMC_POWER_OFF && host->set_pwr)
b6147490
GL		 783 host->set_pwr(host->pdev, 0);
784 tmio_mmc_clk_stop(host);
5fd01579
GL		 785 } else {
786 /* start bus clock */
787 tmio_mmc_clk_start(host);
b6147490
GL		 788 }
789
790 switch (ios->bus_width) {
791 case MMC_BUS_WIDTH_1:
792 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
793 break;
794 case MMC_BUS_WIDTH_4:
795 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
796 break;
797 }
798
799 /* Let things settle. delay taken from winCE driver */
800 udelay(140);
df3ef2d3
GL		 801 if (PTR_ERR(host->mrq) == -EINTR)
802 dev_dbg(&host->pdev->dev,
803 "%s.%d: IOS interrupted: clk %u, mode %u",
804 current->comm, task_pid_nr(current),
805 ios->clock, ios->power_mode);
806 host->mrq = NULL;
b6147490
GL		 807}
808
809static int tmio_mmc_get_ro(struct mmc_host *mmc)
810{
811 struct tmio_mmc_host *host = mmc_priv(mmc);
812 struct tmio_mmc_data *pdata = host->pdata;
813
814 return ((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
815 !(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
816}
817
818static int tmio_mmc_get_cd(struct mmc_host *mmc)
819{
820 struct tmio_mmc_host *host = mmc_priv(mmc);
821 struct tmio_mmc_data *pdata = host->pdata;
822
823 if (!pdata->get_cd)
824 return -ENOSYS;
825 else
826 return pdata->get_cd(host->pdev);
827}
828
829static const struct mmc_host_ops tmio_mmc_ops = {
830 .request = tmio_mmc_request,
831 .set_ios = tmio_mmc_set_ios,
832 .get_ro = tmio_mmc_get_ro,
833 .get_cd = tmio_mmc_get_cd,
834 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
835};
836
837int __devinit tmio_mmc_host_probe(struct tmio_mmc_host **host,
838 struct platform_device *pdev,
839 struct tmio_mmc_data *pdata)
840{
841 struct tmio_mmc_host *_host;
842 struct mmc_host *mmc;
843 struct resource *res_ctl;
844 int ret;
845 u32 irq_mask = TMIO_MASK_CMD;
846
847 res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
848 if (!res_ctl)
849 return -EINVAL;
850
851 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
852 if (!mmc)
853 return -ENOMEM;
854
855 _host = mmc_priv(mmc);
856 _host->pdata = pdata;
857 _host->mmc = mmc;
858 _host->pdev = pdev;
859 platform_set_drvdata(pdev, mmc);
860
861 _host->set_pwr = pdata->set_pwr;
862 _host->set_clk_div = pdata->set_clk_div;
863
864 /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
865 _host->bus_shift = resource_size(res_ctl) >> 10;
866
867 _host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
868 if (!_host->ctl) {
869 ret = -ENOMEM;
870 goto host_free;
871 }
872
873 mmc->ops = &tmio_mmc_ops;
874 mmc->caps = MMC_CAP_4_BIT_DATA | pdata->capabilities;
875 mmc->f_max = pdata->hclk;
876 mmc->f_min = mmc->f_max / 512;
877 mmc->max_segs = 32;
878 mmc->max_blk_size = 512;
879 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
880 mmc->max_segs;
881 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
882 mmc->max_seg_size = mmc->max_req_size;
883 if (pdata->ocr_mask)
884 mmc->ocr_avail = pdata->ocr_mask;
885 else
886 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
887
e6ee7182
GL		 888 pm_runtime_enable(&pdev->dev);
889 ret = pm_runtime_resume(&pdev->dev);
890 if (ret < 0)
891 goto pm_disable;
892
b6147490
GL		 893 tmio_mmc_clk_stop(_host);
894 tmio_mmc_reset(_host);
895
896 ret = platform_get_irq(pdev, 0);
897 if (ret < 0)
e6ee7182 898 goto pm_suspend;
b6147490
GL		 899
900 _host->irq = ret;
901
902 tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
903 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
904 tmio_mmc_enable_sdio_irq(mmc, 0);
905
906 ret = request_irq(_host->irq, tmio_mmc_irq, IRQF_DISABLED |
907 IRQF_TRIGGER_FALLING, dev_name(&pdev->dev), _host);
908 if (ret)
e6ee7182 909 goto pm_suspend;
b6147490
GL		 910
911 spin_lock_init(&_host->lock);
912
913 /* Init delayed work for request timeouts */
914 INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
915
916 /* See if we also get DMA */
917 tmio_mmc_request_dma(_host, pdata);
918
e6ee7182
GL		 919 /* We have to keep the device powered for its card detection to work */
920 pm_runtime_get_noresume(&pdev->dev);
921
b6147490
GL		 922 mmc_add_host(mmc);
923
924 /* Unmask the IRQs we want to know about */
925 if (!_host->chan_rx)
926 irq_mask |= TMIO_MASK_READOP;
927 if (!_host->chan_tx)
928 irq_mask |= TMIO_MASK_WRITEOP;
929
930 tmio_mmc_enable_mmc_irqs(_host, irq_mask);
931
932 *host = _host;
933
934 return 0;
935
e6ee7182
GL		 936pm_suspend:
937 pm_runtime_suspend(&pdev->dev);
938pm_disable:
939 pm_runtime_disable(&pdev->dev);
b6147490
GL		 940 iounmap(_host->ctl);
941host_free:
942 mmc_free_host(mmc);
943
944 return ret;
945}
946EXPORT_SYMBOL(tmio_mmc_host_probe);
947
948void tmio_mmc_host_remove(struct tmio_mmc_host *host)
949{
e6ee7182
GL		 950 struct platform_device *pdev = host->pdev;
951
b6147490
GL		 952 mmc_remove_host(host->mmc);
953 cancel_delayed_work_sync(&host->delayed_reset_work);
954 tmio_mmc_release_dma(host);
955 free_irq(host->irq, host);
956 iounmap(host->ctl);
957 mmc_free_host(host->mmc);
e6ee7182
GL		 958
959 /* Compensate for pm_runtime_get_sync() in probe() above */
960 pm_runtime_put_sync(&pdev->dev);
961 pm_runtime_disable(&pdev->dev);
b6147490
GL		 962}
963EXPORT_SYMBOL(tmio_mmc_host_remove);
964
e6ee7182
GL		 965#ifdef CONFIG_PM
966int tmio_mmc_host_suspend(struct device *dev)
967{
968 struct mmc_host *mmc = dev_get_drvdata(dev);
969 struct tmio_mmc_host *host = mmc_priv(mmc);
970 int ret = mmc_suspend_host(mmc);
971
972 if (!ret)
973 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
974
975 host->pm_error = pm_runtime_put_sync(dev);
976
977 return ret;
978}
979EXPORT_SYMBOL(tmio_mmc_host_suspend);
980
981int tmio_mmc_host_resume(struct device *dev)
982{
983 struct mmc_host *mmc = dev_get_drvdata(dev);
984 struct tmio_mmc_host *host = mmc_priv(mmc);
985
986 if (!host->pm_error)
987 pm_runtime_get_sync(dev);
988
989 tmio_mmc_reset(mmc_priv(mmc));
990 tmio_mmc_request_dma(host, host->pdata);
991
992 return mmc_resume_host(mmc);
993}
994EXPORT_SYMBOL(tmio_mmc_host_resume);
995
996#endif /* CONFIG_PM */
997
b6147490 998MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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