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mmc: mmc_test: Remove set-but-unused variable.
[deliverable/linux.git] / drivers / mmc / host / via-sdmmc.c
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f0bf7f61
HW		 1/*
2 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
3 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 */
10
11#include <linux/pci.h>
12#include <linux/dma-mapping.h>
13#include <linux/highmem.h>
14#include <linux/delay.h>
15
16#include <linux/mmc/host.h>
17
18#define DRV_NAME "via_sdmmc"
19
20#define PCI_DEVICE_ID_VIA_9530 0x9530
21
22#define VIA_CRDR_SDC_OFF 0x200
23#define VIA_CRDR_DDMA_OFF 0x400
24#define VIA_CRDR_PCICTRL_OFF 0x600
25
26#define VIA_CRDR_MIN_CLOCK 375000
27#define VIA_CRDR_MAX_CLOCK 48000000
28
29/*
30 * PCI registers
31 */
32
33#define VIA_CRDR_PCI_WORK_MODE 0x40
34#define VIA_CRDR_PCI_DBG_MODE 0x41
35
36/*
37 * SDC MMIO Registers
38 */
39
40#define VIA_CRDR_SDCTRL 0x0
41#define VIA_CRDR_SDCTRL_START 0x01
42#define VIA_CRDR_SDCTRL_WRITE 0x04
43#define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
44#define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
45#define VIA_CRDR_SDCTRL_MULTI_WR 0x30
46#define VIA_CRDR_SDCTRL_MULTI_RD 0x40
47#define VIA_CRDR_SDCTRL_STOP 0x70
48
49#define VIA_CRDR_SDCTRL_RSP_NONE 0x0
50#define VIA_CRDR_SDCTRL_RSP_R1 0x10000
51#define VIA_CRDR_SDCTRL_RSP_R2 0x20000
52#define VIA_CRDR_SDCTRL_RSP_R3 0x30000
53#define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
54
55#define VIA_CRDR_SDCARG 0x4
56
57#define VIA_CRDR_SDBUSMODE 0x8
58#define VIA_CRDR_SDMODE_4BIT 0x02
59#define VIA_CRDR_SDMODE_CLK_ON 0x40
60
61#define VIA_CRDR_SDBLKLEN 0xc
62/*
63 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
64 * Bit 11 - Bit 13 : Reserved.
65 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
66 * INTEN : Enable SD host interrupt.
67 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
68 */
69#define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
70#define VIA_CRDR_SDBLKLEN_INTEN 0x8000
71#define VIA_CRDR_MAX_BLOCK_COUNT 65536
72#define VIA_CRDR_MAX_BLOCK_LENGTH 2048
73
74#define VIA_CRDR_SDRESP0 0x10
75#define VIA_CRDR_SDRESP1 0x14
76#define VIA_CRDR_SDRESP2 0x18
77#define VIA_CRDR_SDRESP3 0x1c
78
79#define VIA_CRDR_SDCURBLKCNT 0x20
80
81#define VIA_CRDR_SDINTMASK 0x24
82/*
83 * MBDIE : Multiple Blocks transfer Done Interrupt Enable
84 * BDDIE : Block Data transfer Done Interrupt Enable
85 * CIRIE : Card Insertion or Removal Interrupt Enable
86 * CRDIE : Command-Response transfer Done Interrupt Enable
87 * CRTOIE : Command-Response response TimeOut Interrupt Enable
88 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
89 * DTIE : Data access Timeout Interrupt Enable
90 * SCIE : reSponse CRC error Interrupt Enable
91 * RCIE : Read data CRC error Interrupt Enable
92 * WCIE : Write data CRC error Interrupt Enable
93 */
94#define VIA_CRDR_SDINTMASK_MBDIE 0x10
95#define VIA_CRDR_SDINTMASK_BDDIE 0x20
96#define VIA_CRDR_SDINTMASK_CIRIE 0x80
97#define VIA_CRDR_SDINTMASK_CRDIE 0x200
98#define VIA_CRDR_SDINTMASK_CRTOIE 0x400
99#define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
100#define VIA_CRDR_SDINTMASK_DTIE 0x1000
101#define VIA_CRDR_SDINTMASK_SCIE 0x2000
102#define VIA_CRDR_SDINTMASK_RCIE 0x4000
103#define VIA_CRDR_SDINTMASK_WCIE 0x8000
104
105#define VIA_CRDR_SDACTIVE_INTMASK \
106 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
107 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
108 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
109 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
110
111#define VIA_CRDR_SDSTATUS 0x28
112/*
113 * CECC : Reserved
114 * WP : SD card Write Protect status
115 * SLOTD : Reserved
116 * SLOTG : SD SLOT status(Gpi pin status)
117 * MBD : Multiple Blocks transfer Done interrupt status
118 * BDD : Block Data transfer Done interrupt status
119 * CD : Reserved
120 * CIR : Card Insertion or Removal interrupt detected on GPI pin
121 * IO : Reserved
122 * CRD : Command-Response transfer Done interrupt status
123 * CRTO : Command-Response response TimeOut interrupt status
124 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
125 * DT : Data access Timeout interrupt status
126 * SC : reSponse CRC error interrupt status
127 * RC : Read data CRC error interrupt status
128 * WC : Write data CRC error interrupt status
129 */
130#define VIA_CRDR_SDSTS_CECC 0x01
131#define VIA_CRDR_SDSTS_WP 0x02
132#define VIA_CRDR_SDSTS_SLOTD 0x04
133#define VIA_CRDR_SDSTS_SLOTG 0x08
134#define VIA_CRDR_SDSTS_MBD 0x10
135#define VIA_CRDR_SDSTS_BDD 0x20
136#define VIA_CRDR_SDSTS_CD 0x40
137#define VIA_CRDR_SDSTS_CIR 0x80
138#define VIA_CRDR_SDSTS_IO 0x100
139#define VIA_CRDR_SDSTS_CRD 0x200
140#define VIA_CRDR_SDSTS_CRTO 0x400
141#define VIA_CRDR_SDSTS_ASCRDIE 0x800
142#define VIA_CRDR_SDSTS_DT 0x1000
143#define VIA_CRDR_SDSTS_SC 0x2000
144#define VIA_CRDR_SDSTS_RC 0x4000
145#define VIA_CRDR_SDSTS_WC 0x8000
146
147#define VIA_CRDR_SDSTS_IGN_MASK\
148 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
149#define VIA_CRDR_SDSTS_INT_MASK \
150 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
151 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
152 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
153 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
154#define VIA_CRDR_SDSTS_W1C_MASK \
155 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
156 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
157 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
158 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
159#define VIA_CRDR_SDSTS_CMD_MASK \
160 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
161#define VIA_CRDR_SDSTS_DATA_MASK\
162 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
163 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
164
165#define VIA_CRDR_SDSTATUS2 0x2a
166/*
167 * CFE : Enable SD host automatic Clock FReezing
168 */
169#define VIA_CRDR_SDSTS_CFE 0x80
170
171#define VIA_CRDR_SDRSPTMO 0x2C
172
173#define VIA_CRDR_SDCLKSEL 0x30
174
175#define VIA_CRDR_SDEXTCTRL 0x34
176#define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
177#define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
178#define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
179#define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
180#define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
181#define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
182#define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
183#define VIA_CRDR_SDEXTCTRL_HISPD 0x80
184/* 0x38-0xFF reserved */
185
186/*
187 * Data DMA Control Registers
188 */
189
190#define VIA_CRDR_DMABASEADD 0x0
191#define VIA_CRDR_DMACOUNTER 0x4
192
193#define VIA_CRDR_DMACTRL 0x8
194/*
195 * DIR :Transaction Direction
196 * 0 : From card to memory
197 * 1 : From memory to card
198 */
199#define VIA_CRDR_DMACTRL_DIR 0x100
200#define VIA_CRDR_DMACTRL_ENIRQ 0x10000
201#define VIA_CRDR_DMACTRL_SFTRST 0x1000000
202
203#define VIA_CRDR_DMASTS 0xc
204
205#define VIA_CRDR_DMASTART 0x10
206/*0x14-0xFF reserved*/
207
208/*
209 * PCI Control Registers
210 */
211
212/*0x0 - 0x1 reserved*/
213#define VIA_CRDR_PCICLKGATT 0x2
214/*
215 * SFTRST :
216 * 0 : Soft reset all the controller and it will be de-asserted automatically
217 * 1 : Soft reset is de-asserted
218 */
219#define VIA_CRDR_PCICLKGATT_SFTRST 0x01
220/*
221 * 3V3 : Pad power select
222 * 0 : 1.8V
223 * 1 : 3.3V
224 * NOTE : No mater what the actual value should be, this bit always
225 * read as 0. This is a hardware bug.
226 */
227#define VIA_CRDR_PCICLKGATT_3V3 0x10
228/*
229 * PAD_PWRON : Pad Power on/off select
230 * 0 : Power off
231 * 1 : Power on
232 * NOTE : No mater what the actual value should be, this bit always
233 * read as 0. This is a hardware bug.
234 */
235#define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
236
237#define VIA_CRDR_PCISDCCLK 0x5
238
239#define VIA_CRDR_PCIDMACLK 0x7
240#define VIA_CRDR_PCIDMACLK_SDC 0x2
241
242#define VIA_CRDR_PCIINTCTRL 0x8
243#define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
244
245#define VIA_CRDR_PCIINTSTATUS 0x9
246#define VIA_CRDR_PCIINTSTATUS_SDC 0x04
247
248#define VIA_CRDR_PCITMOCTRL 0xa
249#define VIA_CRDR_PCITMOCTRL_NO 0x0
250#define VIA_CRDR_PCITMOCTRL_32US 0x1
251#define VIA_CRDR_PCITMOCTRL_256US 0x2
252#define VIA_CRDR_PCITMOCTRL_1024US 0x3
253#define VIA_CRDR_PCITMOCTRL_256MS 0x4
254#define VIA_CRDR_PCITMOCTRL_512MS 0x5
255#define VIA_CRDR_PCITMOCTRL_1024MS 0x6
256
257/*0xB-0xFF reserved*/
258
259enum PCI_HOST_CLK_CONTROL {
260 PCI_CLK_375K = 0x03,
261 PCI_CLK_8M = 0x04,
262 PCI_CLK_12M = 0x00,
263 PCI_CLK_16M = 0x05,
264 PCI_CLK_24M = 0x01,
265 PCI_CLK_33M = 0x06,
266 PCI_CLK_48M = 0x02
267};
268
269struct sdhcreg {
270 u32 sdcontrol_reg;
271 u32 sdcmdarg_reg;
272 u32 sdbusmode_reg;
273 u32 sdblklen_reg;
274 u32 sdresp_reg[4];
275 u32 sdcurblkcnt_reg;
276 u32 sdintmask_reg;
277 u32 sdstatus_reg;
278 u32 sdrsptmo_reg;
279 u32 sdclksel_reg;
280 u32 sdextctrl_reg;
281};
282
283struct pcictrlreg {
284 u8 reserve[2];
285 u8 pciclkgat_reg;
286 u8 pcinfcclk_reg;
287 u8 pcimscclk_reg;
288 u8 pcisdclk_reg;
289 u8 pcicaclk_reg;
290 u8 pcidmaclk_reg;
291 u8 pciintctrl_reg;
292 u8 pciintstatus_reg;
293 u8 pcitmoctrl_reg;
294 u8 Resv;
295};
296
297struct via_crdr_mmc_host {
298 struct mmc_host *mmc;
299 struct mmc_request *mrq;
300 struct mmc_command *cmd;
301 struct mmc_data *data;
302
303 void __iomem *mmiobase;
304 void __iomem *sdhc_mmiobase;
305 void __iomem *ddma_mmiobase;
306 void __iomem *pcictrl_mmiobase;
307
308 struct pcictrlreg pm_pcictrl_reg;
309 struct sdhcreg pm_sdhc_reg;
310
311 struct work_struct carddet_work;
312 struct tasklet_struct finish_tasklet;
313
314 struct timer_list timer;
315 spinlock_t lock;
316 u8 power;
317 int reject;
318 unsigned int quirks;
319};
320
321/* some devices need a very long delay for power to stabilize */
322#define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
323
324static struct pci_device_id via_ids[] = {
325 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
327 {0,}
328};
329
330MODULE_DEVICE_TABLE(pci, via_ids);
331
332static void via_print_sdchc(struct via_crdr_mmc_host *host)
333{
334 void __iomem *addrbase = host->sdhc_mmiobase;
335
336 pr_debug("SDC MMIO Registers:\n");
337 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
338 readl(addrbase + VIA_CRDR_SDCTRL),
339 readl(addrbase + VIA_CRDR_SDCARG),
340 readl(addrbase + VIA_CRDR_SDBUSMODE));
341 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
342 readl(addrbase + VIA_CRDR_SDBLKLEN),
343 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
344 readl(addrbase + VIA_CRDR_SDINTMASK));
345 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
346 readl(addrbase + VIA_CRDR_SDSTATUS),
347 readl(addrbase + VIA_CRDR_SDCLKSEL),
348 readl(addrbase + VIA_CRDR_SDEXTCTRL));
349}
350
351static void via_print_pcictrl(struct via_crdr_mmc_host *host)
352{
353 void __iomem *addrbase = host->pcictrl_mmiobase;
354
355 pr_debug("PCI Control Registers:\n");
356 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
357 readb(addrbase + VIA_CRDR_PCICLKGATT),
358 readb(addrbase + VIA_CRDR_PCISDCCLK),
359 readb(addrbase + VIA_CRDR_PCIDMACLK));
360 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
361 readb(addrbase + VIA_CRDR_PCIINTCTRL),
362 readb(addrbase + VIA_CRDR_PCIINTSTATUS));
363}
364
365static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
366{
367 struct pcictrlreg *pm_pcictrl_reg;
368 void __iomem *addrbase;
369
370 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
371 addrbase = host->pcictrl_mmiobase;
372
373 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
374 pm_pcictrl_reg->pciclkgat_reg |=
375 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
376 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
377 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
378 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
379 pm_pcictrl_reg->pciintstatus_reg =
380 readb(addrbase + VIA_CRDR_PCIINTSTATUS);
381 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
382}
383
384static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
385{
386 struct pcictrlreg *pm_pcictrl_reg;
387 void __iomem *addrbase;
388
389 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
390 addrbase = host->pcictrl_mmiobase;
391
392 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
393 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
394 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
395 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
396 writeb(pm_pcictrl_reg->pciintstatus_reg,
397 addrbase + VIA_CRDR_PCIINTSTATUS);
398 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
399}
400
401static void via_save_sdcreg(struct via_crdr_mmc_host *host)
402{
403 struct sdhcreg *pm_sdhc_reg;
404 void __iomem *addrbase;
405
406 pm_sdhc_reg = &(host->pm_sdhc_reg);
407 addrbase = host->sdhc_mmiobase;
408
409 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
410 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
411 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
412 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
413 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
414 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
415 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
416 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
417 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
418 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
419}
420
421static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
422{
423 struct sdhcreg *pm_sdhc_reg;
424 void __iomem *addrbase;
425
426 pm_sdhc_reg = &(host->pm_sdhc_reg);
427 addrbase = host->sdhc_mmiobase;
428
429 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
430 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
431 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
432 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
433 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
434 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
435 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
436 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
437 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
438 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
439}
440
441static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
442{
443 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
444 msleep(300);
445 else
446 msleep(3);
447}
448
449static void via_set_ddma(struct via_crdr_mmc_host *host,
450 dma_addr_t dmaaddr, u32 count, int dir, int enirq)
451{
452 void __iomem *addrbase;
453 u32 ctrl_data = 0;
454
455 if (enirq)
456 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
457
458 if (dir)
459 ctrl_data |= VIA_CRDR_DMACTRL_DIR;
460
461 addrbase = host->ddma_mmiobase;
462
463 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
464 writel(count, addrbase + VIA_CRDR_DMACOUNTER);
465 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
466 writel(0x01, addrbase + VIA_CRDR_DMASTART);
467
468 /* It seems that our DMA can not work normally with 375kHz clock */
469 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
470 addrbase = host->pcictrl_mmiobase;
471 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
472 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
473 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
474 }
475}
476
477static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
478 struct mmc_data *data)
479{
480 void __iomem *addrbase;
481 u32 blk_reg;
482 int count;
483
484 WARN_ON(host->data);
485
486 /* Sanity checks */
487 BUG_ON(data->blksz > host->mmc->max_blk_size);
488 BUG_ON(data->blocks > host->mmc->max_blk_count);
489
490 host->data = data;
491
492 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
493 ((data->flags & MMC_DATA_READ) ?
494 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
495 BUG_ON(count != 1);
496
497 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
498 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
499
500 addrbase = host->sdhc_mmiobase;
501
502 blk_reg = data->blksz - 1;
503 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
504 blk_reg |= (data->blocks) << 16;
505
506 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
507}
508
509static void via_sdc_get_response(struct via_crdr_mmc_host *host,
510 struct mmc_command *cmd)
511{
512 void __iomem *addrbase = host->sdhc_mmiobase;
513 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
514 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
515 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
516 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
517
518 if (cmd->flags & MMC_RSP_136) {
519 cmd->resp[0] = ((u8) (dwdata1)) |
520 (((u8) (dwdata0 >> 24)) << 8) |
521 (((u8) (dwdata0 >> 16)) << 16) |
522 (((u8) (dwdata0 >> 8)) << 24);
523
524 cmd->resp[1] = ((u8) (dwdata2)) |
525 (((u8) (dwdata1 >> 24)) << 8) |
526 (((u8) (dwdata1 >> 16)) << 16) |
527 (((u8) (dwdata1 >> 8)) << 24);
528
529 cmd->resp[2] = ((u8) (dwdata3)) |
530 (((u8) (dwdata2 >> 24)) << 8) |
531 (((u8) (dwdata2 >> 16)) << 16) |
532 (((u8) (dwdata2 >> 8)) << 24);
533
534 cmd->resp[3] = 0xff |
535 ((((u8) (dwdata3 >> 24))) << 8) |
536 (((u8) (dwdata3 >> 16)) << 16) |
537 (((u8) (dwdata3 >> 8)) << 24);
538 } else {
539 dwdata0 >>= 8;
540 cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
541 (((dwdata0 >> 8) & 0xff) << 16) |
542 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
543
544 dwdata1 >>= 8;
545 cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
546 (((dwdata1 >> 8) & 0xff) << 16) |
547 (((dwdata1 >> 16) & 0xff) << 8);
548 }
549}
550
551static void via_sdc_send_command(struct via_crdr_mmc_host *host,
552 struct mmc_command *cmd)
553{
554 void __iomem *addrbase;
555 struct mmc_data *data;
556 u32 cmdctrl = 0;
557
558 WARN_ON(host->cmd);
559
560 data = cmd->data;
561 mod_timer(&host->timer, jiffies + HZ);
562 host->cmd = cmd;
563
564 /*Command index*/
565 cmdctrl = cmd->opcode << 8;
566
567 /*Response type*/
568 switch (mmc_resp_type(cmd)) {
569 case MMC_RSP_NONE:
570 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
571 break;
572 case MMC_RSP_R1:
573 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
574 break;
575 case MMC_RSP_R1B:
576 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
577 break;
578 case MMC_RSP_R2:
579 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
580 break;
581 case MMC_RSP_R3:
582 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
583 break;
584 default:
585 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
586 break;
587 }
588
589 if (!(cmd->data))
590 goto nodata;
591
592 via_sdc_preparedata(host, data);
593
594 /*Command control*/
595 if (data->blocks > 1) {
596 if (data->flags & MMC_DATA_WRITE) {
597 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
598 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
599 } else {
600 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
601 }
602 } else {
603 if (data->flags & MMC_DATA_WRITE) {
604 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
605 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
606 } else {
607 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
608 }
609 }
610
611nodata:
612 if (cmd == host->mrq->stop)
613 cmdctrl |= VIA_CRDR_SDCTRL_STOP;
614
615 cmdctrl |= VIA_CRDR_SDCTRL_START;
616
617 addrbase = host->sdhc_mmiobase;
618 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
619 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
620}
621
622static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
623{
624 struct mmc_data *data;
625
626 BUG_ON(!host->data);
627
628 data = host->data;
629 host->data = NULL;
630
631 if (data->error)
632 data->bytes_xfered = 0;
633 else
634 data->bytes_xfered = data->blocks * data->blksz;
635
636 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
637 ((data->flags & MMC_DATA_READ) ?
638 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
639
640 if (data->stop)
641 via_sdc_send_command(host, data->stop);
642 else
643 tasklet_schedule(&host->finish_tasklet);
644}
645
646static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
647{
648 via_sdc_get_response(host, host->cmd);
649
650 host->cmd->error = 0;
651
652 if (!host->cmd->data)
653 tasklet_schedule(&host->finish_tasklet);
654
655 host->cmd = NULL;
656}
657
658static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
659{
660 void __iomem *addrbase;
661 struct via_crdr_mmc_host *host;
662 unsigned long flags;
663 u16 status;
664
665 host = mmc_priv(mmc);
666
667 spin_lock_irqsave(&host->lock, flags);
668
669 addrbase = host->pcictrl_mmiobase;
670 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
671
672 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
673 status &= VIA_CRDR_SDSTS_W1C_MASK;
674 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
675
676 WARN_ON(host->mrq != NULL);
677 host->mrq = mrq;
678
679 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
680 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
681 host->mrq->cmd->error = -ENOMEDIUM;
682 tasklet_schedule(&host->finish_tasklet);
683 } else {
684 via_sdc_send_command(host, mrq->cmd);
685 }
686
687 mmiowb();
688 spin_unlock_irqrestore(&host->lock, flags);
689}
690
691static void via_sdc_set_power(struct via_crdr_mmc_host *host,
692 unsigned short power, unsigned int on)
693{
694 unsigned long flags;
695 u8 gatt;
696
697 spin_lock_irqsave(&host->lock, flags);
698
699 host->power = (1 << power);
700
701 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
702 if (host->power == MMC_VDD_165_195)
703 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
704 else
705 gatt |= VIA_CRDR_PCICLKGATT_3V3;
706 if (on)
707 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
708 else
709 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
710 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
711
712 mmiowb();
713 spin_unlock_irqrestore(&host->lock, flags);
714
715 via_pwron_sleep(host);
716}
717
718static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
719{
720 struct via_crdr_mmc_host *host;
721 unsigned long flags;
722 void __iomem *addrbase;
723 u32 org_data, sdextctrl;
724 u8 clock;
725
726 host = mmc_priv(mmc);
727
728 spin_lock_irqsave(&host->lock, flags);
729
730 addrbase = host->sdhc_mmiobase;
731 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
732 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
733
734 if (ios->bus_width == MMC_BUS_WIDTH_1)
735 org_data &= ~VIA_CRDR_SDMODE_4BIT;
736 else
737 org_data |= VIA_CRDR_SDMODE_4BIT;
738
739 if (ios->power_mode == MMC_POWER_OFF)
740 org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
741 else
742 org_data |= VIA_CRDR_SDMODE_CLK_ON;
743
744 if (ios->timing == MMC_TIMING_SD_HS)
745 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
746 else
747 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
748
749 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
750 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
751
752 if (ios->clock >= 48000000)
753 clock = PCI_CLK_48M;
754 else if (ios->clock >= 33000000)
755 clock = PCI_CLK_33M;
756 else if (ios->clock >= 24000000)
757 clock = PCI_CLK_24M;
758 else if (ios->clock >= 16000000)
759 clock = PCI_CLK_16M;
760 else if (ios->clock >= 12000000)
761 clock = PCI_CLK_12M;
762 else if (ios->clock >= 8000000)
763 clock = PCI_CLK_8M;
764 else
765 clock = PCI_CLK_375K;
766
767 addrbase = host->pcictrl_mmiobase;
768 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
769 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
770
771 mmiowb();
772 spin_unlock_irqrestore(&host->lock, flags);
773
774 if (ios->power_mode != MMC_POWER_OFF)
775 via_sdc_set_power(host, ios->vdd, 1);
776 else
777 via_sdc_set_power(host, ios->vdd, 0);
778}
779
780static int via_sdc_get_ro(struct mmc_host *mmc)
781{
782 struct via_crdr_mmc_host *host;
783 unsigned long flags;
784 u16 status;
785
786 host = mmc_priv(mmc);
787
788 spin_lock_irqsave(&host->lock, flags);
789
790 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
791
792 spin_unlock_irqrestore(&host->lock, flags);
793
794 return !(status & VIA_CRDR_SDSTS_WP);
795}
796
797static const struct mmc_host_ops via_sdc_ops = {
798 .request = via_sdc_request,
799 .set_ios = via_sdc_set_ios,
800 .get_ro = via_sdc_get_ro,
801};
802
803static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
804{
f0bf7f61
HW		 805 unsigned long flags;
806 u8 gatt;
807
f0bf7f61
HW		 808 spin_lock_irqsave(&host->lock, flags);
809
810 via_save_pcictrlreg(host);
811 via_save_sdcreg(host);
812
813 spin_unlock_irqrestore(&host->lock, flags);
814
815 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
816 if (host->power == MMC_VDD_165_195)
817 gatt &= VIA_CRDR_PCICLKGATT_3V3;
818 else
819 gatt |= VIA_CRDR_PCICLKGATT_3V3;
820 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
821 via_pwron_sleep(host);
822 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
823 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
824 msleep(3);
825
826 spin_lock_irqsave(&host->lock, flags);
827
828 via_restore_pcictrlreg(host);
829 via_restore_sdcreg(host);
830
831 mmiowb();
832 spin_unlock_irqrestore(&host->lock, flags);
833}
834
835static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
836{
837 BUG_ON(intmask == 0);
838
839 if (!host->cmd) {
840 pr_err("%s: Got command interrupt 0x%x even "
841 "though no command operation was in progress.\n",
842 mmc_hostname(host->mmc), intmask);
843 return;
844 }
845
846 if (intmask & VIA_CRDR_SDSTS_CRTO)
847 host->cmd->error = -ETIMEDOUT;
848 else if (intmask & VIA_CRDR_SDSTS_SC)
849 host->cmd->error = -EILSEQ;
850
851 if (host->cmd->error)
852 tasklet_schedule(&host->finish_tasklet);
853 else if (intmask & VIA_CRDR_SDSTS_CRD)
854 via_sdc_finish_command(host);
855}
856
857static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
858{
859 BUG_ON(intmask == 0);
860
861 if (intmask & VIA_CRDR_SDSTS_DT)
862 host->data->error = -ETIMEDOUT;
863 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
864 host->data->error = -EILSEQ;
865
866 via_sdc_finish_data(host);
867}
868
869static irqreturn_t via_sdc_isr(int irq, void *dev_id)
870{
871 struct via_crdr_mmc_host *sdhost = dev_id;
872 void __iomem *addrbase;
873 u8 pci_status;
874 u16 sd_status;
875 irqreturn_t result;
876
877 if (!sdhost)
878 return IRQ_NONE;
879
880 spin_lock(&sdhost->lock);
881
882 addrbase = sdhost->pcictrl_mmiobase;
883 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
884 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
885 result = IRQ_NONE;
886 goto out;
887 }
888
889 addrbase = sdhost->sdhc_mmiobase;
890 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
891 sd_status &= VIA_CRDR_SDSTS_INT_MASK;
892 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
893 if (!sd_status) {
894 result = IRQ_NONE;
895 goto out;
896 }
897
898 if (sd_status & VIA_CRDR_SDSTS_CIR) {
899 writew(sd_status & VIA_CRDR_SDSTS_CIR,
900 addrbase + VIA_CRDR_SDSTATUS);
901
902 schedule_work(&sdhost->carddet_work);
903 }
904
905 sd_status &= ~VIA_CRDR_SDSTS_CIR;
906 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
907 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
908 addrbase + VIA_CRDR_SDSTATUS);
909 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
910 }
911 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
912 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
913 addrbase + VIA_CRDR_SDSTATUS);
914 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
915 }
916
917 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
918 if (sd_status) {
919 pr_err("%s: Unexpected interrupt 0x%x\n",
920 mmc_hostname(sdhost->mmc), sd_status);
921 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
922 }
923
924 result = IRQ_HANDLED;
925
926 mmiowb();
927out:
928 spin_unlock(&sdhost->lock);
929
930 return result;
931}
932
933static void via_sdc_timeout(unsigned long ulongdata)
934{
935 struct via_crdr_mmc_host *sdhost;
936 unsigned long flags;
937
938 sdhost = (struct via_crdr_mmc_host *)ulongdata;
939
940 spin_lock_irqsave(&sdhost->lock, flags);
941
942 if (sdhost->mrq) {
943 pr_err("%s: Timeout waiting for hardware interrupt."
944 "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
945 sdhost->mrq->cmd->opcode);
946
947 if (sdhost->data) {
948 writel(VIA_CRDR_DMACTRL_SFTRST,
949 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
950 sdhost->data->error = -ETIMEDOUT;
951 via_sdc_finish_data(sdhost);
952 } else {
953 if (sdhost->cmd)
954 sdhost->cmd->error = -ETIMEDOUT;
955 else
956 sdhost->mrq->cmd->error = -ETIMEDOUT;
957 tasklet_schedule(&sdhost->finish_tasklet);
958 }
959 }
960
961 mmiowb();
962 spin_unlock_irqrestore(&sdhost->lock, flags);
963}
964
965static void via_sdc_tasklet_finish(unsigned long param)
966{
967 struct via_crdr_mmc_host *host;
968 unsigned long flags;
969 struct mmc_request *mrq;
970
971 host = (struct via_crdr_mmc_host *)param;
972
973 spin_lock_irqsave(&host->lock, flags);
974
975 del_timer(&host->timer);
976 mrq = host->mrq;
977 host->mrq = NULL;
978 host->cmd = NULL;
979 host->data = NULL;
980
981 spin_unlock_irqrestore(&host->lock, flags);
982
983 mmc_request_done(host->mmc, mrq);
984}
985
986static void via_sdc_card_detect(struct work_struct *work)
987{
988 struct via_crdr_mmc_host *host;
989 void __iomem *addrbase;
990 unsigned long flags;
991 u16 status;
992
993 host = container_of(work, struct via_crdr_mmc_host, carddet_work);
994
995 addrbase = host->ddma_mmiobase;
996 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
997
998 spin_lock_irqsave(&host->lock, flags);
999
1000 addrbase = host->pcictrl_mmiobase;
1001 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
1002
1003 addrbase = host->sdhc_mmiobase;
1004 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1005 if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
1006 if (host->mrq) {
1007 pr_err("%s: Card removed during transfer!\n",
1008 mmc_hostname(host->mmc));
1009 host->mrq->cmd->error = -ENOMEDIUM;
1010 tasklet_schedule(&host->finish_tasklet);
1011 }
1012
1013 mmiowb();
1014 spin_unlock_irqrestore(&host->lock, flags);
1015
1016 via_reset_pcictrl(host);
1017
1018 spin_lock_irqsave(&host->lock, flags);
1019 }
1020
1021 mmiowb();
1022 spin_unlock_irqrestore(&host->lock, flags);
1023
1024 via_print_pcictrl(host);
1025 via_print_sdchc(host);
1026
1027 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1028}
1029
1030static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1031{
1032 struct mmc_host *mmc = host->mmc;
1033 void __iomem *addrbase;
1034 u32 lenreg;
1035 u32 status;
1036
1037 init_timer(&host->timer);
1038 host->timer.data = (unsigned long)host;
1039 host->timer.function = via_sdc_timeout;
1040
1041 spin_lock_init(&host->lock);
1042
1043 mmc->f_min = VIA_CRDR_MIN_CLOCK;
1044 mmc->f_max = VIA_CRDR_MAX_CLOCK;
1045 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1046 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1047 mmc->ops = &via_sdc_ops;
1048
1049 /*Hardware cannot do scatter lists*/
a36274e0 1050 mmc->max_segs = 1;
f0bf7f61
HW		 1051
1052 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1053 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1054
1055 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1056 mmc->max_req_size = mmc->max_seg_size;
1057
1058 INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1059
1060 tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish,
1061 (unsigned long)host);
1062
1063 addrbase = host->sdhc_mmiobase;
1064 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1065 msleep(1);
1066
1067 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1068 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1069
1070 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1071 status &= VIA_CRDR_SDSTS_W1C_MASK;
1072 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1073
1074 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1075 status |= VIA_CRDR_SDSTS_CFE;
1076 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1077
1078 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1079
1080 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1081 msleep(1);
1082}
1083
1084static int __devinit via_sd_probe(struct pci_dev *pcidev,
1085 const struct pci_device_id *id)
1086{
1087 struct mmc_host *mmc;
1088 struct via_crdr_mmc_host *sdhost;
1089 u32 base, len;
1090 u8 rev, gatt;
1091 int ret;
1092
1093 pci_read_config_byte(pcidev, PCI_CLASS_REVISION, &rev);
1094 pr_info(DRV_NAME
1095 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1096 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1097 (int)rev);
1098
1099 ret = pci_enable_device(pcidev);
1100 if (ret)
1101 return ret;
1102
1103 ret = pci_request_regions(pcidev, DRV_NAME);
1104 if (ret)
1105 goto disable;
1106
1107 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1108 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1109
1110 mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1111 if (!mmc) {
1112 ret = -ENOMEM;
1113 goto release;
1114 }
1115
1116 sdhost = mmc_priv(mmc);
1117 sdhost->mmc = mmc;
1118 dev_set_drvdata(&pcidev->dev, sdhost);
1119
1120 len = pci_resource_len(pcidev, 0);
1121 base = pci_resource_start(pcidev, 0);
1122 sdhost->mmiobase = ioremap_nocache(base, len);
1123 if (!sdhost->mmiobase) {
1124 ret = -ENOMEM;
1125 goto free_mmc_host;
1126 }
1127
1128 sdhost->sdhc_mmiobase =
1129 sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1130 sdhost->ddma_mmiobase =
1131 sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1132 sdhost->pcictrl_mmiobase =
1133 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1134
1135 sdhost->power = MMC_VDD_165_195;
1136
1137 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1138 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1139 via_pwron_sleep(sdhost);
1140 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1141 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1142 msleep(3);
1143
1144 via_init_mmc_host(sdhost);
1145
1146 ret =
1147 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1148 sdhost);
1149 if (ret)
1150 goto unmap;
1151
1152 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1153 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1154 writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1155 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1156
1157 /* device-specific quirks */
1158 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1159 pcidev->subsystem_device == 0x3891)
1160 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1161
1162 mmc_add_host(mmc);
1163
1164 return 0;
1165
1166unmap:
1167 iounmap(sdhost->mmiobase);
1168free_mmc_host:
1169 dev_set_drvdata(&pcidev->dev, NULL);
1170 mmc_free_host(mmc);
1171release:
1172 pci_release_regions(pcidev);
1173disable:
1174 pci_disable_device(pcidev);
1175
1176 return ret;
1177}
1178
1179static void __devexit via_sd_remove(struct pci_dev *pcidev)
1180{
1181 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1182 unsigned long flags;
1183 u8 gatt;
1184
1185 spin_lock_irqsave(&sdhost->lock, flags);
1186
1187 /* Ensure we don't accept more commands from mmc layer */
1188 sdhost->reject = 1;
1189
1190 /* Disable generating further interrupts */
1191 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1192 mmiowb();
1193
1194 if (sdhost->mrq) {
1195 printk(KERN_ERR "%s: Controller removed during "
1196 "transfer\n", mmc_hostname(sdhost->mmc));
1197
1198 /* make sure all DMA is stopped */
1199 writel(VIA_CRDR_DMACTRL_SFTRST,
1200 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1201 mmiowb();
1202 sdhost->mrq->cmd->error = -ENOMEDIUM;
1203 if (sdhost->mrq->stop)
1204 sdhost->mrq->stop->error = -ENOMEDIUM;
1205 tasklet_schedule(&sdhost->finish_tasklet);
1206 }
1207 spin_unlock_irqrestore(&sdhost->lock, flags);
1208
1209 mmc_remove_host(sdhost->mmc);
1210
1211 free_irq(pcidev->irq, sdhost);
1212
1213 del_timer_sync(&sdhost->timer);
1214
1215 tasklet_kill(&sdhost->finish_tasklet);
1216
1217 /* switch off power */
1218 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1219 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1220 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1221
1222 iounmap(sdhost->mmiobase);
1223 dev_set_drvdata(&pcidev->dev, NULL);
1224 mmc_free_host(sdhost->mmc);
1225 pci_release_regions(pcidev);
1226 pci_disable_device(pcidev);
1227
1228 pr_info(DRV_NAME
1229 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1230 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1231}
1232
1233#ifdef CONFIG_PM
1234
1235static void via_init_sdc_pm(struct via_crdr_mmc_host *host)
1236{
1237 struct sdhcreg *pm_sdhcreg;
1238 void __iomem *addrbase;
1239 u32 lenreg;
1240 u16 status;
1241
1242 pm_sdhcreg = &(host->pm_sdhc_reg);
1243 addrbase = host->sdhc_mmiobase;
1244
1245 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1246
1247 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1248 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1249
1250 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1251 status &= VIA_CRDR_SDSTS_W1C_MASK;
1252 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1253
1254 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1255 status |= VIA_CRDR_SDSTS_CFE;
1256 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1257
1258 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1259 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1260 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1261 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1262 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1263 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1264
1265 via_print_pcictrl(host);
1266 via_print_sdchc(host);
1267}
1268
1269static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state)
1270{
1271 struct via_crdr_mmc_host *host;
1272 int ret = 0;
1273
1274 host = pci_get_drvdata(pcidev);
1275
1276 via_save_pcictrlreg(host);
1277 via_save_sdcreg(host);
1278
1a13f8fa 1279 ret = mmc_suspend_host(host->mmc);
f0bf7f61
HW		 1280
1281 pci_save_state(pcidev);
1282 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1283 pci_disable_device(pcidev);
1284 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1285
1286 return ret;
1287}
1288
1289static int via_sd_resume(struct pci_dev *pcidev)
1290{
1291 struct via_crdr_mmc_host *sdhost;
1292 int ret = 0;
1293 u8 gatt;
1294
1295 sdhost = pci_get_drvdata(pcidev);
1296
1297 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1298 if (sdhost->power == MMC_VDD_165_195)
1299 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1300 else
1301 gatt |= VIA_CRDR_PCICLKGATT_3V3;
1302 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1303 via_pwron_sleep(sdhost);
1304 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1305 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1306 msleep(3);
1307
1308 msleep(100);
1309
1310 pci_set_power_state(pcidev, PCI_D0);
1311 pci_restore_state(pcidev);
1312 ret = pci_enable_device(pcidev);
1313 if (ret)
1314 return ret;
1315
1316 via_restore_pcictrlreg(sdhost);
1317 via_init_sdc_pm(sdhost);
1318
1319 ret = mmc_resume_host(sdhost->mmc);
1320
1321 return ret;
1322}
1323
1324#else /* CONFIG_PM */
1325
1326#define via_sd_suspend NULL
1327#define via_sd_resume NULL
1328
1329#endif /* CONFIG_PM */
1330
1331static struct pci_driver via_sd_driver = {
1332 .name = DRV_NAME,
1333 .id_table = via_ids,
1334 .probe = via_sd_probe,
1335 .remove = __devexit_p(via_sd_remove),
1336 .suspend = via_sd_suspend,
1337 .resume = via_sd_resume,
1338};
1339
1340static int __init via_sd_drv_init(void)
1341{
1342 pr_info(DRV_NAME ": VIA SD/MMC Card Reader driver "
1343 "(C) 2008 VIA Technologies, Inc.\n");
1344
1345 return pci_register_driver(&via_sd_driver);
1346}
1347
1348static void __exit via_sd_drv_exit(void)
1349{
1350 pci_unregister_driver(&via_sd_driver);
1351}
1352
1353module_init(via_sd_drv_init);
1354module_exit(via_sd_drv_exit);
1355
1356MODULE_LICENSE("GPL");
1357MODULE_AUTHOR("VIA Technologies Inc.");
1358MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");
Linux kernel - Deliverables
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