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3a96dff0 TP |
1 | /* |
2 | * WM8505/WM8650 SD/MMC Host Controller | |
3 | * | |
4 | * Copyright (C) 2010 Tony Prisk | |
5 | * Copyright (C) 2008 WonderMedia Technologies, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/gpio.h> | |
23 | ||
24 | #include <linux/of.h> | |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/of_device.h> | |
28 | ||
29 | #include <linux/mmc/host.h> | |
30 | #include <linux/mmc/mmc.h> | |
31 | #include <linux/mmc/sd.h> | |
32 | ||
33 | #include <asm/byteorder.h> | |
34 | ||
35 | ||
36 | #define DRIVER_NAME "wmt-sdhc" | |
37 | ||
38 | ||
39 | /* MMC/SD controller registers */ | |
40 | #define SDMMC_CTLR 0x00 | |
41 | #define SDMMC_CMD 0x01 | |
42 | #define SDMMC_RSPTYPE 0x02 | |
43 | #define SDMMC_ARG 0x04 | |
44 | #define SDMMC_BUSMODE 0x08 | |
45 | #define SDMMC_BLKLEN 0x0C | |
46 | #define SDMMC_BLKCNT 0x0E | |
47 | #define SDMMC_RSP 0x10 | |
48 | #define SDMMC_CBCR 0x20 | |
49 | #define SDMMC_INTMASK0 0x24 | |
50 | #define SDMMC_INTMASK1 0x25 | |
51 | #define SDMMC_STS0 0x28 | |
52 | #define SDMMC_STS1 0x29 | |
53 | #define SDMMC_STS2 0x2A | |
54 | #define SDMMC_STS3 0x2B | |
55 | #define SDMMC_RSPTIMEOUT 0x2C | |
56 | #define SDMMC_CLK 0x30 /* VT8500 only */ | |
57 | #define SDMMC_EXTCTRL 0x34 | |
58 | #define SDMMC_SBLKLEN 0x38 | |
59 | #define SDMMC_DMATIMEOUT 0x3C | |
60 | ||
61 | ||
62 | /* SDMMC_CTLR bit fields */ | |
63 | #define CTLR_CMD_START 0x01 | |
64 | #define CTLR_CMD_WRITE 0x04 | |
65 | #define CTLR_FIFO_RESET 0x08 | |
66 | ||
67 | /* SDMMC_BUSMODE bit fields */ | |
68 | #define BM_SPI_MODE 0x01 | |
69 | #define BM_FOURBIT_MODE 0x02 | |
70 | #define BM_EIGHTBIT_MODE 0x04 | |
71 | #define BM_SD_OFF 0x10 | |
72 | #define BM_SPI_CS 0x20 | |
73 | #define BM_SD_POWER 0x40 | |
74 | #define BM_SOFT_RESET 0x80 | |
3a96dff0 TP |
75 | |
76 | /* SDMMC_BLKLEN bit fields */ | |
77 | #define BLKL_CRCERR_ABORT 0x0800 | |
78 | #define BLKL_CD_POL_HIGH 0x1000 | |
79 | #define BLKL_GPI_CD 0x2000 | |
80 | #define BLKL_DATA3_CD 0x4000 | |
81 | #define BLKL_INT_ENABLE 0x8000 | |
82 | ||
83 | /* SDMMC_INTMASK0 bit fields */ | |
84 | #define INT0_MBLK_TRAN_DONE_INT_EN 0x10 | |
85 | #define INT0_BLK_TRAN_DONE_INT_EN 0x20 | |
86 | #define INT0_CD_INT_EN 0x40 | |
87 | #define INT0_DI_INT_EN 0x80 | |
88 | ||
89 | /* SDMMC_INTMASK1 bit fields */ | |
90 | #define INT1_CMD_RES_TRAN_DONE_INT_EN 0x02 | |
91 | #define INT1_CMD_RES_TOUT_INT_EN 0x04 | |
92 | #define INT1_MBLK_AUTO_STOP_INT_EN 0x08 | |
93 | #define INT1_DATA_TOUT_INT_EN 0x10 | |
94 | #define INT1_RESCRC_ERR_INT_EN 0x20 | |
95 | #define INT1_RCRC_ERR_INT_EN 0x40 | |
96 | #define INT1_WCRC_ERR_INT_EN 0x80 | |
97 | ||
98 | /* SDMMC_STS0 bit fields */ | |
99 | #define STS0_WRITE_PROTECT 0x02 | |
100 | #define STS0_CD_DATA3 0x04 | |
101 | #define STS0_CD_GPI 0x08 | |
102 | #define STS0_MBLK_DONE 0x10 | |
103 | #define STS0_BLK_DONE 0x20 | |
104 | #define STS0_CARD_DETECT 0x40 | |
105 | #define STS0_DEVICE_INS 0x80 | |
106 | ||
107 | /* SDMMC_STS1 bit fields */ | |
108 | #define STS1_SDIO_INT 0x01 | |
109 | #define STS1_CMDRSP_DONE 0x02 | |
110 | #define STS1_RSP_TIMEOUT 0x04 | |
111 | #define STS1_AUTOSTOP_DONE 0x08 | |
112 | #define STS1_DATA_TIMEOUT 0x10 | |
113 | #define STS1_RSP_CRC_ERR 0x20 | |
114 | #define STS1_RCRC_ERR 0x40 | |
115 | #define STS1_WCRC_ERR 0x80 | |
116 | ||
117 | /* SDMMC_STS2 bit fields */ | |
118 | #define STS2_CMD_RES_BUSY 0x10 | |
119 | #define STS2_DATARSP_BUSY 0x20 | |
120 | #define STS2_DIS_FORCECLK 0x80 | |
121 | ||
889c9e04 AL |
122 | /* SDMMC_EXTCTRL bit fields */ |
123 | #define EXT_EIGHTBIT 0x04 | |
3a96dff0 TP |
124 | |
125 | /* MMC/SD DMA Controller Registers */ | |
126 | #define SDDMA_GCR 0x100 | |
127 | #define SDDMA_IER 0x104 | |
128 | #define SDDMA_ISR 0x108 | |
129 | #define SDDMA_DESPR 0x10C | |
130 | #define SDDMA_RBR 0x110 | |
131 | #define SDDMA_DAR 0x114 | |
132 | #define SDDMA_BAR 0x118 | |
133 | #define SDDMA_CPR 0x11C | |
134 | #define SDDMA_CCR 0x120 | |
135 | ||
136 | ||
137 | /* SDDMA_GCR bit fields */ | |
138 | #define DMA_GCR_DMA_EN 0x00000001 | |
139 | #define DMA_GCR_SOFT_RESET 0x00000100 | |
140 | ||
141 | /* SDDMA_IER bit fields */ | |
142 | #define DMA_IER_INT_EN 0x00000001 | |
143 | ||
144 | /* SDDMA_ISR bit fields */ | |
145 | #define DMA_ISR_INT_STS 0x00000001 | |
146 | ||
147 | /* SDDMA_RBR bit fields */ | |
148 | #define DMA_RBR_FORMAT 0x40000000 | |
149 | #define DMA_RBR_END 0x80000000 | |
150 | ||
151 | /* SDDMA_CCR bit fields */ | |
152 | #define DMA_CCR_RUN 0x00000080 | |
153 | #define DMA_CCR_IF_TO_PERIPHERAL 0x00000000 | |
154 | #define DMA_CCR_PERIPHERAL_TO_IF 0x00400000 | |
155 | ||
156 | /* SDDMA_CCR event status */ | |
157 | #define DMA_CCR_EVT_NO_STATUS 0x00000000 | |
158 | #define DMA_CCR_EVT_UNDERRUN 0x00000001 | |
159 | #define DMA_CCR_EVT_OVERRUN 0x00000002 | |
160 | #define DMA_CCR_EVT_DESP_READ 0x00000003 | |
161 | #define DMA_CCR_EVT_DATA_RW 0x00000004 | |
162 | #define DMA_CCR_EVT_EARLY_END 0x00000005 | |
163 | #define DMA_CCR_EVT_SUCCESS 0x0000000F | |
164 | ||
165 | #define PDMA_READ 0x00 | |
166 | #define PDMA_WRITE 0x01 | |
167 | ||
168 | #define WMT_SD_POWER_OFF 0 | |
169 | #define WMT_SD_POWER_ON 1 | |
170 | ||
171 | struct wmt_dma_descriptor { | |
172 | u32 flags; | |
173 | u32 data_buffer_addr; | |
174 | u32 branch_addr; | |
175 | u32 reserved1; | |
176 | }; | |
177 | ||
178 | struct wmt_mci_caps { | |
179 | unsigned int f_min; | |
180 | unsigned int f_max; | |
181 | u32 ocr_avail; | |
182 | u32 caps; | |
183 | u32 max_seg_size; | |
184 | u32 max_segs; | |
185 | u32 max_blk_size; | |
186 | }; | |
187 | ||
188 | struct wmt_mci_priv { | |
189 | struct mmc_host *mmc; | |
190 | void __iomem *sdmmc_base; | |
191 | ||
192 | int irq_regular; | |
193 | int irq_dma; | |
194 | ||
195 | void *dma_desc_buffer; | |
196 | dma_addr_t dma_desc_device_addr; | |
197 | ||
198 | struct completion cmdcomp; | |
199 | struct completion datacomp; | |
200 | ||
201 | struct completion *comp_cmd; | |
202 | struct completion *comp_dma; | |
203 | ||
204 | struct mmc_request *req; | |
205 | struct mmc_command *cmd; | |
206 | ||
207 | struct clk *clk_sdmmc; | |
208 | struct device *dev; | |
209 | ||
210 | u8 power_inverted; | |
211 | u8 cd_inverted; | |
212 | }; | |
213 | ||
214 | static void wmt_set_sd_power(struct wmt_mci_priv *priv, int enable) | |
215 | { | |
7b239903 AL |
216 | u32 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); |
217 | ||
218 | if (enable ^ priv->power_inverted) | |
219 | reg_tmp &= ~BM_SD_OFF; | |
220 | else | |
221 | reg_tmp |= BM_SD_OFF; | |
222 | ||
223 | writeb(reg_tmp, priv->sdmmc_base + SDMMC_BUSMODE); | |
3a96dff0 TP |
224 | } |
225 | ||
226 | static void wmt_mci_read_response(struct mmc_host *mmc) | |
227 | { | |
228 | struct wmt_mci_priv *priv; | |
229 | int idx1, idx2; | |
230 | u8 tmp_resp; | |
231 | u32 response; | |
232 | ||
233 | priv = mmc_priv(mmc); | |
234 | ||
235 | for (idx1 = 0; idx1 < 4; idx1++) { | |
236 | response = 0; | |
237 | for (idx2 = 0; idx2 < 4; idx2++) { | |
238 | if ((idx1 == 3) && (idx2 == 3)) | |
239 | tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP); | |
240 | else | |
241 | tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP + | |
242 | (idx1*4) + idx2 + 1); | |
243 | response |= (tmp_resp << (idx2 * 8)); | |
244 | } | |
245 | priv->cmd->resp[idx1] = cpu_to_be32(response); | |
246 | } | |
247 | } | |
248 | ||
249 | static void wmt_mci_start_command(struct wmt_mci_priv *priv) | |
250 | { | |
251 | u32 reg_tmp; | |
252 | ||
253 | reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR); | |
254 | writeb(reg_tmp | CTLR_CMD_START, priv->sdmmc_base + SDMMC_CTLR); | |
255 | } | |
256 | ||
257 | static int wmt_mci_send_command(struct mmc_host *mmc, u8 command, u8 cmdtype, | |
258 | u32 arg, u8 rsptype) | |
259 | { | |
260 | struct wmt_mci_priv *priv; | |
261 | u32 reg_tmp; | |
262 | ||
263 | priv = mmc_priv(mmc); | |
264 | ||
265 | /* write command, arg, resptype registers */ | |
266 | writeb(command, priv->sdmmc_base + SDMMC_CMD); | |
267 | writel(arg, priv->sdmmc_base + SDMMC_ARG); | |
268 | writeb(rsptype, priv->sdmmc_base + SDMMC_RSPTYPE); | |
269 | ||
270 | /* reset response FIFO */ | |
271 | reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR); | |
272 | writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR); | |
273 | ||
274 | /* ensure clock enabled - VT3465 */ | |
275 | wmt_set_sd_power(priv, WMT_SD_POWER_ON); | |
276 | ||
277 | /* clear status bits */ | |
278 | writeb(0xFF, priv->sdmmc_base + SDMMC_STS0); | |
279 | writeb(0xFF, priv->sdmmc_base + SDMMC_STS1); | |
280 | writeb(0xFF, priv->sdmmc_base + SDMMC_STS2); | |
281 | writeb(0xFF, priv->sdmmc_base + SDMMC_STS3); | |
282 | ||
283 | /* set command type */ | |
284 | reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR); | |
285 | writeb((reg_tmp & 0x0F) | (cmdtype << 4), | |
286 | priv->sdmmc_base + SDMMC_CTLR); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | static void wmt_mci_disable_dma(struct wmt_mci_priv *priv) | |
292 | { | |
293 | writel(DMA_ISR_INT_STS, priv->sdmmc_base + SDDMA_ISR); | |
294 | writel(0, priv->sdmmc_base + SDDMA_IER); | |
295 | } | |
296 | ||
297 | static void wmt_complete_data_request(struct wmt_mci_priv *priv) | |
298 | { | |
299 | struct mmc_request *req; | |
300 | req = priv->req; | |
301 | ||
302 | req->data->bytes_xfered = req->data->blksz * req->data->blocks; | |
303 | ||
304 | /* unmap the DMA pages used for write data */ | |
305 | if (req->data->flags & MMC_DATA_WRITE) | |
306 | dma_unmap_sg(mmc_dev(priv->mmc), req->data->sg, | |
307 | req->data->sg_len, DMA_TO_DEVICE); | |
308 | else | |
309 | dma_unmap_sg(mmc_dev(priv->mmc), req->data->sg, | |
310 | req->data->sg_len, DMA_FROM_DEVICE); | |
311 | ||
312 | /* Check if the DMA ISR returned a data error */ | |
313 | if ((req->cmd->error) || (req->data->error)) | |
314 | mmc_request_done(priv->mmc, req); | |
315 | else { | |
316 | wmt_mci_read_response(priv->mmc); | |
317 | if (!req->data->stop) { | |
318 | /* single-block read/write requests end here */ | |
319 | mmc_request_done(priv->mmc, req); | |
320 | } else { | |
321 | /* | |
322 | * we change the priv->cmd variable so the response is | |
323 | * stored in the stop struct rather than the original | |
324 | * calling command struct | |
325 | */ | |
326 | priv->comp_cmd = &priv->cmdcomp; | |
327 | init_completion(priv->comp_cmd); | |
328 | priv->cmd = req->data->stop; | |
329 | wmt_mci_send_command(priv->mmc, req->data->stop->opcode, | |
330 | 7, req->data->stop->arg, 9); | |
331 | wmt_mci_start_command(priv); | |
332 | } | |
333 | } | |
334 | } | |
335 | ||
336 | static irqreturn_t wmt_mci_dma_isr(int irq_num, void *data) | |
337 | { | |
3a96dff0 TP |
338 | struct wmt_mci_priv *priv; |
339 | ||
340 | int status; | |
341 | ||
342 | priv = (struct wmt_mci_priv *)data; | |
3a96dff0 TP |
343 | |
344 | status = readl(priv->sdmmc_base + SDDMA_CCR) & 0x0F; | |
345 | ||
346 | if (status != DMA_CCR_EVT_SUCCESS) { | |
347 | dev_err(priv->dev, "DMA Error: Status = %d\n", status); | |
348 | priv->req->data->error = -ETIMEDOUT; | |
349 | complete(priv->comp_dma); | |
350 | return IRQ_HANDLED; | |
351 | } | |
352 | ||
353 | priv->req->data->error = 0; | |
354 | ||
355 | wmt_mci_disable_dma(priv); | |
356 | ||
357 | complete(priv->comp_dma); | |
358 | ||
359 | if (priv->comp_cmd) { | |
360 | if (completion_done(priv->comp_cmd)) { | |
361 | /* | |
362 | * if the command (regular) interrupt has already | |
363 | * completed, finish off the request otherwise we wait | |
364 | * for the command interrupt and finish from there. | |
365 | */ | |
366 | wmt_complete_data_request(priv); | |
367 | } | |
368 | } | |
369 | ||
370 | return IRQ_HANDLED; | |
371 | } | |
372 | ||
373 | static irqreturn_t wmt_mci_regular_isr(int irq_num, void *data) | |
374 | { | |
375 | struct wmt_mci_priv *priv; | |
376 | u32 status0; | |
377 | u32 status1; | |
378 | u32 status2; | |
379 | u32 reg_tmp; | |
380 | int cmd_done; | |
381 | ||
382 | priv = (struct wmt_mci_priv *)data; | |
383 | cmd_done = 0; | |
384 | status0 = readb(priv->sdmmc_base + SDMMC_STS0); | |
385 | status1 = readb(priv->sdmmc_base + SDMMC_STS1); | |
386 | status2 = readb(priv->sdmmc_base + SDMMC_STS2); | |
387 | ||
388 | /* Check for card insertion */ | |
389 | reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0); | |
390 | if ((reg_tmp & INT0_DI_INT_EN) && (status0 & STS0_DEVICE_INS)) { | |
391 | mmc_detect_change(priv->mmc, 0); | |
392 | if (priv->cmd) | |
393 | priv->cmd->error = -ETIMEDOUT; | |
394 | if (priv->comp_cmd) | |
395 | complete(priv->comp_cmd); | |
396 | if (priv->comp_dma) { | |
397 | wmt_mci_disable_dma(priv); | |
398 | complete(priv->comp_dma); | |
399 | } | |
400 | writeb(STS0_DEVICE_INS, priv->sdmmc_base + SDMMC_STS0); | |
401 | return IRQ_HANDLED; | |
402 | } | |
403 | ||
404 | if ((!priv->req->data) || | |
405 | ((priv->req->data->stop) && (priv->cmd == priv->req->data->stop))) { | |
406 | /* handle non-data & stop_transmission requests */ | |
407 | if (status1 & STS1_CMDRSP_DONE) { | |
408 | priv->cmd->error = 0; | |
409 | cmd_done = 1; | |
410 | } else if ((status1 & STS1_RSP_TIMEOUT) || | |
411 | (status1 & STS1_DATA_TIMEOUT)) { | |
412 | priv->cmd->error = -ETIMEDOUT; | |
413 | cmd_done = 1; | |
414 | } | |
415 | ||
416 | if (cmd_done) { | |
417 | priv->comp_cmd = NULL; | |
418 | ||
419 | if (!priv->cmd->error) | |
420 | wmt_mci_read_response(priv->mmc); | |
421 | ||
422 | priv->cmd = NULL; | |
423 | ||
424 | mmc_request_done(priv->mmc, priv->req); | |
425 | } | |
426 | } else { | |
427 | /* handle data requests */ | |
428 | if (status1 & STS1_CMDRSP_DONE) { | |
429 | if (priv->cmd) | |
430 | priv->cmd->error = 0; | |
431 | if (priv->comp_cmd) | |
432 | complete(priv->comp_cmd); | |
433 | } | |
434 | ||
435 | if ((status1 & STS1_RSP_TIMEOUT) || | |
436 | (status1 & STS1_DATA_TIMEOUT)) { | |
437 | if (priv->cmd) | |
438 | priv->cmd->error = -ETIMEDOUT; | |
439 | if (priv->comp_cmd) | |
440 | complete(priv->comp_cmd); | |
441 | if (priv->comp_dma) { | |
442 | wmt_mci_disable_dma(priv); | |
443 | complete(priv->comp_dma); | |
444 | } | |
445 | } | |
446 | ||
447 | if (priv->comp_dma) { | |
448 | /* | |
449 | * If the dma interrupt has already completed, finish | |
450 | * off the request; otherwise we wait for the DMA | |
451 | * interrupt and finish from there. | |
452 | */ | |
453 | if (completion_done(priv->comp_dma)) | |
454 | wmt_complete_data_request(priv); | |
455 | } | |
456 | } | |
457 | ||
458 | writeb(status0, priv->sdmmc_base + SDMMC_STS0); | |
459 | writeb(status1, priv->sdmmc_base + SDMMC_STS1); | |
460 | writeb(status2, priv->sdmmc_base + SDMMC_STS2); | |
461 | ||
462 | return IRQ_HANDLED; | |
463 | } | |
464 | ||
465 | static void wmt_reset_hardware(struct mmc_host *mmc) | |
466 | { | |
467 | struct wmt_mci_priv *priv; | |
468 | u32 reg_tmp; | |
469 | ||
470 | priv = mmc_priv(mmc); | |
471 | ||
472 | /* reset controller */ | |
473 | reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); | |
474 | writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE); | |
475 | ||
476 | /* reset response FIFO */ | |
477 | reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR); | |
478 | writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR); | |
479 | ||
480 | /* enable GPI pin to detect card */ | |
481 | writew(BLKL_INT_ENABLE | BLKL_GPI_CD, priv->sdmmc_base + SDMMC_BLKLEN); | |
482 | ||
483 | /* clear interrupt status */ | |
484 | writeb(0xFF, priv->sdmmc_base + SDMMC_STS0); | |
485 | writeb(0xFF, priv->sdmmc_base + SDMMC_STS1); | |
486 | ||
487 | /* setup interrupts */ | |
488 | writeb(INT0_CD_INT_EN | INT0_DI_INT_EN, priv->sdmmc_base + | |
489 | SDMMC_INTMASK0); | |
490 | writeb(INT1_DATA_TOUT_INT_EN | INT1_CMD_RES_TRAN_DONE_INT_EN | | |
491 | INT1_CMD_RES_TOUT_INT_EN, priv->sdmmc_base + SDMMC_INTMASK1); | |
492 | ||
493 | /* set the DMA timeout */ | |
494 | writew(8191, priv->sdmmc_base + SDMMC_DMATIMEOUT); | |
495 | ||
496 | /* auto clock freezing enable */ | |
497 | reg_tmp = readb(priv->sdmmc_base + SDMMC_STS2); | |
498 | writeb(reg_tmp | STS2_DIS_FORCECLK, priv->sdmmc_base + SDMMC_STS2); | |
499 | ||
500 | /* set a default clock speed of 400Khz */ | |
501 | clk_set_rate(priv->clk_sdmmc, 400000); | |
502 | } | |
503 | ||
504 | static int wmt_dma_init(struct mmc_host *mmc) | |
505 | { | |
506 | struct wmt_mci_priv *priv; | |
507 | ||
508 | priv = mmc_priv(mmc); | |
509 | ||
510 | writel(DMA_GCR_SOFT_RESET, priv->sdmmc_base + SDDMA_GCR); | |
511 | writel(DMA_GCR_DMA_EN, priv->sdmmc_base + SDDMA_GCR); | |
512 | if ((readl(priv->sdmmc_base + SDDMA_GCR) & DMA_GCR_DMA_EN) != 0) | |
513 | return 0; | |
514 | else | |
515 | return 1; | |
516 | } | |
517 | ||
518 | static void wmt_dma_init_descriptor(struct wmt_dma_descriptor *desc, | |
519 | u16 req_count, u32 buffer_addr, u32 branch_addr, int end) | |
520 | { | |
521 | desc->flags = 0x40000000 | req_count; | |
522 | if (end) | |
523 | desc->flags |= 0x80000000; | |
524 | desc->data_buffer_addr = buffer_addr; | |
525 | desc->branch_addr = branch_addr; | |
526 | } | |
527 | ||
528 | static void wmt_dma_config(struct mmc_host *mmc, u32 descaddr, u8 dir) | |
529 | { | |
530 | struct wmt_mci_priv *priv; | |
531 | u32 reg_tmp; | |
532 | ||
533 | priv = mmc_priv(mmc); | |
534 | ||
535 | /* Enable DMA Interrupts */ | |
536 | writel(DMA_IER_INT_EN, priv->sdmmc_base + SDDMA_IER); | |
537 | ||
538 | /* Write DMA Descriptor Pointer Register */ | |
539 | writel(descaddr, priv->sdmmc_base + SDDMA_DESPR); | |
540 | ||
541 | writel(0x00, priv->sdmmc_base + SDDMA_CCR); | |
542 | ||
543 | if (dir == PDMA_WRITE) { | |
544 | reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR); | |
545 | writel(reg_tmp & DMA_CCR_IF_TO_PERIPHERAL, priv->sdmmc_base + | |
546 | SDDMA_CCR); | |
547 | } else { | |
548 | reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR); | |
549 | writel(reg_tmp | DMA_CCR_PERIPHERAL_TO_IF, priv->sdmmc_base + | |
550 | SDDMA_CCR); | |
551 | } | |
552 | } | |
553 | ||
554 | static void wmt_dma_start(struct wmt_mci_priv *priv) | |
555 | { | |
556 | u32 reg_tmp; | |
557 | ||
558 | reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR); | |
559 | writel(reg_tmp | DMA_CCR_RUN, priv->sdmmc_base + SDDMA_CCR); | |
560 | } | |
561 | ||
562 | static void wmt_mci_request(struct mmc_host *mmc, struct mmc_request *req) | |
563 | { | |
564 | struct wmt_mci_priv *priv; | |
565 | struct wmt_dma_descriptor *desc; | |
566 | u8 command; | |
567 | u8 cmdtype; | |
568 | u32 arg; | |
569 | u8 rsptype; | |
570 | u32 reg_tmp; | |
571 | ||
572 | struct scatterlist *sg; | |
573 | int i; | |
574 | int sg_cnt; | |
575 | int offset; | |
576 | u32 dma_address; | |
577 | int desc_cnt; | |
578 | ||
579 | priv = mmc_priv(mmc); | |
580 | priv->req = req; | |
581 | ||
582 | /* | |
583 | * Use the cmd variable to pass a pointer to the resp[] structure | |
584 | * This is required on multi-block requests to pass the pointer to the | |
585 | * stop command | |
586 | */ | |
587 | priv->cmd = req->cmd; | |
588 | ||
589 | command = req->cmd->opcode; | |
590 | arg = req->cmd->arg; | |
591 | rsptype = mmc_resp_type(req->cmd); | |
592 | cmdtype = 0; | |
593 | ||
594 | /* rsptype=7 only valid for SPI commands - should be =2 for SD */ | |
595 | if (rsptype == 7) | |
596 | rsptype = 2; | |
597 | /* rsptype=21 is R1B, convert for controller */ | |
598 | if (rsptype == 21) | |
599 | rsptype = 9; | |
600 | ||
601 | if (!req->data) { | |
602 | wmt_mci_send_command(mmc, command, cmdtype, arg, rsptype); | |
603 | wmt_mci_start_command(priv); | |
604 | /* completion is now handled in the regular_isr() */ | |
605 | } | |
606 | if (req->data) { | |
607 | priv->comp_cmd = &priv->cmdcomp; | |
608 | init_completion(priv->comp_cmd); | |
609 | ||
610 | wmt_dma_init(mmc); | |
611 | ||
612 | /* set controller data length */ | |
613 | reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN); | |
614 | writew((reg_tmp & 0xF800) | (req->data->blksz - 1), | |
615 | priv->sdmmc_base + SDMMC_BLKLEN); | |
616 | ||
617 | /* set controller block count */ | |
618 | writew(req->data->blocks, priv->sdmmc_base + SDMMC_BLKCNT); | |
619 | ||
620 | desc = (struct wmt_dma_descriptor *)priv->dma_desc_buffer; | |
621 | ||
622 | if (req->data->flags & MMC_DATA_WRITE) { | |
623 | sg_cnt = dma_map_sg(mmc_dev(mmc), req->data->sg, | |
624 | req->data->sg_len, DMA_TO_DEVICE); | |
625 | cmdtype = 1; | |
626 | if (req->data->blocks > 1) | |
627 | cmdtype = 3; | |
628 | } else { | |
629 | sg_cnt = dma_map_sg(mmc_dev(mmc), req->data->sg, | |
630 | req->data->sg_len, DMA_FROM_DEVICE); | |
631 | cmdtype = 2; | |
632 | if (req->data->blocks > 1) | |
633 | cmdtype = 4; | |
634 | } | |
635 | ||
636 | dma_address = priv->dma_desc_device_addr + 16; | |
637 | desc_cnt = 0; | |
638 | ||
639 | for_each_sg(req->data->sg, sg, sg_cnt, i) { | |
640 | offset = 0; | |
641 | while (offset < sg_dma_len(sg)) { | |
642 | wmt_dma_init_descriptor(desc, req->data->blksz, | |
643 | sg_dma_address(sg)+offset, | |
644 | dma_address, 0); | |
645 | desc++; | |
646 | desc_cnt++; | |
647 | offset += req->data->blksz; | |
648 | dma_address += 16; | |
649 | if (desc_cnt == req->data->blocks) | |
650 | break; | |
651 | } | |
652 | } | |
653 | desc--; | |
654 | desc->flags |= 0x80000000; | |
655 | ||
656 | if (req->data->flags & MMC_DATA_WRITE) | |
657 | wmt_dma_config(mmc, priv->dma_desc_device_addr, | |
658 | PDMA_WRITE); | |
659 | else | |
660 | wmt_dma_config(mmc, priv->dma_desc_device_addr, | |
661 | PDMA_READ); | |
662 | ||
663 | wmt_mci_send_command(mmc, command, cmdtype, arg, rsptype); | |
664 | ||
665 | priv->comp_dma = &priv->datacomp; | |
666 | init_completion(priv->comp_dma); | |
667 | ||
668 | wmt_dma_start(priv); | |
669 | wmt_mci_start_command(priv); | |
670 | } | |
671 | } | |
672 | ||
673 | static void wmt_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
674 | { | |
675 | struct wmt_mci_priv *priv; | |
889c9e04 | 676 | u32 busmode, extctrl; |
3a96dff0 TP |
677 | |
678 | priv = mmc_priv(mmc); | |
679 | ||
680 | if (ios->power_mode == MMC_POWER_UP) { | |
681 | wmt_reset_hardware(mmc); | |
682 | ||
683 | wmt_set_sd_power(priv, WMT_SD_POWER_ON); | |
684 | } | |
685 | if (ios->power_mode == MMC_POWER_OFF) | |
686 | wmt_set_sd_power(priv, WMT_SD_POWER_OFF); | |
687 | ||
688 | if (ios->clock != 0) | |
689 | clk_set_rate(priv->clk_sdmmc, ios->clock); | |
690 | ||
889c9e04 AL |
691 | busmode = readb(priv->sdmmc_base + SDMMC_BUSMODE); |
692 | extctrl = readb(priv->sdmmc_base + SDMMC_EXTCTRL); | |
693 | ||
694 | busmode &= ~(BM_EIGHTBIT_MODE | BM_FOURBIT_MODE); | |
695 | extctrl &= ~EXT_EIGHTBIT; | |
696 | ||
3a96dff0 TP |
697 | switch (ios->bus_width) { |
698 | case MMC_BUS_WIDTH_8: | |
889c9e04 AL |
699 | busmode |= BM_EIGHTBIT_MODE; |
700 | extctrl |= EXT_EIGHTBIT; | |
3a96dff0 TP |
701 | break; |
702 | case MMC_BUS_WIDTH_4: | |
889c9e04 | 703 | busmode |= BM_FOURBIT_MODE; |
3a96dff0 TP |
704 | break; |
705 | case MMC_BUS_WIDTH_1: | |
3a96dff0 TP |
706 | break; |
707 | } | |
889c9e04 AL |
708 | |
709 | writeb(busmode, priv->sdmmc_base + SDMMC_BUSMODE); | |
710 | writeb(extctrl, priv->sdmmc_base + SDMMC_EXTCTRL); | |
3a96dff0 TP |
711 | } |
712 | ||
713 | static int wmt_mci_get_ro(struct mmc_host *mmc) | |
714 | { | |
715 | struct wmt_mci_priv *priv = mmc_priv(mmc); | |
716 | ||
717 | return !(readb(priv->sdmmc_base + SDMMC_STS0) & STS0_WRITE_PROTECT); | |
718 | } | |
719 | ||
720 | static int wmt_mci_get_cd(struct mmc_host *mmc) | |
721 | { | |
722 | struct wmt_mci_priv *priv = mmc_priv(mmc); | |
723 | u32 cd = (readb(priv->sdmmc_base + SDMMC_STS0) & STS0_CD_GPI) >> 3; | |
724 | ||
725 | return !(cd ^ priv->cd_inverted); | |
726 | } | |
727 | ||
728 | static struct mmc_host_ops wmt_mci_ops = { | |
729 | .request = wmt_mci_request, | |
730 | .set_ios = wmt_mci_set_ios, | |
731 | .get_ro = wmt_mci_get_ro, | |
732 | .get_cd = wmt_mci_get_cd, | |
733 | }; | |
734 | ||
735 | /* Controller capabilities */ | |
736 | static struct wmt_mci_caps wm8505_caps = { | |
737 | .f_min = 390425, | |
738 | .f_max = 50000000, | |
739 | .ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34, | |
740 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | | |
741 | MMC_CAP_SD_HIGHSPEED, | |
742 | .max_seg_size = 65024, | |
743 | .max_segs = 128, | |
744 | .max_blk_size = 2048, | |
745 | }; | |
746 | ||
2530fd73 | 747 | static const struct of_device_id wmt_mci_dt_ids[] = { |
3a96dff0 TP |
748 | { .compatible = "wm,wm8505-sdhc", .data = &wm8505_caps }, |
749 | { /* Sentinel */ }, | |
750 | }; | |
751 | ||
4e608e4e | 752 | static int wmt_mci_probe(struct platform_device *pdev) |
3a96dff0 TP |
753 | { |
754 | struct mmc_host *mmc; | |
755 | struct wmt_mci_priv *priv; | |
756 | struct device_node *np = pdev->dev.of_node; | |
757 | const struct of_device_id *of_id = | |
758 | of_match_device(wmt_mci_dt_ids, &pdev->dev); | |
43aaa50f | 759 | const struct wmt_mci_caps *wmt_caps; |
3a96dff0 TP |
760 | int ret; |
761 | int regular_irq, dma_irq; | |
762 | ||
763 | if (!of_id || !of_id->data) { | |
764 | dev_err(&pdev->dev, "Controller capabilities data missing\n"); | |
765 | return -EFAULT; | |
766 | } | |
767 | ||
43aaa50f SK |
768 | wmt_caps = of_id->data; |
769 | ||
3a96dff0 TP |
770 | if (!np) { |
771 | dev_err(&pdev->dev, "Missing SDMMC description in devicetree\n"); | |
772 | return -EFAULT; | |
773 | } | |
774 | ||
775 | regular_irq = irq_of_parse_and_map(np, 0); | |
776 | dma_irq = irq_of_parse_and_map(np, 1); | |
777 | ||
778 | if (!regular_irq || !dma_irq) { | |
779 | dev_err(&pdev->dev, "Getting IRQs failed!\n"); | |
780 | ret = -ENXIO; | |
781 | goto fail1; | |
782 | } | |
783 | ||
784 | mmc = mmc_alloc_host(sizeof(struct wmt_mci_priv), &pdev->dev); | |
785 | if (!mmc) { | |
786 | dev_err(&pdev->dev, "Failed to allocate mmc_host\n"); | |
787 | ret = -ENOMEM; | |
788 | goto fail1; | |
789 | } | |
790 | ||
791 | mmc->ops = &wmt_mci_ops; | |
792 | mmc->f_min = wmt_caps->f_min; | |
793 | mmc->f_max = wmt_caps->f_max; | |
794 | mmc->ocr_avail = wmt_caps->ocr_avail; | |
795 | mmc->caps = wmt_caps->caps; | |
796 | ||
797 | mmc->max_seg_size = wmt_caps->max_seg_size; | |
798 | mmc->max_segs = wmt_caps->max_segs; | |
799 | mmc->max_blk_size = wmt_caps->max_blk_size; | |
800 | ||
801 | mmc->max_req_size = (16*512*mmc->max_segs); | |
802 | mmc->max_blk_count = mmc->max_req_size / 512; | |
803 | ||
804 | priv = mmc_priv(mmc); | |
805 | priv->mmc = mmc; | |
806 | priv->dev = &pdev->dev; | |
807 | ||
808 | priv->power_inverted = 0; | |
809 | priv->cd_inverted = 0; | |
810 | ||
811 | if (of_get_property(np, "sdon-inverted", NULL)) | |
812 | priv->power_inverted = 1; | |
813 | if (of_get_property(np, "cd-inverted", NULL)) | |
814 | priv->cd_inverted = 1; | |
815 | ||
816 | priv->sdmmc_base = of_iomap(np, 0); | |
817 | if (!priv->sdmmc_base) { | |
818 | dev_err(&pdev->dev, "Failed to map IO space\n"); | |
819 | ret = -ENOMEM; | |
820 | goto fail2; | |
821 | } | |
822 | ||
823 | priv->irq_regular = regular_irq; | |
824 | priv->irq_dma = dma_irq; | |
825 | ||
826 | ret = request_irq(regular_irq, wmt_mci_regular_isr, 0, "sdmmc", priv); | |
827 | if (ret) { | |
828 | dev_err(&pdev->dev, "Register regular IRQ fail\n"); | |
829 | goto fail3; | |
830 | } | |
831 | ||
5c87456b | 832 | ret = request_irq(dma_irq, wmt_mci_dma_isr, 0, "sdmmc", priv); |
3a96dff0 TP |
833 | if (ret) { |
834 | dev_err(&pdev->dev, "Register DMA IRQ fail\n"); | |
835 | goto fail4; | |
836 | } | |
837 | ||
838 | /* alloc some DMA buffers for descriptors/transfers */ | |
839 | priv->dma_desc_buffer = dma_alloc_coherent(&pdev->dev, | |
840 | mmc->max_blk_count * 16, | |
841 | &priv->dma_desc_device_addr, | |
6f243f63 | 842 | GFP_KERNEL); |
3a96dff0 TP |
843 | if (!priv->dma_desc_buffer) { |
844 | dev_err(&pdev->dev, "DMA alloc fail\n"); | |
845 | ret = -EPERM; | |
846 | goto fail5; | |
847 | } | |
848 | ||
849 | platform_set_drvdata(pdev, mmc); | |
850 | ||
851 | priv->clk_sdmmc = of_clk_get(np, 0); | |
852 | if (IS_ERR(priv->clk_sdmmc)) { | |
853 | dev_err(&pdev->dev, "Error getting clock\n"); | |
854 | ret = PTR_ERR(priv->clk_sdmmc); | |
855 | goto fail5; | |
856 | } | |
857 | ||
858 | clk_prepare_enable(priv->clk_sdmmc); | |
859 | ||
860 | /* configure the controller to a known 'ready' state */ | |
861 | wmt_reset_hardware(mmc); | |
862 | ||
863 | mmc_add_host(mmc); | |
864 | ||
865 | dev_info(&pdev->dev, "WMT SDHC Controller initialized\n"); | |
866 | ||
867 | return 0; | |
868 | fail5: | |
869 | free_irq(dma_irq, priv); | |
870 | fail4: | |
871 | free_irq(regular_irq, priv); | |
872 | fail3: | |
873 | iounmap(priv->sdmmc_base); | |
874 | fail2: | |
875 | mmc_free_host(mmc); | |
876 | fail1: | |
877 | return ret; | |
878 | } | |
879 | ||
4e608e4e | 880 | static int wmt_mci_remove(struct platform_device *pdev) |
3a96dff0 TP |
881 | { |
882 | struct mmc_host *mmc; | |
883 | struct wmt_mci_priv *priv; | |
884 | struct resource *res; | |
885 | u32 reg_tmp; | |
886 | ||
887 | mmc = platform_get_drvdata(pdev); | |
888 | priv = mmc_priv(mmc); | |
889 | ||
890 | /* reset SD controller */ | |
891 | reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); | |
892 | writel(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE); | |
893 | reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN); | |
894 | writew(reg_tmp & ~(0xA000), priv->sdmmc_base + SDMMC_BLKLEN); | |
895 | writeb(0xFF, priv->sdmmc_base + SDMMC_STS0); | |
896 | writeb(0xFF, priv->sdmmc_base + SDMMC_STS1); | |
897 | ||
898 | /* release the dma buffers */ | |
899 | dma_free_coherent(&pdev->dev, priv->mmc->max_blk_count * 16, | |
900 | priv->dma_desc_buffer, priv->dma_desc_device_addr); | |
901 | ||
902 | mmc_remove_host(mmc); | |
903 | ||
904 | free_irq(priv->irq_regular, priv); | |
905 | free_irq(priv->irq_dma, priv); | |
906 | ||
907 | iounmap(priv->sdmmc_base); | |
908 | ||
909 | clk_disable_unprepare(priv->clk_sdmmc); | |
910 | clk_put(priv->clk_sdmmc); | |
911 | ||
912 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
22119901 | 913 | release_mem_region(res->start, resource_size(res)); |
3a96dff0 TP |
914 | |
915 | mmc_free_host(mmc); | |
916 | ||
3a96dff0 TP |
917 | dev_info(&pdev->dev, "WMT MCI device removed\n"); |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
922 | #ifdef CONFIG_PM | |
923 | static int wmt_mci_suspend(struct device *dev) | |
924 | { | |
925 | u32 reg_tmp; | |
926 | struct platform_device *pdev = to_platform_device(dev); | |
927 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
928 | struct wmt_mci_priv *priv; | |
3a96dff0 TP |
929 | |
930 | if (!mmc) | |
931 | return 0; | |
932 | ||
933 | priv = mmc_priv(mmc); | |
7af37663 UH |
934 | reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); |
935 | writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + | |
936 | SDMMC_BUSMODE); | |
3a96dff0 | 937 | |
7af37663 UH |
938 | reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN); |
939 | writew(reg_tmp & 0x5FFF, priv->sdmmc_base + SDMMC_BLKLEN); | |
3a96dff0 | 940 | |
7af37663 UH |
941 | writeb(0xFF, priv->sdmmc_base + SDMMC_STS0); |
942 | writeb(0xFF, priv->sdmmc_base + SDMMC_STS1); | |
3a96dff0 | 943 | |
7af37663 UH |
944 | clk_disable(priv->clk_sdmmc); |
945 | return 0; | |
3a96dff0 TP |
946 | } |
947 | ||
948 | static int wmt_mci_resume(struct device *dev) | |
949 | { | |
950 | u32 reg_tmp; | |
951 | struct platform_device *pdev = to_platform_device(dev); | |
952 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
953 | struct wmt_mci_priv *priv; | |
3a96dff0 TP |
954 | |
955 | if (mmc) { | |
956 | priv = mmc_priv(mmc); | |
957 | clk_enable(priv->clk_sdmmc); | |
958 | ||
959 | reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); | |
960 | writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + | |
961 | SDMMC_BUSMODE); | |
962 | ||
963 | reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN); | |
964 | writew(reg_tmp | (BLKL_GPI_CD | BLKL_INT_ENABLE), | |
965 | priv->sdmmc_base + SDMMC_BLKLEN); | |
966 | ||
967 | reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0); | |
968 | writeb(reg_tmp | INT0_DI_INT_EN, priv->sdmmc_base + | |
969 | SDMMC_INTMASK0); | |
970 | ||
3a96dff0 TP |
971 | } |
972 | ||
7af37663 | 973 | return 0; |
3a96dff0 TP |
974 | } |
975 | ||
976 | static const struct dev_pm_ops wmt_mci_pm = { | |
977 | .suspend = wmt_mci_suspend, | |
978 | .resume = wmt_mci_resume, | |
979 | }; | |
980 | ||
981 | #define wmt_mci_pm_ops (&wmt_mci_pm) | |
982 | ||
983 | #else /* !CONFIG_PM */ | |
984 | ||
985 | #define wmt_mci_pm_ops NULL | |
986 | ||
987 | #endif | |
988 | ||
989 | static struct platform_driver wmt_mci_driver = { | |
990 | .probe = wmt_mci_probe, | |
893613b0 | 991 | .remove = wmt_mci_remove, |
3a96dff0 TP |
992 | .driver = { |
993 | .name = DRIVER_NAME, | |
3a96dff0 TP |
994 | .pm = wmt_mci_pm_ops, |
995 | .of_match_table = wmt_mci_dt_ids, | |
996 | }, | |
997 | }; | |
998 | ||
999 | module_platform_driver(wmt_mci_driver); | |
1000 | ||
1001 | MODULE_DESCRIPTION("Wondermedia MMC/SD Driver"); | |
1002 | MODULE_AUTHOR("Tony Prisk"); | |
1003 | MODULE_LICENSE("GPL v2"); | |
1004 | MODULE_DEVICE_TABLE(of, wmt_mci_dt_ids); |