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56ca9040 PP |
1 | /* |
2 | * linux/drivers/mmc/imxmmc.c - Motorola i.MX MMCI driver | |
3 | * | |
4 | * Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de> | |
5 | * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> | |
6 | * | |
7 | * derived from pxamci.c by Russell King | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz> | |
14 | * Changed to conform redesigned i.MX scatter gather DMA interface | |
15 | * | |
16 | * 2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz> | |
17 | * Updated for 2.6.14 kernel | |
18 | * | |
19 | * 2005-12-13 Jay Monkman <jtm@smoothsmoothie.com> | |
20 | * Found and corrected problems in the write path | |
21 | * | |
22 | * 2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz> | |
23 | * The event handling rewritten right way in softirq. | |
24 | * Added many ugly hacks and delays to overcome SDHC | |
25 | * deficiencies | |
26 | * | |
27 | */ | |
28 | #include <linux/config.h> | |
29 | ||
30 | #ifdef CONFIG_MMC_DEBUG | |
31 | #define DEBUG | |
32 | #else | |
33 | #undef DEBUG | |
34 | #endif | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/platform_device.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/blkdev.h> | |
42 | #include <linux/dma-mapping.h> | |
43 | #include <linux/mmc/host.h> | |
44 | #include <linux/mmc/card.h> | |
45 | #include <linux/mmc/protocol.h> | |
46 | #include <linux/delay.h> | |
47 | ||
48 | #include <asm/dma.h> | |
49 | #include <asm/io.h> | |
50 | #include <asm/irq.h> | |
51 | #include <asm/sizes.h> | |
52 | #include <asm/arch/mmc.h> | |
53 | #include <asm/arch/imx-dma.h> | |
54 | ||
55 | #include "imxmmc.h" | |
56 | ||
57 | #define DRIVER_NAME "imx-mmc" | |
58 | ||
59 | #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \ | |
60 | INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \ | |
61 | INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO) | |
62 | ||
63 | struct imxmci_host { | |
64 | struct mmc_host *mmc; | |
65 | spinlock_t lock; | |
66 | struct resource *res; | |
67 | int irq; | |
68 | imx_dmach_t dma; | |
69 | unsigned int clkrt; | |
70 | unsigned int cmdat; | |
71 | volatile unsigned int imask; | |
72 | unsigned int power_mode; | |
73 | unsigned int present; | |
74 | struct imxmmc_platform_data *pdata; | |
75 | ||
76 | struct mmc_request *req; | |
77 | struct mmc_command *cmd; | |
78 | struct mmc_data *data; | |
79 | ||
80 | struct timer_list timer; | |
81 | struct tasklet_struct tasklet; | |
82 | unsigned int status_reg; | |
83 | unsigned long pending_events; | |
84 | /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */ | |
85 | u16 *data_ptr; | |
86 | unsigned int data_cnt; | |
87 | atomic_t stuck_timeout; | |
88 | ||
89 | unsigned int dma_nents; | |
90 | unsigned int dma_size; | |
91 | unsigned int dma_dir; | |
92 | int dma_allocated; | |
93 | ||
94 | unsigned char actual_bus_width; | |
95 | }; | |
96 | ||
97 | #define IMXMCI_PEND_IRQ_b 0 | |
98 | #define IMXMCI_PEND_DMA_END_b 1 | |
99 | #define IMXMCI_PEND_DMA_ERR_b 2 | |
100 | #define IMXMCI_PEND_WAIT_RESP_b 3 | |
101 | #define IMXMCI_PEND_DMA_DATA_b 4 | |
102 | #define IMXMCI_PEND_CPU_DATA_b 5 | |
103 | #define IMXMCI_PEND_CARD_XCHG_b 6 | |
104 | #define IMXMCI_PEND_SET_INIT_b 7 | |
81d38428 | 105 | #define IMXMCI_PEND_STARTED_b 8 |
56ca9040 PP |
106 | |
107 | #define IMXMCI_PEND_IRQ_m (1 << IMXMCI_PEND_IRQ_b) | |
108 | #define IMXMCI_PEND_DMA_END_m (1 << IMXMCI_PEND_DMA_END_b) | |
109 | #define IMXMCI_PEND_DMA_ERR_m (1 << IMXMCI_PEND_DMA_ERR_b) | |
110 | #define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b) | |
111 | #define IMXMCI_PEND_DMA_DATA_m (1 << IMXMCI_PEND_DMA_DATA_b) | |
112 | #define IMXMCI_PEND_CPU_DATA_m (1 << IMXMCI_PEND_CPU_DATA_b) | |
113 | #define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b) | |
114 | #define IMXMCI_PEND_SET_INIT_m (1 << IMXMCI_PEND_SET_INIT_b) | |
81d38428 | 115 | #define IMXMCI_PEND_STARTED_m (1 << IMXMCI_PEND_STARTED_b) |
56ca9040 PP |
116 | |
117 | static void imxmci_stop_clock(struct imxmci_host *host) | |
118 | { | |
119 | int i = 0; | |
120 | MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK; | |
121 | while(i < 0x1000) { | |
122 | if(!(i & 0x7f)) | |
123 | MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK; | |
124 | ||
125 | if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) { | |
126 | /* Check twice before cut */ | |
127 | if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) | |
128 | return; | |
129 | } | |
130 | ||
131 | i++; | |
132 | } | |
133 | dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n"); | |
134 | } | |
135 | ||
81d38428 | 136 | static int imxmci_start_clock(struct imxmci_host *host) |
56ca9040 | 137 | { |
81d38428 PP |
138 | unsigned int trials = 0; |
139 | unsigned int delay_limit = 128; | |
140 | unsigned long flags; | |
141 | ||
56ca9040 | 142 | MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK; |
56ca9040 | 143 | |
81d38428 PP |
144 | clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events); |
145 | ||
146 | /* | |
147 | * Command start of the clock, this usually succeeds in less | |
148 | * then 6 delay loops, but during card detection (low clockrate) | |
149 | * it takes up to 5000 delay loops and sometimes fails for the first time | |
150 | */ | |
151 | MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK; | |
152 | ||
153 | do { | |
154 | unsigned int delay = delay_limit; | |
155 | ||
156 | while(delay--){ | |
56ca9040 | 157 | if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) |
81d38428 PP |
158 | /* Check twice before cut */ |
159 | if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) | |
160 | return 0; | |
161 | ||
162 | if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) | |
163 | return 0; | |
56ca9040 PP |
164 | } |
165 | ||
81d38428 PP |
166 | local_irq_save(flags); |
167 | /* | |
168 | * Ensure, that request is not doubled under all possible circumstances. | |
169 | * It is possible, that cock running state is missed, because some other | |
170 | * IRQ or schedule delays this function execution and the clocks has | |
171 | * been already stopped by other means (response processing, SDHC HW) | |
172 | */ | |
173 | if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) | |
174 | MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK; | |
175 | local_irq_restore(flags); | |
176 | ||
177 | } while(++trials<256); | |
178 | ||
179 | dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n"); | |
180 | ||
181 | return -1; | |
56ca9040 PP |
182 | } |
183 | ||
184 | static void imxmci_softreset(void) | |
185 | { | |
186 | /* reset sequence */ | |
187 | MMC_STR_STP_CLK = 0x8; | |
188 | MMC_STR_STP_CLK = 0xD; | |
189 | MMC_STR_STP_CLK = 0x5; | |
190 | MMC_STR_STP_CLK = 0x5; | |
191 | MMC_STR_STP_CLK = 0x5; | |
192 | MMC_STR_STP_CLK = 0x5; | |
193 | MMC_STR_STP_CLK = 0x5; | |
194 | MMC_STR_STP_CLK = 0x5; | |
195 | MMC_STR_STP_CLK = 0x5; | |
196 | MMC_STR_STP_CLK = 0x5; | |
197 | ||
198 | MMC_RES_TO = 0xff; | |
199 | MMC_BLK_LEN = 512; | |
200 | MMC_NOB = 1; | |
201 | } | |
202 | ||
203 | static int imxmci_busy_wait_for_status(struct imxmci_host *host, | |
204 | unsigned int *pstat, unsigned int stat_mask, | |
205 | int timeout, const char *where) | |
206 | { | |
207 | int loops=0; | |
208 | while(!(*pstat & stat_mask)) { | |
209 | loops+=2; | |
210 | if(loops >= timeout) { | |
211 | dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n", | |
212 | where, *pstat, stat_mask); | |
213 | return -1; | |
214 | } | |
215 | udelay(2); | |
216 | *pstat |= MMC_STATUS; | |
217 | } | |
218 | if(!loops) | |
219 | return 0; | |
220 | ||
221 | dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n", | |
222 | loops, where, *pstat, stat_mask); | |
223 | return loops; | |
224 | } | |
225 | ||
226 | static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) | |
227 | { | |
228 | unsigned int nob = data->blocks; | |
229 | unsigned int blksz = 1 << data->blksz_bits; | |
230 | unsigned int datasz = nob * blksz; | |
231 | int i; | |
232 | ||
233 | if (data->flags & MMC_DATA_STREAM) | |
234 | nob = 0xffff; | |
235 | ||
236 | host->data = data; | |
237 | data->bytes_xfered = 0; | |
238 | ||
239 | MMC_NOB = nob; | |
240 | MMC_BLK_LEN = blksz; | |
241 | ||
242 | /* | |
243 | * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise. | |
244 | * We are in big troubles for non-512 byte transfers according to note in the paragraph | |
245 | * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least. | |
246 | * The situation is even more complex in reality. The SDHC in not able to handle wll | |
247 | * partial FIFO fills and reads. The length has to be rounded up to burst size multiple. | |
248 | * This is required for SCR read at least. | |
249 | */ | |
250 | if (datasz < 64) { | |
251 | host->dma_size = datasz; | |
252 | if (data->flags & MMC_DATA_READ) { | |
253 | host->dma_dir = DMA_FROM_DEVICE; | |
254 | ||
255 | /* Hack to enable read SCR */ | |
256 | if(datasz < 16) { | |
257 | MMC_NOB = 1; | |
258 | MMC_BLK_LEN = 16; | |
259 | } | |
260 | } else { | |
261 | host->dma_dir = DMA_TO_DEVICE; | |
262 | } | |
263 | ||
264 | /* Convert back to virtual address */ | |
265 | host->data_ptr = (u16*)(page_address(data->sg->page) + data->sg->offset); | |
266 | host->data_cnt = 0; | |
267 | ||
268 | clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events); | |
269 | set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events); | |
270 | ||
271 | return; | |
272 | } | |
273 | ||
274 | if (data->flags & MMC_DATA_READ) { | |
275 | host->dma_dir = DMA_FROM_DEVICE; | |
276 | host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
277 | data->sg_len, host->dma_dir); | |
278 | ||
279 | imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, | |
280 | host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ); | |
281 | ||
282 | /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/ | |
283 | CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN; | |
284 | } else { | |
285 | host->dma_dir = DMA_TO_DEVICE; | |
286 | ||
287 | host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
288 | data->sg_len, host->dma_dir); | |
289 | ||
290 | imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, | |
291 | host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE); | |
292 | ||
293 | /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/ | |
294 | CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN; | |
295 | } | |
296 | ||
297 | #if 1 /* This code is there only for consistency checking and can be disabled in future */ | |
298 | host->dma_size = 0; | |
299 | for(i=0; i<host->dma_nents; i++) | |
300 | host->dma_size+=data->sg[i].length; | |
301 | ||
302 | if (datasz > host->dma_size) { | |
303 | dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n", | |
304 | datasz, host->dma_size); | |
305 | } | |
306 | #endif | |
307 | ||
308 | host->dma_size = datasz; | |
309 | ||
310 | wmb(); | |
311 | ||
312 | if(host->actual_bus_width == MMC_BUS_WIDTH_4) | |
313 | BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */ | |
314 | else | |
315 | BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */ | |
316 | ||
317 | RSSR(host->dma) = DMA_REQ_SDHC; | |
318 | ||
319 | set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events); | |
320 | clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events); | |
321 | ||
322 | /* start DMA engine for read, write is delayed after initial response */ | |
323 | if (host->dma_dir == DMA_FROM_DEVICE) { | |
324 | imx_dma_enable(host->dma); | |
325 | } | |
326 | } | |
327 | ||
328 | static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat) | |
329 | { | |
330 | unsigned long flags; | |
331 | u32 imask; | |
332 | ||
333 | WARN_ON(host->cmd != NULL); | |
334 | host->cmd = cmd; | |
335 | ||
336 | if (cmd->flags & MMC_RSP_BUSY) | |
337 | cmdat |= CMD_DAT_CONT_BUSY; | |
338 | ||
339 | switch (mmc_resp_type(cmd)) { | |
340 | case MMC_RSP_R1: /* short CRC, OPCODE */ | |
341 | case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ | |
342 | cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1; | |
343 | break; | |
344 | case MMC_RSP_R2: /* long 136 bit + CRC */ | |
345 | cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2; | |
346 | break; | |
347 | case MMC_RSP_R3: /* short */ | |
348 | cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3; | |
349 | break; | |
350 | case MMC_RSP_R6: /* short CRC */ | |
351 | cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R6; | |
352 | break; | |
353 | default: | |
354 | break; | |
355 | } | |
356 | ||
357 | if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) ) | |
358 | cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */ | |
359 | ||
360 | if ( host->actual_bus_width == MMC_BUS_WIDTH_4 ) | |
361 | cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; | |
362 | ||
363 | MMC_CMD = cmd->opcode; | |
364 | MMC_ARGH = cmd->arg >> 16; | |
365 | MMC_ARGL = cmd->arg & 0xffff; | |
366 | MMC_CMD_DAT_CONT = cmdat; | |
367 | ||
368 | atomic_set(&host->stuck_timeout, 0); | |
369 | set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events); | |
370 | ||
371 | ||
372 | imask = IMXMCI_INT_MASK_DEFAULT; | |
373 | imask &= ~INT_MASK_END_CMD_RES; | |
374 | if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) { | |
375 | /*imask &= ~INT_MASK_BUF_READY;*/ | |
376 | imask &= ~INT_MASK_DATA_TRAN; | |
377 | if ( cmdat & CMD_DAT_CONT_WRITE ) | |
378 | imask &= ~INT_MASK_WRITE_OP_DONE; | |
379 | if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) | |
380 | imask &= ~INT_MASK_BUF_READY; | |
381 | } | |
382 | ||
383 | spin_lock_irqsave(&host->lock, flags); | |
384 | host->imask = imask; | |
385 | MMC_INT_MASK = host->imask; | |
386 | spin_unlock_irqrestore(&host->lock, flags); | |
387 | ||
388 | dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n", | |
389 | cmd->opcode, cmd->opcode, imask); | |
390 | ||
391 | imxmci_start_clock(host); | |
392 | } | |
393 | ||
394 | static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req) | |
395 | { | |
396 | unsigned long flags; | |
397 | ||
398 | spin_lock_irqsave(&host->lock, flags); | |
399 | ||
400 | host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m | | |
401 | IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m); | |
402 | ||
403 | host->imask = IMXMCI_INT_MASK_DEFAULT; | |
404 | MMC_INT_MASK = host->imask; | |
405 | ||
406 | spin_unlock_irqrestore(&host->lock, flags); | |
407 | ||
408 | host->req = NULL; | |
409 | host->cmd = NULL; | |
410 | host->data = NULL; | |
411 | mmc_request_done(host->mmc, req); | |
412 | } | |
413 | ||
414 | static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat) | |
415 | { | |
416 | struct mmc_data *data = host->data; | |
417 | int data_error; | |
418 | ||
419 | if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){ | |
420 | imx_dma_disable(host->dma); | |
421 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents, | |
422 | host->dma_dir); | |
423 | } | |
424 | ||
425 | if ( stat & STATUS_ERR_MASK ) { | |
426 | dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat); | |
427 | if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR)) | |
428 | data->error = MMC_ERR_BADCRC; | |
429 | else if(stat & STATUS_TIME_OUT_READ) | |
430 | data->error = MMC_ERR_TIMEOUT; | |
431 | else | |
432 | data->error = MMC_ERR_FAILED; | |
433 | } else { | |
434 | data->bytes_xfered = host->dma_size; | |
435 | } | |
436 | ||
437 | data_error = data->error; | |
438 | ||
439 | host->data = NULL; | |
440 | ||
441 | return data_error; | |
442 | } | |
443 | ||
444 | static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat) | |
445 | { | |
446 | struct mmc_command *cmd = host->cmd; | |
447 | int i; | |
448 | u32 a,b,c; | |
449 | struct mmc_data *data = host->data; | |
450 | ||
451 | if (!cmd) | |
452 | return 0; | |
453 | ||
454 | host->cmd = NULL; | |
455 | ||
456 | if (stat & STATUS_TIME_OUT_RESP) { | |
457 | dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); | |
458 | cmd->error = MMC_ERR_TIMEOUT; | |
459 | } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { | |
460 | dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); | |
461 | cmd->error = MMC_ERR_BADCRC; | |
462 | } | |
463 | ||
464 | if(cmd->flags & MMC_RSP_PRESENT) { | |
465 | if(cmd->flags & MMC_RSP_136) { | |
466 | for (i = 0; i < 4; i++) { | |
467 | u32 a = MMC_RES_FIFO & 0xffff; | |
468 | u32 b = MMC_RES_FIFO & 0xffff; | |
469 | cmd->resp[i] = a<<16 | b; | |
470 | } | |
471 | } else { | |
472 | a = MMC_RES_FIFO & 0xffff; | |
473 | b = MMC_RES_FIFO & 0xffff; | |
474 | c = MMC_RES_FIFO & 0xffff; | |
475 | cmd->resp[0] = a<<24 | b<<8 | c>>8; | |
476 | } | |
477 | } | |
478 | ||
479 | dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n", | |
480 | cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error); | |
481 | ||
482 | if (data && (cmd->error == MMC_ERR_NONE) && !(stat & STATUS_ERR_MASK)) { | |
483 | if (host->req->data->flags & MMC_DATA_WRITE) { | |
484 | ||
485 | /* Wait for FIFO to be empty before starting DMA write */ | |
486 | ||
487 | stat = MMC_STATUS; | |
488 | if(imxmci_busy_wait_for_status(host, &stat, | |
489 | STATUS_APPL_BUFF_FE, | |
490 | 40, "imxmci_cmd_done DMA WR") < 0) { | |
491 | cmd->error = MMC_ERR_FIFO; | |
492 | imxmci_finish_data(host, stat); | |
493 | if(host->req) | |
494 | imxmci_finish_request(host, host->req); | |
495 | dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n", | |
496 | stat); | |
497 | return 0; | |
498 | } | |
499 | ||
500 | if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { | |
501 | imx_dma_enable(host->dma); | |
502 | } | |
503 | } | |
504 | } else { | |
505 | struct mmc_request *req; | |
506 | imxmci_stop_clock(host); | |
507 | req = host->req; | |
508 | ||
509 | if(data) | |
510 | imxmci_finish_data(host, stat); | |
511 | ||
512 | if( req ) { | |
513 | imxmci_finish_request(host, req); | |
514 | } else { | |
515 | dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n"); | |
516 | } | |
517 | } | |
518 | ||
519 | return 1; | |
520 | } | |
521 | ||
522 | static int imxmci_data_done(struct imxmci_host *host, unsigned int stat) | |
523 | { | |
524 | struct mmc_data *data = host->data; | |
525 | int data_error; | |
526 | ||
527 | if (!data) | |
528 | return 0; | |
529 | ||
530 | data_error = imxmci_finish_data(host, stat); | |
531 | ||
58741e8b | 532 | if (host->req->stop) { |
56ca9040 PP |
533 | imxmci_stop_clock(host); |
534 | imxmci_start_cmd(host, host->req->stop, 0); | |
535 | } else { | |
536 | struct mmc_request *req; | |
537 | req = host->req; | |
538 | if( req ) { | |
539 | imxmci_finish_request(host, req); | |
540 | } else { | |
541 | dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n"); | |
542 | } | |
543 | } | |
544 | ||
545 | return 1; | |
546 | } | |
547 | ||
548 | static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) | |
549 | { | |
550 | int i; | |
551 | int burst_len; | |
552 | int flush_len; | |
553 | int trans_done = 0; | |
554 | unsigned int stat = *pstat; | |
555 | ||
556 | if(host->actual_bus_width == MMC_BUS_WIDTH_4) | |
557 | burst_len = 16; | |
558 | else | |
559 | burst_len = 64; | |
560 | ||
561 | /* This is unfortunately required */ | |
562 | dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n", | |
563 | stat); | |
564 | ||
565 | if(host->dma_dir == DMA_FROM_DEVICE) { | |
566 | imxmci_busy_wait_for_status(host, &stat, | |
567 | STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE, | |
568 | 20, "imxmci_cpu_driven_data read"); | |
569 | ||
570 | while((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) && | |
571 | (host->data_cnt < host->dma_size)) { | |
572 | if(burst_len >= host->dma_size - host->data_cnt) { | |
573 | flush_len = burst_len; | |
574 | burst_len = host->dma_size - host->data_cnt; | |
575 | flush_len -= burst_len; | |
576 | host->data_cnt = host->dma_size; | |
577 | trans_done = 1; | |
578 | } else { | |
579 | flush_len = 0; | |
580 | host->data_cnt += burst_len; | |
581 | } | |
582 | ||
583 | for(i = burst_len; i>=2 ; i-=2) { | |
584 | *(host->data_ptr++) = MMC_BUFFER_ACCESS; | |
585 | udelay(20); /* required for clocks < 8MHz*/ | |
586 | } | |
587 | ||
588 | if(i == 1) | |
589 | *(u8*)(host->data_ptr) = MMC_BUFFER_ACCESS; | |
590 | ||
591 | stat = MMC_STATUS; | |
592 | ||
593 | /* Flush extra bytes from FIFO */ | |
594 | while(flush_len >= 2){ | |
595 | flush_len -= 2; | |
596 | i = MMC_BUFFER_ACCESS; | |
597 | stat = MMC_STATUS; | |
598 | stat &= ~STATUS_CRC_READ_ERR; /* Stupid but required there */ | |
599 | } | |
600 | ||
601 | dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read burst %d STATUS = 0x%x\n", | |
602 | burst_len, stat); | |
603 | } | |
604 | } else { | |
605 | imxmci_busy_wait_for_status(host, &stat, | |
606 | STATUS_APPL_BUFF_FE, | |
607 | 20, "imxmci_cpu_driven_data write"); | |
608 | ||
609 | while((stat & STATUS_APPL_BUFF_FE) && | |
610 | (host->data_cnt < host->dma_size)) { | |
611 | if(burst_len >= host->dma_size - host->data_cnt) { | |
612 | burst_len = host->dma_size - host->data_cnt; | |
613 | host->data_cnt = host->dma_size; | |
614 | trans_done = 1; | |
615 | } else { | |
616 | host->data_cnt += burst_len; | |
617 | } | |
618 | ||
619 | for(i = burst_len; i>0 ; i-=2) | |
620 | MMC_BUFFER_ACCESS = *(host->data_ptr++); | |
621 | ||
622 | stat = MMC_STATUS; | |
623 | ||
624 | dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n", | |
625 | burst_len, stat); | |
626 | } | |
627 | } | |
628 | ||
629 | *pstat = stat; | |
630 | ||
631 | return trans_done; | |
632 | } | |
633 | ||
634 | static void imxmci_dma_irq(int dma, void *devid, struct pt_regs *regs) | |
635 | { | |
636 | struct imxmci_host *host = devid; | |
637 | uint32_t stat = MMC_STATUS; | |
638 | ||
639 | atomic_set(&host->stuck_timeout, 0); | |
640 | host->status_reg = stat; | |
641 | set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events); | |
642 | tasklet_schedule(&host->tasklet); | |
643 | } | |
644 | ||
645 | static irqreturn_t imxmci_irq(int irq, void *devid, struct pt_regs *regs) | |
646 | { | |
647 | struct imxmci_host *host = devid; | |
648 | uint32_t stat = MMC_STATUS; | |
649 | int handled = 1; | |
650 | ||
651 | MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT; | |
652 | ||
653 | atomic_set(&host->stuck_timeout, 0); | |
654 | host->status_reg = stat; | |
655 | set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events); | |
81d38428 | 656 | set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events); |
56ca9040 PP |
657 | tasklet_schedule(&host->tasklet); |
658 | ||
659 | return IRQ_RETVAL(handled);; | |
660 | } | |
661 | ||
662 | static void imxmci_tasklet_fnc(unsigned long data) | |
663 | { | |
664 | struct imxmci_host *host = (struct imxmci_host *)data; | |
665 | u32 stat; | |
666 | unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */ | |
667 | int timeout = 0; | |
668 | ||
669 | if(atomic_read(&host->stuck_timeout) > 4) { | |
670 | char *what; | |
671 | timeout = 1; | |
672 | stat = MMC_STATUS; | |
673 | host->status_reg = stat; | |
674 | if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) | |
675 | if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) | |
676 | what = "RESP+DMA"; | |
677 | else | |
678 | what = "RESP"; | |
679 | else | |
680 | if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) | |
681 | if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events)) | |
682 | what = "DATA"; | |
683 | else | |
684 | what = "DMA"; | |
685 | else | |
686 | what = "???"; | |
687 | ||
688 | dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n", | |
689 | what, stat, MMC_INT_MASK); | |
690 | dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n", | |
691 | MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma)); | |
692 | dev_err(mmc_dev(host->mmc), "CMD%d, bus %d-bit, dma_size = 0x%x\n", | |
693 | host->cmd?host->cmd->opcode:0, 1<<host->actual_bus_width, host->dma_size); | |
694 | } | |
695 | ||
696 | if(!host->present || timeout) | |
697 | host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ | | |
698 | STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR; | |
699 | ||
700 | if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) { | |
701 | clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events); | |
702 | ||
703 | stat = MMC_STATUS; | |
704 | /* | |
705 | * This is not required in theory, but there is chance to miss some flag | |
706 | * which clears automatically by mask write, FreeScale original code keeps | |
707 | * stat from IRQ time so do I | |
708 | */ | |
709 | stat |= host->status_reg; | |
710 | ||
711 | if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { | |
712 | imxmci_busy_wait_for_status(host, &stat, | |
713 | STATUS_END_CMD_RESP | STATUS_ERR_MASK, | |
714 | 20, "imxmci_tasklet_fnc resp (ERRATUM #4)"); | |
715 | } | |
716 | ||
717 | if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) { | |
718 | if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) | |
719 | imxmci_cmd_done(host, stat); | |
720 | if(host->data && (stat & STATUS_ERR_MASK)) | |
721 | imxmci_data_done(host, stat); | |
722 | } | |
723 | ||
724 | if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) { | |
725 | stat |= MMC_STATUS; | |
726 | if(imxmci_cpu_driven_data(host, &stat)){ | |
727 | if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) | |
728 | imxmci_cmd_done(host, stat); | |
729 | atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m, | |
730 | &host->pending_events); | |
731 | imxmci_data_done(host, stat); | |
732 | } | |
733 | } | |
734 | } | |
735 | ||
736 | if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) && | |
737 | !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { | |
738 | ||
739 | stat = MMC_STATUS; | |
740 | /* Same as above */ | |
741 | stat |= host->status_reg; | |
742 | ||
743 | if(host->dma_dir == DMA_TO_DEVICE) { | |
744 | data_dir_mask = STATUS_WRITE_OP_DONE; | |
745 | } else { | |
746 | data_dir_mask = STATUS_DATA_TRANS_DONE; | |
747 | } | |
748 | ||
749 | imxmci_busy_wait_for_status(host, &stat, | |
750 | data_dir_mask, | |
751 | 50, "imxmci_tasklet_fnc data"); | |
752 | ||
753 | if(stat & data_dir_mask) { | |
754 | clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events); | |
755 | imxmci_data_done(host, stat); | |
756 | } | |
757 | } | |
758 | ||
759 | if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) { | |
760 | ||
761 | if(host->cmd) | |
762 | imxmci_cmd_done(host, STATUS_TIME_OUT_RESP); | |
763 | ||
764 | if(host->data) | |
765 | imxmci_data_done(host, STATUS_TIME_OUT_READ | | |
766 | STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR); | |
767 | ||
768 | if(host->req) | |
769 | imxmci_finish_request(host, host->req); | |
770 | ||
771 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); | |
772 | ||
773 | } | |
774 | } | |
775 | ||
776 | static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req) | |
777 | { | |
778 | struct imxmci_host *host = mmc_priv(mmc); | |
779 | unsigned int cmdat; | |
780 | ||
781 | WARN_ON(host->req != NULL); | |
782 | ||
783 | host->req = req; | |
784 | ||
785 | cmdat = 0; | |
786 | ||
787 | if (req->data) { | |
788 | imxmci_setup_data(host, req->data); | |
789 | ||
790 | cmdat |= CMD_DAT_CONT_DATA_ENABLE; | |
791 | ||
792 | if (req->data->flags & MMC_DATA_WRITE) | |
793 | cmdat |= CMD_DAT_CONT_WRITE; | |
794 | ||
795 | if (req->data->flags & MMC_DATA_STREAM) { | |
796 | cmdat |= CMD_DAT_CONT_STREAM_BLOCK; | |
797 | } | |
798 | } | |
799 | ||
800 | imxmci_start_cmd(host, req->cmd, cmdat); | |
801 | } | |
802 | ||
803 | #define CLK_RATE 19200000 | |
804 | ||
805 | static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
806 | { | |
807 | struct imxmci_host *host = mmc_priv(mmc); | |
808 | int prescaler; | |
809 | ||
56ca9040 PP |
810 | if( ios->bus_width==MMC_BUS_WIDTH_4 ) { |
811 | host->actual_bus_width = MMC_BUS_WIDTH_4; | |
812 | imx_gpio_mode(PB11_PF_SD_DAT3); | |
813 | }else{ | |
814 | host->actual_bus_width = MMC_BUS_WIDTH_1; | |
815 | imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11); | |
816 | } | |
817 | ||
818 | if ( host->power_mode != ios->power_mode ) { | |
819 | switch (ios->power_mode) { | |
820 | case MMC_POWER_OFF: | |
821 | break; | |
822 | case MMC_POWER_UP: | |
823 | set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); | |
824 | break; | |
825 | case MMC_POWER_ON: | |
826 | break; | |
827 | } | |
828 | host->power_mode = ios->power_mode; | |
829 | } | |
830 | ||
831 | if ( ios->clock ) { | |
832 | unsigned int clk; | |
833 | ||
834 | /* The prescaler is 5 for PERCLK2 equal to 96MHz | |
835 | * then 96MHz / 5 = 19.2 MHz | |
836 | */ | |
837 | clk=imx_get_perclk2(); | |
838 | prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE; | |
839 | switch(prescaler) { | |
840 | case 0: | |
841 | case 1: prescaler = 0; | |
842 | break; | |
843 | case 2: prescaler = 1; | |
844 | break; | |
845 | case 3: prescaler = 2; | |
846 | break; | |
847 | case 4: prescaler = 4; | |
848 | break; | |
849 | default: | |
850 | case 5: prescaler = 5; | |
851 | break; | |
852 | } | |
853 | ||
854 | dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n", | |
855 | clk, prescaler); | |
856 | ||
857 | for(clk=0; clk<8; clk++) { | |
858 | int x; | |
859 | x = CLK_RATE / (1<<clk); | |
860 | if( x <= ios->clock) | |
861 | break; | |
862 | } | |
863 | ||
864 | MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */ | |
865 | ||
866 | imxmci_stop_clock(host); | |
867 | MMC_CLK_RATE = (prescaler<<3) | clk; | |
868 | imxmci_start_clock(host); | |
869 | ||
870 | dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE); | |
871 | } else { | |
872 | imxmci_stop_clock(host); | |
873 | } | |
874 | } | |
875 | ||
876 | static struct mmc_host_ops imxmci_ops = { | |
877 | .request = imxmci_request, | |
878 | .set_ios = imxmci_set_ios, | |
879 | }; | |
880 | ||
881 | static struct resource *platform_device_resource(struct platform_device *dev, unsigned int mask, int nr) | |
882 | { | |
883 | int i; | |
884 | ||
885 | for (i = 0; i < dev->num_resources; i++) | |
886 | if (dev->resource[i].flags == mask && nr-- == 0) | |
887 | return &dev->resource[i]; | |
888 | return NULL; | |
889 | } | |
890 | ||
891 | static int platform_device_irq(struct platform_device *dev, int nr) | |
892 | { | |
893 | int i; | |
894 | ||
895 | for (i = 0; i < dev->num_resources; i++) | |
896 | if (dev->resource[i].flags == IORESOURCE_IRQ && nr-- == 0) | |
897 | return dev->resource[i].start; | |
898 | return NO_IRQ; | |
899 | } | |
900 | ||
901 | static void imxmci_check_status(unsigned long data) | |
902 | { | |
903 | struct imxmci_host *host = (struct imxmci_host *)data; | |
904 | ||
905 | if( host->pdata->card_present() != host->present ) { | |
906 | host->present ^= 1; | |
907 | dev_info(mmc_dev(host->mmc), "card %s\n", | |
908 | host->present ? "inserted" : "removed"); | |
909 | ||
910 | set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events); | |
911 | tasklet_schedule(&host->tasklet); | |
912 | } | |
913 | ||
914 | if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) || | |
915 | test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { | |
916 | atomic_inc(&host->stuck_timeout); | |
917 | if(atomic_read(&host->stuck_timeout) > 4) | |
918 | tasklet_schedule(&host->tasklet); | |
919 | } else { | |
920 | atomic_set(&host->stuck_timeout, 0); | |
921 | ||
922 | } | |
923 | ||
924 | mod_timer(&host->timer, jiffies + (HZ>>1)); | |
925 | } | |
926 | ||
927 | static int imxmci_probe(struct platform_device *pdev) | |
928 | { | |
929 | struct mmc_host *mmc; | |
930 | struct imxmci_host *host = NULL; | |
931 | struct resource *r; | |
932 | int ret = 0, irq; | |
933 | ||
934 | printk(KERN_INFO "i.MX mmc driver\n"); | |
935 | ||
936 | r = platform_device_resource(pdev, IORESOURCE_MEM, 0); | |
937 | irq = platform_device_irq(pdev, 0); | |
938 | if (!r || irq == NO_IRQ) | |
939 | return -ENXIO; | |
940 | ||
941 | r = request_mem_region(r->start, 0x100, "IMXMCI"); | |
942 | if (!r) | |
943 | return -EBUSY; | |
944 | ||
945 | mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev); | |
946 | if (!mmc) { | |
947 | ret = -ENOMEM; | |
948 | goto out; | |
949 | } | |
950 | ||
951 | mmc->ops = &imxmci_ops; | |
952 | mmc->f_min = 150000; | |
953 | mmc->f_max = CLK_RATE/2; | |
954 | mmc->ocr_avail = MMC_VDD_32_33; | |
955 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
956 | ||
957 | /* MMC core transfer sizes tunable parameters */ | |
958 | mmc->max_hw_segs = 64; | |
959 | mmc->max_phys_segs = 64; | |
960 | mmc->max_sectors = 64; /* default 1 << (PAGE_CACHE_SHIFT - 9) */ | |
961 | mmc->max_seg_size = 64*512; /* default PAGE_CACHE_SIZE */ | |
962 | ||
963 | host = mmc_priv(mmc); | |
964 | host->mmc = mmc; | |
965 | host->dma_allocated = 0; | |
966 | host->pdata = pdev->dev.platform_data; | |
967 | ||
968 | spin_lock_init(&host->lock); | |
969 | host->res = r; | |
970 | host->irq = irq; | |
971 | ||
972 | imx_gpio_mode(PB8_PF_SD_DAT0); | |
973 | imx_gpio_mode(PB9_PF_SD_DAT1); | |
974 | imx_gpio_mode(PB10_PF_SD_DAT2); | |
975 | /* Configured as GPIO with pull-up to ensure right MCC card mode */ | |
976 | /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */ | |
977 | imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11); | |
978 | /* imx_gpio_mode(PB11_PF_SD_DAT3); */ | |
979 | imx_gpio_mode(PB12_PF_SD_CLK); | |
980 | imx_gpio_mode(PB13_PF_SD_CMD); | |
981 | ||
982 | imxmci_softreset(); | |
983 | ||
984 | if ( MMC_REV_NO != 0x390 ) { | |
985 | dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", | |
986 | MMC_REV_NO); | |
987 | goto out; | |
988 | } | |
989 | ||
990 | MMC_READ_TO = 0x2db4; /* recommended in data sheet */ | |
991 | ||
992 | host->imask = IMXMCI_INT_MASK_DEFAULT; | |
993 | MMC_INT_MASK = host->imask; | |
994 | ||
995 | ||
996 | if(imx_dma_request_by_prio(&host->dma, DRIVER_NAME, DMA_PRIO_LOW)<0){ | |
997 | dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n"); | |
998 | ret = -EBUSY; | |
999 | goto out; | |
1000 | } | |
1001 | host->dma_allocated=1; | |
1002 | imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host); | |
1003 | ||
1004 | tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host); | |
1005 | host->status_reg=0; | |
1006 | host->pending_events=0; | |
1007 | ||
1008 | ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host); | |
1009 | if (ret) | |
1010 | goto out; | |
1011 | ||
1012 | host->present = host->pdata->card_present(); | |
1013 | init_timer(&host->timer); | |
1014 | host->timer.data = (unsigned long)host; | |
1015 | host->timer.function = imxmci_check_status; | |
1016 | add_timer(&host->timer); | |
1017 | mod_timer(&host->timer, jiffies + (HZ>>1)); | |
1018 | ||
1019 | platform_set_drvdata(pdev, mmc); | |
1020 | ||
1021 | mmc_add_host(mmc); | |
1022 | ||
1023 | return 0; | |
1024 | ||
1025 | out: | |
1026 | if (host) { | |
1027 | if(host->dma_allocated){ | |
1028 | imx_dma_free(host->dma); | |
1029 | host->dma_allocated=0; | |
1030 | } | |
1031 | } | |
1032 | if (mmc) | |
1033 | mmc_free_host(mmc); | |
1034 | release_resource(r); | |
1035 | return ret; | |
1036 | } | |
1037 | ||
1038 | static int imxmci_remove(struct platform_device *pdev) | |
1039 | { | |
1040 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1041 | ||
1042 | platform_set_drvdata(pdev, NULL); | |
1043 | ||
1044 | if (mmc) { | |
1045 | struct imxmci_host *host = mmc_priv(mmc); | |
1046 | ||
1047 | tasklet_disable(&host->tasklet); | |
1048 | ||
1049 | del_timer_sync(&host->timer); | |
1050 | mmc_remove_host(mmc); | |
1051 | ||
1052 | free_irq(host->irq, host); | |
1053 | if(host->dma_allocated){ | |
1054 | imx_dma_free(host->dma); | |
1055 | host->dma_allocated=0; | |
1056 | } | |
1057 | ||
1058 | tasklet_kill(&host->tasklet); | |
1059 | ||
1060 | release_resource(host->res); | |
1061 | ||
1062 | mmc_free_host(mmc); | |
1063 | } | |
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | #ifdef CONFIG_PM | |
1068 | static int imxmci_suspend(struct platform_device *dev, pm_message_t state) | |
1069 | { | |
1070 | struct mmc_host *mmc = platform_get_drvdata(dev); | |
1071 | int ret = 0; | |
1072 | ||
1073 | if (mmc) | |
1074 | ret = mmc_suspend_host(mmc, state); | |
1075 | ||
1076 | return ret; | |
1077 | } | |
1078 | ||
1079 | static int imxmci_resume(struct platform_device *dev) | |
1080 | { | |
1081 | struct mmc_host *mmc = platform_get_drvdata(dev); | |
1082 | struct imxmci_host *host; | |
1083 | int ret = 0; | |
1084 | ||
1085 | if (mmc) { | |
1086 | host = mmc_priv(mmc); | |
1087 | if(host) | |
1088 | set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); | |
1089 | ret = mmc_resume_host(mmc); | |
1090 | } | |
1091 | ||
1092 | return ret; | |
1093 | } | |
1094 | #else | |
1095 | #define imxmci_suspend NULL | |
1096 | #define imxmci_resume NULL | |
1097 | #endif /* CONFIG_PM */ | |
1098 | ||
1099 | static struct platform_driver imxmci_driver = { | |
1100 | .probe = imxmci_probe, | |
1101 | .remove = imxmci_remove, | |
1102 | .suspend = imxmci_suspend, | |
1103 | .resume = imxmci_resume, | |
1104 | .driver = { | |
1105 | .name = DRIVER_NAME, | |
1106 | } | |
1107 | }; | |
1108 | ||
1109 | static int __init imxmci_init(void) | |
1110 | { | |
1111 | return platform_driver_register(&imxmci_driver); | |
1112 | } | |
1113 | ||
1114 | static void __exit imxmci_exit(void) | |
1115 | { | |
1116 | platform_driver_unregister(&imxmci_driver); | |
1117 | } | |
1118 | ||
1119 | module_init(imxmci_init); | |
1120 | module_exit(imxmci_exit); | |
1121 | ||
1122 | MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); | |
1123 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
1124 | MODULE_LICENSE("GPL"); |