[deliverable/linux.git] / drivers / mmc / mmci.c

/*
 *  linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver
 *
 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/config.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/highmem.h>
#include <linux/mmc/host.h>
#include <linux/mmc/protocol.h>
#include <linux/amba/bus.h>
#include <linux/clk.h>

#include <asm/cacheflush.h>
#include <asm/div64.h>
#include <asm/io.h>
#include <asm/scatterlist.h>
#include <asm/sizes.h>
#include <asm/mach/mmc.h>

#include "mmci.h"

#define DRIVER_NAME "mmci-pl18x"

#define DBG(host,fmt,args...)	\
	pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)

static unsigned int fmax = 515633;

static void
mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
{
	writel(0, host->base + MMCICOMMAND);

	host->mrq = NULL;
	host->cmd = NULL;

	if (mrq->data)
		mrq->data->bytes_xfered = host->data_xfered;

	/*
	 * Need to drop the host lock here; mmc_request_done may call
	 * back into the driver...
	 */
	spin_unlock(&host->lock);
	mmc_request_done(host->mmc, mrq);
	spin_lock(&host->lock);
}

static void mmci_stop_data(struct mmci_host *host)
{
	writel(0, host->base + MMCIDATACTRL);
	writel(0, host->base + MMCIMASK1);
	host->data = NULL;
}

static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
{
	unsigned int datactrl, timeout, irqmask;
	unsigned long long clks;
	void __iomem *base;

	DBG(host, "blksz %04x blks %04x flags %08x\n",
	    1 << data->blksz_bits, data->blocks, data->flags);

	host->data = data;
	host->size = data->blocks << data->blksz_bits;
	host->data_xfered = 0;

	mmci_init_sg(host, data);

	clks = (unsigned long long)data->timeout_ns * host->cclk;
	do_div(clks, 1000000000UL);

	timeout = data->timeout_clks + (unsigned int)clks;

	base = host->base;
	writel(timeout, base + MMCIDATATIMER);
	writel(host->size, base + MMCIDATALENGTH);

	datactrl = MCI_DPSM_ENABLE | data->blksz_bits << 4;
	if (data->flags & MMC_DATA_READ) {
		datactrl |= MCI_DPSM_DIRECTION;
		irqmask = MCI_RXFIFOHALFFULLMASK;

		/*
		 * If we have less than a FIFOSIZE of bytes to transfer,
		 * trigger a PIO interrupt as soon as any data is available.
		 */
		if (host->size < MCI_FIFOSIZE)
			irqmask |= MCI_RXDATAAVLBLMASK;
	} else {
		/*
		 * We don't actually need to include "FIFO empty" here
		 * since its implicit in "FIFO half empty".
		 */
		irqmask = MCI_TXFIFOHALFEMPTYMASK;
	}

	writel(datactrl, base + MMCIDATACTRL);
	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
	writel(irqmask, base + MMCIMASK1);
}

static void
mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
{
	void __iomem *base = host->base;

	DBG(host, "op %02x arg %08x flags %08x\n",
	    cmd->opcode, cmd->arg, cmd->flags);

	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
		writel(0, base + MMCICOMMAND);
		udelay(1);
	}

	c |= cmd->opcode | MCI_CPSM_ENABLE;
	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136)
			c |= MCI_CPSM_LONGRSP;
		c |= MCI_CPSM_RESPONSE;
	}
	if (/*interrupt*/0)
		c |= MCI_CPSM_INTERRUPT;

	host->cmd = cmd;

	writel(cmd->arg, base + MMCIARGUMENT);
	writel(c, base + MMCICOMMAND);
}

static void
mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
	      unsigned int status)
{
	if (status & MCI_DATABLOCKEND) {
		host->data_xfered += 1 << data->blksz_bits;
	}
	if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
		if (status & MCI_DATACRCFAIL)
			data->error = MMC_ERR_BADCRC;
		else if (status & MCI_DATATIMEOUT)
			data->error = MMC_ERR_TIMEOUT;
		else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
			data->error = MMC_ERR_FIFO;
		status |= MCI_DATAEND;

		/*
		 * We hit an error condition.  Ensure that any data
		 * partially written to a page is properly coherent.
		 */
		if (host->sg_len && data->flags & MMC_DATA_READ)
			flush_dcache_page(host->sg_ptr->page);
	}
	if (status & MCI_DATAEND) {
		mmci_stop_data(host);

		if (!data->stop) {
			mmci_request_end(host, data->mrq);
		} else {
			mmci_start_command(host, data->stop, 0);
		}
	}
}

static void
mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
	     unsigned int status)
{
	void __iomem *base = host->base;

	host->cmd = NULL;

	cmd->resp[0] = readl(base + MMCIRESPONSE0);
	cmd->resp[1] = readl(base + MMCIRESPONSE1);
	cmd->resp[2] = readl(base + MMCIRESPONSE2);
	cmd->resp[3] = readl(base + MMCIRESPONSE3);

	if (status & MCI_CMDTIMEOUT) {
		cmd->error = MMC_ERR_TIMEOUT;
	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
		cmd->error = MMC_ERR_BADCRC;
	}

	if (!cmd->data || cmd->error != MMC_ERR_NONE) {
		mmci_request_end(host, cmd->mrq);
	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
		mmci_start_data(host, cmd->data);
	}
}

static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
{
	void __iomem *base = host->base;
	char *ptr = buffer;
	u32 status;

	do {
		int count = host->size - (readl(base + MMCIFIFOCNT) << 2);

		if (count > remain)
			count = remain;

		if (count <= 0)
			break;

		readsl(base + MMCIFIFO, ptr, count >> 2);

		ptr += count;
		remain -= count;

		if (remain == 0)
			break;

		status = readl(base + MMCISTATUS);
	} while (status & MCI_RXDATAAVLBL);

	return ptr - buffer;
}

static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
{
	void __iomem *base = host->base;
	char *ptr = buffer;

	do {
		unsigned int count, maxcnt;

		maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
		count = min(remain, maxcnt);

		writesl(base + MMCIFIFO, ptr, count >> 2);

		ptr += count;
		remain -= count;

		if (remain == 0)
			break;

		status = readl(base + MMCISTATUS);
	} while (status & MCI_TXFIFOHALFEMPTY);

	return ptr - buffer;
}

/*
 * PIO data transfer IRQ handler.
 */
static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs)
{
	struct mmci_host *host = dev_id;
	void __iomem *base = host->base;
	u32 status;

	status = readl(base + MMCISTATUS);

	DBG(host, "irq1 %08x\n", status);

	do {
		unsigned long flags;
		unsigned int remain, len;
		char *buffer;

		/*
		 * For write, we only need to test the half-empty flag
		 * here - if the FIFO is completely empty, then by
		 * definition it is more than half empty.
		 *
		 * For read, check for data available.
		 */
		if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
			break;

		/*
		 * Map the current scatter buffer.
		 */
		buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
		remain = host->sg_ptr->length - host->sg_off;

		len = 0;
		if (status & MCI_RXACTIVE)
			len = mmci_pio_read(host, buffer, remain);
		if (status & MCI_TXACTIVE)
			len = mmci_pio_write(host, buffer, remain, status);

		/*
		 * Unmap the buffer.
		 */
		mmci_kunmap_atomic(host, buffer, &flags);

		host->sg_off += len;
		host->size -= len;
		remain -= len;

		if (remain)
			break;

		/*
		 * If we were reading, and we have completed this
		 * page, ensure that the data cache is coherent.
		 */
		if (status & MCI_RXACTIVE)
			flush_dcache_page(host->sg_ptr->page);

		if (!mmci_next_sg(host))
			break;

		status = readl(base + MMCISTATUS);
	} while (1);

	/*
	 * If we're nearing the end of the read, switch to
	 * "any data available" mode.
	 */
	if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
		writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);

	/*
	 * If we run out of data, disable the data IRQs; this
	 * prevents a race where the FIFO becomes empty before
	 * the chip itself has disabled the data path, and
	 * stops us racing with our data end IRQ.
	 */
	if (host->size == 0) {
		writel(0, base + MMCIMASK1);
		writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
	}

	return IRQ_HANDLED;
}

/*
 * Handle completion of command and data transfers.
 */
static irqreturn_t mmci_irq(int irq, void *dev_id, struct pt_regs *regs)
{
	struct mmci_host *host = dev_id;
	u32 status;
	int ret = 0;

	spin_lock(&host->lock);

	do {
		struct mmc_command *cmd;
		struct mmc_data *data;

		status = readl(host->base + MMCISTATUS);
		status &= readl(host->base + MMCIMASK0);
		writel(status, host->base + MMCICLEAR);

		DBG(host, "irq0 %08x\n", status);

		data = host->data;
		if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
			      MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
			mmci_data_irq(host, data, status);

		cmd = host->cmd;
		if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
			mmci_cmd_irq(host, cmd, status);

		ret = 1;
	} while (status);

	spin_unlock(&host->lock);

	return IRQ_RETVAL(ret);
}

static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct mmci_host *host = mmc_priv(mmc);

	WARN_ON(host->mrq != NULL);

	spin_lock_irq(&host->lock);

	host->mrq = mrq;

	if (mrq->data && mrq->data->flags & MMC_DATA_READ)
		mmci_start_data(host, mrq->data);

	mmci_start_command(host, mrq->cmd, 0);

	spin_unlock_irq(&host->lock);
}

static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct mmci_host *host = mmc_priv(mmc);
	u32 clk = 0, pwr = 0;

	DBG(host, "clock %uHz busmode %u powermode %u Vdd %u\n",
	    ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);

	if (ios->clock) {
		if (ios->clock >= host->mclk) {
			clk = MCI_CLK_BYPASS;
			host->cclk = host->mclk;
		} else {
			clk = host->mclk / (2 * ios->clock) - 1;
			if (clk > 256)
				clk = 255;
			host->cclk = host->mclk / (2 * (clk + 1));
		}
		clk |= MCI_CLK_ENABLE;
	}

	if (host->plat->translate_vdd)
		pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);

	switch (ios->power_mode) {
	case MMC_POWER_OFF:
		break;
	case MMC_POWER_UP:
		pwr |= MCI_PWR_UP;
		break;
	case MMC_POWER_ON:
		pwr |= MCI_PWR_ON;
		break;
	}

	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
		pwr |= MCI_ROD;

	writel(clk, host->base + MMCICLOCK);

	if (host->pwr != pwr) {
		host->pwr = pwr;
		writel(pwr, host->base + MMCIPOWER);
	}
}

static struct mmc_host_ops mmci_ops = {
	.request	= mmci_request,
	.set_ios	= mmci_set_ios,
};

static void mmci_check_status(unsigned long data)
{
	struct mmci_host *host = (struct mmci_host *)data;
	unsigned int status;

	status = host->plat->status(mmc_dev(host->mmc));
	if (status ^ host->oldstat)
		mmc_detect_change(host->mmc, 0);

	host->oldstat = status;
	mod_timer(&host->timer, jiffies + HZ);
}

static int mmci_probe(struct amba_device *dev, void *id)
{
	struct mmc_platform_data *plat = dev->dev.platform_data;
	struct mmci_host *host;
	struct mmc_host *mmc;
	int ret;

	/* must have platform data */
	if (!plat) {
		ret = -EINVAL;
		goto out;
	}

	ret = amba_request_regions(dev, DRIVER_NAME);
	if (ret)
		goto out;

	mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
	if (!mmc) {
		ret = -ENOMEM;
		goto rel_regions;
	}

	host = mmc_priv(mmc);
	host->clk = clk_get(&dev->dev, "MCLK");
	if (IS_ERR(host->clk)) {
		ret = PTR_ERR(host->clk);
		host->clk = NULL;
		goto host_free;
	}

	ret = clk_enable(host->clk);
	if (ret)
		goto clk_free;

	host->plat = plat;
	host->mclk = clk_get_rate(host->clk);
	host->mmc = mmc;
	host->base = ioremap(dev->res.start, SZ_4K);
	if (!host->base) {
		ret = -ENOMEM;
		goto clk_disable;
	}

	mmc->ops = &mmci_ops;
	mmc->f_min = (host->mclk + 511) / 512;
	mmc->f_max = min(host->mclk, fmax);
	mmc->ocr_avail = plat->ocr_mask;

	/*
	 * We can do SGIO
	 */
	mmc->max_hw_segs = 16;
	mmc->max_phys_segs = NR_SG;

	/*
	 * Since we only have a 16-bit data length register, we must
	 * ensure that we don't exceed 2^16-1 bytes in a single request.
	 * Choose 64 (512-byte) sectors as the limit.
	 */
	mmc->max_sectors = 64;

	/*
	 * Set the maximum segment size.  Since we aren't doing DMA
	 * (yet) we are only limited by the data length register.
	 */
	mmc->max_seg_size = mmc->max_sectors << 9;

	spin_lock_init(&host->lock);

	writel(0, host->base + MMCIMASK0);
	writel(0, host->base + MMCIMASK1);
	writel(0xfff, host->base + MMCICLEAR);

	ret = request_irq(dev->irq[0], mmci_irq, SA_SHIRQ, DRIVER_NAME " (cmd)", host);
	if (ret)
		goto unmap;

	ret = request_irq(dev->irq[1], mmci_pio_irq, SA_SHIRQ, DRIVER_NAME " (pio)", host);
	if (ret)
		goto irq0_free;

	writel(MCI_IRQENABLE, host->base + MMCIMASK0);

	amba_set_drvdata(dev, mmc);

	mmc_add_host(mmc);

	printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%08lx irq %d,%d\n",
		mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
		dev->res.start, dev->irq[0], dev->irq[1]);

	init_timer(&host->timer);
	host->timer.data = (unsigned long)host;
	host->timer.function = mmci_check_status;
	host->timer.expires = jiffies + HZ;
	add_timer(&host->timer);

	return 0;

 irq0_free:
	free_irq(dev->irq[0], host);
 unmap:
	iounmap(host->base);
 clk_disable:
	clk_disable(host->clk);
 clk_free:
	clk_put(host->clk);
 host_free:
	mmc_free_host(mmc);
 rel_regions:
	amba_release_regions(dev);
 out:
	return ret;
}

static int mmci_remove(struct amba_device *dev)
{
	struct mmc_host *mmc = amba_get_drvdata(dev);

	amba_set_drvdata(dev, NULL);

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);

		del_timer_sync(&host->timer);

		mmc_remove_host(mmc);

		writel(0, host->base + MMCIMASK0);
		writel(0, host->base + MMCIMASK1);

		writel(0, host->base + MMCICOMMAND);
		writel(0, host->base + MMCIDATACTRL);

		free_irq(dev->irq[0], host);
		free_irq(dev->irq[1], host);

		iounmap(host->base);
		clk_disable(host->clk);
		clk_put(host->clk);

		mmc_free_host(mmc);

		amba_release_regions(dev);
	}

	return 0;
}

#ifdef CONFIG_PM
static int mmci_suspend(struct amba_device *dev, pm_message_t state)
{
	struct mmc_host *mmc = amba_get_drvdata(dev);
	int ret = 0;

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);

		ret = mmc_suspend_host(mmc, state);
		if (ret == 0)
			writel(0, host->base + MMCIMASK0);
	}

	return ret;
}

static int mmci_resume(struct amba_device *dev)
{
	struct mmc_host *mmc = amba_get_drvdata(dev);
	int ret = 0;

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);

		writel(MCI_IRQENABLE, host->base + MMCIMASK0);

		ret = mmc_resume_host(mmc);
	}

	return ret;
}
#else
#define mmci_suspend	NULL
#define mmci_resume	NULL
#endif

static struct amba_id mmci_ids[] = {
	{
		.id	= 0x00041180,
		.mask	= 0x000fffff,
	},
	{
		.id	= 0x00041181,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};

static struct amba_driver mmci_driver = {
	.drv		= {
		.name	= DRIVER_NAME,
	},
	.probe		= mmci_probe,
	.remove		= mmci_remove,
	.suspend	= mmci_suspend,
	.resume		= mmci_resume,
	.id_table	= mmci_ids,
};

static int __init mmci_init(void)
{
	return amba_driver_register(&mmci_driver);
}

static void __exit mmci_exit(void)
{
	amba_driver_unregister(&mmci_driver);
}

module_init(mmci_init);
module_exit(mmci_exit);
module_param(fmax, uint, 0444);

MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#include <linux/config.h>
	11	#include <linux/module.h>
	12	#include <linux/moduleparam.h>
	13	#include <linux/init.h>
	14	#include <linux/ioport.h>
	15	#include <linux/device.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/delay.h>
	18	#include <linux/err.h>
	19	#include <linux/highmem.h>
	20	#include <linux/mmc/host.h>
	21	#include <linux/mmc/protocol.h>
a62c80e5	22	#include <linux/amba/bus.h>
f8ce2547	23	#include <linux/clk.h>
1da177e4	24
e9c091b4	25	#include <asm/cacheflush.h>
7b09cdac	26	#include <asm/div64.h>
1da177e4	27	#include <asm/io.h>
1da177e4	28	#include <asm/scatterlist.h>
c6b8fdad	29	#include <asm/sizes.h>
1da177e4 LT	30	#include <asm/mach/mmc.h>
	31
	32	#include "mmci.h"
	33
	34	#define DRIVER_NAME "mmci-pl18x"
	35
1da177e4	36	#define DBG(host,fmt,args...) \
d366b643	37	pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
1da177e4 LT	38
	39	static unsigned int fmax = 515633;
	40
	41	static void
	42	mmci_request_end(struct mmci_host host, struct mmc_request mrq)
	43	{
	44	writel(0, host->base + MMCICOMMAND);
	45
	46	host->mrq = NULL;
	47	host->cmd = NULL;
	48
	49	if (mrq->data)
	50	mrq->data->bytes_xfered = host->data_xfered;
	51
	52	/*
	53	* Need to drop the host lock here; mmc_request_done may call
	54	* back into the driver...
	55	*/
	56	spin_unlock(&host->lock);
	57	mmc_request_done(host->mmc, mrq);
	58	spin_lock(&host->lock);
	59	}
	60
	61	static void mmci_stop_data(struct mmci_host *host)
	62	{
	63	writel(0, host->base + MMCIDATACTRL);
	64	writel(0, host->base + MMCIMASK1);
	65	host->data = NULL;
	66	}
	67
	68	static void mmci_start_data(struct mmci_host host, struct mmc_data data)
	69	{
	70	unsigned int datactrl, timeout, irqmask;
7b09cdac	71	unsigned long long clks;
1da177e4 LT	72	void __iomem *base;
	73
	74	DBG(host, "blksz %04x blks %04x flags %08x\n",
	75	1 << data->blksz_bits, data->blocks, data->flags);
	76
	77	host->data = data;
	78	host->size = data->blocks << data->blksz_bits;
	79	host->data_xfered = 0;
	80
	81	mmci_init_sg(host, data);
	82
7b09cdac RK	83	clks = (unsigned long long)data->timeout_ns * host->cclk;
	84	do_div(clks, 1000000000UL);
	85
	86	timeout = data->timeout_clks + (unsigned int)clks;
1da177e4 LT	87
	88	base = host->base;
	89	writel(timeout, base + MMCIDATATIMER);
	90	writel(host->size, base + MMCIDATALENGTH);
	91
	92	datactrl = MCI_DPSM_ENABLE \| data->blksz_bits << 4;
	93	if (data->flags & MMC_DATA_READ) {
	94	datactrl \|= MCI_DPSM_DIRECTION;
	95	irqmask = MCI_RXFIFOHALFFULLMASK;
0425a142 RK	96
	97	/*
	98	* If we have less than a FIFOSIZE of bytes to transfer,
	99	* trigger a PIO interrupt as soon as any data is available.
	100	*/
	101	if (host->size < MCI_FIFOSIZE)
	102	irqmask \|= MCI_RXDATAAVLBLMASK;
1da177e4 LT	103	} else {
	104	/*
	105	* We don't actually need to include "FIFO empty" here
	106	* since its implicit in "FIFO half empty".
	107	*/
	108	irqmask = MCI_TXFIFOHALFEMPTYMASK;
	109	}
	110
	111	writel(datactrl, base + MMCIDATACTRL);
	112	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
	113	writel(irqmask, base + MMCIMASK1);
	114	}
	115
	116	static void
	117	mmci_start_command(struct mmci_host host, struct mmc_command cmd, u32 c)
	118	{
	119	void __iomem *base = host->base;
	120
	121	DBG(host, "op %02x arg %08x flags %08x\n",
	122	cmd->opcode, cmd->arg, cmd->flags);
	123
	124	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
	125	writel(0, base + MMCICOMMAND);
	126	udelay(1);
	127	}
	128
	129	c \|= cmd->opcode \| MCI_CPSM_ENABLE;
e9225176 RK	130	if (cmd->flags & MMC_RSP_PRESENT) {
	131	if (cmd->flags & MMC_RSP_136)
	132	c \|= MCI_CPSM_LONGRSP;
1da177e4	133	c \|= MCI_CPSM_RESPONSE;
1da177e4 LT	134	}
	135	if (/interrupt/0)
	136	c \|= MCI_CPSM_INTERRUPT;
	137
	138	host->cmd = cmd;
	139
	140	writel(cmd->arg, base + MMCIARGUMENT);
	141	writel(c, base + MMCICOMMAND);
	142	}
	143
	144	static void
	145	mmci_data_irq(struct mmci_host host, struct mmc_data data,
	146	unsigned int status)
	147	{
	148	if (status & MCI_DATABLOCKEND) {
	149	host->data_xfered += 1 << data->blksz_bits;
	150	}
	151	if (status & (MCI_DATACRCFAIL\|MCI_DATATIMEOUT\|MCI_TXUNDERRUN\|MCI_RXOVERRUN)) {
	152	if (status & MCI_DATACRCFAIL)
	153	data->error = MMC_ERR_BADCRC;
	154	else if (status & MCI_DATATIMEOUT)
	155	data->error = MMC_ERR_TIMEOUT;
	156	else if (status & (MCI_TXUNDERRUN\|MCI_RXOVERRUN))
	157	data->error = MMC_ERR_FIFO;
	158	status \|= MCI_DATAEND;
e9c091b4 RK	159
	160	/*
	161	* We hit an error condition. Ensure that any data
	162	* partially written to a page is properly coherent.
	163	*/
	164	if (host->sg_len && data->flags & MMC_DATA_READ)
	165	flush_dcache_page(host->sg_ptr->page);
1da177e4 LT	166	}
	167	if (status & MCI_DATAEND) {
	168	mmci_stop_data(host);
	169
	170	if (!data->stop) {
	171	mmci_request_end(host, data->mrq);
	172	} else {
	173	mmci_start_command(host, data->stop, 0);
	174	}
	175	}
	176	}
	177
	178	static void
	179	mmci_cmd_irq(struct mmci_host host, struct mmc_command cmd,
	180	unsigned int status)
	181	{
	182	void __iomem *base = host->base;
	183
	184	host->cmd = NULL;
	185
	186	cmd->resp[0] = readl(base + MMCIRESPONSE0);
	187	cmd->resp[1] = readl(base + MMCIRESPONSE1);
	188	cmd->resp[2] = readl(base + MMCIRESPONSE2);
	189	cmd->resp[3] = readl(base + MMCIRESPONSE3);
	190
	191	if (status & MCI_CMDTIMEOUT) {
	192	cmd->error = MMC_ERR_TIMEOUT;
	193	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
	194	cmd->error = MMC_ERR_BADCRC;
	195	}
	196
	197	if (!cmd->data \|\| cmd->error != MMC_ERR_NONE) {
	198	mmci_request_end(host, cmd->mrq);
	199	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
	200	mmci_start_data(host, cmd->data);
	201	}
	202	}
	203
	204	static int mmci_pio_read(struct mmci_host host, char buffer, unsigned int remain)
	205	{
	206	void __iomem *base = host->base;
	207	char *ptr = buffer;
	208	u32 status;
	209
	210	do {
	211	int count = host->size - (readl(base + MMCIFIFOCNT) << 2);
	212
	213	if (count > remain)
	214	count = remain;
	215
	216	if (count <= 0)
	217	break;
	218
	219	readsl(base + MMCIFIFO, ptr, count >> 2);
	220
	221	ptr += count;
	222	remain -= count;
	223
	224	if (remain == 0)
	225	break;
	226
	227	status = readl(base + MMCISTATUS);
	228	} while (status & MCI_RXDATAAVLBL);
	229
230	return ptr - buffer;
231	}
232
233	static int mmci_pio_write(struct mmci_host host, char buffer, unsigned int remain, u32 status)
234	{
235	void __iomem *base = host->base;
236	char *ptr = buffer;
237
238	do {
239	unsigned int count, maxcnt;
240
241	maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
242	count = min(remain, maxcnt);
243
244	writesl(base + MMCIFIFO, ptr, count >> 2);
245
246	ptr += count;
247	remain -= count;
248
249	if (remain == 0)
250	break;
251
252	status = readl(base + MMCISTATUS);
253	} while (status & MCI_TXFIFOHALFEMPTY);
254
255	return ptr - buffer;
256	}
257
258	/*
259	* PIO data transfer IRQ handler.
260	*/
261	static irqreturn_t mmci_pio_irq(int irq, void dev_id, struct pt_regs regs)
262	{
263	struct mmci_host *host = dev_id;
264	void __iomem *base = host->base;
265	u32 status;
266
267	status = readl(base + MMCISTATUS);
268
269	DBG(host, "irq1 %08x\n", status);
270
271	do {
272	unsigned long flags;
273	unsigned int remain, len;
274	char *buffer;
275
276	/*
277	* For write, we only need to test the half-empty flag
278	* here - if the FIFO is completely empty, then by
279	* definition it is more than half empty.
280	*
281	* For read, check for data available.
282	*/
283	if (!(status & (MCI_TXFIFOHALFEMPTY\|MCI_RXDATAAVLBL)))
284	break;
285
286	/*
287	* Map the current scatter buffer.
288	*/
289	buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
290	remain = host->sg_ptr->length - host->sg_off;
291
292	len = 0;
293	if (status & MCI_RXACTIVE)
294	len = mmci_pio_read(host, buffer, remain);
295	if (status & MCI_TXACTIVE)
296	len = mmci_pio_write(host, buffer, remain, status);
297
298	/*
299	* Unmap the buffer.
300	*/
f3e2628b	301	mmci_kunmap_atomic(host, buffer, &flags);
1da177e4 LT	302
	303	host->sg_off += len;
	304	host->size -= len;
	305	remain -= len;
	306
	307	if (remain)
	308	break;
	309
e9c091b4 RK	310	/*
	311	* If we were reading, and we have completed this
	312	* page, ensure that the data cache is coherent.
	313	*/
	314	if (status & MCI_RXACTIVE)
	315	flush_dcache_page(host->sg_ptr->page);
	316
1da177e4 LT	317	if (!mmci_next_sg(host))
	318	break;
	319
	320	status = readl(base + MMCISTATUS);
	321	} while (1);
	322
	323	/*
	324	* If we're nearing the end of the read, switch to
	325	* "any data available" mode.
	326	*/
	327	if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
	328	writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
	329
	330	/*
	331	* If we run out of data, disable the data IRQs; this
	332	* prevents a race where the FIFO becomes empty before
	333	* the chip itself has disabled the data path, and
	334	* stops us racing with our data end IRQ.
	335	*/
	336	if (host->size == 0) {
	337	writel(0, base + MMCIMASK1);
	338	writel(readl(base + MMCIMASK0) \| MCI_DATAENDMASK, base + MMCIMASK0);
	339	}
	340
	341	return IRQ_HANDLED;
	342	}
	343
	344	/*
	345	* Handle completion of command and data transfers.
	346	*/
	347	static irqreturn_t mmci_irq(int irq, void dev_id, struct pt_regs regs)
	348	{
	349	struct mmci_host *host = dev_id;
	350	u32 status;
	351	int ret = 0;
	352
	353	spin_lock(&host->lock);
	354
	355	do {
	356	struct mmc_command *cmd;
	357	struct mmc_data *data;
	358
	359	status = readl(host->base + MMCISTATUS);
	360	status &= readl(host->base + MMCIMASK0);
	361	writel(status, host->base + MMCICLEAR);
	362
	363	DBG(host, "irq0 %08x\n", status);
	364
	365	data = host->data;
	366	if (status & (MCI_DATACRCFAIL\|MCI_DATATIMEOUT\|MCI_TXUNDERRUN\|
	367	MCI_RXOVERRUN\|MCI_DATAEND\|MCI_DATABLOCKEND) && data)
	368	mmci_data_irq(host, data, status);
	369
	370	cmd = host->cmd;
	371	if (status & (MCI_CMDCRCFAIL\|MCI_CMDTIMEOUT\|MCI_CMDSENT\|MCI_CMDRESPEND) && cmd)
	372	mmci_cmd_irq(host, cmd, status);
	373
	374	ret = 1;
	375	} while (status);
	376
	377	spin_unlock(&host->lock);
	378
	379	return IRQ_RETVAL(ret);
	380	}
381
382	static void mmci_request(struct mmc_host mmc, struct mmc_request mrq)
383	{
384	struct mmci_host *host = mmc_priv(mmc);
385
386	WARN_ON(host->mrq != NULL);
387
388	spin_lock_irq(&host->lock);
389
390	host->mrq = mrq;
391
392	if (mrq->data && mrq->data->flags & MMC_DATA_READ)
393	mmci_start_data(host, mrq->data);
394
395	mmci_start_command(host, mrq->cmd, 0);
396
397	spin_unlock_irq(&host->lock);
398	}
399
400	static void mmci_set_ios(struct mmc_host mmc, struct mmc_ios ios)
401	{
402	struct mmci_host *host = mmc_priv(mmc);
403	u32 clk = 0, pwr = 0;
404
405	DBG(host, "clock %uHz busmode %u powermode %u Vdd %u\n",
406	ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);
407
408	if (ios->clock) {
409	if (ios->clock >= host->mclk) {
410	clk = MCI_CLK_BYPASS;
411	host->cclk = host->mclk;
412	} else {
413	clk = host->mclk / (2 * ios->clock) - 1;
414	if (clk > 256)
415	clk = 255;
416	host->cclk = host->mclk / (2 * (clk + 1));
417	}
418	clk \|= MCI_CLK_ENABLE;
419	}
420
421	if (host->plat->translate_vdd)
422	pwr \|= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
423
424	switch (ios->power_mode) {
425	case MMC_POWER_OFF:
426	break;
427	case MMC_POWER_UP:
428	pwr \|= MCI_PWR_UP;
429	break;
430	case MMC_POWER_ON:
431	pwr \|= MCI_PWR_ON;
432	break;
433	}
434
435	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
436	pwr \|= MCI_ROD;
437
438	writel(clk, host->base + MMCICLOCK);
439
440	if (host->pwr != pwr) {
441	host->pwr = pwr;
442	writel(pwr, host->base + MMCIPOWER);
443	}
444	}
445
446	static struct mmc_host_ops mmci_ops = {
447	.request = mmci_request,
448	.set_ios = mmci_set_ios,
449	};
450
451	static void mmci_check_status(unsigned long data)
452	{
453	struct mmci_host host = (struct mmci_host )data;
454	unsigned int status;
455
456	status = host->plat->status(mmc_dev(host->mmc));
457	if (status ^ host->oldstat)
8dc00335	458	mmc_detect_change(host->mmc, 0);
1da177e4 LT	459
	460	host->oldstat = status;
	461	mod_timer(&host->timer, jiffies + HZ);
	462	}
	463
	464	static int mmci_probe(struct amba_device dev, void id)
	465	{
	466	struct mmc_platform_data *plat = dev->dev.platform_data;
	467	struct mmci_host *host;
	468	struct mmc_host *mmc;
	469	int ret;
	470
	471	/* must have platform data */
	472	if (!plat) {
	473	ret = -EINVAL;
	474	goto out;
	475	}
	476
	477	ret = amba_request_regions(dev, DRIVER_NAME);
	478	if (ret)
	479	goto out;
	480
	481	mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
	482	if (!mmc) {
	483	ret = -ENOMEM;
	484	goto rel_regions;
	485	}
	486
	487	host = mmc_priv(mmc);
	488	host->clk = clk_get(&dev->dev, "MCLK");
	489	if (IS_ERR(host->clk)) {
	490	ret = PTR_ERR(host->clk);
	491	host->clk = NULL;
	492	goto host_free;
	493	}
	494
1da177e4 LT	495	ret = clk_enable(host->clk);
1da177e4 LT	496	if (ret)
a8d3584a	497	goto clk_free;
1da177e4 LT	498
	499	host->plat = plat;
	500	host->mclk = clk_get_rate(host->clk);
	501	host->mmc = mmc;
	502	host->base = ioremap(dev->res.start, SZ_4K);
	503	if (!host->base) {
	504	ret = -ENOMEM;
	505	goto clk_disable;
	506	}
	507
	508	mmc->ops = &mmci_ops;
	509	mmc->f_min = (host->mclk + 511) / 512;
	510	mmc->f_max = min(host->mclk, fmax);
	511	mmc->ocr_avail = plat->ocr_mask;
	512
	513	/*
	514	* We can do SGIO
	515	*/
	516	mmc->max_hw_segs = 16;
	517	mmc->max_phys_segs = NR_SG;
	518
	519	/*
	520	* Since we only have a 16-bit data length register, we must
	521	* ensure that we don't exceed 2^16-1 bytes in a single request.
	522	* Choose 64 (512-byte) sectors as the limit.
	523	*/
	524	mmc->max_sectors = 64;
	525
	526	/*
	527	* Set the maximum segment size. Since we aren't doing DMA
	528	* (yet) we are only limited by the data length register.
	529	*/
	530	mmc->max_seg_size = mmc->max_sectors << 9;
	531
	532	spin_lock_init(&host->lock);
	533
	534	writel(0, host->base + MMCIMASK0);
	535	writel(0, host->base + MMCIMASK1);
	536	writel(0xfff, host->base + MMCICLEAR);
	537
	538	ret = request_irq(dev->irq[0], mmci_irq, SA_SHIRQ, DRIVER_NAME " (cmd)", host);
	539	if (ret)
	540	goto unmap;
	541
	542	ret = request_irq(dev->irq[1], mmci_pio_irq, SA_SHIRQ, DRIVER_NAME " (pio)", host);
	543	if (ret)
	544	goto irq0_free;
	545
	546	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
	547
	548	amba_set_drvdata(dev, mmc);
	549
	550	mmc_add_host(mmc);
	551
	552	printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%08lx irq %d,%d\n",
d366b643	553	mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
1da177e4 LT	554	dev->res.start, dev->irq[0], dev->irq[1]);
	555
	556	init_timer(&host->timer);
	557	host->timer.data = (unsigned long)host;
	558	host->timer.function = mmci_check_status;
	559	host->timer.expires = jiffies + HZ;
	560	add_timer(&host->timer);
	561
	562	return 0;
	563
	564	irq0_free:
	565	free_irq(dev->irq[0], host);
	566	unmap:
	567	iounmap(host->base);
	568	clk_disable:
	569	clk_disable(host->clk);
1da177e4 LT	570	clk_free:
	571	clk_put(host->clk);
	572	host_free:
	573	mmc_free_host(mmc);
	574	rel_regions:
	575	amba_release_regions(dev);
	576	out:
	577	return ret;
	578	}
	579
	580	static int mmci_remove(struct amba_device *dev)
	581	{
	582	struct mmc_host *mmc = amba_get_drvdata(dev);
	583
	584	amba_set_drvdata(dev, NULL);
	585
	586	if (mmc) {
	587	struct mmci_host *host = mmc_priv(mmc);
	588
	589	del_timer_sync(&host->timer);
	590
	591	mmc_remove_host(mmc);
	592
	593	writel(0, host->base + MMCIMASK0);
	594	writel(0, host->base + MMCIMASK1);
	595
	596	writel(0, host->base + MMCICOMMAND);
	597	writel(0, host->base + MMCIDATACTRL);
	598
	599	free_irq(dev->irq[0], host);
	600	free_irq(dev->irq[1], host);
	601
	602	iounmap(host->base);
	603	clk_disable(host->clk);
1da177e4 LT	604	clk_put(host->clk);
	605
	606	mmc_free_host(mmc);
	607
	608	amba_release_regions(dev);
	609	}
	610
	611	return 0;
	612	}
	613
	614	#ifdef CONFIG_PM
e5378ca8	615	static int mmci_suspend(struct amba_device *dev, pm_message_t state)
1da177e4 LT	616	{
	617	struct mmc_host *mmc = amba_get_drvdata(dev);
	618	int ret = 0;
	619
	620	if (mmc) {
	621	struct mmci_host *host = mmc_priv(mmc);
	622
	623	ret = mmc_suspend_host(mmc, state);
	624	if (ret == 0)
	625	writel(0, host->base + MMCIMASK0);
	626	}
	627
	628	return ret;
	629	}
	630
	631	static int mmci_resume(struct amba_device *dev)
	632	{
	633	struct mmc_host *mmc = amba_get_drvdata(dev);
	634	int ret = 0;
	635
	636	if (mmc) {
	637	struct mmci_host *host = mmc_priv(mmc);
	638
	639	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
	640
	641	ret = mmc_resume_host(mmc);
	642	}
	643
	644	return ret;
	645	}
	646	#else
	647	#define mmci_suspend NULL
	648	#define mmci_resume NULL
	649	#endif
	650
	651	static struct amba_id mmci_ids[] = {
	652	{
	653	.id = 0x00041180,
	654	.mask = 0x000fffff,
	655	},
	656	{
	657	.id = 0x00041181,
	658	.mask = 0x000fffff,
	659	},
	660	{ 0, 0 },
	661	};
	662
	663	static struct amba_driver mmci_driver = {
	664	.drv = {
	665	.name = DRIVER_NAME,
	666	},
	667	.probe = mmci_probe,
	668	.remove = mmci_remove,
	669	.suspend = mmci_suspend,
	670	.resume = mmci_resume,
	671	.id_table = mmci_ids,
	672	};
	673
	674	static int __init mmci_init(void)
	675	{
	676	return amba_driver_register(&mmci_driver);
	677	}
	678
	679	static void __exit mmci_exit(void)
680	{
681	amba_driver_unregister(&mmci_driver);
682	}
683
684	module_init(mmci_init);
685	module_exit(mmci_exit);
686	module_param(fmax, uint, 0444);
687
688	MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
689	MODULE_LICENSE("GPL");