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1da177e4 LT |
1 | /* |
2 | * linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver | |
3 | * | |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/config.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/highmem.h> | |
20 | #include <linux/mmc/host.h> | |
21 | #include <linux/mmc/protocol.h> | |
22 | ||
e9c091b4 | 23 | #include <asm/cacheflush.h> |
7b09cdac | 24 | #include <asm/div64.h> |
1da177e4 | 25 | #include <asm/io.h> |
1da177e4 | 26 | #include <asm/scatterlist.h> |
c6b8fdad | 27 | #include <asm/sizes.h> |
1da177e4 LT |
28 | #include <asm/hardware/amba.h> |
29 | #include <asm/hardware/clock.h> | |
30 | #include <asm/mach/mmc.h> | |
31 | ||
32 | #include "mmci.h" | |
33 | ||
34 | #define DRIVER_NAME "mmci-pl18x" | |
35 | ||
36 | #ifdef CONFIG_MMC_DEBUG | |
37 | #define DBG(host,fmt,args...) \ | |
d366b643 | 38 | pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args) |
1da177e4 LT |
39 | #else |
40 | #define DBG(host,fmt,args...) do { } while (0) | |
41 | #endif | |
42 | ||
43 | static unsigned int fmax = 515633; | |
44 | ||
45 | static void | |
46 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
47 | { | |
48 | writel(0, host->base + MMCICOMMAND); | |
49 | ||
50 | host->mrq = NULL; | |
51 | host->cmd = NULL; | |
52 | ||
53 | if (mrq->data) | |
54 | mrq->data->bytes_xfered = host->data_xfered; | |
55 | ||
56 | /* | |
57 | * Need to drop the host lock here; mmc_request_done may call | |
58 | * back into the driver... | |
59 | */ | |
60 | spin_unlock(&host->lock); | |
61 | mmc_request_done(host->mmc, mrq); | |
62 | spin_lock(&host->lock); | |
63 | } | |
64 | ||
65 | static void mmci_stop_data(struct mmci_host *host) | |
66 | { | |
67 | writel(0, host->base + MMCIDATACTRL); | |
68 | writel(0, host->base + MMCIMASK1); | |
69 | host->data = NULL; | |
70 | } | |
71 | ||
72 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) | |
73 | { | |
74 | unsigned int datactrl, timeout, irqmask; | |
7b09cdac | 75 | unsigned long long clks; |
1da177e4 LT |
76 | void __iomem *base; |
77 | ||
78 | DBG(host, "blksz %04x blks %04x flags %08x\n", | |
79 | 1 << data->blksz_bits, data->blocks, data->flags); | |
80 | ||
81 | host->data = data; | |
82 | host->size = data->blocks << data->blksz_bits; | |
83 | host->data_xfered = 0; | |
84 | ||
85 | mmci_init_sg(host, data); | |
86 | ||
7b09cdac RK |
87 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
88 | do_div(clks, 1000000000UL); | |
89 | ||
90 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
91 | |
92 | base = host->base; | |
93 | writel(timeout, base + MMCIDATATIMER); | |
94 | writel(host->size, base + MMCIDATALENGTH); | |
95 | ||
96 | datactrl = MCI_DPSM_ENABLE | data->blksz_bits << 4; | |
97 | if (data->flags & MMC_DATA_READ) { | |
98 | datactrl |= MCI_DPSM_DIRECTION; | |
99 | irqmask = MCI_RXFIFOHALFFULLMASK; | |
100 | } else { | |
101 | /* | |
102 | * We don't actually need to include "FIFO empty" here | |
103 | * since its implicit in "FIFO half empty". | |
104 | */ | |
105 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
106 | } | |
107 | ||
108 | writel(datactrl, base + MMCIDATACTRL); | |
109 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
110 | writel(irqmask, base + MMCIMASK1); | |
111 | } | |
112 | ||
113 | static void | |
114 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
115 | { | |
116 | void __iomem *base = host->base; | |
117 | ||
118 | DBG(host, "op %02x arg %08x flags %08x\n", | |
119 | cmd->opcode, cmd->arg, cmd->flags); | |
120 | ||
121 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
122 | writel(0, base + MMCICOMMAND); | |
123 | udelay(1); | |
124 | } | |
125 | ||
126 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
127 | switch (cmd->flags & MMC_RSP_MASK) { | |
128 | case MMC_RSP_NONE: | |
129 | default: | |
130 | break; | |
131 | case MMC_RSP_LONG: | |
132 | c |= MCI_CPSM_LONGRSP; | |
133 | case MMC_RSP_SHORT: | |
134 | c |= MCI_CPSM_RESPONSE; | |
135 | break; | |
136 | } | |
137 | if (/*interrupt*/0) | |
138 | c |= MCI_CPSM_INTERRUPT; | |
139 | ||
140 | host->cmd = cmd; | |
141 | ||
142 | writel(cmd->arg, base + MMCIARGUMENT); | |
143 | writel(c, base + MMCICOMMAND); | |
144 | } | |
145 | ||
146 | static void | |
147 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
148 | unsigned int status) | |
149 | { | |
150 | if (status & MCI_DATABLOCKEND) { | |
151 | host->data_xfered += 1 << data->blksz_bits; | |
152 | } | |
153 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
154 | if (status & MCI_DATACRCFAIL) | |
155 | data->error = MMC_ERR_BADCRC; | |
156 | else if (status & MCI_DATATIMEOUT) | |
157 | data->error = MMC_ERR_TIMEOUT; | |
158 | else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) | |
159 | data->error = MMC_ERR_FIFO; | |
160 | status |= MCI_DATAEND; | |
e9c091b4 RK |
161 | |
162 | /* | |
163 | * We hit an error condition. Ensure that any data | |
164 | * partially written to a page is properly coherent. | |
165 | */ | |
166 | if (host->sg_len && data->flags & MMC_DATA_READ) | |
167 | flush_dcache_page(host->sg_ptr->page); | |
1da177e4 LT |
168 | } |
169 | if (status & MCI_DATAEND) { | |
170 | mmci_stop_data(host); | |
171 | ||
172 | if (!data->stop) { | |
173 | mmci_request_end(host, data->mrq); | |
174 | } else { | |
175 | mmci_start_command(host, data->stop, 0); | |
176 | } | |
177 | } | |
178 | } | |
179 | ||
180 | static void | |
181 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
182 | unsigned int status) | |
183 | { | |
184 | void __iomem *base = host->base; | |
185 | ||
186 | host->cmd = NULL; | |
187 | ||
188 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
189 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
190 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
191 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
192 | ||
193 | if (status & MCI_CMDTIMEOUT) { | |
194 | cmd->error = MMC_ERR_TIMEOUT; | |
195 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { | |
196 | cmd->error = MMC_ERR_BADCRC; | |
197 | } | |
198 | ||
199 | if (!cmd->data || cmd->error != MMC_ERR_NONE) { | |
200 | mmci_request_end(host, cmd->mrq); | |
201 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
202 | mmci_start_data(host, cmd->data); | |
203 | } | |
204 | } | |
205 | ||
206 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
207 | { | |
208 | void __iomem *base = host->base; | |
209 | char *ptr = buffer; | |
210 | u32 status; | |
211 | ||
212 | do { | |
213 | int count = host->size - (readl(base + MMCIFIFOCNT) << 2); | |
214 | ||
215 | if (count > remain) | |
216 | count = remain; | |
217 | ||
218 | if (count <= 0) | |
219 | break; | |
220 | ||
221 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
222 | ||
223 | ptr += count; | |
224 | remain -= count; | |
225 | ||
226 | if (remain == 0) | |
227 | break; | |
228 | ||
229 | status = readl(base + MMCISTATUS); | |
230 | } while (status & MCI_RXDATAAVLBL); | |
231 | ||
232 | return ptr - buffer; | |
233 | } | |
234 | ||
235 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
236 | { | |
237 | void __iomem *base = host->base; | |
238 | char *ptr = buffer; | |
239 | ||
240 | do { | |
241 | unsigned int count, maxcnt; | |
242 | ||
243 | maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; | |
244 | count = min(remain, maxcnt); | |
245 | ||
246 | writesl(base + MMCIFIFO, ptr, count >> 2); | |
247 | ||
248 | ptr += count; | |
249 | remain -= count; | |
250 | ||
251 | if (remain == 0) | |
252 | break; | |
253 | ||
254 | status = readl(base + MMCISTATUS); | |
255 | } while (status & MCI_TXFIFOHALFEMPTY); | |
256 | ||
257 | return ptr - buffer; | |
258 | } | |
259 | ||
260 | /* | |
261 | * PIO data transfer IRQ handler. | |
262 | */ | |
263 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs) | |
264 | { | |
265 | struct mmci_host *host = dev_id; | |
266 | void __iomem *base = host->base; | |
267 | u32 status; | |
268 | ||
269 | status = readl(base + MMCISTATUS); | |
270 | ||
271 | DBG(host, "irq1 %08x\n", status); | |
272 | ||
273 | do { | |
274 | unsigned long flags; | |
275 | unsigned int remain, len; | |
276 | char *buffer; | |
277 | ||
278 | /* | |
279 | * For write, we only need to test the half-empty flag | |
280 | * here - if the FIFO is completely empty, then by | |
281 | * definition it is more than half empty. | |
282 | * | |
283 | * For read, check for data available. | |
284 | */ | |
285 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
286 | break; | |
287 | ||
288 | /* | |
289 | * Map the current scatter buffer. | |
290 | */ | |
291 | buffer = mmci_kmap_atomic(host, &flags) + host->sg_off; | |
292 | remain = host->sg_ptr->length - host->sg_off; | |
293 | ||
294 | len = 0; | |
295 | if (status & MCI_RXACTIVE) | |
296 | len = mmci_pio_read(host, buffer, remain); | |
297 | if (status & MCI_TXACTIVE) | |
298 | len = mmci_pio_write(host, buffer, remain, status); | |
299 | ||
300 | /* | |
301 | * Unmap the buffer. | |
302 | */ | |
303 | mmci_kunmap_atomic(host, &flags); | |
304 | ||
305 | host->sg_off += len; | |
306 | host->size -= len; | |
307 | remain -= len; | |
308 | ||
309 | if (remain) | |
310 | break; | |
311 | ||
e9c091b4 RK |
312 | /* |
313 | * If we were reading, and we have completed this | |
314 | * page, ensure that the data cache is coherent. | |
315 | */ | |
316 | if (status & MCI_RXACTIVE) | |
317 | flush_dcache_page(host->sg_ptr->page); | |
318 | ||
1da177e4 LT |
319 | if (!mmci_next_sg(host)) |
320 | break; | |
321 | ||
322 | status = readl(base + MMCISTATUS); | |
323 | } while (1); | |
324 | ||
325 | /* | |
326 | * If we're nearing the end of the read, switch to | |
327 | * "any data available" mode. | |
328 | */ | |
329 | if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) | |
330 | writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); | |
331 | ||
332 | /* | |
333 | * If we run out of data, disable the data IRQs; this | |
334 | * prevents a race where the FIFO becomes empty before | |
335 | * the chip itself has disabled the data path, and | |
336 | * stops us racing with our data end IRQ. | |
337 | */ | |
338 | if (host->size == 0) { | |
339 | writel(0, base + MMCIMASK1); | |
340 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); | |
341 | } | |
342 | ||
343 | return IRQ_HANDLED; | |
344 | } | |
345 | ||
346 | /* | |
347 | * Handle completion of command and data transfers. | |
348 | */ | |
349 | static irqreturn_t mmci_irq(int irq, void *dev_id, struct pt_regs *regs) | |
350 | { | |
351 | struct mmci_host *host = dev_id; | |
352 | u32 status; | |
353 | int ret = 0; | |
354 | ||
355 | spin_lock(&host->lock); | |
356 | ||
357 | do { | |
358 | struct mmc_command *cmd; | |
359 | struct mmc_data *data; | |
360 | ||
361 | status = readl(host->base + MMCISTATUS); | |
362 | status &= readl(host->base + MMCIMASK0); | |
363 | writel(status, host->base + MMCICLEAR); | |
364 | ||
365 | DBG(host, "irq0 %08x\n", status); | |
366 | ||
367 | data = host->data; | |
368 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | |
369 | MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) | |
370 | mmci_data_irq(host, data, status); | |
371 | ||
372 | cmd = host->cmd; | |
373 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
374 | mmci_cmd_irq(host, cmd, status); | |
375 | ||
376 | ret = 1; | |
377 | } while (status); | |
378 | ||
379 | spin_unlock(&host->lock); | |
380 | ||
381 | return IRQ_RETVAL(ret); | |
382 | } | |
383 | ||
384 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
385 | { | |
386 | struct mmci_host *host = mmc_priv(mmc); | |
387 | ||
388 | WARN_ON(host->mrq != NULL); | |
389 | ||
390 | spin_lock_irq(&host->lock); | |
391 | ||
392 | host->mrq = mrq; | |
393 | ||
394 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) | |
395 | mmci_start_data(host, mrq->data); | |
396 | ||
397 | mmci_start_command(host, mrq->cmd, 0); | |
398 | ||
399 | spin_unlock_irq(&host->lock); | |
400 | } | |
401 | ||
402 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
403 | { | |
404 | struct mmci_host *host = mmc_priv(mmc); | |
405 | u32 clk = 0, pwr = 0; | |
406 | ||
407 | DBG(host, "clock %uHz busmode %u powermode %u Vdd %u\n", | |
408 | ios->clock, ios->bus_mode, ios->power_mode, ios->vdd); | |
409 | ||
410 | if (ios->clock) { | |
411 | if (ios->clock >= host->mclk) { | |
412 | clk = MCI_CLK_BYPASS; | |
413 | host->cclk = host->mclk; | |
414 | } else { | |
415 | clk = host->mclk / (2 * ios->clock) - 1; | |
416 | if (clk > 256) | |
417 | clk = 255; | |
418 | host->cclk = host->mclk / (2 * (clk + 1)); | |
419 | } | |
420 | clk |= MCI_CLK_ENABLE; | |
421 | } | |
422 | ||
423 | if (host->plat->translate_vdd) | |
424 | pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); | |
425 | ||
426 | switch (ios->power_mode) { | |
427 | case MMC_POWER_OFF: | |
428 | break; | |
429 | case MMC_POWER_UP: | |
430 | pwr |= MCI_PWR_UP; | |
431 | break; | |
432 | case MMC_POWER_ON: | |
433 | pwr |= MCI_PWR_ON; | |
434 | break; | |
435 | } | |
436 | ||
437 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
438 | pwr |= MCI_ROD; | |
439 | ||
440 | writel(clk, host->base + MMCICLOCK); | |
441 | ||
442 | if (host->pwr != pwr) { | |
443 | host->pwr = pwr; | |
444 | writel(pwr, host->base + MMCIPOWER); | |
445 | } | |
446 | } | |
447 | ||
448 | static struct mmc_host_ops mmci_ops = { | |
449 | .request = mmci_request, | |
450 | .set_ios = mmci_set_ios, | |
451 | }; | |
452 | ||
453 | static void mmci_check_status(unsigned long data) | |
454 | { | |
455 | struct mmci_host *host = (struct mmci_host *)data; | |
456 | unsigned int status; | |
457 | ||
458 | status = host->plat->status(mmc_dev(host->mmc)); | |
459 | if (status ^ host->oldstat) | |
8dc00335 | 460 | mmc_detect_change(host->mmc, 0); |
1da177e4 LT |
461 | |
462 | host->oldstat = status; | |
463 | mod_timer(&host->timer, jiffies + HZ); | |
464 | } | |
465 | ||
466 | static int mmci_probe(struct amba_device *dev, void *id) | |
467 | { | |
468 | struct mmc_platform_data *plat = dev->dev.platform_data; | |
469 | struct mmci_host *host; | |
470 | struct mmc_host *mmc; | |
471 | int ret; | |
472 | ||
473 | /* must have platform data */ | |
474 | if (!plat) { | |
475 | ret = -EINVAL; | |
476 | goto out; | |
477 | } | |
478 | ||
479 | ret = amba_request_regions(dev, DRIVER_NAME); | |
480 | if (ret) | |
481 | goto out; | |
482 | ||
483 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
484 | if (!mmc) { | |
485 | ret = -ENOMEM; | |
486 | goto rel_regions; | |
487 | } | |
488 | ||
489 | host = mmc_priv(mmc); | |
490 | host->clk = clk_get(&dev->dev, "MCLK"); | |
491 | if (IS_ERR(host->clk)) { | |
492 | ret = PTR_ERR(host->clk); | |
493 | host->clk = NULL; | |
494 | goto host_free; | |
495 | } | |
496 | ||
497 | ret = clk_use(host->clk); | |
498 | if (ret) | |
499 | goto clk_free; | |
500 | ||
501 | ret = clk_enable(host->clk); | |
502 | if (ret) | |
503 | goto clk_unuse; | |
504 | ||
505 | host->plat = plat; | |
506 | host->mclk = clk_get_rate(host->clk); | |
507 | host->mmc = mmc; | |
508 | host->base = ioremap(dev->res.start, SZ_4K); | |
509 | if (!host->base) { | |
510 | ret = -ENOMEM; | |
511 | goto clk_disable; | |
512 | } | |
513 | ||
514 | mmc->ops = &mmci_ops; | |
515 | mmc->f_min = (host->mclk + 511) / 512; | |
516 | mmc->f_max = min(host->mclk, fmax); | |
517 | mmc->ocr_avail = plat->ocr_mask; | |
518 | ||
519 | /* | |
520 | * We can do SGIO | |
521 | */ | |
522 | mmc->max_hw_segs = 16; | |
523 | mmc->max_phys_segs = NR_SG; | |
524 | ||
525 | /* | |
526 | * Since we only have a 16-bit data length register, we must | |
527 | * ensure that we don't exceed 2^16-1 bytes in a single request. | |
528 | * Choose 64 (512-byte) sectors as the limit. | |
529 | */ | |
530 | mmc->max_sectors = 64; | |
531 | ||
532 | /* | |
533 | * Set the maximum segment size. Since we aren't doing DMA | |
534 | * (yet) we are only limited by the data length register. | |
535 | */ | |
536 | mmc->max_seg_size = mmc->max_sectors << 9; | |
537 | ||
538 | spin_lock_init(&host->lock); | |
539 | ||
540 | writel(0, host->base + MMCIMASK0); | |
541 | writel(0, host->base + MMCIMASK1); | |
542 | writel(0xfff, host->base + MMCICLEAR); | |
543 | ||
544 | ret = request_irq(dev->irq[0], mmci_irq, SA_SHIRQ, DRIVER_NAME " (cmd)", host); | |
545 | if (ret) | |
546 | goto unmap; | |
547 | ||
548 | ret = request_irq(dev->irq[1], mmci_pio_irq, SA_SHIRQ, DRIVER_NAME " (pio)", host); | |
549 | if (ret) | |
550 | goto irq0_free; | |
551 | ||
552 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
553 | ||
554 | amba_set_drvdata(dev, mmc); | |
555 | ||
556 | mmc_add_host(mmc); | |
557 | ||
558 | printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%08lx irq %d,%d\n", | |
d366b643 | 559 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), |
1da177e4 LT |
560 | dev->res.start, dev->irq[0], dev->irq[1]); |
561 | ||
562 | init_timer(&host->timer); | |
563 | host->timer.data = (unsigned long)host; | |
564 | host->timer.function = mmci_check_status; | |
565 | host->timer.expires = jiffies + HZ; | |
566 | add_timer(&host->timer); | |
567 | ||
568 | return 0; | |
569 | ||
570 | irq0_free: | |
571 | free_irq(dev->irq[0], host); | |
572 | unmap: | |
573 | iounmap(host->base); | |
574 | clk_disable: | |
575 | clk_disable(host->clk); | |
576 | clk_unuse: | |
577 | clk_unuse(host->clk); | |
578 | clk_free: | |
579 | clk_put(host->clk); | |
580 | host_free: | |
581 | mmc_free_host(mmc); | |
582 | rel_regions: | |
583 | amba_release_regions(dev); | |
584 | out: | |
585 | return ret; | |
586 | } | |
587 | ||
588 | static int mmci_remove(struct amba_device *dev) | |
589 | { | |
590 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
591 | ||
592 | amba_set_drvdata(dev, NULL); | |
593 | ||
594 | if (mmc) { | |
595 | struct mmci_host *host = mmc_priv(mmc); | |
596 | ||
597 | del_timer_sync(&host->timer); | |
598 | ||
599 | mmc_remove_host(mmc); | |
600 | ||
601 | writel(0, host->base + MMCIMASK0); | |
602 | writel(0, host->base + MMCIMASK1); | |
603 | ||
604 | writel(0, host->base + MMCICOMMAND); | |
605 | writel(0, host->base + MMCIDATACTRL); | |
606 | ||
607 | free_irq(dev->irq[0], host); | |
608 | free_irq(dev->irq[1], host); | |
609 | ||
610 | iounmap(host->base); | |
611 | clk_disable(host->clk); | |
612 | clk_unuse(host->clk); | |
613 | clk_put(host->clk); | |
614 | ||
615 | mmc_free_host(mmc); | |
616 | ||
617 | amba_release_regions(dev); | |
618 | } | |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
623 | #ifdef CONFIG_PM | |
e5378ca8 | 624 | static int mmci_suspend(struct amba_device *dev, pm_message_t state) |
1da177e4 LT |
625 | { |
626 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
627 | int ret = 0; | |
628 | ||
629 | if (mmc) { | |
630 | struct mmci_host *host = mmc_priv(mmc); | |
631 | ||
632 | ret = mmc_suspend_host(mmc, state); | |
633 | if (ret == 0) | |
634 | writel(0, host->base + MMCIMASK0); | |
635 | } | |
636 | ||
637 | return ret; | |
638 | } | |
639 | ||
640 | static int mmci_resume(struct amba_device *dev) | |
641 | { | |
642 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
643 | int ret = 0; | |
644 | ||
645 | if (mmc) { | |
646 | struct mmci_host *host = mmc_priv(mmc); | |
647 | ||
648 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
649 | ||
650 | ret = mmc_resume_host(mmc); | |
651 | } | |
652 | ||
653 | return ret; | |
654 | } | |
655 | #else | |
656 | #define mmci_suspend NULL | |
657 | #define mmci_resume NULL | |
658 | #endif | |
659 | ||
660 | static struct amba_id mmci_ids[] = { | |
661 | { | |
662 | .id = 0x00041180, | |
663 | .mask = 0x000fffff, | |
664 | }, | |
665 | { | |
666 | .id = 0x00041181, | |
667 | .mask = 0x000fffff, | |
668 | }, | |
669 | { 0, 0 }, | |
670 | }; | |
671 | ||
672 | static struct amba_driver mmci_driver = { | |
673 | .drv = { | |
674 | .name = DRIVER_NAME, | |
675 | }, | |
676 | .probe = mmci_probe, | |
677 | .remove = mmci_remove, | |
678 | .suspend = mmci_suspend, | |
679 | .resume = mmci_resume, | |
680 | .id_table = mmci_ids, | |
681 | }; | |
682 | ||
683 | static int __init mmci_init(void) | |
684 | { | |
685 | return amba_driver_register(&mmci_driver); | |
686 | } | |
687 | ||
688 | static void __exit mmci_exit(void) | |
689 | { | |
690 | amba_driver_unregister(&mmci_driver); | |
691 | } | |
692 | ||
693 | module_init(mmci_init); | |
694 | module_exit(mmci_exit); | |
695 | module_param(fmax, uint, 0444); | |
696 | ||
697 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
698 | MODULE_LICENSE("GPL"); |