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Merge master.kernel.org:/pub/scm/linux/kernel/git/mchehab/v4l-dvb
[deliverable/linux.git] / drivers / mmc / sdhci.c
CommitLineData
d129bceb
PO		 1/*
2 * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
d129bceb
PO		 11#include <linux/delay.h>
12#include <linux/highmem.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15
16#include <linux/mmc/host.h>
17#include <linux/mmc/protocol.h>
18
19#include <asm/scatterlist.h>
20
21#include "sdhci.h"
22
23#define DRIVER_NAME "sdhci"
2c5f3940 24#define DRIVER_VERSION "0.12"
d129bceb
PO		 25
26#define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
27
d129bceb 28#define DBG(f, x...) \
c6563178 29 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 30
67435274
PO		 31static unsigned int debug_nodma = 0;
32static unsigned int debug_forcedma = 0;
df673b22 33static unsigned int debug_quirks = 0;
67435274 34
645289dc 35#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
98608076 36#define SDHCI_QUIRK_FORCE_DMA (1<<1)
645289dc 37
d129bceb 38static const struct pci_device_id pci_ids[] __devinitdata = {
645289dc
PO		 39 {
40 .vendor = PCI_VENDOR_ID_RICOH,
41 .device = PCI_DEVICE_ID_RICOH_R5C822,
42 .subvendor = PCI_VENDOR_ID_IBM,
43 .subdevice = PCI_ANY_ID,
98608076
PO		 44 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
45 SDHCI_QUIRK_FORCE_DMA,
46 },
47
48 {
49 .vendor = PCI_VENDOR_ID_RICOH,
50 .device = PCI_DEVICE_ID_RICOH_R5C822,
51 .subvendor = PCI_ANY_ID,
52 .subdevice = PCI_ANY_ID,
53 .driver_data = SDHCI_QUIRK_FORCE_DMA,
54 },
55
56 {
57 .vendor = PCI_VENDOR_ID_TI,
58 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
59 .subvendor = PCI_ANY_ID,
60 .subdevice = PCI_ANY_ID,
61 .driver_data = SDHCI_QUIRK_FORCE_DMA,
645289dc
PO		 62 },
63
64 { /* Generic SD host controller */
65 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
66 },
67
d129bceb
PO		 68 { /* end: all zeroes */ },
69};
70
71MODULE_DEVICE_TABLE(pci, pci_ids);
72
73static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
74static void sdhci_finish_data(struct sdhci_host *);
75
76static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
77static void sdhci_finish_command(struct sdhci_host *);
78
79static void sdhci_dumpregs(struct sdhci_host *host)
80{
81 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
82
83 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
84 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
85 readw(host->ioaddr + SDHCI_HOST_VERSION));
86 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
87 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
88 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
89 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
90 readl(host->ioaddr + SDHCI_ARGUMENT),
91 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
92 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
93 readl(host->ioaddr + SDHCI_PRESENT_STATE),
94 readb(host->ioaddr + SDHCI_HOST_CONTROL));
95 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
96 readb(host->ioaddr + SDHCI_POWER_CONTROL),
97 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
98 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
99 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
100 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
101 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
102 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
103 readl(host->ioaddr + SDHCI_INT_STATUS));
104 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
105 readl(host->ioaddr + SDHCI_INT_ENABLE),
106 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
107 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
108 readw(host->ioaddr + SDHCI_ACMD12_ERR),
109 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
110 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
111 readl(host->ioaddr + SDHCI_CAPABILITIES),
112 readl(host->ioaddr + SDHCI_MAX_CURRENT));
113
114 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
115}
116
117/*****************************************************************************\
118 * *
119 * Low level functions *
120 * *
121\*****************************************************************************/
122
123static void sdhci_reset(struct sdhci_host *host, u8 mask)
124{
e16514d8
PO		 125 unsigned long timeout;
126
d129bceb
PO		 127 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
128
e16514d8 129 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 130 host->clock = 0;
131
e16514d8
PO		 132 /* Wait max 100 ms */
133 timeout = 100;
134
135 /* hw clears the bit when it's done */
136 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
137 if (timeout == 0) {
138 printk(KERN_ERR "%s: Reset 0x%x never completed. "
139 "Please report this to " BUGMAIL ".\n",
140 mmc_hostname(host->mmc), (int)mask);
141 sdhci_dumpregs(host);
142 return;
143 }
144 timeout--;
145 mdelay(1);
d129bceb
PO		 146 }
147}
148
149static void sdhci_init(struct sdhci_host *host)
150{
151 u32 intmask;
152
153 sdhci_reset(host, SDHCI_RESET_ALL);
154
3192a28f
PO		 155 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
156 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
157 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
158 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 159 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
3192a28f 160 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
d129bceb
PO		 161
162 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
163 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 164}
165
166static void sdhci_activate_led(struct sdhci_host *host)
167{
168 u8 ctrl;
169
170 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
171 ctrl |= SDHCI_CTRL_LED;
172 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
173}
174
175static void sdhci_deactivate_led(struct sdhci_host *host)
176{
177 u8 ctrl;
178
179 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
180 ctrl &= ~SDHCI_CTRL_LED;
181 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
182}
183
184/*****************************************************************************\
185 * *
186 * Core functions *
187 * *
188\*****************************************************************************/
189
190static inline char* sdhci_kmap_sg(struct sdhci_host* host)
191{
192 host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
193 return host->mapped_sg + host->cur_sg->offset;
194}
195
196static inline void sdhci_kunmap_sg(struct sdhci_host* host)
197{
198 kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
199}
200
201static inline int sdhci_next_sg(struct sdhci_host* host)
202{
203 /*
204 * Skip to next SG entry.
205 */
206 host->cur_sg++;
207 host->num_sg--;
208
209 /*
210 * Any entries left?
211 */
212 if (host->num_sg > 0) {
213 host->offset = 0;
214 host->remain = host->cur_sg->length;
215 }
216
217 return host->num_sg;
218}
219
a406f5a3 220static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 221{
a406f5a3
PO		 222 int blksize, chunk_remain;
223 u32 data;
d129bceb 224 char *buffer;
a406f5a3 225 int size;
d129bceb 226
a406f5a3 227 DBG("PIO reading\n");
d129bceb 228
a406f5a3
PO		 229 blksize = host->data->blksz;
230 chunk_remain = 0;
231 data = 0;
d129bceb
PO		 232
233 buffer = sdhci_kmap_sg(host) + host->offset;
234
a406f5a3
PO		 235 while (blksize) {
236 if (chunk_remain == 0) {
237 data = readl(host->ioaddr + SDHCI_BUFFER);
238 chunk_remain = min(blksize, 4);
239 }
d129bceb 240
a406f5a3
PO		 241 size = min(host->size, host->remain);
242 size = min(size, chunk_remain);
d129bceb 243
a406f5a3
PO		 244 chunk_remain -= size;
245 blksize -= size;
246 host->offset += size;
247 host->remain -= size;
248 host->size -= size;
249 while (size) {
250 *buffer = data & 0xFF;
251 buffer++;
252 data >>= 8;
253 size--;
254 }
d129bceb 255
a406f5a3
PO		 256 if (host->remain == 0) {
257 sdhci_kunmap_sg(host);
258 if (sdhci_next_sg(host) == 0) {
259 BUG_ON(blksize != 0);
260 return;
261 }
262 buffer = sdhci_kmap_sg(host);
d129bceb 263 }
a406f5a3 264 }
d129bceb 265
a406f5a3
PO		 266 sdhci_kunmap_sg(host);
267}
d129bceb 268
a406f5a3
PO		 269static void sdhci_write_block_pio(struct sdhci_host *host)
270{
271 int blksize, chunk_remain;
272 u32 data;
273 char *buffer;
274 int bytes, size;
d129bceb 275
a406f5a3
PO		 276 DBG("PIO writing\n");
277
278 blksize = host->data->blksz;
279 chunk_remain = 4;
280 data = 0;
d129bceb 281
a406f5a3
PO		 282 bytes = 0;
283 buffer = sdhci_kmap_sg(host) + host->offset;
d129bceb 284
a406f5a3
PO		 285 while (blksize) {
286 size = min(host->size, host->remain);
287 size = min(size, chunk_remain);
288
289 chunk_remain -= size;
290 blksize -= size;
d129bceb
PO		 291 host->offset += size;
292 host->remain -= size;
d129bceb 293 host->size -= size;
a406f5a3
PO		 294 while (size) {
295 data >>= 8;
296 data |= (u32)*buffer << 24;
297 buffer++;
298 size--;
299 }
300
301 if (chunk_remain == 0) {
302 writel(data, host->ioaddr + SDHCI_BUFFER);
303 chunk_remain = min(blksize, 4);
304 }
d129bceb
PO		 305
306 if (host->remain == 0) {
307 sdhci_kunmap_sg(host);
308 if (sdhci_next_sg(host) == 0) {
a406f5a3 309 BUG_ON(blksize != 0);
d129bceb
PO		 310 return;
311 }
312 buffer = sdhci_kmap_sg(host);
313 }
314 }
315
316 sdhci_kunmap_sg(host);
a406f5a3
PO		 317}
318
319static void sdhci_transfer_pio(struct sdhci_host *host)
320{
321 u32 mask;
322
323 BUG_ON(!host->data);
324
325 if (host->size == 0)
326 return;
327
328 if (host->data->flags & MMC_DATA_READ)
329 mask = SDHCI_DATA_AVAILABLE;
330 else
331 mask = SDHCI_SPACE_AVAILABLE;
332
333 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
334 if (host->data->flags & MMC_DATA_READ)
335 sdhci_read_block_pio(host);
336 else
337 sdhci_write_block_pio(host);
d129bceb 338
a406f5a3
PO		 339 if (host->size == 0)
340 break;
341
342 BUG_ON(host->num_sg == 0);
343 }
d129bceb 344
a406f5a3 345 DBG("PIO transfer complete.\n");
d129bceb
PO		 346}
347
348static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
349{
1c8cde92
PO		 350 u8 count;
351 unsigned target_timeout, current_timeout;
d129bceb
PO		 352
353 WARN_ON(host->data);
354
c7fa9963 355 if (data == NULL)
d129bceb 356 return;
d129bceb
PO		 357
358 DBG("blksz %04x blks %04x flags %08x\n",
a3fd4a1b 359 data->blksz, data->blocks, data->flags);
d129bceb
PO		 360 DBG("tsac %d ms nsac %d clk\n",
361 data->timeout_ns / 1000000, data->timeout_clks);
362
bab76961
PO		 363 /* Sanity checks */
364 BUG_ON(data->blksz * data->blocks > 524288);
1d676e02
PO		 365 BUG_ON(data->blksz > host->max_block);
366 BUG_ON(data->blocks > 65535);
d129bceb 367
1c8cde92
PO		 368 /* timeout in us */
369 target_timeout = data->timeout_ns / 1000 +
370 data->timeout_clks / host->clock;
d129bceb 371
1c8cde92
PO		 372 /*
373 * Figure out needed cycles.
374 * We do this in steps in order to fit inside a 32 bit int.
375 * The first step is the minimum timeout, which will have a
376 * minimum resolution of 6 bits:
377 * (1) 2^13*1000 > 2^22,
378 * (2) host->timeout_clk < 2^16
379 * =>
380 * (1) / (2) > 2^6
381 */
382 count = 0;
383 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
384 while (current_timeout < target_timeout) {
385 count++;
386 current_timeout <<= 1;
387 if (count >= 0xF)
388 break;
389 }
390
391 if (count >= 0xF) {
392 printk(KERN_WARNING "%s: Too large timeout requested!\n",
393 mmc_hostname(host->mmc));
394 count = 0xE;
395 }
396
397 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb
PO		 398
399 if (host->flags & SDHCI_USE_DMA) {
400 int count;
401
402 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
403 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
404 BUG_ON(count != 1);
405
406 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
407 } else {
a3fd4a1b 408 host->size = data->blksz * data->blocks;
d129bceb
PO		 409
410 host->cur_sg = data->sg;
411 host->num_sg = data->sg_len;
412
413 host->offset = 0;
414 host->remain = host->cur_sg->length;
415 }
c7fa9963 416
bab76961
PO		 417 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
418 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
419 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 420 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
421}
422
423static void sdhci_set_transfer_mode(struct sdhci_host *host,
424 struct mmc_data *data)
425{
426 u16 mode;
427
428 WARN_ON(host->data);
429
430 if (data == NULL)
431 return;
432
433 mode = SDHCI_TRNS_BLK_CNT_EN;
434 if (data->blocks > 1)
435 mode |= SDHCI_TRNS_MULTI;
436 if (data->flags & MMC_DATA_READ)
437 mode |= SDHCI_TRNS_READ;
438 if (host->flags & SDHCI_USE_DMA)
439 mode |= SDHCI_TRNS_DMA;
440
441 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 442}
443
444static void sdhci_finish_data(struct sdhci_host *host)
445{
446 struct mmc_data *data;
d129bceb
PO		 447 u16 blocks;
448
449 BUG_ON(!host->data);
450
451 data = host->data;
452 host->data = NULL;
453
454 if (host->flags & SDHCI_USE_DMA) {
455 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
456 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
d129bceb
PO		 457 }
458
459 /*
460 * Controller doesn't count down when in single block mode.
461 */
462 if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
463 blocks = 0;
464 else
465 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
a3fd4a1b 466 data->bytes_xfered = data->blksz * (data->blocks - blocks);
d129bceb
PO		 467
468 if ((data->error == MMC_ERR_NONE) && blocks) {
469 printk(KERN_ERR "%s: Controller signalled completion even "
470 "though there were blocks left. Please report this "
471 "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
472 data->error = MMC_ERR_FAILED;
4cca56c5 473 } else if (host->size != 0) {
d129bceb
PO		 474 printk(KERN_ERR "%s: %d bytes were left untransferred. "
475 "Please report this to " BUGMAIL ".\n",
476 mmc_hostname(host->mmc), host->size);
477 data->error = MMC_ERR_FAILED;
478 }
479
480 DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
481
482 if (data->stop) {
483 /*
484 * The controller needs a reset of internal state machines
485 * upon error conditions.
486 */
487 if (data->error != MMC_ERR_NONE) {
488 sdhci_reset(host, SDHCI_RESET_CMD);
489 sdhci_reset(host, SDHCI_RESET_DATA);
490 }
491
492 sdhci_send_command(host, data->stop);
493 } else
494 tasklet_schedule(&host->finish_tasklet);
495}
496
497static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
498{
499 int flags;
fd2208d7 500 u32 mask;
7cb2c76f 501 unsigned long timeout;
d129bceb
PO		 502
503 WARN_ON(host->cmd);
504
505 DBG("Sending cmd (%x)\n", cmd->opcode);
506
507 /* Wait max 10 ms */
7cb2c76f 508 timeout = 10;
fd2208d7
PO		 509
510 mask = SDHCI_CMD_INHIBIT;
511 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
512 mask |= SDHCI_DATA_INHIBIT;
513
514 /* We shouldn't wait for data inihibit for stop commands, even
515 though they might use busy signaling */
516 if (host->mrq->data && (cmd == host->mrq->data->stop))
517 mask &= ~SDHCI_DATA_INHIBIT;
518
519 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 520 if (timeout == 0) {
d129bceb 521 printk(KERN_ERR "%s: Controller never released "
fd2208d7 522 "inhibit bit(s). Please report this to "
d129bceb
PO		 523 BUGMAIL ".\n", mmc_hostname(host->mmc));
524 sdhci_dumpregs(host);
525 cmd->error = MMC_ERR_FAILED;
526 tasklet_schedule(&host->finish_tasklet);
527 return;
528 }
7cb2c76f
PO		 529 timeout--;
530 mdelay(1);
531 }
d129bceb
PO		 532
533 mod_timer(&host->timer, jiffies + 10 * HZ);
534
535 host->cmd = cmd;
536
537 sdhci_prepare_data(host, cmd->data);
538
539 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
540
c7fa9963
PO		 541 sdhci_set_transfer_mode(host, cmd->data);
542
d129bceb
PO		 543 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
544 printk(KERN_ERR "%s: Unsupported response type! "
545 "Please report this to " BUGMAIL ".\n",
546 mmc_hostname(host->mmc));
547 cmd->error = MMC_ERR_INVALID;
548 tasklet_schedule(&host->finish_tasklet);
549 return;
550 }
551
552 if (!(cmd->flags & MMC_RSP_PRESENT))
553 flags = SDHCI_CMD_RESP_NONE;
554 else if (cmd->flags & MMC_RSP_136)
555 flags = SDHCI_CMD_RESP_LONG;
556 else if (cmd->flags & MMC_RSP_BUSY)
557 flags = SDHCI_CMD_RESP_SHORT_BUSY;
558 else
559 flags = SDHCI_CMD_RESP_SHORT;
560
561 if (cmd->flags & MMC_RSP_CRC)
562 flags |= SDHCI_CMD_CRC;
563 if (cmd->flags & MMC_RSP_OPCODE)
564 flags |= SDHCI_CMD_INDEX;
565 if (cmd->data)
566 flags |= SDHCI_CMD_DATA;
567
fb61e289 568 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 569 host->ioaddr + SDHCI_COMMAND);
570}
571
572static void sdhci_finish_command(struct sdhci_host *host)
573{
574 int i;
575
576 BUG_ON(host->cmd == NULL);
577
578 if (host->cmd->flags & MMC_RSP_PRESENT) {
579 if (host->cmd->flags & MMC_RSP_136) {
580 /* CRC is stripped so we need to do some shifting. */
581 for (i = 0;i < 4;i++) {
582 host->cmd->resp[i] = readl(host->ioaddr +
583 SDHCI_RESPONSE + (3-i)*4) << 8;
584 if (i != 3)
585 host->cmd->resp[i] |=
586 readb(host->ioaddr +
587 SDHCI_RESPONSE + (3-i)*4-1);
588 }
589 } else {
590 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
591 }
592 }
593
594 host->cmd->error = MMC_ERR_NONE;
595
596 DBG("Ending cmd (%x)\n", host->cmd->opcode);
597
3192a28f 598 if (host->cmd->data)
d129bceb 599 host->data = host->cmd->data;
3192a28f 600 else
d129bceb
PO		 601 tasklet_schedule(&host->finish_tasklet);
602
603 host->cmd = NULL;
604}
605
606static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
607{
608 int div;
609 u16 clk;
7cb2c76f 610 unsigned long timeout;
d129bceb
PO		 611
612 if (clock == host->clock)
613 return;
614
615 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
616
617 if (clock == 0)
618 goto out;
619
620 for (div = 1;div < 256;div *= 2) {
621 if ((host->max_clk / div) <= clock)
622 break;
623 }
624 div >>= 1;
625
626 clk = div << SDHCI_DIVIDER_SHIFT;
627 clk |= SDHCI_CLOCK_INT_EN;
628 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
629
630 /* Wait max 10 ms */
7cb2c76f
PO		 631 timeout = 10;
632 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
633 & SDHCI_CLOCK_INT_STABLE)) {
634 if (timeout == 0) {
d129bceb
PO		 635 printk(KERN_ERR "%s: Internal clock never stabilised. "
636 "Please report this to " BUGMAIL ".\n",
637 mmc_hostname(host->mmc));
638 sdhci_dumpregs(host);
639 return;
640 }
7cb2c76f
PO		 641 timeout--;
642 mdelay(1);
643 }
d129bceb
PO		 644
645 clk |= SDHCI_CLOCK_CARD_EN;
646 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
647
648out:
649 host->clock = clock;
650}
651
146ad66e
PO		 652static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
653{
654 u8 pwr;
655
656 if (host->power == power)
657 return;
658
659 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
660
661 if (power == (unsigned short)-1)
662 goto out;
663
664 pwr = SDHCI_POWER_ON;
665
666 switch (power) {
667 case MMC_VDD_170:
668 case MMC_VDD_180:
669 case MMC_VDD_190:
670 pwr |= SDHCI_POWER_180;
671 break;
672 case MMC_VDD_290:
673 case MMC_VDD_300:
674 case MMC_VDD_310:
675 pwr |= SDHCI_POWER_300;
676 break;
677 case MMC_VDD_320:
678 case MMC_VDD_330:
679 case MMC_VDD_340:
680 pwr |= SDHCI_POWER_330;
681 break;
682 default:
683 BUG();
684 }
685
686 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
687
688out:
689 host->power = power;
690}
691
d129bceb
PO		 692/*****************************************************************************\
693 * *
694 * MMC callbacks *
695 * *
696\*****************************************************************************/
697
698static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
699{
700 struct sdhci_host *host;
701 unsigned long flags;
702
703 host = mmc_priv(mmc);
704
705 spin_lock_irqsave(&host->lock, flags);
706
707 WARN_ON(host->mrq != NULL);
708
709 sdhci_activate_led(host);
710
711 host->mrq = mrq;
712
713 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
714 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
715 tasklet_schedule(&host->finish_tasklet);
716 } else
717 sdhci_send_command(host, mrq->cmd);
718
719 spin_unlock_irqrestore(&host->lock, flags);
720}
721
722static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
723{
724 struct sdhci_host *host;
725 unsigned long flags;
726 u8 ctrl;
727
728 host = mmc_priv(mmc);
729
730 spin_lock_irqsave(&host->lock, flags);
731
d129bceb
PO		 732 /*
733 * Reset the chip on each power off.
734 * Should clear out any weird states.
735 */
736 if (ios->power_mode == MMC_POWER_OFF) {
737 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 738 sdhci_init(host);
d129bceb
PO		 739 }
740
741 sdhci_set_clock(host, ios->clock);
742
743 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 744 sdhci_set_power(host, -1);
d129bceb 745 else
146ad66e 746 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 747
748 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
749 if (ios->bus_width == MMC_BUS_WIDTH_4)
750 ctrl |= SDHCI_CTRL_4BITBUS;
751 else
752 ctrl &= ~SDHCI_CTRL_4BITBUS;
753 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
754
755 spin_unlock_irqrestore(&host->lock, flags);
756}
757
758static int sdhci_get_ro(struct mmc_host *mmc)
759{
760 struct sdhci_host *host;
761 unsigned long flags;
762 int present;
763
764 host = mmc_priv(mmc);
765
766 spin_lock_irqsave(&host->lock, flags);
767
768 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
769
770 spin_unlock_irqrestore(&host->lock, flags);
771
772 return !(present & SDHCI_WRITE_PROTECT);
773}
774
775static struct mmc_host_ops sdhci_ops = {
776 .request = sdhci_request,
777 .set_ios = sdhci_set_ios,
778 .get_ro = sdhci_get_ro,
779};
780
781/*****************************************************************************\
782 * *
783 * Tasklets *
784 * *
785\*****************************************************************************/
786
787static void sdhci_tasklet_card(unsigned long param)
788{
789 struct sdhci_host *host;
790 unsigned long flags;
791
792 host = (struct sdhci_host*)param;
793
794 spin_lock_irqsave(&host->lock, flags);
795
796 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
797 if (host->mrq) {
798 printk(KERN_ERR "%s: Card removed during transfer!\n",
799 mmc_hostname(host->mmc));
800 printk(KERN_ERR "%s: Resetting controller.\n",
801 mmc_hostname(host->mmc));
802
803 sdhci_reset(host, SDHCI_RESET_CMD);
804 sdhci_reset(host, SDHCI_RESET_DATA);
805
806 host->mrq->cmd->error = MMC_ERR_FAILED;
807 tasklet_schedule(&host->finish_tasklet);
808 }
809 }
810
811 spin_unlock_irqrestore(&host->lock, flags);
812
813 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
814}
815
816static void sdhci_tasklet_finish(unsigned long param)
817{
818 struct sdhci_host *host;
819 unsigned long flags;
820 struct mmc_request *mrq;
821
822 host = (struct sdhci_host*)param;
823
824 spin_lock_irqsave(&host->lock, flags);
825
826 del_timer(&host->timer);
827
828 mrq = host->mrq;
829
830 DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
831
832 /*
833 * The controller needs a reset of internal state machines
834 * upon error conditions.
835 */
836 if ((mrq->cmd->error != MMC_ERR_NONE) ||
837 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
838 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
645289dc
PO		 839
840 /* Some controllers need this kick or reset won't work here */
841 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
842 unsigned int clock;
843
844 /* This is to force an update */
845 clock = host->clock;
846 host->clock = 0;
847 sdhci_set_clock(host, clock);
848 }
849
850 /* Spec says we should do both at the same time, but Ricoh
851 controllers do not like that. */
d129bceb
PO		 852 sdhci_reset(host, SDHCI_RESET_CMD);
853 sdhci_reset(host, SDHCI_RESET_DATA);
854 }
855
856 host->mrq = NULL;
857 host->cmd = NULL;
858 host->data = NULL;
859
860 sdhci_deactivate_led(host);
861
862 spin_unlock_irqrestore(&host->lock, flags);
863
864 mmc_request_done(host->mmc, mrq);
865}
866
867static void sdhci_timeout_timer(unsigned long data)
868{
869 struct sdhci_host *host;
870 unsigned long flags;
871
872 host = (struct sdhci_host*)data;
873
874 spin_lock_irqsave(&host->lock, flags);
875
876 if (host->mrq) {
877 printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
878 "Please report this to " BUGMAIL ".\n",
879 mmc_hostname(host->mmc));
880 sdhci_dumpregs(host);
881
882 if (host->data) {
883 host->data->error = MMC_ERR_TIMEOUT;
884 sdhci_finish_data(host);
885 } else {
886 if (host->cmd)
887 host->cmd->error = MMC_ERR_TIMEOUT;
888 else
889 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
890
891 tasklet_schedule(&host->finish_tasklet);
892 }
893 }
894
895 spin_unlock_irqrestore(&host->lock, flags);
896}
897
898/*****************************************************************************\
899 * *
900 * Interrupt handling *
901 * *
902\*****************************************************************************/
903
904static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
905{
906 BUG_ON(intmask == 0);
907
908 if (!host->cmd) {
909 printk(KERN_ERR "%s: Got command interrupt even though no "
910 "command operation was in progress.\n",
911 mmc_hostname(host->mmc));
912 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
913 mmc_hostname(host->mmc));
914 sdhci_dumpregs(host);
915 return;
916 }
917
918 if (intmask & SDHCI_INT_RESPONSE)
919 sdhci_finish_command(host);
920 else {
921 if (intmask & SDHCI_INT_TIMEOUT)
922 host->cmd->error = MMC_ERR_TIMEOUT;
923 else if (intmask & SDHCI_INT_CRC)
924 host->cmd->error = MMC_ERR_BADCRC;
925 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
926 host->cmd->error = MMC_ERR_FAILED;
927 else
928 host->cmd->error = MMC_ERR_INVALID;
929
930 tasklet_schedule(&host->finish_tasklet);
931 }
932}
933
934static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
935{
936 BUG_ON(intmask == 0);
937
938 if (!host->data) {
939 /*
940 * A data end interrupt is sent together with the response
941 * for the stop command.
942 */
943 if (intmask & SDHCI_INT_DATA_END)
944 return;
945
946 printk(KERN_ERR "%s: Got data interrupt even though no "
947 "data operation was in progress.\n",
948 mmc_hostname(host->mmc));
949 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
950 mmc_hostname(host->mmc));
951 sdhci_dumpregs(host);
952
953 return;
954 }
955
956 if (intmask & SDHCI_INT_DATA_TIMEOUT)
957 host->data->error = MMC_ERR_TIMEOUT;
958 else if (intmask & SDHCI_INT_DATA_CRC)
959 host->data->error = MMC_ERR_BADCRC;
960 else if (intmask & SDHCI_INT_DATA_END_BIT)
961 host->data->error = MMC_ERR_FAILED;
962
963 if (host->data->error != MMC_ERR_NONE)
964 sdhci_finish_data(host);
965 else {
a406f5a3 966 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 967 sdhci_transfer_pio(host);
968
969 if (intmask & SDHCI_INT_DATA_END)
970 sdhci_finish_data(host);
971 }
972}
973
974static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
975{
976 irqreturn_t result;
977 struct sdhci_host* host = dev_id;
978 u32 intmask;
979
980 spin_lock(&host->lock);
981
982 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
983
984 if (!intmask) {
985 result = IRQ_NONE;
986 goto out;
987 }
988
989 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
990
3192a28f
PO		 991 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
992 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
993 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 994 tasklet_schedule(&host->card_tasklet);
3192a28f 995 }
d129bceb 996
3192a28f 997 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 998
3192a28f 999 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1000 writel(intmask & SDHCI_INT_CMD_MASK,
1001 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1002 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1003 }
1004
1005 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1006 writel(intmask & SDHCI_INT_DATA_MASK,
1007 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1008 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1009 }
1010
1011 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1012
d129bceb 1013 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1014 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1015 mmc_hostname(host->mmc));
3192a28f 1016 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1017 }
1018
3192a28f
PO		 1019 intmask &= SDHCI_INT_BUS_POWER;
1020
1021 if (intmask) {
1022 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
d129bceb 1023 "report this to " BUGMAIL ".\n",
3192a28f 1024 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1025 sdhci_dumpregs(host);
1026
d129bceb 1027 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1028 }
d129bceb
PO		 1029
1030 result = IRQ_HANDLED;
1031
1032out:
1033 spin_unlock(&host->lock);
1034
1035 return result;
1036}
1037
1038/*****************************************************************************\
1039 * *
1040 * Suspend/resume *
1041 * *
1042\*****************************************************************************/
1043
1044#ifdef CONFIG_PM
1045
1046static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1047{
1048 struct sdhci_chip *chip;
1049 int i, ret;
1050
1051 chip = pci_get_drvdata(pdev);
1052 if (!chip)
1053 return 0;
1054
1055 DBG("Suspending...\n");
1056
1057 for (i = 0;i < chip->num_slots;i++) {
1058 if (!chip->hosts[i])
1059 continue;
1060 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1061 if (ret) {
1062 for (i--;i >= 0;i--)
1063 mmc_resume_host(chip->hosts[i]->mmc);
1064 return ret;
1065 }
1066 }
1067
1068 pci_save_state(pdev);
1069 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1070 pci_disable_device(pdev);
1071 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1072
1073 return 0;
1074}
1075
1076static int sdhci_resume (struct pci_dev *pdev)
1077{
1078 struct sdhci_chip *chip;
1079 int i, ret;
1080
1081 chip = pci_get_drvdata(pdev);
1082 if (!chip)
1083 return 0;
1084
1085 DBG("Resuming...\n");
1086
1087 pci_set_power_state(pdev, PCI_D0);
1088 pci_restore_state(pdev);
1089 pci_enable_device(pdev);
1090
1091 for (i = 0;i < chip->num_slots;i++) {
1092 if (!chip->hosts[i])
1093 continue;
1094 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1095 pci_set_master(pdev);
1096 sdhci_init(chip->hosts[i]);
1097 ret = mmc_resume_host(chip->hosts[i]->mmc);
1098 if (ret)
1099 return ret;
1100 }
1101
1102 return 0;
1103}
1104
1105#else /* CONFIG_PM */
1106
1107#define sdhci_suspend NULL
1108#define sdhci_resume NULL
1109
1110#endif /* CONFIG_PM */
1111
1112/*****************************************************************************\
1113 * *
1114 * Device probing/removal *
1115 * *
1116\*****************************************************************************/
1117
1118static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1119{
1120 int ret;
4a965505 1121 unsigned int version;
d129bceb
PO		 1122 struct sdhci_chip *chip;
1123 struct mmc_host *mmc;
1124 struct sdhci_host *host;
1125
1126 u8 first_bar;
1127 unsigned int caps;
1128
1129 chip = pci_get_drvdata(pdev);
1130 BUG_ON(!chip);
1131
1132 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1133 if (ret)
1134 return ret;
1135
1136 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1137
1138 if (first_bar > 5) {
1139 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1140 return -ENODEV;
1141 }
1142
1143 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1144 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1145 return -ENODEV;
1146 }
1147
1148 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1149 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
1150 return -ENODEV;
1151 }
1152
67435274
PO		 1153 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1154 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1155 return -ENODEV;
1156 }
1157
1158 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1159 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1160 return -ENODEV;
1161 }
1162
d129bceb
PO		 1163 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1164 if (!mmc)
1165 return -ENOMEM;
1166
1167 host = mmc_priv(mmc);
1168 host->mmc = mmc;
1169
1170 host->bar = first_bar + slot;
1171
1172 host->addr = pci_resource_start(pdev, host->bar);
1173 host->irq = pdev->irq;
1174
1175 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1176
1177 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1178
1179 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1180 if (ret)
1181 goto free;
1182
1183 host->ioaddr = ioremap_nocache(host->addr,
1184 pci_resource_len(pdev, host->bar));
1185 if (!host->ioaddr) {
1186 ret = -ENOMEM;
1187 goto release;
1188 }
1189
d96649ed
PO		 1190 sdhci_reset(host, SDHCI_RESET_ALL);
1191
4a965505
PO		 1192 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1193 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1194 if (version != 0) {
1195 printk(KERN_ERR "%s: Unknown controller version (%d). "
8b1b2185 1196 "You may experience problems.\n", host->slot_descr,
4a965505 1197 version);
4a965505
PO		 1198 }
1199
d129bceb
PO		 1200 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1201
67435274
PO		 1202 if (debug_nodma)
1203 DBG("DMA forced off\n");
1204 else if (debug_forcedma) {
1205 DBG("DMA forced on\n");
1206 host->flags |= SDHCI_USE_DMA;
98608076
PO		 1207 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1208 host->flags |= SDHCI_USE_DMA;
1209 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
67435274
PO		 1210 DBG("Controller doesn't have DMA interface\n");
1211 else if (!(caps & SDHCI_CAN_DO_DMA))
1212 DBG("Controller doesn't have DMA capability\n");
1213 else
d129bceb
PO		 1214 host->flags |= SDHCI_USE_DMA;
1215
1216 if (host->flags & SDHCI_USE_DMA) {
1217 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1218 printk(KERN_WARNING "%s: No suitable DMA available. "
1219 "Falling back to PIO.\n", host->slot_descr);
1220 host->flags &= ~SDHCI_USE_DMA;
1221 }
1222 }
1223
1224 if (host->flags & SDHCI_USE_DMA)
1225 pci_set_master(pdev);
1226 else /* XXX: Hack to get MMC layer to avoid highmem */
1227 pdev->dma_mask = 0;
1228
8ef1a143
PO		 1229 host->max_clk =
1230 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1231 if (host->max_clk == 0) {
1232 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1233 "frequency.\n", host->slot_descr);
1234 ret = -ENODEV;
1235 goto unmap;
1236 }
d129bceb
PO		 1237 host->max_clk *= 1000000;
1238
1c8cde92
PO		 1239 host->timeout_clk =
1240 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1241 if (host->timeout_clk == 0) {
1242 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1243 "frequency.\n", host->slot_descr);
1244 ret = -ENODEV;
1245 goto unmap;
1246 }
1247 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1248 host->timeout_clk *= 1000;
d129bceb 1249
1d676e02
PO		 1250 host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1251 if (host->max_block >= 3) {
1252 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1253 host->slot_descr);
1254 ret = -ENODEV;
1255 goto unmap;
1256 }
1257 host->max_block = 512 << host->max_block;
1258
d129bceb
PO		 1259 /*
1260 * Set host parameters.
1261 */
1262 mmc->ops = &sdhci_ops;
1263 mmc->f_min = host->max_clk / 256;
1264 mmc->f_max = host->max_clk;
42431acb 1265 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
d129bceb 1266
146ad66e
PO		 1267 mmc->ocr_avail = 0;
1268 if (caps & SDHCI_CAN_VDD_330)
1269 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1270 else if (caps & SDHCI_CAN_VDD_300)
1271 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1272 else if (caps & SDHCI_CAN_VDD_180)
1273 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
1274
1275 if (mmc->ocr_avail == 0) {
1276 printk(KERN_ERR "%s: Hardware doesn't report any "
1277 "support voltages.\n", host->slot_descr);
1278 ret = -ENODEV;
1279 goto unmap;
1280 }
1281
d129bceb
PO		 1282 spin_lock_init(&host->lock);
1283
1284 /*
1285 * Maximum number of segments. Hardware cannot do scatter lists.
1286 */
1287 if (host->flags & SDHCI_USE_DMA)
1288 mmc->max_hw_segs = 1;
1289 else
1290 mmc->max_hw_segs = 16;
1291 mmc->max_phys_segs = 16;
1292
1293 /*
bab76961
PO		 1294 * Maximum number of sectors in one transfer. Limited by DMA boundary
1295 * size (512KiB), which means (512 KiB/512=) 1024 entries.
d129bceb 1296 */
bab76961 1297 mmc->max_sectors = 1024;
d129bceb
PO		 1298
1299 /*
1300 * Maximum segment size. Could be one segment with the maximum number
1301 * of sectors.
1302 */
1303 mmc->max_seg_size = mmc->max_sectors * 512;
1304
1305 /*
1306 * Init tasklets.
1307 */
1308 tasklet_init(&host->card_tasklet,
1309 sdhci_tasklet_card, (unsigned long)host);
1310 tasklet_init(&host->finish_tasklet,
1311 sdhci_tasklet_finish, (unsigned long)host);
1312
e474c66b 1313 setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
d129bceb 1314
dace1453 1315 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
d129bceb
PO		 1316 host->slot_descr, host);
1317 if (ret)
8ef1a143 1318 goto untasklet;
d129bceb
PO		 1319
1320 sdhci_init(host);
1321
1322#ifdef CONFIG_MMC_DEBUG
1323 sdhci_dumpregs(host);
1324#endif
1325
1326 host->chip = chip;
1327 chip->hosts[slot] = host;
1328
1329 mmc_add_host(mmc);
1330
1331 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1332 host->addr, host->irq,
1333 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1334
1335 return 0;
1336
8ef1a143 1337untasklet:
d129bceb
PO		 1338 tasklet_kill(&host->card_tasklet);
1339 tasklet_kill(&host->finish_tasklet);
8ef1a143 1340unmap:
d129bceb
PO		 1341 iounmap(host->ioaddr);
1342release:
1343 pci_release_region(pdev, host->bar);
1344free:
1345 mmc_free_host(mmc);
1346
1347 return ret;
1348}
1349
1350static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1351{
1352 struct sdhci_chip *chip;
1353 struct mmc_host *mmc;
1354 struct sdhci_host *host;
1355
1356 chip = pci_get_drvdata(pdev);
1357 host = chip->hosts[slot];
1358 mmc = host->mmc;
1359
1360 chip->hosts[slot] = NULL;
1361
1362 mmc_remove_host(mmc);
1363
1364 sdhci_reset(host, SDHCI_RESET_ALL);
1365
1366 free_irq(host->irq, host);
1367
1368 del_timer_sync(&host->timer);
1369
1370 tasklet_kill(&host->card_tasklet);
1371 tasklet_kill(&host->finish_tasklet);
1372
1373 iounmap(host->ioaddr);
1374
1375 pci_release_region(pdev, host->bar);
1376
1377 mmc_free_host(mmc);
1378}
1379
1380static int __devinit sdhci_probe(struct pci_dev *pdev,
1381 const struct pci_device_id *ent)
1382{
1383 int ret, i;
51f82bc0 1384 u8 slots, rev;
d129bceb
PO		 1385 struct sdhci_chip *chip;
1386
1387 BUG_ON(pdev == NULL);
1388 BUG_ON(ent == NULL);
1389
51f82bc0
PO		 1390 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1391
1392 printk(KERN_INFO DRIVER_NAME
1393 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1394 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1395 (int)rev);
d129bceb
PO		 1396
1397 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1398 if (ret)
1399 return ret;
1400
1401 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1402 DBG("found %d slot(s)\n", slots);
1403 if (slots == 0)
1404 return -ENODEV;
1405
1406 ret = pci_enable_device(pdev);
1407 if (ret)
1408 return ret;
1409
1410 chip = kzalloc(sizeof(struct sdhci_chip) +
1411 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1412 if (!chip) {
1413 ret = -ENOMEM;
1414 goto err;
1415 }
1416
1417 chip->pdev = pdev;
df673b22
PO		 1418 chip->quirks = ent->driver_data;
1419
1420 if (debug_quirks)
1421 chip->quirks = debug_quirks;
d129bceb
PO		 1422
1423 chip->num_slots = slots;
1424 pci_set_drvdata(pdev, chip);
1425
1426 for (i = 0;i < slots;i++) {
1427 ret = sdhci_probe_slot(pdev, i);
1428 if (ret) {
1429 for (i--;i >= 0;i--)
1430 sdhci_remove_slot(pdev, i);
1431 goto free;
1432 }
1433 }
1434
1435 return 0;
1436
1437free:
1438 pci_set_drvdata(pdev, NULL);
1439 kfree(chip);
1440
1441err:
1442 pci_disable_device(pdev);
1443 return ret;
1444}
1445
1446static void __devexit sdhci_remove(struct pci_dev *pdev)
1447{
1448 int i;
1449 struct sdhci_chip *chip;
1450
1451 chip = pci_get_drvdata(pdev);
1452
1453 if (chip) {
1454 for (i = 0;i < chip->num_slots;i++)
1455 sdhci_remove_slot(pdev, i);
1456
1457 pci_set_drvdata(pdev, NULL);
1458
1459 kfree(chip);
1460 }
1461
1462 pci_disable_device(pdev);
1463}
1464
1465static struct pci_driver sdhci_driver = {
1466 .name = DRIVER_NAME,
1467 .id_table = pci_ids,
1468 .probe = sdhci_probe,
1469 .remove = __devexit_p(sdhci_remove),
1470 .suspend = sdhci_suspend,
1471 .resume = sdhci_resume,
1472};
1473
1474/*****************************************************************************\
1475 * *
1476 * Driver init/exit *
1477 * *
1478\*****************************************************************************/
1479
1480static int __init sdhci_drv_init(void)
1481{
1482 printk(KERN_INFO DRIVER_NAME
1483 ": Secure Digital Host Controller Interface driver, "
1484 DRIVER_VERSION "\n");
1485 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1486
1487 return pci_register_driver(&sdhci_driver);
1488}
1489
1490static void __exit sdhci_drv_exit(void)
1491{
1492 DBG("Exiting\n");
1493
1494 pci_unregister_driver(&sdhci_driver);
1495}
1496
1497module_init(sdhci_drv_init);
1498module_exit(sdhci_drv_exit);
1499
67435274
PO		 1500module_param(debug_nodma, uint, 0444);
1501module_param(debug_forcedma, uint, 0444);
df673b22 1502module_param(debug_quirks, uint, 0444);
67435274 1503
d129bceb
PO		 1504MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1505MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1506MODULE_VERSION(DRIVER_VERSION);
1507MODULE_LICENSE("GPL");
67435274
PO		 1508
1509MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1510MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
df673b22 1511MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux kernel - Deliverables
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