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V4L/DVB (5101): Renamed video_mux to cx88_video_mux
[deliverable/linux.git] / drivers / mmc / tifm_sd.c
CommitLineData
4020f2d7
AD		 1/*
2 * tifm_sd.c - TI FlashMedia driver
3 *
4 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12
13#include <linux/tifm.h>
14#include <linux/mmc/protocol.h>
15#include <linux/mmc/host.h>
16#include <linux/highmem.h>
2099c99e 17#include <asm/io.h>
4020f2d7
AD		 18
19#define DRIVER_NAME "tifm_sd"
1289335a 20#define DRIVER_VERSION "0.7"
4020f2d7
AD		 21
22static int no_dma = 0;
23static int fixed_timeout = 0;
24module_param(no_dma, bool, 0644);
25module_param(fixed_timeout, bool, 0644);
26
27/* Constants here are mostly from OMAP5912 datasheet */
28#define TIFM_MMCSD_RESET 0x0002
29#define TIFM_MMCSD_CLKMASK 0x03ff
30#define TIFM_MMCSD_POWER 0x0800
31#define TIFM_MMCSD_4BBUS 0x8000
32#define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
33#define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
34#define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
35#define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
36#define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
37#define TIFM_MMCSD_READ 0x8000
38
12c83452
AD		 39#define TIFM_MMCSD_DATAMASK 0x401d /* set bits: CERR, EOFB, BRS, CB, EOC */
40#define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
4020f2d7
AD		 41#define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
42#define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
43#define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
44#define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
45#define TIFM_MMCSD_DTO 0x0020 /* data time-out */
46#define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
47#define TIFM_MMCSD_CTO 0x0080 /* command time-out */
48#define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
49#define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
50#define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
51#define TIFM_MMCSD_CERR 0x4000 /* card status error */
52
53#define TIFM_MMCSD_FIFO_SIZE 0x0020
54
55#define TIFM_MMCSD_RSP_R0 0x0000
56#define TIFM_MMCSD_RSP_R1 0x0100
57#define TIFM_MMCSD_RSP_R2 0x0200
58#define TIFM_MMCSD_RSP_R3 0x0300
59#define TIFM_MMCSD_RSP_R4 0x0400
60#define TIFM_MMCSD_RSP_R5 0x0500
61#define TIFM_MMCSD_RSP_R6 0x0600
62
63#define TIFM_MMCSD_RSP_BUSY 0x0800
64
65#define TIFM_MMCSD_CMD_BC 0x0000
66#define TIFM_MMCSD_CMD_BCR 0x1000
67#define TIFM_MMCSD_CMD_AC 0x2000
68#define TIFM_MMCSD_CMD_ADTC 0x3000
69
70typedef enum {
71 IDLE = 0,
72 CMD, /* main command ended */
73 BRS, /* block transfer finished */
74 SCMD, /* stop command ended */
75 CARD, /* card left busy state */
76 FIFO, /* FIFO operation completed (uncertain) */
77 READY
78} card_state_t;
79
80enum {
81 FIFO_RDY = 0x0001, /* hardware dependent value */
4020f2d7
AD		 82 EJECT = 0x0004,
83 EJECT_DONE = 0x0008,
84 CARD_BUSY = 0x0010,
85 OPENDRAIN = 0x0040, /* hardware dependent value */
86 CARD_EVENT = 0x0100, /* hardware dependent value */
87 CARD_RO = 0x0200, /* hardware dependent value */
88 FIFO_EVENT = 0x10000 }; /* hardware dependent value */
89
90struct tifm_sd {
91 struct tifm_dev *dev;
92
93 unsigned int flags;
94 card_state_t state;
95 unsigned int clk_freq;
96 unsigned int clk_div;
0803dd0c 97 unsigned long timeout_jiffies;
4020f2d7 98
8e02f858 99 struct tasklet_struct finish_tasklet;
0803dd0c 100 struct timer_list timer;
4020f2d7 101 struct mmc_request *req;
8e02f858 102 wait_queue_head_t notify;
4020f2d7
AD		 103
104 size_t written_blocks;
4020f2d7
AD		 105 size_t buffer_size;
106 size_t buffer_pos;
107
108};
109
f9d429a2 110static char* tifm_sd_data_buffer(struct mmc_data *data)
255ef22e 111{
f9d429a2 112 return page_address(data->sg->page) + data->sg->offset;
255ef22e
AD		 113}
114
4020f2d7 115static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
2e8ce5e7 116 unsigned int host_status)
4020f2d7
AD		 117{
118 struct mmc_command *cmd = host->req->cmd;
119 unsigned int t_val = 0, cnt = 0;
255ef22e 120 char *buffer;
4020f2d7
AD		 121
122 if (host_status & TIFM_MMCSD_BRS) {
123 /* in non-dma rx mode BRS fires when fifo is still not empty */
255ef22e 124 if (no_dma && (cmd->data->flags & MMC_DATA_READ)) {
f9d429a2 125 buffer = tifm_sd_data_buffer(host->req->data);
4020f2d7
AD		 126 while (host->buffer_size > host->buffer_pos) {
127 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
255ef22e
AD		 128 buffer[host->buffer_pos++] = t_val & 0xff;
129 buffer[host->buffer_pos++] =
4020f2d7
AD		 130 (t_val >> 8) & 0xff;
131 }
132 }
133 return 1;
255ef22e 134 } else if (no_dma) {
f9d429a2 135 buffer = tifm_sd_data_buffer(host->req->data);
4020f2d7
AD		 136 if ((cmd->data->flags & MMC_DATA_READ) &&
137 (host_status & TIFM_MMCSD_AF)) {
138 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
139 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
140 if (host->buffer_size > host->buffer_pos) {
255ef22e 141 buffer[host->buffer_pos++] =
4020f2d7 142 t_val & 0xff;
255ef22e 143 buffer[host->buffer_pos++] =
4020f2d7
AD		 144 (t_val >> 8) & 0xff;
145 }
146 }
147 } else if ((cmd->data->flags & MMC_DATA_WRITE)
148 && (host_status & TIFM_MMCSD_AE)) {
149 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
150 if (host->buffer_size > host->buffer_pos) {
255ef22e
AD		 151 t_val = buffer[host->buffer_pos++]
152 & 0x00ff;
153 t_val |= ((buffer[host->buffer_pos++])
154 << 8) & 0xff00;
4020f2d7 155 writel(t_val,
2e8ce5e7 156 sock->addr + SOCK_MMCSD_DATA);
4020f2d7
AD		 157 }
158 }
159 }
160 }
161 return 0;
162}
163
164static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
165{
166 unsigned int rc = 0;
167
168 switch (mmc_resp_type(cmd)) {
169 case MMC_RSP_NONE:
170 rc |= TIFM_MMCSD_RSP_R0;
171 break;
172 case MMC_RSP_R1B:
173 rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
174 case MMC_RSP_R1:
175 rc |= TIFM_MMCSD_RSP_R1;
176 break;
177 case MMC_RSP_R2:
178 rc |= TIFM_MMCSD_RSP_R2;
179 break;
180 case MMC_RSP_R3:
181 rc |= TIFM_MMCSD_RSP_R3;
182 break;
4020f2d7
AD		 183 default:
184 BUG();
185 }
186
187 switch (mmc_cmd_type(cmd)) {
188 case MMC_CMD_BC:
189 rc |= TIFM_MMCSD_CMD_BC;
190 break;
191 case MMC_CMD_BCR:
192 rc |= TIFM_MMCSD_CMD_BCR;
193 break;
194 case MMC_CMD_AC:
195 rc |= TIFM_MMCSD_CMD_AC;
196 break;
197 case MMC_CMD_ADTC:
198 rc |= TIFM_MMCSD_CMD_ADTC;
199 break;
200 default:
201 BUG();
202 }
203 return rc;
204}
205
206static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
207{
208 struct tifm_dev *sock = host->dev;
209 unsigned int cmd_mask = tifm_sd_op_flags(cmd) |
210 (host->flags & OPENDRAIN);
211
212 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
213 cmd_mask |= TIFM_MMCSD_READ;
214
215 dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
2e8ce5e7 216 cmd->opcode, cmd->arg, cmd_mask);
4020f2d7
AD		 217
218 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
219 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
220 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
221}
222
223static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
224{
225 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
226 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
227 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
228 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
229 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
230 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
231 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
232 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
233}
234
235static void tifm_sd_process_cmd(struct tifm_dev *sock, struct tifm_sd *host,
236 unsigned int host_status)
237{
238 struct mmc_command *cmd = host->req->cmd;
239
240change_state:
241 switch (host->state) {
242 case IDLE:
243 return;
244 case CMD:
12c83452 245 if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
4020f2d7
AD		 246 tifm_sd_fetch_resp(cmd, sock);
247 if (cmd->data) {
248 host->state = BRS;
1289335a 249 } else {
4020f2d7 250 host->state = READY;
1289335a 251 }
4020f2d7
AD		 252 goto change_state;
253 }
254 break;
255 case BRS:
256 if (tifm_sd_transfer_data(sock, host, host_status)) {
1289335a
AD		 257 if (cmd->data->flags & MMC_DATA_WRITE) {
258 host->state = CARD;
259 } else {
260 if (no_dma) {
261 if (host->req->stop) {
262 tifm_sd_exec(host, host->req->stop);
263 host->state = SCMD;
264 } else {
265 host->state = READY;
266 }
4020f2d7 267 } else {
1289335a 268 host->state = FIFO;
4020f2d7 269 }
4020f2d7 270 }
1289335a 271 goto change_state;
4020f2d7
AD		 272 }
273 break;
274 case SCMD:
275 if (host_status & TIFM_MMCSD_EOC) {
276 tifm_sd_fetch_resp(host->req->stop, sock);
1289335a 277 host->state = READY;
4020f2d7
AD		 278 goto change_state;
279 }
280 break;
281 case CARD:
1289335a
AD		 282 dev_dbg(&sock->dev, "waiting for CARD, have %zd blocks\n",
283 host->written_blocks);
4020f2d7
AD		 284 if (!(host->flags & CARD_BUSY)
285 && (host->written_blocks == cmd->data->blocks)) {
1289335a
AD		 286 if (no_dma) {
287 if (host->req->stop) {
288 tifm_sd_exec(host, host->req->stop);
289 host->state = SCMD;
290 } else {
291 host->state = READY;
292 }
293 } else {
294 host->state = FIFO;
295 }
4020f2d7
AD		 296 goto change_state;
297 }
298 break;
299 case FIFO:
300 if (host->flags & FIFO_RDY) {
4020f2d7 301 host->flags &= ~FIFO_RDY;
1289335a
AD		 302 if (host->req->stop) {
303 tifm_sd_exec(host, host->req->stop);
304 host->state = SCMD;
305 } else {
306 host->state = READY;
307 }
4020f2d7
AD		 308 goto change_state;
309 }
310 break;
311 case READY:
8e02f858 312 tasklet_schedule(&host->finish_tasklet);
4020f2d7
AD		 313 return;
314 }
315
4020f2d7
AD		 316}
317
318/* Called from interrupt handler */
50743f4c
AD		 319static void tifm_sd_signal_irq(struct tifm_dev *sock,
320 unsigned int sock_irq_status)
4020f2d7
AD		 321{
322 struct tifm_sd *host;
323 unsigned int host_status = 0, fifo_status = 0;
324 int error_code = 0;
325
326 spin_lock(&sock->lock);
327 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
4020f2d7
AD		 328
329 if (sock_irq_status & FIFO_EVENT) {
330 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
331 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
332
333 host->flags |= fifo_status & FIFO_RDY;
334 }
335
336 if (sock_irq_status & CARD_EVENT) {
337 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
338 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
339
4020f2d7
AD		 340 if (!host->req)
341 goto done;
342
343 if (host_status & TIFM_MMCSD_ERRMASK) {
12c83452 344 if (host_status & (TIFM_MMCSD_CTO | TIFM_MMCSD_DTO))
4020f2d7 345 error_code = MMC_ERR_TIMEOUT;
2e8ce5e7
AD		 346 else if (host_status
347 & (TIFM_MMCSD_CCRC | TIFM_MMCSD_DCRC))
4020f2d7
AD		 348 error_code = MMC_ERR_BADCRC;
349
350 writel(TIFM_FIFO_INT_SETALL,
351 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
352 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
353
354 if (host->req->stop) {
355 if (host->state == SCMD) {
356 host->req->stop->error = error_code;
1289335a
AD		 357 } else if (host->state == BRS
358 || host->state == CARD
359 || host->state == FIFO) {
4020f2d7
AD		 360 host->req->cmd->error = error_code;
361 tifm_sd_exec(host, host->req->stop);
4020f2d7
AD		 362 host->state = SCMD;
363 goto done;
364 } else {
365 host->req->cmd->error = error_code;
366 }
367 } else {
368 host->req->cmd->error = error_code;
369 }
370 host->state = READY;
371 }
372
373 if (host_status & TIFM_MMCSD_CB)
374 host->flags |= CARD_BUSY;
2e8ce5e7
AD		 375 if ((host_status & TIFM_MMCSD_EOFB)
376 && (host->flags & CARD_BUSY)) {
4020f2d7
AD		 377 host->written_blocks++;
378 host->flags &= ~CARD_BUSY;
379 }
380 }
381
382 if (host->req)
383 tifm_sd_process_cmd(sock, host, host_status);
384done:
385 dev_dbg(&sock->dev, "host_status %x, fifo_status %x\n",
2e8ce5e7 386 host_status, fifo_status);
4020f2d7 387 spin_unlock(&sock->lock);
4020f2d7
AD		 388}
389
2e8ce5e7 390static void tifm_sd_prepare_data(struct tifm_sd *host, struct mmc_command *cmd)
4020f2d7 391{
2e8ce5e7 392 struct tifm_dev *sock = host->dev;
4020f2d7
AD		 393 unsigned int dest_cnt;
394
395 /* DMA style IO */
2e8ce5e7
AD		 396 dev_dbg(&sock->dev, "setting dma for %d blocks\n",
397 cmd->data->blocks);
4020f2d7 398 writel(TIFM_FIFO_INT_SETALL,
2e8ce5e7 399 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
f0d1b0b3 400 writel(ilog2(cmd->data->blksz) - 2,
2e8ce5e7 401 sock->addr + SOCK_FIFO_PAGE_SIZE);
4020f2d7
AD		 402 writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
403 writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
404
405 dest_cnt = (cmd->data->blocks) << 8;
406
407 writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
408
409 writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
410 writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
411
412 if (cmd->data->flags & MMC_DATA_WRITE) {
413 writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
414 writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
2e8ce5e7 415 sock->addr + SOCK_DMA_CONTROL);
4020f2d7
AD		 416 } else {
417 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
418 writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
419 }
420}
421
422static void tifm_sd_set_data_timeout(struct tifm_sd *host,
2e8ce5e7 423 struct mmc_data *data)
4020f2d7
AD		 424{
425 struct tifm_dev *sock = host->dev;
426 unsigned int data_timeout = data->timeout_clks;
427
428 if (fixed_timeout)
429 return;
430
431 data_timeout += data->timeout_ns /
83d420ba 432 ((1000000000UL / host->clk_freq) * host->clk_div);
4020f2d7
AD		 433
434 if (data_timeout < 0xffff) {
4020f2d7 435 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 436 writel((~TIFM_MMCSD_DPE)
437 & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
438 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7 439 } else {
4020f2d7 440 data_timeout = (data_timeout >> 10) + 1;
2e8ce5e7 441 if (data_timeout > 0xffff)
4020f2d7
AD		 442 data_timeout = 0; /* set to unlimited */
443 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 444 writel(TIFM_MMCSD_DPE
445 | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
446 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7
AD		 447 }
448}
449
450static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
451{
452 struct tifm_sd *host = mmc_priv(mmc);
453 struct tifm_dev *sock = host->dev;
454 unsigned long flags;
455 int sg_count = 0;
456 struct mmc_data *r_data = mrq->cmd->data;
457
458 spin_lock_irqsave(&sock->lock, flags);
459 if (host->flags & EJECT) {
460 spin_unlock_irqrestore(&sock->lock, flags);
461 goto err_out;
462 }
463
464 if (host->req) {
465 printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
466 spin_unlock_irqrestore(&sock->lock, flags);
467 goto err_out;
468 }
469
470 if (r_data) {
471 tifm_sd_set_data_timeout(host, r_data);
472
473 sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
474 mrq->cmd->flags & MMC_DATA_WRITE
475 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
476 if (sg_count != 1) {
477 printk(KERN_ERR DRIVER_NAME
478 ": scatterlist map failed\n");
479 spin_unlock_irqrestore(&sock->lock, flags);
480 goto err_out;
481 }
482
483 host->written_blocks = 0;
484 host->flags &= ~CARD_BUSY;
485 tifm_sd_prepare_data(host, mrq->cmd);
486 }
487
488 host->req = mrq;
0803dd0c 489 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7 490 host->state = CMD;
4020f2d7 491 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 492 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 493 tifm_sd_exec(host, mrq->cmd);
494 spin_unlock_irqrestore(&sock->lock, flags);
495 return;
496
497err_out:
498 if (sg_count > 0)
499 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
500 (r_data->flags & MMC_DATA_WRITE)
501 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
502
503 mrq->cmd->error = MMC_ERR_TIMEOUT;
504 mmc_request_done(mmc, mrq);
505}
506
8e02f858 507static void tifm_sd_end_cmd(unsigned long data)
4020f2d7 508{
8e02f858 509 struct tifm_sd *host = (struct tifm_sd*)data;
4020f2d7
AD		 510 struct tifm_dev *sock = host->dev;
511 struct mmc_host *mmc = tifm_get_drvdata(sock);
512 struct mmc_request *mrq;
e069d79d 513 struct mmc_data *r_data = NULL;
4020f2d7
AD		 514 unsigned long flags;
515
516 spin_lock_irqsave(&sock->lock, flags);
517
0803dd0c 518 del_timer(&host->timer);
4020f2d7 519 mrq = host->req;
e069d79d 520 host->req = NULL;
4020f2d7
AD		 521 host->state = IDLE;
522
523 if (!mrq) {
524 printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
525 spin_unlock_irqrestore(&sock->lock, flags);
526 return;
527 }
528
529 r_data = mrq->cmd->data;
530 if (r_data) {
531 if (r_data->flags & MMC_DATA_WRITE) {
2e8ce5e7
AD		 532 r_data->bytes_xfered = host->written_blocks
533 * r_data->blksz;
4020f2d7
AD		 534 } else {
535 r_data->bytes_xfered = r_data->blocks -
536 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
537 r_data->bytes_xfered *= r_data->blksz;
538 r_data->bytes_xfered += r_data->blksz -
539 readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
540 }
541 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
542 (r_data->flags & MMC_DATA_WRITE)
543 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
544 }
545
546 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 547 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 548
549 spin_unlock_irqrestore(&sock->lock, flags);
550 mmc_request_done(mmc, mrq);
551}
552
553static void tifm_sd_request_nodma(struct mmc_host *mmc, struct mmc_request *mrq)
554{
555 struct tifm_sd *host = mmc_priv(mmc);
556 struct tifm_dev *sock = host->dev;
557 unsigned long flags;
558 struct mmc_data *r_data = mrq->cmd->data;
4020f2d7
AD		 559
560 spin_lock_irqsave(&sock->lock, flags);
561 if (host->flags & EJECT) {
562 spin_unlock_irqrestore(&sock->lock, flags);
563 goto err_out;
564 }
565
566 if (host->req) {
567 printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
568 spin_unlock_irqrestore(&sock->lock, flags);
569 goto err_out;
570 }
571
572 if (r_data) {
573 tifm_sd_set_data_timeout(host, r_data);
574
2e8ce5e7
AD		 575 host->buffer_size = mrq->cmd->data->blocks
576 * mrq->cmd->data->blksz;
4020f2d7 577
2e8ce5e7
AD		 578 writel(TIFM_MMCSD_BUFINT
579 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
4020f2d7 580 sock->addr + SOCK_MMCSD_INT_ENABLE);
2e8ce5e7
AD		 581 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
582 | (TIFM_MMCSD_FIFO_SIZE - 1),
4020f2d7
AD		 583 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
584
585 host->written_blocks = 0;
586 host->flags &= ~CARD_BUSY;
587 host->buffer_pos = 0;
588 writel(r_data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
589 writel(r_data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
590 }
591
592 host->req = mrq;
0803dd0c 593 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7 594 host->state = CMD;
4020f2d7 595 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 596 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 597 tifm_sd_exec(host, mrq->cmd);
598 spin_unlock_irqrestore(&sock->lock, flags);
599 return;
600
601err_out:
4020f2d7
AD		 602 mrq->cmd->error = MMC_ERR_TIMEOUT;
603 mmc_request_done(mmc, mrq);
604}
605
8e02f858 606static void tifm_sd_end_cmd_nodma(unsigned long data)
4020f2d7 607{
8e02f858 608 struct tifm_sd *host = (struct tifm_sd*)data;
4020f2d7
AD		 609 struct tifm_dev *sock = host->dev;
610 struct mmc_host *mmc = tifm_get_drvdata(sock);
611 struct mmc_request *mrq;
e069d79d 612 struct mmc_data *r_data = NULL;
4020f2d7
AD		 613 unsigned long flags;
614
615 spin_lock_irqsave(&sock->lock, flags);
616
0803dd0c 617 del_timer(&host->timer);
4020f2d7 618 mrq = host->req;
e069d79d 619 host->req = NULL;
4020f2d7
AD		 620 host->state = IDLE;
621
622 if (!mrq) {
623 printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
624 spin_unlock_irqrestore(&sock->lock, flags);
625 return;
626 }
627
628 r_data = mrq->cmd->data;
629 if (r_data) {
630 writel((~TIFM_MMCSD_BUFINT) &
631 readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
632 sock->addr + SOCK_MMCSD_INT_ENABLE);
633
634 if (r_data->flags & MMC_DATA_WRITE) {
2e8ce5e7
AD		 635 r_data->bytes_xfered = host->written_blocks
636 * r_data->blksz;
4020f2d7
AD		 637 } else {
638 r_data->bytes_xfered = r_data->blocks -
639 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
640 r_data->bytes_xfered *= r_data->blksz;
641 r_data->bytes_xfered += r_data->blksz -
642 readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
643 }
4020f2d7
AD		 644 host->buffer_pos = 0;
645 host->buffer_size = 0;
646 }
647
648 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 649 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 650
651 spin_unlock_irqrestore(&sock->lock, flags);
652
4020f2d7
AD		 653 mmc_request_done(mmc, mrq);
654}
655
8e02f858
AD		 656static void tifm_sd_terminate(struct tifm_sd *host)
657{
658 struct tifm_dev *sock = host->dev;
659 unsigned long flags;
660
661 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
662 mmiowb();
663 spin_lock_irqsave(&sock->lock, flags);
664 host->flags |= EJECT;
665 if (host->req) {
666 writel(TIFM_FIFO_INT_SETALL,
667 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
668 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
669 tasklet_schedule(&host->finish_tasklet);
670 }
671 spin_unlock_irqrestore(&sock->lock, flags);
672}
673
0803dd0c 674static void tifm_sd_abort(unsigned long data)
4020f2d7 675{
8e02f858
AD		 676 struct tifm_sd *host = (struct tifm_sd*)data;
677
4020f2d7 678 printk(KERN_ERR DRIVER_NAME
0803dd0c 679 ": card failed to respond for a long period of time");
8e02f858
AD		 680
681 tifm_sd_terminate(host);
682 tifm_eject(host->dev);
4020f2d7
AD		 683}
684
685static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
686{
687 struct tifm_sd *host = mmc_priv(mmc);
688 struct tifm_dev *sock = host->dev;
689 unsigned int clk_div1, clk_div2;
690 unsigned long flags;
691
692 spin_lock_irqsave(&sock->lock, flags);
693
694 dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
695 ios->power_mode);
696 if (ios->bus_width == MMC_BUS_WIDTH_4) {
697 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
698 sock->addr + SOCK_MMCSD_CONFIG);
699 } else {
2e8ce5e7
AD		 700 writel((~TIFM_MMCSD_4BBUS)
701 & readl(sock->addr + SOCK_MMCSD_CONFIG),
702 sock->addr + SOCK_MMCSD_CONFIG);
4020f2d7
AD		 703 }
704
705 if (ios->clock) {
706 clk_div1 = 20000000 / ios->clock;
707 if (!clk_div1)
708 clk_div1 = 1;
709
710 clk_div2 = 24000000 / ios->clock;
711 if (!clk_div2)
712 clk_div2 = 1;
713
714 if ((20000000 / clk_div1) > ios->clock)
715 clk_div1++;
716 if ((24000000 / clk_div2) > ios->clock)
717 clk_div2++;
718 if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
719 host->clk_freq = 20000000;
720 host->clk_div = clk_div1;
2e8ce5e7
AD		 721 writel((~TIFM_CTRL_FAST_CLK)
722 & readl(sock->addr + SOCK_CONTROL),
723 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 724 } else {
725 host->clk_freq = 24000000;
726 host->clk_div = clk_div2;
2e8ce5e7
AD		 727 writel(TIFM_CTRL_FAST_CLK
728 | readl(sock->addr + SOCK_CONTROL),
729 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 730 }
731 } else {
732 host->clk_div = 0;
733 }
734 host->clk_div &= TIFM_MMCSD_CLKMASK;
2e8ce5e7
AD		 735 writel(host->clk_div
736 | ((~TIFM_MMCSD_CLKMASK)
737 & readl(sock->addr + SOCK_MMCSD_CONFIG)),
738 sock->addr + SOCK_MMCSD_CONFIG);
4020f2d7
AD		 739
740 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
741 host->flags |= OPENDRAIN;
742 else
743 host->flags &= ~OPENDRAIN;
744
745 /* chip_select : maybe later */
746 //vdd
747 //power is set before probe / after remove
748 //I believe, power_off when already marked for eject is sufficient to
749 // allow removal.
750 if ((host->flags & EJECT) && ios->power_mode == MMC_POWER_OFF) {
751 host->flags |= EJECT_DONE;
8e02f858 752 wake_up_all(&host->notify);
4020f2d7
AD		 753 }
754
755 spin_unlock_irqrestore(&sock->lock, flags);
756}
757
758static int tifm_sd_ro(struct mmc_host *mmc)
759{
760 int rc;
761 struct tifm_sd *host = mmc_priv(mmc);
762 struct tifm_dev *sock = host->dev;
763 unsigned long flags;
764
765 spin_lock_irqsave(&sock->lock, flags);
766
767 host->flags |= (CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE));
768 rc = (host->flags & CARD_RO) ? 1 : 0;
769
770 spin_unlock_irqrestore(&sock->lock, flags);
771 return rc;
772}
773
774static struct mmc_host_ops tifm_sd_ops = {
775 .request = tifm_sd_request,
776 .set_ios = tifm_sd_ios,
777 .get_ro = tifm_sd_ro
778};
779
8e02f858 780static int tifm_sd_initialize_host(struct tifm_sd *host)
4020f2d7 781{
8e02f858
AD		 782 int rc;
783 unsigned int host_status = 0;
4020f2d7 784 struct tifm_dev *sock = host->dev;
4020f2d7 785
8e02f858
AD		 786 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
787 mmiowb();
788 host->clk_div = 61;
789 host->clk_freq = 20000000;
790 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
791 writel(host->clk_div | TIFM_MMCSD_POWER,
792 sock->addr + SOCK_MMCSD_CONFIG);
793
794 /* wait up to 0.51 sec for reset */
795 for (rc = 2; rc <= 256; rc <<= 1) {
796 if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
797 rc = 0;
798 break;
799 }
800 msleep(rc);
801 }
802
803 if (rc) {
804 printk(KERN_ERR DRIVER_NAME
805 ": controller failed to reset\n");
806 return -ENODEV;
807 }
808
809 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
810 writel(host->clk_div | TIFM_MMCSD_POWER,
811 sock->addr + SOCK_MMCSD_CONFIG);
812 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
813
814 // command timeout fixed to 64 clocks for now
815 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
816 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
817
818 /* INAB should take much less than reset */
819 for (rc = 1; rc <= 16; rc <<= 1) {
820 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
821 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
822 if (!(host_status & TIFM_MMCSD_ERRMASK)
823 && (host_status & TIFM_MMCSD_EOC)) {
824 rc = 0;
825 break;
826 }
827 msleep(rc);
828 }
829
830 if (rc) {
831 printk(KERN_ERR DRIVER_NAME
832 ": card not ready - probe failed on initialization\n");
833 return -ENODEV;
834 }
835
836 writel(TIFM_MMCSD_DATAMASK | TIFM_MMCSD_ERRMASK,
837 sock->addr + SOCK_MMCSD_INT_ENABLE);
838 mmiowb();
839
840 return 0;
4020f2d7
AD		 841}
842
843static int tifm_sd_probe(struct tifm_dev *sock)
844{
845 struct mmc_host *mmc;
846 struct tifm_sd *host;
847 int rc = -EIO;
848
2e8ce5e7
AD		 849 if (!(TIFM_SOCK_STATE_OCCUPIED
850 & readl(sock->addr + SOCK_PRESENT_STATE))) {
4020f2d7
AD		 851 printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
852 return rc;
853 }
854
855 mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
856 if (!mmc)
857 return -ENOMEM;
858
859 host = mmc_priv(mmc);
4020f2d7 860 tifm_set_drvdata(sock, mmc);
8e02f858 861 host->dev = sock;
4020f2d7
AD		 862 host->timeout_jiffies = msecs_to_jiffies(1000);
863
8e02f858
AD		 864 init_waitqueue_head(&host->notify);
865 tasklet_init(&host->finish_tasklet,
866 no_dma ? tifm_sd_end_cmd_nodma : tifm_sd_end_cmd,
867 (unsigned long)host);
868 setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
869
4020f2d7
AD		 870 tifm_sd_ops.request = no_dma ? tifm_sd_request_nodma : tifm_sd_request;
871 mmc->ops = &tifm_sd_ops;
872 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
8e02f858 873 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
4020f2d7
AD		 874 mmc->f_min = 20000000 / 60;
875 mmc->f_max = 24000000;
876 mmc->max_hw_segs = 1;
877 mmc->max_phys_segs = 1;
55db890a
PO		 878 // limited by DMA counter - it's safer to stick with
879 // block counter has 11 bits though
880 mmc->max_blk_count = 256;
881 // 2k maximum hw block length
fe4a3c7a 882 mmc->max_blk_size = 2048;
55db890a
PO		 883 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
884 mmc->max_seg_size = mmc->max_req_size;
8e02f858
AD		 885 sock->signal_irq = tifm_sd_signal_irq;
886 rc = tifm_sd_initialize_host(host);
4020f2d7 887
8e02f858
AD		 888 if (!rc)
889 rc = mmc_add_host(mmc);
890 if (rc)
891 goto out_free_mmc;
4020f2d7
AD		 892
893 return 0;
8e02f858
AD		 894out_free_mmc:
895 mmc_free_host(mmc);
4020f2d7
AD		 896 return rc;
897}
898
899static void tifm_sd_remove(struct tifm_dev *sock)
900{
901 struct mmc_host *mmc = tifm_get_drvdata(sock);
902 struct tifm_sd *host = mmc_priv(mmc);
4020f2d7 903
0803dd0c 904 del_timer_sync(&host->timer);
8e02f858
AD		 905 tifm_sd_terminate(host);
906 wait_event_timeout(host->notify, host->flags & EJECT_DONE,
907 host->timeout_jiffies);
908 tasklet_kill(&host->finish_tasklet);
909 mmc_remove_host(mmc);
4020f2d7
AD		 910
911 /* The meaning of the bit majority in this constant is unknown. */
912 writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 913 sock->addr + SOCK_CONTROL);
4020f2d7 914
e069d79d 915 tifm_set_drvdata(sock, NULL);
4020f2d7
AD		 916 mmc_free_host(mmc);
917}
918
dba4acca
AD		 919#ifdef CONFIG_PM
920
921static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
922{
923 struct mmc_host *mmc = tifm_get_drvdata(sock);
924 int rc;
925
926 rc = mmc_suspend_host(mmc, state);
927 /* The meaning of the bit majority in this constant is unknown. */
928 writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
929 sock->addr + SOCK_CONTROL);
930 return rc;
931}
932
933static int tifm_sd_resume(struct tifm_dev *sock)
934{
935 struct mmc_host *mmc = tifm_get_drvdata(sock);
936 struct tifm_sd *host = mmc_priv(mmc);
937
938 if (sock->media_id != FM_SD
939 || tifm_sd_initialize_host(host)) {
940 tifm_eject(sock);
941 return 0;
942 } else {
943 return mmc_resume_host(mmc);
944 }
945}
946
947#else
948
949#define tifm_sd_suspend NULL
950#define tifm_sd_resume NULL
951
952#endif /* CONFIG_PM */
953
4020f2d7
AD		 954static tifm_media_id tifm_sd_id_tbl[] = {
955 FM_SD, 0
956};
957
958static struct tifm_driver tifm_sd_driver = {
959 .driver = {
960 .name = DRIVER_NAME,
961 .owner = THIS_MODULE
962 },
963 .id_table = tifm_sd_id_tbl,
964 .probe = tifm_sd_probe,
dba4acca
AD		 965 .remove = tifm_sd_remove,
966 .suspend = tifm_sd_suspend,
967 .resume = tifm_sd_resume
4020f2d7
AD		 968};
969
970static int __init tifm_sd_init(void)
971{
972 return tifm_register_driver(&tifm_sd_driver);
973}
974
975static void __exit tifm_sd_exit(void)
976{
977 tifm_unregister_driver(&tifm_sd_driver);
978}
979
980MODULE_AUTHOR("Alex Dubov");
981MODULE_DESCRIPTION("TI FlashMedia SD driver");
982MODULE_LICENSE("GPL");
983MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
984MODULE_VERSION(DRIVER_VERSION);
985
986module_init(tifm_sd_init);
987module_exit(tifm_sd_exit);
Linux kernel - Deliverables
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