Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
[deliverable/linux.git] / drivers / mmc / wbsd.c
CommitLineData
1da177e4
LT
1/*
2 * linux/drivers/mmc/wbsd.c - Winbond W83L51xD SD/MMC driver
3 *
4 * Copyright (C) 2004-2005 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *
11 * Warning!
12 *
13 * Changes to the FIFO system should be done with extreme care since
14 * the hardware is full of bugs related to the FIFO. Known issues are:
15 *
16 * - FIFO size field in FSR is always zero.
17 *
18 * - FIFO interrupts tend not to work as they should. Interrupts are
19 * triggered only for full/empty events, not for threshold values.
20 *
21 * - On APIC systems the FIFO empty interrupt is sometimes lost.
22 */
23
24#include <linux/config.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/ioport.h>
d052d1be 29#include <linux/platform_device.h>
1da177e4 30#include <linux/interrupt.h>
85bcc130 31#include <linux/dma-mapping.h>
1da177e4 32#include <linux/delay.h>
85bcc130 33#include <linux/pnp.h>
1da177e4
LT
34#include <linux/highmem.h>
35#include <linux/mmc/host.h>
36#include <linux/mmc/protocol.h>
37
38#include <asm/io.h>
39#include <asm/dma.h>
40#include <asm/scatterlist.h>
41
42#include "wbsd.h"
43
44#define DRIVER_NAME "wbsd"
402771c7 45#define DRIVER_VERSION "1.5"
1da177e4 46
1da177e4 47#define DBG(x...) \
c6563178 48 pr_debug(DRIVER_NAME ": " x)
1da177e4 49#define DBGF(f, x...) \
c6563178 50 pr_debug(DRIVER_NAME " [%s()]: " f, __func__ , ##x)
1da177e4 51
85bcc130
PO
52/*
53 * Device resources
54 */
55
56#ifdef CONFIG_PNP
57
58static const struct pnp_device_id pnp_dev_table[] = {
59 { "WEC0517", 0 },
60 { "WEC0518", 0 },
61 { "", 0 },
62};
63
64MODULE_DEVICE_TABLE(pnp, pnp_dev_table);
65
66#endif /* CONFIG_PNP */
67
3eee0d03
AB
68static const int config_ports[] = { 0x2E, 0x4E };
69static const int unlock_codes[] = { 0x83, 0x87 };
70
71static const int valid_ids[] = {
72 0x7112,
73 };
74
85bcc130
PO
75#ifdef CONFIG_PNP
76static unsigned int nopnp = 0;
77#else
78static const unsigned int nopnp = 1;
79#endif
80static unsigned int io = 0x248;
81static unsigned int irq = 6;
82static int dma = 2;
83
1da177e4
LT
84/*
85 * Basic functions
86 */
87
cfa7f521 88static inline void wbsd_unlock_config(struct wbsd_host *host)
1da177e4 89{
85bcc130 90 BUG_ON(host->config == 0);
fecf92ba 91
1da177e4
LT
92 outb(host->unlock_code, host->config);
93 outb(host->unlock_code, host->config);
94}
95
cfa7f521 96static inline void wbsd_lock_config(struct wbsd_host *host)
1da177e4 97{
85bcc130 98 BUG_ON(host->config == 0);
fecf92ba 99
1da177e4
LT
100 outb(LOCK_CODE, host->config);
101}
102
cfa7f521 103static inline void wbsd_write_config(struct wbsd_host *host, u8 reg, u8 value)
1da177e4 104{
85bcc130 105 BUG_ON(host->config == 0);
fecf92ba 106
1da177e4
LT
107 outb(reg, host->config);
108 outb(value, host->config + 1);
109}
110
cfa7f521 111static inline u8 wbsd_read_config(struct wbsd_host *host, u8 reg)
1da177e4 112{
85bcc130 113 BUG_ON(host->config == 0);
fecf92ba 114
1da177e4
LT
115 outb(reg, host->config);
116 return inb(host->config + 1);
117}
118
cfa7f521 119static inline void wbsd_write_index(struct wbsd_host *host, u8 index, u8 value)
1da177e4
LT
120{
121 outb(index, host->base + WBSD_IDXR);
122 outb(value, host->base + WBSD_DATAR);
123}
124
cfa7f521 125static inline u8 wbsd_read_index(struct wbsd_host *host, u8 index)
1da177e4
LT
126{
127 outb(index, host->base + WBSD_IDXR);
128 return inb(host->base + WBSD_DATAR);
129}
130
131/*
132 * Common routines
133 */
134
cfa7f521 135static void wbsd_init_device(struct wbsd_host *host)
1da177e4
LT
136{
137 u8 setup, ier;
fecf92ba 138
1da177e4
LT
139 /*
140 * Reset chip (SD/MMC part) and fifo.
141 */
142 setup = wbsd_read_index(host, WBSD_IDX_SETUP);
143 setup |= WBSD_FIFO_RESET | WBSD_SOFT_RESET;
144 wbsd_write_index(host, WBSD_IDX_SETUP, setup);
fecf92ba 145
85bcc130
PO
146 /*
147 * Set DAT3 to input
148 */
149 setup &= ~WBSD_DAT3_H;
150 wbsd_write_index(host, WBSD_IDX_SETUP, setup);
151 host->flags &= ~WBSD_FIGNORE_DETECT;
fecf92ba 152
1da177e4
LT
153 /*
154 * Read back default clock.
155 */
156 host->clk = wbsd_read_index(host, WBSD_IDX_CLK);
157
158 /*
159 * Power down port.
160 */
161 outb(WBSD_POWER_N, host->base + WBSD_CSR);
fecf92ba 162
1da177e4
LT
163 /*
164 * Set maximum timeout.
165 */
166 wbsd_write_index(host, WBSD_IDX_TAAC, 0x7F);
fecf92ba 167
85bcc130
PO
168 /*
169 * Test for card presence
170 */
171 if (inb(host->base + WBSD_CSR) & WBSD_CARDPRESENT)
172 host->flags |= WBSD_FCARD_PRESENT;
173 else
174 host->flags &= ~WBSD_FCARD_PRESENT;
fecf92ba 175
1da177e4
LT
176 /*
177 * Enable interesting interrupts.
178 */
179 ier = 0;
180 ier |= WBSD_EINT_CARD;
181 ier |= WBSD_EINT_FIFO_THRE;
182 ier |= WBSD_EINT_CCRC;
183 ier |= WBSD_EINT_TIMEOUT;
184 ier |= WBSD_EINT_CRC;
185 ier |= WBSD_EINT_TC;
186
187 outb(ier, host->base + WBSD_EIR);
188
189 /*
190 * Clear interrupts.
191 */
192 inb(host->base + WBSD_ISR);
193}
194
cfa7f521 195static void wbsd_reset(struct wbsd_host *host)
1da177e4
LT
196{
197 u8 setup;
fecf92ba 198
d191634f 199 printk(KERN_ERR "%s: Resetting chip\n", mmc_hostname(host->mmc));
fecf92ba 200
1da177e4
LT
201 /*
202 * Soft reset of chip (SD/MMC part).
203 */
204 setup = wbsd_read_index(host, WBSD_IDX_SETUP);
205 setup |= WBSD_SOFT_RESET;
206 wbsd_write_index(host, WBSD_IDX_SETUP, setup);
207}
208
cfa7f521 209static void wbsd_request_end(struct wbsd_host *host, struct mmc_request *mrq)
1da177e4
LT
210{
211 unsigned long dmaflags;
fecf92ba 212
1da177e4 213 DBGF("Ending request, cmd (%x)\n", mrq->cmd->opcode);
fecf92ba 214
cfa7f521 215 if (host->dma >= 0) {
1da177e4
LT
216 /*
217 * Release ISA DMA controller.
218 */
219 dmaflags = claim_dma_lock();
220 disable_dma(host->dma);
221 clear_dma_ff(host->dma);
222 release_dma_lock(dmaflags);
223
224 /*
225 * Disable DMA on host.
226 */
227 wbsd_write_index(host, WBSD_IDX_DMA, 0);
228 }
fecf92ba 229
1da177e4
LT
230 host->mrq = NULL;
231
232 /*
233 * MMC layer might call back into the driver so first unlock.
234 */
235 spin_unlock(&host->lock);
236 mmc_request_done(host->mmc, mrq);
237 spin_lock(&host->lock);
238}
239
240/*
241 * Scatter/gather functions
242 */
243
cfa7f521 244static inline void wbsd_init_sg(struct wbsd_host *host, struct mmc_data *data)
1da177e4
LT
245{
246 /*
247 * Get info. about SG list from data structure.
248 */
249 host->cur_sg = data->sg;
250 host->num_sg = data->sg_len;
251
252 host->offset = 0;
253 host->remain = host->cur_sg->length;
254}
255
cfa7f521 256static inline int wbsd_next_sg(struct wbsd_host *host)
1da177e4
LT
257{
258 /*
259 * Skip to next SG entry.
260 */
261 host->cur_sg++;
262 host->num_sg--;
263
264 /*
265 * Any entries left?
266 */
cfa7f521
PO
267 if (host->num_sg > 0) {
268 host->offset = 0;
269 host->remain = host->cur_sg->length;
270 }
fecf92ba 271
1da177e4
LT
272 return host->num_sg;
273}
274
cfa7f521 275static inline char *wbsd_kmap_sg(struct wbsd_host *host)
1da177e4
LT
276{
277 host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ) +
278 host->cur_sg->offset;
279 return host->mapped_sg;
280}
281
cfa7f521 282static inline void wbsd_kunmap_sg(struct wbsd_host *host)
1da177e4
LT
283{
284 kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
285}
286
cfa7f521 287static inline void wbsd_sg_to_dma(struct wbsd_host *host, struct mmc_data *data)
1da177e4
LT
288{
289 unsigned int len, i, size;
cfa7f521
PO
290 struct scatterlist *sg;
291 char *dmabuf = host->dma_buffer;
292 char *sgbuf;
fecf92ba 293
1da177e4 294 size = host->size;
fecf92ba 295
1da177e4
LT
296 sg = data->sg;
297 len = data->sg_len;
fecf92ba 298
1da177e4
LT
299 /*
300 * Just loop through all entries. Size might not
301 * be the entire list though so make sure that
302 * we do not transfer too much.
303 */
cfa7f521 304 for (i = 0; i < len; i++) {
1da177e4
LT
305 sgbuf = kmap_atomic(sg[i].page, KM_BIO_SRC_IRQ) + sg[i].offset;
306 if (size < sg[i].length)
307 memcpy(dmabuf, sgbuf, size);
308 else
309 memcpy(dmabuf, sgbuf, sg[i].length);
310 kunmap_atomic(sgbuf, KM_BIO_SRC_IRQ);
311 dmabuf += sg[i].length;
fecf92ba 312
1da177e4
LT
313 if (size < sg[i].length)
314 size = 0;
315 else
316 size -= sg[i].length;
fecf92ba 317
1da177e4
LT
318 if (size == 0)
319 break;
320 }
fecf92ba 321
1da177e4
LT
322 /*
323 * Check that we didn't get a request to transfer
324 * more data than can fit into the SG list.
325 */
fecf92ba 326
1da177e4 327 BUG_ON(size != 0);
fecf92ba 328
1da177e4
LT
329 host->size -= size;
330}
331
cfa7f521 332static inline void wbsd_dma_to_sg(struct wbsd_host *host, struct mmc_data *data)
1da177e4
LT
333{
334 unsigned int len, i, size;
cfa7f521
PO
335 struct scatterlist *sg;
336 char *dmabuf = host->dma_buffer;
337 char *sgbuf;
fecf92ba 338
1da177e4 339 size = host->size;
fecf92ba 340
1da177e4
LT
341 sg = data->sg;
342 len = data->sg_len;
fecf92ba 343
1da177e4
LT
344 /*
345 * Just loop through all entries. Size might not
346 * be the entire list though so make sure that
347 * we do not transfer too much.
348 */
cfa7f521 349 for (i = 0; i < len; i++) {
1da177e4
LT
350 sgbuf = kmap_atomic(sg[i].page, KM_BIO_SRC_IRQ) + sg[i].offset;
351 if (size < sg[i].length)
352 memcpy(sgbuf, dmabuf, size);
353 else
354 memcpy(sgbuf, dmabuf, sg[i].length);
355 kunmap_atomic(sgbuf, KM_BIO_SRC_IRQ);
356 dmabuf += sg[i].length;
fecf92ba 357
1da177e4
LT
358 if (size < sg[i].length)
359 size = 0;
360 else
361 size -= sg[i].length;
fecf92ba 362
1da177e4
LT
363 if (size == 0)
364 break;
365 }
fecf92ba 366
1da177e4
LT
367 /*
368 * Check that we didn't get a request to transfer
369 * more data than can fit into the SG list.
370 */
fecf92ba 371
1da177e4 372 BUG_ON(size != 0);
fecf92ba 373
1da177e4
LT
374 host->size -= size;
375}
376
377/*
378 * Command handling
379 */
fecf92ba 380
cfa7f521
PO
381static inline void wbsd_get_short_reply(struct wbsd_host *host,
382 struct mmc_command *cmd)
1da177e4
LT
383{
384 /*
385 * Correct response type?
386 */
cfa7f521 387 if (wbsd_read_index(host, WBSD_IDX_RSPLEN) != WBSD_RSP_SHORT) {
1da177e4
LT
388 cmd->error = MMC_ERR_INVALID;
389 return;
390 }
fecf92ba 391
cfa7f521
PO
392 cmd->resp[0] = wbsd_read_index(host, WBSD_IDX_RESP12) << 24;
393 cmd->resp[0] |= wbsd_read_index(host, WBSD_IDX_RESP13) << 16;
394 cmd->resp[0] |= wbsd_read_index(host, WBSD_IDX_RESP14) << 8;
395 cmd->resp[0] |= wbsd_read_index(host, WBSD_IDX_RESP15) << 0;
396 cmd->resp[1] = wbsd_read_index(host, WBSD_IDX_RESP16) << 24;
1da177e4
LT
397}
398
cfa7f521
PO
399static inline void wbsd_get_long_reply(struct wbsd_host *host,
400 struct mmc_command *cmd)
1da177e4
LT
401{
402 int i;
fecf92ba 403
1da177e4
LT
404 /*
405 * Correct response type?
406 */
cfa7f521 407 if (wbsd_read_index(host, WBSD_IDX_RSPLEN) != WBSD_RSP_LONG) {
1da177e4
LT
408 cmd->error = MMC_ERR_INVALID;
409 return;
410 }
fecf92ba 411
cfa7f521 412 for (i = 0; i < 4; i++) {
1da177e4
LT
413 cmd->resp[i] =
414 wbsd_read_index(host, WBSD_IDX_RESP1 + i * 4) << 24;
415 cmd->resp[i] |=
416 wbsd_read_index(host, WBSD_IDX_RESP2 + i * 4) << 16;
417 cmd->resp[i] |=
418 wbsd_read_index(host, WBSD_IDX_RESP3 + i * 4) << 8;
419 cmd->resp[i] |=
420 wbsd_read_index(host, WBSD_IDX_RESP4 + i * 4) << 0;
421 }
422}
423
cfa7f521 424static void wbsd_send_command(struct wbsd_host *host, struct mmc_command *cmd)
1da177e4
LT
425{
426 int i;
427 u8 status, isr;
fecf92ba 428
1da177e4
LT
429 DBGF("Sending cmd (%x)\n", cmd->opcode);
430
431 /*
432 * Clear accumulated ISR. The interrupt routine
433 * will fill this one with events that occur during
434 * transfer.
435 */
436 host->isr = 0;
fecf92ba 437
1da177e4
LT
438 /*
439 * Send the command (CRC calculated by host).
440 */
441 outb(cmd->opcode, host->base + WBSD_CMDR);
cfa7f521 442 for (i = 3; i >= 0; i--)
1da177e4 443 outb((cmd->arg >> (i * 8)) & 0xff, host->base + WBSD_CMDR);
fecf92ba 444
1da177e4 445 cmd->error = MMC_ERR_NONE;
fecf92ba 446
1da177e4
LT
447 /*
448 * Wait for the request to complete.
449 */
450 do {
451 status = wbsd_read_index(host, WBSD_IDX_STATUS);
452 } while (status & WBSD_CARDTRAFFIC);
453
454 /*
455 * Do we expect a reply?
456 */
e9225176 457 if (cmd->flags & MMC_RSP_PRESENT) {
1da177e4
LT
458 /*
459 * Read back status.
460 */
461 isr = host->isr;
fecf92ba 462
1da177e4
LT
463 /* Card removed? */
464 if (isr & WBSD_INT_CARD)
465 cmd->error = MMC_ERR_TIMEOUT;
466 /* Timeout? */
467 else if (isr & WBSD_INT_TIMEOUT)
468 cmd->error = MMC_ERR_TIMEOUT;
469 /* CRC? */
470 else if ((cmd->flags & MMC_RSP_CRC) && (isr & WBSD_INT_CRC))
471 cmd->error = MMC_ERR_BADCRC;
472 /* All ok */
cfa7f521 473 else {
e9225176 474 if (cmd->flags & MMC_RSP_136)
1da177e4 475 wbsd_get_long_reply(host, cmd);
e9225176
RK
476 else
477 wbsd_get_short_reply(host, cmd);
1da177e4
LT
478 }
479 }
480
481 DBGF("Sent cmd (%x), res %d\n", cmd->opcode, cmd->error);
482}
483
484/*
485 * Data functions
486 */
487
cfa7f521 488static void wbsd_empty_fifo(struct wbsd_host *host)
1da177e4 489{
cfa7f521
PO
490 struct mmc_data *data = host->mrq->cmd->data;
491 char *buffer;
1da177e4 492 int i, fsr, fifo;
fecf92ba 493
1da177e4
LT
494 /*
495 * Handle excessive data.
496 */
497 if (data->bytes_xfered == host->size)
498 return;
fecf92ba 499
1da177e4
LT
500 buffer = wbsd_kmap_sg(host) + host->offset;
501
502 /*
503 * Drain the fifo. This has a tendency to loop longer
504 * than the FIFO length (usually one block).
505 */
cfa7f521 506 while (!((fsr = inb(host->base + WBSD_FSR)) & WBSD_FIFO_EMPTY)) {
1da177e4
LT
507 /*
508 * The size field in the FSR is broken so we have to
509 * do some guessing.
fecf92ba 510 */
1da177e4
LT
511 if (fsr & WBSD_FIFO_FULL)
512 fifo = 16;
513 else if (fsr & WBSD_FIFO_FUTHRE)
514 fifo = 8;
515 else
516 fifo = 1;
fecf92ba 517
cfa7f521 518 for (i = 0; i < fifo; i++) {
1da177e4
LT
519 *buffer = inb(host->base + WBSD_DFR);
520 buffer++;
521 host->offset++;
522 host->remain--;
523
524 data->bytes_xfered++;
fecf92ba 525
1da177e4
LT
526 /*
527 * Transfer done?
528 */
cfa7f521 529 if (data->bytes_xfered == host->size) {
fecf92ba 530 wbsd_kunmap_sg(host);
1da177e4
LT
531 return;
532 }
fecf92ba 533
1da177e4
LT
534 /*
535 * End of scatter list entry?
536 */
cfa7f521 537 if (host->remain == 0) {
1da177e4 538 wbsd_kunmap_sg(host);
fecf92ba 539
1da177e4
LT
540 /*
541 * Get next entry. Check if last.
542 */
cfa7f521 543 if (!wbsd_next_sg(host)) {
1da177e4
LT
544 /*
545 * We should never reach this point.
546 * It means that we're trying to
547 * transfer more blocks than can fit
548 * into the scatter list.
549 */
550 BUG_ON(1);
fecf92ba 551
1da177e4 552 host->size = data->bytes_xfered;
fecf92ba 553
1da177e4
LT
554 return;
555 }
fecf92ba 556
1da177e4
LT
557 buffer = wbsd_kmap_sg(host);
558 }
559 }
560 }
fecf92ba 561
1da177e4
LT
562 wbsd_kunmap_sg(host);
563
564 /*
565 * This is a very dirty hack to solve a
566 * hardware problem. The chip doesn't trigger
567 * FIFO threshold interrupts properly.
568 */
569 if ((host->size - data->bytes_xfered) < 16)
570 tasklet_schedule(&host->fifo_tasklet);
571}
572
cfa7f521 573static void wbsd_fill_fifo(struct wbsd_host *host)
1da177e4 574{
cfa7f521
PO
575 struct mmc_data *data = host->mrq->cmd->data;
576 char *buffer;
1da177e4 577 int i, fsr, fifo;
fecf92ba 578
1da177e4
LT
579 /*
580 * Check that we aren't being called after the
581 * entire buffer has been transfered.
582 */
583 if (data->bytes_xfered == host->size)
584 return;
585
586 buffer = wbsd_kmap_sg(host) + host->offset;
587
588 /*
589 * Fill the fifo. This has a tendency to loop longer
590 * than the FIFO length (usually one block).
591 */
cfa7f521 592 while (!((fsr = inb(host->base + WBSD_FSR)) & WBSD_FIFO_FULL)) {
1da177e4
LT
593 /*
594 * The size field in the FSR is broken so we have to
595 * do some guessing.
fecf92ba 596 */
1da177e4
LT
597 if (fsr & WBSD_FIFO_EMPTY)
598 fifo = 0;
599 else if (fsr & WBSD_FIFO_EMTHRE)
600 fifo = 8;
601 else
602 fifo = 15;
603
cfa7f521 604 for (i = 16; i > fifo; i--) {
1da177e4
LT
605 outb(*buffer, host->base + WBSD_DFR);
606 buffer++;
607 host->offset++;
608 host->remain--;
fecf92ba 609
1da177e4 610 data->bytes_xfered++;
fecf92ba 611
1da177e4
LT
612 /*
613 * Transfer done?
614 */
cfa7f521 615 if (data->bytes_xfered == host->size) {
1da177e4
LT
616 wbsd_kunmap_sg(host);
617 return;
618 }
619
620 /*
621 * End of scatter list entry?
622 */
cfa7f521 623 if (host->remain == 0) {
1da177e4 624 wbsd_kunmap_sg(host);
fecf92ba 625
1da177e4
LT
626 /*
627 * Get next entry. Check if last.
628 */
cfa7f521 629 if (!wbsd_next_sg(host)) {
1da177e4
LT
630 /*
631 * We should never reach this point.
632 * It means that we're trying to
633 * transfer more blocks than can fit
634 * into the scatter list.
635 */
636 BUG_ON(1);
fecf92ba 637
1da177e4 638 host->size = data->bytes_xfered;
fecf92ba 639
1da177e4
LT
640 return;
641 }
fecf92ba 642
1da177e4
LT
643 buffer = wbsd_kmap_sg(host);
644 }
645 }
646 }
fecf92ba 647
1da177e4 648 wbsd_kunmap_sg(host);
fecf92ba 649
85bcc130
PO
650 /*
651 * The controller stops sending interrupts for
652 * 'FIFO empty' under certain conditions. So we
653 * need to be a bit more pro-active.
654 */
655 tasklet_schedule(&host->fifo_tasklet);
1da177e4
LT
656}
657
cfa7f521 658static void wbsd_prepare_data(struct wbsd_host *host, struct mmc_data *data)
1da177e4
LT
659{
660 u16 blksize;
661 u8 setup;
662 unsigned long dmaflags;
663
664 DBGF("blksz %04x blks %04x flags %08x\n",
665 1 << data->blksz_bits, data->blocks, data->flags);
666 DBGF("tsac %d ms nsac %d clk\n",
667 data->timeout_ns / 1000000, data->timeout_clks);
fecf92ba 668
1da177e4
LT
669 /*
670 * Calculate size.
671 */
672 host->size = data->blocks << data->blksz_bits;
673
674 /*
675 * Check timeout values for overflow.
676 * (Yes, some cards cause this value to overflow).
677 */
678 if (data->timeout_ns > 127000000)
679 wbsd_write_index(host, WBSD_IDX_TAAC, 127);
cfa7f521
PO
680 else {
681 wbsd_write_index(host, WBSD_IDX_TAAC,
682 data->timeout_ns / 1000000);
683 }
fecf92ba 684
1da177e4
LT
685 if (data->timeout_clks > 255)
686 wbsd_write_index(host, WBSD_IDX_NSAC, 255);
687 else
688 wbsd_write_index(host, WBSD_IDX_NSAC, data->timeout_clks);
fecf92ba 689
1da177e4
LT
690 /*
691 * Inform the chip of how large blocks will be
692 * sent. It needs this to determine when to
693 * calculate CRC.
694 *
695 * Space for CRC must be included in the size.
65ae2118 696 * Two bytes are needed for each data line.
1da177e4 697 */
cfa7f521 698 if (host->bus_width == MMC_BUS_WIDTH_1) {
65ae2118
PO
699 blksize = (1 << data->blksz_bits) + 2;
700
701 wbsd_write_index(host, WBSD_IDX_PBSMSB, (blksize >> 4) & 0xF0);
702 wbsd_write_index(host, WBSD_IDX_PBSLSB, blksize & 0xFF);
cfa7f521 703 } else if (host->bus_width == MMC_BUS_WIDTH_4) {
65ae2118 704 blksize = (1 << data->blksz_bits) + 2 * 4;
fecf92ba 705
cfa7f521
PO
706 wbsd_write_index(host, WBSD_IDX_PBSMSB,
707 ((blksize >> 4) & 0xF0) | WBSD_DATA_WIDTH);
65ae2118 708 wbsd_write_index(host, WBSD_IDX_PBSLSB, blksize & 0xFF);
cfa7f521 709 } else {
65ae2118
PO
710 data->error = MMC_ERR_INVALID;
711 return;
712 }
1da177e4
LT
713
714 /*
715 * Clear the FIFO. This is needed even for DMA
716 * transfers since the chip still uses the FIFO
717 * internally.
718 */
719 setup = wbsd_read_index(host, WBSD_IDX_SETUP);
720 setup |= WBSD_FIFO_RESET;
721 wbsd_write_index(host, WBSD_IDX_SETUP, setup);
fecf92ba 722
1da177e4
LT
723 /*
724 * DMA transfer?
725 */
cfa7f521 726 if (host->dma >= 0) {
1da177e4
LT
727 /*
728 * The buffer for DMA is only 64 kB.
729 */
730 BUG_ON(host->size > 0x10000);
cfa7f521 731 if (host->size > 0x10000) {
1da177e4
LT
732 data->error = MMC_ERR_INVALID;
733 return;
734 }
fecf92ba 735
1da177e4
LT
736 /*
737 * Transfer data from the SG list to
738 * the DMA buffer.
739 */
740 if (data->flags & MMC_DATA_WRITE)
741 wbsd_sg_to_dma(host, data);
fecf92ba 742
1da177e4
LT
743 /*
744 * Initialise the ISA DMA controller.
fecf92ba 745 */
1da177e4
LT
746 dmaflags = claim_dma_lock();
747 disable_dma(host->dma);
748 clear_dma_ff(host->dma);
749 if (data->flags & MMC_DATA_READ)
750 set_dma_mode(host->dma, DMA_MODE_READ & ~0x40);
751 else
752 set_dma_mode(host->dma, DMA_MODE_WRITE & ~0x40);
753 set_dma_addr(host->dma, host->dma_addr);
754 set_dma_count(host->dma, host->size);
755
756 enable_dma(host->dma);
757 release_dma_lock(dmaflags);
758
759 /*
760 * Enable DMA on the host.
761 */
762 wbsd_write_index(host, WBSD_IDX_DMA, WBSD_DMA_ENABLE);
cfa7f521 763 } else {
1da177e4
LT
764 /*
765 * This flag is used to keep printk
766 * output to a minimum.
767 */
768 host->firsterr = 1;
fecf92ba 769
1da177e4
LT
770 /*
771 * Initialise the SG list.
772 */
773 wbsd_init_sg(host, data);
fecf92ba 774
1da177e4
LT
775 /*
776 * Turn off DMA.
777 */
778 wbsd_write_index(host, WBSD_IDX_DMA, 0);
fecf92ba 779
1da177e4
LT
780 /*
781 * Set up FIFO threshold levels (and fill
782 * buffer if doing a write).
783 */
cfa7f521 784 if (data->flags & MMC_DATA_READ) {
1da177e4
LT
785 wbsd_write_index(host, WBSD_IDX_FIFOEN,
786 WBSD_FIFOEN_FULL | 8);
cfa7f521 787 } else {
1da177e4
LT
788 wbsd_write_index(host, WBSD_IDX_FIFOEN,
789 WBSD_FIFOEN_EMPTY | 8);
790 wbsd_fill_fifo(host);
791 }
fecf92ba
PO
792 }
793
1da177e4
LT
794 data->error = MMC_ERR_NONE;
795}
796
cfa7f521 797static void wbsd_finish_data(struct wbsd_host *host, struct mmc_data *data)
1da177e4
LT
798{
799 unsigned long dmaflags;
800 int count;
801 u8 status;
fecf92ba 802
1da177e4
LT
803 WARN_ON(host->mrq == NULL);
804
805 /*
806 * Send a stop command if needed.
807 */
808 if (data->stop)
809 wbsd_send_command(host, data->stop);
810
811 /*
812 * Wait for the controller to leave data
813 * transfer state.
814 */
cfa7f521 815 do {
1da177e4
LT
816 status = wbsd_read_index(host, WBSD_IDX_STATUS);
817 } while (status & (WBSD_BLOCK_READ | WBSD_BLOCK_WRITE));
fecf92ba 818
1da177e4
LT
819 /*
820 * DMA transfer?
821 */
cfa7f521 822 if (host->dma >= 0) {
1da177e4
LT
823 /*
824 * Disable DMA on the host.
825 */
826 wbsd_write_index(host, WBSD_IDX_DMA, 0);
fecf92ba 827
1da177e4
LT
828 /*
829 * Turn of ISA DMA controller.
830 */
831 dmaflags = claim_dma_lock();
832 disable_dma(host->dma);
833 clear_dma_ff(host->dma);
834 count = get_dma_residue(host->dma);
835 release_dma_lock(dmaflags);
fecf92ba 836
1da177e4
LT
837 /*
838 * Any leftover data?
839 */
cfa7f521 840 if (count) {
d191634f
PO
841 printk(KERN_ERR "%s: Incomplete DMA transfer. "
842 "%d bytes left.\n",
843 mmc_hostname(host->mmc), count);
fecf92ba 844
1da177e4 845 data->error = MMC_ERR_FAILED;
cfa7f521 846 } else {
1da177e4
LT
847 /*
848 * Transfer data from DMA buffer to
849 * SG list.
850 */
851 if (data->flags & MMC_DATA_READ)
852 wbsd_dma_to_sg(host, data);
fecf92ba 853
1da177e4
LT
854 data->bytes_xfered = host->size;
855 }
856 }
fecf92ba 857
1da177e4 858 DBGF("Ending data transfer (%d bytes)\n", data->bytes_xfered);
fecf92ba 859
1da177e4
LT
860 wbsd_request_end(host, host->mrq);
861}
862
85bcc130
PO
863/*****************************************************************************\
864 * *
865 * MMC layer callbacks *
866 * *
867\*****************************************************************************/
1da177e4 868
cfa7f521 869static void wbsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
1da177e4 870{
cfa7f521
PO
871 struct wbsd_host *host = mmc_priv(mmc);
872 struct mmc_command *cmd;
1da177e4
LT
873
874 /*
875 * Disable tasklets to avoid a deadlock.
876 */
877 spin_lock_bh(&host->lock);
878
879 BUG_ON(host->mrq != NULL);
880
881 cmd = mrq->cmd;
882
883 host->mrq = mrq;
fecf92ba 884
1da177e4
LT
885 /*
886 * If there is no card in the slot then
887 * timeout immediatly.
888 */
cfa7f521 889 if (!(host->flags & WBSD_FCARD_PRESENT)) {
1da177e4
LT
890 cmd->error = MMC_ERR_TIMEOUT;
891 goto done;
892 }
893
894 /*
895 * Does the request include data?
896 */
cfa7f521 897 if (cmd->data) {
1da177e4 898 wbsd_prepare_data(host, cmd->data);
fecf92ba 899
1da177e4
LT
900 if (cmd->data->error != MMC_ERR_NONE)
901 goto done;
902 }
fecf92ba 903
1da177e4
LT
904 wbsd_send_command(host, cmd);
905
906 /*
907 * If this is a data transfer the request
908 * will be finished after the data has
909 * transfered.
fecf92ba 910 */
cfa7f521 911 if (cmd->data && (cmd->error == MMC_ERR_NONE)) {
1da177e4
LT
912 /*
913 * Dirty fix for hardware bug.
914 */
915 if (host->dma == -1)
916 tasklet_schedule(&host->fifo_tasklet);
917
918 spin_unlock_bh(&host->lock);
919
920 return;
921 }
fecf92ba 922
1da177e4
LT
923done:
924 wbsd_request_end(host, mrq);
925
926 spin_unlock_bh(&host->lock);
927}
928
cfa7f521 929static void wbsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1da177e4 930{
cfa7f521 931 struct wbsd_host *host = mmc_priv(mmc);
1da177e4 932 u8 clk, setup, pwr;
fecf92ba 933
65ae2118 934 DBGF("clock %uHz busmode %u powermode %u cs %u Vdd %u width %u\n",
cfa7f521
PO
935 ios->clock, ios->bus_mode, ios->power_mode, ios->chip_select,
936 ios->vdd, ios->bus_width);
1da177e4
LT
937
938 spin_lock_bh(&host->lock);
939
940 /*
941 * Reset the chip on each power off.
942 * Should clear out any weird states.
943 */
944 if (ios->power_mode == MMC_POWER_OFF)
945 wbsd_init_device(host);
fecf92ba 946
1da177e4
LT
947 if (ios->clock >= 24000000)
948 clk = WBSD_CLK_24M;
949 else if (ios->clock >= 16000000)
950 clk = WBSD_CLK_16M;
951 else if (ios->clock >= 12000000)
952 clk = WBSD_CLK_12M;
953 else
954 clk = WBSD_CLK_375K;
955
956 /*
957 * Only write to the clock register when
958 * there is an actual change.
959 */
cfa7f521 960 if (clk != host->clk) {
1da177e4
LT
961 wbsd_write_index(host, WBSD_IDX_CLK, clk);
962 host->clk = clk;
963 }
964
85bcc130
PO
965 /*
966 * Power up card.
967 */
cfa7f521 968 if (ios->power_mode != MMC_POWER_OFF) {
1da177e4
LT
969 pwr = inb(host->base + WBSD_CSR);
970 pwr &= ~WBSD_POWER_N;
971 outb(pwr, host->base + WBSD_CSR);
1da177e4
LT
972 }
973
85bcc130
PO
974 /*
975 * MMC cards need to have pin 1 high during init.
85bcc130 976 * It wreaks havoc with the card detection though so
1656fa57 977 * that needs to be disabled.
85bcc130
PO
978 */
979 setup = wbsd_read_index(host, WBSD_IDX_SETUP);
cfa7f521 980 if (ios->chip_select == MMC_CS_HIGH) {
65ae2118 981 BUG_ON(ios->bus_width != MMC_BUS_WIDTH_1);
85bcc130
PO
982 setup |= WBSD_DAT3_H;
983 host->flags |= WBSD_FIGNORE_DETECT;
cfa7f521
PO
984 } else {
985 if (setup & WBSD_DAT3_H) {
19c1f3ca 986 setup &= ~WBSD_DAT3_H;
1656fa57 987
19c1f3ca
PO
988 /*
989 * We cannot resume card detection immediatly
990 * because of capacitance and delays in the chip.
991 */
cfa7f521 992 mod_timer(&host->ignore_timer, jiffies + HZ / 100);
19c1f3ca 993 }
85bcc130
PO
994 }
995 wbsd_write_index(host, WBSD_IDX_SETUP, setup);
fecf92ba 996
65ae2118
PO
997 /*
998 * Store bus width for later. Will be used when
999 * setting up the data transfer.
1000 */
1001 host->bus_width = ios->bus_width;
1002
1da177e4
LT
1003 spin_unlock_bh(&host->lock);
1004}
1005
cfa7f521 1006static int wbsd_get_ro(struct mmc_host *mmc)
65ae2118 1007{
cfa7f521 1008 struct wbsd_host *host = mmc_priv(mmc);
65ae2118
PO
1009 u8 csr;
1010
1011 spin_lock_bh(&host->lock);
1012
1013 csr = inb(host->base + WBSD_CSR);
1014 csr |= WBSD_MSLED;
1015 outb(csr, host->base + WBSD_CSR);
1016
1017 mdelay(1);
1018
1019 csr = inb(host->base + WBSD_CSR);
1020 csr &= ~WBSD_MSLED;
1021 outb(csr, host->base + WBSD_CSR);
1022
1023 spin_unlock_bh(&host->lock);
1024
1025 return csr & WBSD_WRPT;
1026}
1027
85bcc130
PO
1028static struct mmc_host_ops wbsd_ops = {
1029 .request = wbsd_request,
1030 .set_ios = wbsd_set_ios,
65ae2118 1031 .get_ro = wbsd_get_ro,
85bcc130
PO
1032};
1033
1034/*****************************************************************************\
1035 * *
1036 * Interrupt handling *
1037 * *
1038\*****************************************************************************/
1039
1656fa57
PO
1040/*
1041 * Helper function to reset detection ignore
1042 */
1043
1044static void wbsd_reset_ignore(unsigned long data)
1045{
cfa7f521 1046 struct wbsd_host *host = (struct wbsd_host *)data;
1656fa57
PO
1047
1048 BUG_ON(host == NULL);
1049
1050 DBG("Resetting card detection ignore\n");
1051
1052 spin_lock_bh(&host->lock);
1053
1054 host->flags &= ~WBSD_FIGNORE_DETECT;
1055
1056 /*
1057 * Card status might have changed during the
1058 * blackout.
1059 */
1060 tasklet_schedule(&host->card_tasklet);
1061
1062 spin_unlock_bh(&host->lock);
1063}
1064
1da177e4
LT
1065/*
1066 * Tasklets
1067 */
1068
cfa7f521 1069static inline struct mmc_data *wbsd_get_data(struct wbsd_host *host)
1da177e4
LT
1070{
1071 WARN_ON(!host->mrq);
1072 if (!host->mrq)
1073 return NULL;
1074
1075 WARN_ON(!host->mrq->cmd);
1076 if (!host->mrq->cmd)
1077 return NULL;
1078
1079 WARN_ON(!host->mrq->cmd->data);
1080 if (!host->mrq->cmd->data)
1081 return NULL;
fecf92ba 1082
1da177e4
LT
1083 return host->mrq->cmd->data;
1084}
1085
1086static void wbsd_tasklet_card(unsigned long param)
1087{
cfa7f521 1088 struct wbsd_host *host = (struct wbsd_host *)param;
1da177e4 1089 u8 csr;
210ce2a7 1090 int delay = -1;
fecf92ba 1091
1da177e4 1092 spin_lock(&host->lock);
fecf92ba 1093
cfa7f521 1094 if (host->flags & WBSD_FIGNORE_DETECT) {
85bcc130
PO
1095 spin_unlock(&host->lock);
1096 return;
1097 }
fecf92ba 1098
1da177e4
LT
1099 csr = inb(host->base + WBSD_CSR);
1100 WARN_ON(csr == 0xff);
fecf92ba 1101
cfa7f521
PO
1102 if (csr & WBSD_CARDPRESENT) {
1103 if (!(host->flags & WBSD_FCARD_PRESENT)) {
85bcc130
PO
1104 DBG("Card inserted\n");
1105 host->flags |= WBSD_FCARD_PRESENT;
fecf92ba 1106
210ce2a7 1107 delay = 500;
85bcc130 1108 }
cfa7f521 1109 } else if (host->flags & WBSD_FCARD_PRESENT) {
1da177e4 1110 DBG("Card removed\n");
85bcc130 1111 host->flags &= ~WBSD_FCARD_PRESENT;
fecf92ba 1112
cfa7f521 1113 if (host->mrq) {
d191634f
PO
1114 printk(KERN_ERR "%s: Card removed during transfer!\n",
1115 mmc_hostname(host->mmc));
1da177e4 1116 wbsd_reset(host);
fecf92ba 1117
1da177e4
LT
1118 host->mrq->cmd->error = MMC_ERR_FAILED;
1119 tasklet_schedule(&host->finish_tasklet);
1120 }
fecf92ba 1121
210ce2a7 1122 delay = 0;
6e6293dd 1123 }
210ce2a7
PO
1124
1125 /*
1126 * Unlock first since we might get a call back.
1127 */
1128
1129 spin_unlock(&host->lock);
1130
1131 if (delay != -1)
1132 mmc_detect_change(host->mmc, msecs_to_jiffies(delay));
1da177e4
LT
1133}
1134
1135static void wbsd_tasklet_fifo(unsigned long param)
1136{
cfa7f521
PO
1137 struct wbsd_host *host = (struct wbsd_host *)param;
1138 struct mmc_data *data;
fecf92ba 1139
1da177e4 1140 spin_lock(&host->lock);
fecf92ba 1141
1da177e4
LT
1142 if (!host->mrq)
1143 goto end;
fecf92ba 1144
1da177e4
LT
1145 data = wbsd_get_data(host);
1146 if (!data)
1147 goto end;
1148
1149 if (data->flags & MMC_DATA_WRITE)
1150 wbsd_fill_fifo(host);
1151 else
1152 wbsd_empty_fifo(host);
1153
1154 /*
1155 * Done?
1156 */
cfa7f521 1157 if (host->size == data->bytes_xfered) {
1da177e4
LT
1158 wbsd_write_index(host, WBSD_IDX_FIFOEN, 0);
1159 tasklet_schedule(&host->finish_tasklet);
1160 }
1161
fecf92ba 1162end:
1da177e4
LT
1163 spin_unlock(&host->lock);
1164}
1165
1166static void wbsd_tasklet_crc(unsigned long param)
1167{
cfa7f521
PO
1168 struct wbsd_host *host = (struct wbsd_host *)param;
1169 struct mmc_data *data;
fecf92ba 1170
1da177e4 1171 spin_lock(&host->lock);
fecf92ba 1172
1da177e4
LT
1173 if (!host->mrq)
1174 goto end;
fecf92ba 1175
1da177e4
LT
1176 data = wbsd_get_data(host);
1177 if (!data)
1178 goto end;
fecf92ba 1179
1da177e4
LT
1180 DBGF("CRC error\n");
1181
1182 data->error = MMC_ERR_BADCRC;
fecf92ba 1183
1da177e4
LT
1184 tasklet_schedule(&host->finish_tasklet);
1185
fecf92ba 1186end:
1da177e4
LT
1187 spin_unlock(&host->lock);
1188}
1189
1190static void wbsd_tasklet_timeout(unsigned long param)
1191{
cfa7f521
PO
1192 struct wbsd_host *host = (struct wbsd_host *)param;
1193 struct mmc_data *data;
fecf92ba 1194
1da177e4 1195 spin_lock(&host->lock);
fecf92ba 1196
1da177e4
LT
1197 if (!host->mrq)
1198 goto end;
fecf92ba 1199
1da177e4
LT
1200 data = wbsd_get_data(host);
1201 if (!data)
1202 goto end;
fecf92ba 1203
1da177e4
LT
1204 DBGF("Timeout\n");
1205
1206 data->error = MMC_ERR_TIMEOUT;
fecf92ba 1207
1da177e4
LT
1208 tasklet_schedule(&host->finish_tasklet);
1209
fecf92ba 1210end:
1da177e4
LT
1211 spin_unlock(&host->lock);
1212}
1213
1214static void wbsd_tasklet_finish(unsigned long param)
1215{
cfa7f521
PO
1216 struct wbsd_host *host = (struct wbsd_host *)param;
1217 struct mmc_data *data;
fecf92ba 1218
1da177e4 1219 spin_lock(&host->lock);
fecf92ba 1220
1da177e4
LT
1221 WARN_ON(!host->mrq);
1222 if (!host->mrq)
1223 goto end;
fecf92ba 1224
1da177e4
LT
1225 data = wbsd_get_data(host);
1226 if (!data)
1227 goto end;
1228
1229 wbsd_finish_data(host, data);
fecf92ba
PO
1230
1231end:
1da177e4
LT
1232 spin_unlock(&host->lock);
1233}
1234
1235static void wbsd_tasklet_block(unsigned long param)
1236{
cfa7f521
PO
1237 struct wbsd_host *host = (struct wbsd_host *)param;
1238 struct mmc_data *data;
fecf92ba 1239
1da177e4
LT
1240 spin_lock(&host->lock);
1241
1242 if ((wbsd_read_index(host, WBSD_IDX_CRCSTATUS) & WBSD_CRC_MASK) !=
cfa7f521 1243 WBSD_CRC_OK) {
1da177e4
LT
1244 data = wbsd_get_data(host);
1245 if (!data)
1246 goto end;
fecf92ba 1247
1da177e4
LT
1248 DBGF("CRC error\n");
1249
1250 data->error = MMC_ERR_BADCRC;
fecf92ba 1251
1da177e4
LT
1252 tasklet_schedule(&host->finish_tasklet);
1253 }
1254
fecf92ba 1255end:
1da177e4
LT
1256 spin_unlock(&host->lock);
1257}
1258
1259/*
1260 * Interrupt handling
1261 */
1262
1263static irqreturn_t wbsd_irq(int irq, void *dev_id, struct pt_regs *regs)
1264{
cfa7f521 1265 struct wbsd_host *host = dev_id;
1da177e4 1266 int isr;
fecf92ba 1267
1da177e4
LT
1268 isr = inb(host->base + WBSD_ISR);
1269
1270 /*
1271 * Was it actually our hardware that caused the interrupt?
1272 */
1273 if (isr == 0xff || isr == 0x00)
1274 return IRQ_NONE;
fecf92ba 1275
1da177e4
LT
1276 host->isr |= isr;
1277
1278 /*
1279 * Schedule tasklets as needed.
1280 */
1281 if (isr & WBSD_INT_CARD)
1282 tasklet_schedule(&host->card_tasklet);
1283 if (isr & WBSD_INT_FIFO_THRE)
1284 tasklet_schedule(&host->fifo_tasklet);
1285 if (isr & WBSD_INT_CRC)
1286 tasklet_hi_schedule(&host->crc_tasklet);
1287 if (isr & WBSD_INT_TIMEOUT)
1288 tasklet_hi_schedule(&host->timeout_tasklet);
1289 if (isr & WBSD_INT_BUSYEND)
1290 tasklet_hi_schedule(&host->block_tasklet);
1291 if (isr & WBSD_INT_TC)
1292 tasklet_schedule(&host->finish_tasklet);
fecf92ba 1293
1da177e4
LT
1294 return IRQ_HANDLED;
1295}
1296
85bcc130
PO
1297/*****************************************************************************\
1298 * *
1299 * Device initialisation and shutdown *
1300 * *
1301\*****************************************************************************/
1302
1da177e4 1303/*
85bcc130 1304 * Allocate/free MMC structure.
1da177e4
LT
1305 */
1306
cfa7f521 1307static int __devinit wbsd_alloc_mmc(struct device *dev)
85bcc130 1308{
cfa7f521
PO
1309 struct mmc_host *mmc;
1310 struct wbsd_host *host;
fecf92ba 1311
85bcc130
PO
1312 /*
1313 * Allocate MMC structure.
1314 */
1315 mmc = mmc_alloc_host(sizeof(struct wbsd_host), dev);
1316 if (!mmc)
1317 return -ENOMEM;
fecf92ba 1318
85bcc130
PO
1319 host = mmc_priv(mmc);
1320 host->mmc = mmc;
1321
1322 host->dma = -1;
1323
1324 /*
1325 * Set host parameters.
1326 */
1327 mmc->ops = &wbsd_ops;
1328 mmc->f_min = 375000;
1329 mmc->f_max = 24000000;
cfa7f521 1330 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
65ae2118 1331 mmc->caps = MMC_CAP_4_BIT_DATA;
fecf92ba 1332
85bcc130 1333 spin_lock_init(&host->lock);
fecf92ba 1334
6e6293dd 1335 /*
1656fa57 1336 * Set up timers
6e6293dd 1337 */
1656fa57
PO
1338 init_timer(&host->ignore_timer);
1339 host->ignore_timer.data = (unsigned long)host;
1340 host->ignore_timer.function = wbsd_reset_ignore;
fecf92ba 1341
85bcc130
PO
1342 /*
1343 * Maximum number of segments. Worst case is one sector per segment
1344 * so this will be 64kB/512.
1345 */
1346 mmc->max_hw_segs = 128;
1347 mmc->max_phys_segs = 128;
fecf92ba 1348
85bcc130
PO
1349 /*
1350 * Maximum number of sectors in one transfer. Also limited by 64kB
1351 * buffer.
1352 */
1353 mmc->max_sectors = 128;
fecf92ba 1354
85bcc130
PO
1355 /*
1356 * Maximum segment size. Could be one segment with the maximum number
1357 * of segments.
1358 */
1359 mmc->max_seg_size = mmc->max_sectors * 512;
fecf92ba 1360
85bcc130 1361 dev_set_drvdata(dev, mmc);
fecf92ba 1362
85bcc130
PO
1363 return 0;
1364}
1365
cfa7f521 1366static void __devexit wbsd_free_mmc(struct device *dev)
85bcc130 1367{
cfa7f521
PO
1368 struct mmc_host *mmc;
1369 struct wbsd_host *host;
fecf92ba 1370
85bcc130
PO
1371 mmc = dev_get_drvdata(dev);
1372 if (!mmc)
1373 return;
fecf92ba 1374
6e6293dd
PO
1375 host = mmc_priv(mmc);
1376 BUG_ON(host == NULL);
fecf92ba 1377
1656fa57 1378 del_timer_sync(&host->ignore_timer);
fecf92ba 1379
85bcc130 1380 mmc_free_host(mmc);
fecf92ba 1381
85bcc130
PO
1382 dev_set_drvdata(dev, NULL);
1383}
1384
1385/*
1386 * Scan for known chip id:s
1387 */
1388
cfa7f521 1389static int __devinit wbsd_scan(struct wbsd_host *host)
1da177e4
LT
1390{
1391 int i, j, k;
1392 int id;
fecf92ba 1393
1da177e4
LT
1394 /*
1395 * Iterate through all ports, all codes to
1396 * find hardware that is in our known list.
1397 */
63648fb5 1398 for (i = 0; i < ARRAY_SIZE(config_ports); i++) {
1da177e4
LT
1399 if (!request_region(config_ports[i], 2, DRIVER_NAME))
1400 continue;
fecf92ba 1401
63648fb5 1402 for (j = 0; j < ARRAY_SIZE(unlock_codes); j++) {
1da177e4 1403 id = 0xFFFF;
fecf92ba 1404
19c1f3ca
PO
1405 host->config = config_ports[i];
1406 host->unlock_code = unlock_codes[j];
1407
1408 wbsd_unlock_config(host);
fecf92ba 1409
1da177e4
LT
1410 outb(WBSD_CONF_ID_HI, config_ports[i]);
1411 id = inb(config_ports[i] + 1) << 8;
1412
1413 outb(WBSD_CONF_ID_LO, config_ports[i]);
1414 id |= inb(config_ports[i] + 1);
fecf92ba 1415
19c1f3ca
PO
1416 wbsd_lock_config(host);
1417
63648fb5 1418 for (k = 0; k < ARRAY_SIZE(valid_ids); k++) {
cfa7f521 1419 if (id == valid_ids[k]) {
1da177e4 1420 host->chip_id = id;
fecf92ba 1421
1da177e4
LT
1422 return 0;
1423 }
1424 }
fecf92ba 1425
cfa7f521 1426 if (id != 0xFFFF) {
1da177e4
LT
1427 DBG("Unknown hardware (id %x) found at %x\n",
1428 id, config_ports[i]);
1429 }
1da177e4 1430 }
fecf92ba 1431
1da177e4
LT
1432 release_region(config_ports[i], 2);
1433 }
fecf92ba 1434
19c1f3ca
PO
1435 host->config = 0;
1436 host->unlock_code = 0;
1437
1da177e4
LT
1438 return -ENODEV;
1439}
1440
85bcc130
PO
1441/*
1442 * Allocate/free io port ranges
1443 */
1444
cfa7f521 1445static int __devinit wbsd_request_region(struct wbsd_host *host, int base)
1da177e4
LT
1446{
1447 if (io & 0x7)
1448 return -EINVAL;
fecf92ba 1449
85bcc130 1450 if (!request_region(base, 8, DRIVER_NAME))
1da177e4 1451 return -EIO;
fecf92ba 1452
1da177e4 1453 host->base = io;
fecf92ba 1454
1da177e4
LT
1455 return 0;
1456}
1457
cfa7f521 1458static void __devexit wbsd_release_regions(struct wbsd_host *host)
1da177e4
LT
1459{
1460 if (host->base)
1461 release_region(host->base, 8);
fecf92ba 1462
85bcc130 1463 host->base = 0;
1da177e4
LT
1464
1465 if (host->config)
1466 release_region(host->config, 2);
fecf92ba 1467
85bcc130 1468 host->config = 0;
1da177e4
LT
1469}
1470
85bcc130
PO
1471/*
1472 * Allocate/free DMA port and buffer
1473 */
1474
cfa7f521 1475static void __devinit wbsd_request_dma(struct wbsd_host *host, int dma)
1da177e4 1476{
1da177e4
LT
1477 if (dma < 0)
1478 return;
fecf92ba 1479
1da177e4
LT
1480 if (request_dma(dma, DRIVER_NAME))
1481 goto err;
fecf92ba 1482
1da177e4
LT
1483 /*
1484 * We need to allocate a special buffer in
1485 * order for ISA to be able to DMA to it.
1486 */
85bcc130 1487 host->dma_buffer = kmalloc(WBSD_DMA_SIZE,
1da177e4
LT
1488 GFP_NOIO | GFP_DMA | __GFP_REPEAT | __GFP_NOWARN);
1489 if (!host->dma_buffer)
1490 goto free;
1491
1492 /*
1493 * Translate the address to a physical address.
1494 */
85bcc130
PO
1495 host->dma_addr = dma_map_single(host->mmc->dev, host->dma_buffer,
1496 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL);
fecf92ba 1497
1da177e4
LT
1498 /*
1499 * ISA DMA must be aligned on a 64k basis.
1500 */
1501 if ((host->dma_addr & 0xffff) != 0)
1502 goto kfree;
1503 /*
1504 * ISA cannot access memory above 16 MB.
1505 */
1506 else if (host->dma_addr >= 0x1000000)
1507 goto kfree;
1508
1509 host->dma = dma;
fecf92ba 1510
1da177e4 1511 return;
fecf92ba 1512
1da177e4
LT
1513kfree:
1514 /*
1515 * If we've gotten here then there is some kind of alignment bug
1516 */
1517 BUG_ON(1);
fecf92ba 1518
cfa7f521
PO
1519 dma_unmap_single(host->mmc->dev, host->dma_addr,
1520 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL);
85bcc130 1521 host->dma_addr = (dma_addr_t)NULL;
fecf92ba 1522
1da177e4
LT
1523 kfree(host->dma_buffer);
1524 host->dma_buffer = NULL;
1525
1526free:
1527 free_dma(dma);
1528
1529err:
1530 printk(KERN_WARNING DRIVER_NAME ": Unable to allocate DMA %d. "
1531 "Falling back on FIFO.\n", dma);
1532}
1533
cfa7f521 1534static void __devexit wbsd_release_dma(struct wbsd_host *host)
85bcc130 1535{
cfa7f521
PO
1536 if (host->dma_addr) {
1537 dma_unmap_single(host->mmc->dev, host->dma_addr,
1538 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL);
1539 }
6044ec88 1540 kfree(host->dma_buffer);
85bcc130
PO
1541 if (host->dma >= 0)
1542 free_dma(host->dma);
fecf92ba 1543
85bcc130
PO
1544 host->dma = -1;
1545 host->dma_buffer = NULL;
1546 host->dma_addr = (dma_addr_t)NULL;
1547}
1da177e4
LT
1548
1549/*
85bcc130 1550 * Allocate/free IRQ.
1da177e4
LT
1551 */
1552
cfa7f521 1553static int __devinit wbsd_request_irq(struct wbsd_host *host, int irq)
1da177e4 1554{
1da177e4 1555 int ret;
fecf92ba 1556
1da177e4 1557 /*
85bcc130 1558 * Allocate interrupt.
1da177e4 1559 */
85bcc130
PO
1560
1561 ret = request_irq(irq, wbsd_irq, SA_SHIRQ, DRIVER_NAME, host);
1562 if (ret)
1563 return ret;
fecf92ba 1564
85bcc130
PO
1565 host->irq = irq;
1566
1da177e4 1567 /*
85bcc130 1568 * Set up tasklets.
1da177e4 1569 */
cfa7f521
PO
1570 tasklet_init(&host->card_tasklet, wbsd_tasklet_card,
1571 (unsigned long)host);
1572 tasklet_init(&host->fifo_tasklet, wbsd_tasklet_fifo,
1573 (unsigned long)host);
1574 tasklet_init(&host->crc_tasklet, wbsd_tasklet_crc,
1575 (unsigned long)host);
1576 tasklet_init(&host->timeout_tasklet, wbsd_tasklet_timeout,
1577 (unsigned long)host);
1578 tasklet_init(&host->finish_tasklet, wbsd_tasklet_finish,
1579 (unsigned long)host);
1580 tasklet_init(&host->block_tasklet, wbsd_tasklet_block,
1581 (unsigned long)host);
fecf92ba 1582
85bcc130
PO
1583 return 0;
1584}
1da177e4 1585
cfa7f521 1586static void __devexit wbsd_release_irq(struct wbsd_host *host)
85bcc130
PO
1587{
1588 if (!host->irq)
1589 return;
1da177e4 1590
85bcc130 1591 free_irq(host->irq, host);
fecf92ba 1592
85bcc130 1593 host->irq = 0;
fecf92ba 1594
85bcc130
PO
1595 tasklet_kill(&host->card_tasklet);
1596 tasklet_kill(&host->fifo_tasklet);
1597 tasklet_kill(&host->crc_tasklet);
1598 tasklet_kill(&host->timeout_tasklet);
1599 tasklet_kill(&host->finish_tasklet);
1600 tasklet_kill(&host->block_tasklet);
1601}
1602
1603/*
1604 * Allocate all resources for the host.
1605 */
1606
cfa7f521 1607static int __devinit wbsd_request_resources(struct wbsd_host *host,
85bcc130
PO
1608 int base, int irq, int dma)
1609{
1610 int ret;
fecf92ba 1611
1da177e4
LT
1612 /*
1613 * Allocate I/O ports.
1614 */
85bcc130 1615 ret = wbsd_request_region(host, base);
1da177e4 1616 if (ret)
85bcc130 1617 return ret;
1da177e4
LT
1618
1619 /*
85bcc130 1620 * Allocate interrupt.
1da177e4 1621 */
85bcc130
PO
1622 ret = wbsd_request_irq(host, irq);
1623 if (ret)
1624 return ret;
1625
1626 /*
1627 * Allocate DMA.
1628 */
1629 wbsd_request_dma(host, dma);
fecf92ba 1630
85bcc130
PO
1631 return 0;
1632}
1633
1634/*
1635 * Release all resources for the host.
1636 */
1637
cfa7f521 1638static void __devexit wbsd_release_resources(struct wbsd_host *host)
85bcc130
PO
1639{
1640 wbsd_release_dma(host);
1641 wbsd_release_irq(host);
1642 wbsd_release_regions(host);
1643}
1644
1645/*
1646 * Configure the resources the chip should use.
1647 */
1648
cfa7f521 1649static void wbsd_chip_config(struct wbsd_host *host)
85bcc130 1650{
19c1f3ca
PO
1651 wbsd_unlock_config(host);
1652
85bcc130
PO
1653 /*
1654 * Reset the chip.
fecf92ba 1655 */
85bcc130
PO
1656 wbsd_write_config(host, WBSD_CONF_SWRST, 1);
1657 wbsd_write_config(host, WBSD_CONF_SWRST, 0);
1da177e4
LT
1658
1659 /*
1660 * Select SD/MMC function.
1661 */
1662 wbsd_write_config(host, WBSD_CONF_DEVICE, DEVICE_SD);
fecf92ba 1663
1da177e4
LT
1664 /*
1665 * Set up card detection.
1666 */
85bcc130 1667 wbsd_write_config(host, WBSD_CONF_PINS, WBSD_PINS_DETECT_GP11);
fecf92ba 1668
1da177e4 1669 /*
85bcc130 1670 * Configure chip
1da177e4
LT
1671 */
1672 wbsd_write_config(host, WBSD_CONF_PORT_HI, host->base >> 8);
1673 wbsd_write_config(host, WBSD_CONF_PORT_LO, host->base & 0xff);
fecf92ba 1674
85bcc130 1675 wbsd_write_config(host, WBSD_CONF_IRQ, host->irq);
fecf92ba 1676
85bcc130
PO
1677 if (host->dma >= 0)
1678 wbsd_write_config(host, WBSD_CONF_DRQ, host->dma);
fecf92ba 1679
1da177e4 1680 /*
85bcc130 1681 * Enable and power up chip.
1da177e4 1682 */
85bcc130
PO
1683 wbsd_write_config(host, WBSD_CONF_ENABLE, 1);
1684 wbsd_write_config(host, WBSD_CONF_POWER, 0x20);
19c1f3ca
PO
1685
1686 wbsd_lock_config(host);
85bcc130
PO
1687}
1688
1689/*
1690 * Check that configured resources are correct.
1691 */
fecf92ba 1692
cfa7f521 1693static int wbsd_chip_validate(struct wbsd_host *host)
85bcc130
PO
1694{
1695 int base, irq, dma;
fecf92ba 1696
19c1f3ca
PO
1697 wbsd_unlock_config(host);
1698
1da177e4 1699 /*
85bcc130 1700 * Select SD/MMC function.
1da177e4 1701 */
85bcc130 1702 wbsd_write_config(host, WBSD_CONF_DEVICE, DEVICE_SD);
fecf92ba 1703
1da177e4 1704 /*
85bcc130 1705 * Read configuration.
1da177e4 1706 */
85bcc130
PO
1707 base = wbsd_read_config(host, WBSD_CONF_PORT_HI) << 8;
1708 base |= wbsd_read_config(host, WBSD_CONF_PORT_LO);
fecf92ba 1709
85bcc130 1710 irq = wbsd_read_config(host, WBSD_CONF_IRQ);
fecf92ba 1711
85bcc130 1712 dma = wbsd_read_config(host, WBSD_CONF_DRQ);
fecf92ba 1713
19c1f3ca
PO
1714 wbsd_lock_config(host);
1715
1da177e4 1716 /*
85bcc130 1717 * Validate against given configuration.
1da177e4 1718 */
85bcc130
PO
1719 if (base != host->base)
1720 return 0;
1721 if (irq != host->irq)
1722 return 0;
1723 if ((dma != host->dma) && (host->dma != -1))
1724 return 0;
fecf92ba 1725
85bcc130
PO
1726 return 1;
1727}
1728
19c1f3ca
PO
1729/*
1730 * Powers down the SD function
1731 */
1732
cfa7f521 1733static void wbsd_chip_poweroff(struct wbsd_host *host)
19c1f3ca
PO
1734{
1735 wbsd_unlock_config(host);
1736
1737 wbsd_write_config(host, WBSD_CONF_DEVICE, DEVICE_SD);
1738 wbsd_write_config(host, WBSD_CONF_ENABLE, 0);
1739
1740 wbsd_lock_config(host);
1741}
1742
85bcc130
PO
1743/*****************************************************************************\
1744 * *
1745 * Devices setup and shutdown *
1746 * *
1747\*****************************************************************************/
1748
cfa7f521 1749static int __devinit wbsd_init(struct device *dev, int base, int irq, int dma,
85bcc130
PO
1750 int pnp)
1751{
cfa7f521
PO
1752 struct wbsd_host *host = NULL;
1753 struct mmc_host *mmc = NULL;
85bcc130 1754 int ret;
fecf92ba 1755
85bcc130
PO
1756 ret = wbsd_alloc_mmc(dev);
1757 if (ret)
1758 return ret;
fecf92ba 1759
85bcc130
PO
1760 mmc = dev_get_drvdata(dev);
1761 host = mmc_priv(mmc);
fecf92ba 1762
1da177e4 1763 /*
85bcc130 1764 * Scan for hardware.
1da177e4 1765 */
85bcc130 1766 ret = wbsd_scan(host);
cfa7f521
PO
1767 if (ret) {
1768 if (pnp && (ret == -ENODEV)) {
85bcc130
PO
1769 printk(KERN_WARNING DRIVER_NAME
1770 ": Unable to confirm device presence. You may "
1771 "experience lock-ups.\n");
cfa7f521 1772 } else {
85bcc130
PO
1773 wbsd_free_mmc(dev);
1774 return ret;
1775 }
1776 }
fecf92ba 1777
1da177e4 1778 /*
85bcc130 1779 * Request resources.
1da177e4 1780 */
85bcc130 1781 ret = wbsd_request_resources(host, io, irq, dma);
cfa7f521 1782 if (ret) {
85bcc130
PO
1783 wbsd_release_resources(host);
1784 wbsd_free_mmc(dev);
1785 return ret;
1786 }
fecf92ba 1787
1da177e4 1788 /*
85bcc130 1789 * See if chip needs to be configured.
1da177e4 1790 */
cfa7f521
PO
1791 if (pnp) {
1792 if ((host->config != 0) && !wbsd_chip_validate(host)) {
85bcc130
PO
1793 printk(KERN_WARNING DRIVER_NAME
1794 ": PnP active but chip not configured! "
1795 "You probably have a buggy BIOS. "
1796 "Configuring chip manually.\n");
1797 wbsd_chip_config(host);
1798 }
cfa7f521 1799 } else
85bcc130 1800 wbsd_chip_config(host);
fecf92ba 1801
1da177e4
LT
1802 /*
1803 * Power Management stuff. No idea how this works.
1804 * Not tested.
1805 */
1806#ifdef CONFIG_PM
cfa7f521 1807 if (host->config) {
19c1f3ca 1808 wbsd_unlock_config(host);
85bcc130 1809 wbsd_write_config(host, WBSD_CONF_PME, 0xA0);
19c1f3ca
PO
1810 wbsd_lock_config(host);
1811 }
1da177e4 1812#endif
85bcc130
PO
1813 /*
1814 * Allow device to initialise itself properly.
1815 */
1816 mdelay(5);
1da177e4
LT
1817
1818 /*
1819 * Reset the chip into a known state.
1820 */
1821 wbsd_init_device(host);
fecf92ba 1822
1da177e4
LT
1823 mmc_add_host(mmc);
1824
d366b643 1825 printk(KERN_INFO "%s: W83L51xD", mmc_hostname(mmc));
85bcc130
PO
1826 if (host->chip_id != 0)
1827 printk(" id %x", (int)host->chip_id);
1828 printk(" at 0x%x irq %d", (int)host->base, (int)host->irq);
1829 if (host->dma >= 0)
1830 printk(" dma %d", (int)host->dma);
1831 else
1832 printk(" FIFO");
1833 if (pnp)
1834 printk(" PnP");
1835 printk("\n");
1da177e4
LT
1836
1837 return 0;
1da177e4
LT
1838}
1839
cfa7f521 1840static void __devexit wbsd_shutdown(struct device *dev, int pnp)
1da177e4 1841{
cfa7f521
PO
1842 struct mmc_host *mmc = dev_get_drvdata(dev);
1843 struct wbsd_host *host;
fecf92ba 1844
1da177e4 1845 if (!mmc)
85bcc130 1846 return;
1da177e4
LT
1847
1848 host = mmc_priv(mmc);
fecf92ba 1849
1da177e4
LT
1850 mmc_remove_host(mmc);
1851
19c1f3ca
PO
1852 /*
1853 * Power down the SD/MMC function.
1854 */
85bcc130 1855 if (!pnp)
19c1f3ca 1856 wbsd_chip_poweroff(host);
fecf92ba 1857
85bcc130 1858 wbsd_release_resources(host);
fecf92ba 1859
85bcc130
PO
1860 wbsd_free_mmc(dev);
1861}
1da177e4 1862
85bcc130
PO
1863/*
1864 * Non-PnP
1865 */
1866
cfa7f521 1867static int __devinit wbsd_probe(struct platform_device *dev)
85bcc130 1868{
3ae5eaec 1869 return wbsd_init(&dev->dev, io, irq, dma, 0);
85bcc130
PO
1870}
1871
cfa7f521 1872static int __devexit wbsd_remove(struct platform_device *dev)
85bcc130 1873{
3ae5eaec 1874 wbsd_shutdown(&dev->dev, 0);
85bcc130
PO
1875
1876 return 0;
1877}
1878
1879/*
1880 * PnP
1881 */
1882
1883#ifdef CONFIG_PNP
1884
1885static int __devinit
cfa7f521 1886wbsd_pnp_probe(struct pnp_dev *pnpdev, const struct pnp_device_id *dev_id)
85bcc130
PO
1887{
1888 int io, irq, dma;
fecf92ba 1889
85bcc130
PO
1890 /*
1891 * Get resources from PnP layer.
1892 */
1893 io = pnp_port_start(pnpdev, 0);
1894 irq = pnp_irq(pnpdev, 0);
1895 if (pnp_dma_valid(pnpdev, 0))
1896 dma = pnp_dma(pnpdev, 0);
1897 else
1898 dma = -1;
fecf92ba 1899
85bcc130 1900 DBGF("PnP resources: port %3x irq %d dma %d\n", io, irq, dma);
fecf92ba 1901
85bcc130
PO
1902 return wbsd_init(&pnpdev->dev, io, irq, dma, 1);
1903}
1da177e4 1904
cfa7f521 1905static void __devexit wbsd_pnp_remove(struct pnp_dev *dev)
85bcc130
PO
1906{
1907 wbsd_shutdown(&dev->dev, 1);
1da177e4
LT
1908}
1909
85bcc130
PO
1910#endif /* CONFIG_PNP */
1911
1da177e4
LT
1912/*
1913 * Power management
1914 */
1915
1916#ifdef CONFIG_PM
19c1f3ca 1917
5e68d95d
PO
1918static int wbsd_suspend(struct wbsd_host *host, pm_message_t state)
1919{
1920 BUG_ON(host == NULL);
1921
1922 return mmc_suspend_host(host->mmc, state);
1923}
1924
1925static int wbsd_resume(struct wbsd_host *host)
1926{
1927 BUG_ON(host == NULL);
1928
1929 wbsd_init_device(host);
1930
1931 return mmc_resume_host(host->mmc);
1932}
1933
cfa7f521
PO
1934static int wbsd_platform_suspend(struct platform_device *dev,
1935 pm_message_t state)
1da177e4 1936{
3ae5eaec 1937 struct mmc_host *mmc = platform_get_drvdata(dev);
19c1f3ca
PO
1938 struct wbsd_host *host;
1939 int ret;
1940
5e68d95d 1941 if (mmc == NULL)
19c1f3ca
PO
1942 return 0;
1943
5e68d95d 1944 DBGF("Suspending...\n");
19c1f3ca
PO
1945
1946 host = mmc_priv(mmc);
1947
5e68d95d
PO
1948 ret = wbsd_suspend(host, state);
1949 if (ret)
1950 return ret;
1951
19c1f3ca 1952 wbsd_chip_poweroff(host);
1da177e4
LT
1953
1954 return 0;
1955}
1956
5e68d95d 1957static int wbsd_platform_resume(struct platform_device *dev)
1da177e4 1958{
3ae5eaec 1959 struct mmc_host *mmc = platform_get_drvdata(dev);
19c1f3ca 1960 struct wbsd_host *host;
1da177e4 1961
5e68d95d 1962 if (mmc == NULL)
19c1f3ca
PO
1963 return 0;
1964
5e68d95d 1965 DBGF("Resuming...\n");
19c1f3ca
PO
1966
1967 host = mmc_priv(mmc);
1968
1969 wbsd_chip_config(host);
1970
1971 /*
1972 * Allow device to initialise itself properly.
1973 */
1974 mdelay(5);
1975
5e68d95d
PO
1976 return wbsd_resume(host);
1977}
1978
1979#ifdef CONFIG_PNP
1980
1981static int wbsd_pnp_suspend(struct pnp_dev *pnp_dev, pm_message_t state)
1982{
1983 struct mmc_host *mmc = dev_get_drvdata(&pnp_dev->dev);
1984 struct wbsd_host *host;
1985
1986 if (mmc == NULL)
1987 return 0;
19c1f3ca 1988
5e68d95d
PO
1989 DBGF("Suspending...\n");
1990
1991 host = mmc_priv(mmc);
1992
1993 return wbsd_suspend(host, state);
1da177e4 1994}
19c1f3ca 1995
5e68d95d
PO
1996static int wbsd_pnp_resume(struct pnp_dev *pnp_dev)
1997{
1998 struct mmc_host *mmc = dev_get_drvdata(&pnp_dev->dev);
1999 struct wbsd_host *host;
2000
2001 if (mmc == NULL)
2002 return 0;
2003
2004 DBGF("Resuming...\n");
2005
2006 host = mmc_priv(mmc);
2007
2008 /*
2009 * See if chip needs to be configured.
2010 */
cfa7f521
PO
2011 if (host->config != 0) {
2012 if (!wbsd_chip_validate(host)) {
5e68d95d
PO
2013 printk(KERN_WARNING DRIVER_NAME
2014 ": PnP active but chip not configured! "
2015 "You probably have a buggy BIOS. "
2016 "Configuring chip manually.\n");
2017 wbsd_chip_config(host);
2018 }
2019 }
2020
2021 /*
2022 * Allow device to initialise itself properly.
2023 */
2024 mdelay(5);
2025
2026 return wbsd_resume(host);
2027}
2028
2029#endif /* CONFIG_PNP */
2030
19c1f3ca
PO
2031#else /* CONFIG_PM */
2032
5e68d95d
PO
2033#define wbsd_platform_suspend NULL
2034#define wbsd_platform_resume NULL
2035
2036#define wbsd_pnp_suspend NULL
2037#define wbsd_pnp_resume NULL
19c1f3ca
PO
2038
2039#endif /* CONFIG_PM */
1da177e4 2040
85bcc130 2041static struct platform_device *wbsd_device;
1da177e4 2042
3ae5eaec 2043static struct platform_driver wbsd_driver = {
1da177e4 2044 .probe = wbsd_probe,
93968d75 2045 .remove = __devexit_p(wbsd_remove),
fecf92ba 2046
5e68d95d
PO
2047 .suspend = wbsd_platform_suspend,
2048 .resume = wbsd_platform_resume,
3ae5eaec
RK
2049 .driver = {
2050 .name = DRIVER_NAME,
2051 },
1da177e4
LT
2052};
2053
85bcc130
PO
2054#ifdef CONFIG_PNP
2055
2056static struct pnp_driver wbsd_pnp_driver = {
2057 .name = DRIVER_NAME,
2058 .id_table = pnp_dev_table,
2059 .probe = wbsd_pnp_probe,
93968d75 2060 .remove = __devexit_p(wbsd_pnp_remove),
5e68d95d
PO
2061
2062 .suspend = wbsd_pnp_suspend,
2063 .resume = wbsd_pnp_resume,
85bcc130
PO
2064};
2065
2066#endif /* CONFIG_PNP */
2067
1da177e4
LT
2068/*
2069 * Module loading/unloading
2070 */
2071
2072static int __init wbsd_drv_init(void)
2073{
2074 int result;
fecf92ba 2075
1da177e4
LT
2076 printk(KERN_INFO DRIVER_NAME
2077 ": Winbond W83L51xD SD/MMC card interface driver, "
2078 DRIVER_VERSION "\n");
2079 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1da177e4 2080
85bcc130
PO
2081#ifdef CONFIG_PNP
2082
cfa7f521 2083 if (!nopnp) {
85bcc130
PO
2084 result = pnp_register_driver(&wbsd_pnp_driver);
2085 if (result < 0)
2086 return result;
2087 }
fecf92ba
PO
2088#endif /* CONFIG_PNP */
2089
cfa7f521 2090 if (nopnp) {
3ae5eaec 2091 result = platform_driver_register(&wbsd_driver);
85bcc130
PO
2092 if (result < 0)
2093 return result;
2094
21500bb3 2095 wbsd_device = platform_device_alloc(DRIVER_NAME, -1);
cfa7f521 2096 if (!wbsd_device) {
21500bb3
DT
2097 platform_driver_unregister(&wbsd_driver);
2098 return -ENOMEM;
2099 }
2100
2101 result = platform_device_add(wbsd_device);
cfa7f521 2102 if (result) {
21500bb3
DT
2103 platform_device_put(wbsd_device);
2104 platform_driver_unregister(&wbsd_driver);
2105 return result;
2106 }
85bcc130 2107 }
1da177e4
LT
2108
2109 return 0;
2110}
2111
2112static void __exit wbsd_drv_exit(void)
2113{
85bcc130
PO
2114#ifdef CONFIG_PNP
2115
2116 if (!nopnp)
2117 pnp_unregister_driver(&wbsd_pnp_driver);
fecf92ba
PO
2118
2119#endif /* CONFIG_PNP */
85bcc130 2120
cfa7f521 2121 if (nopnp) {
85bcc130 2122 platform_device_unregister(wbsd_device);
fecf92ba 2123
3ae5eaec 2124 platform_driver_unregister(&wbsd_driver);
85bcc130 2125 }
1da177e4
LT
2126
2127 DBG("unloaded\n");
2128}
2129
2130module_init(wbsd_drv_init);
2131module_exit(wbsd_drv_exit);
85bcc130
PO
2132#ifdef CONFIG_PNP
2133module_param(nopnp, uint, 0444);
2134#endif
1da177e4
LT
2135module_param(io, uint, 0444);
2136module_param(irq, uint, 0444);
2137module_param(dma, int, 0444);
2138
2139MODULE_LICENSE("GPL");
de1d09e3 2140MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1da177e4
LT
2141MODULE_DESCRIPTION("Winbond W83L51xD SD/MMC card interface driver");
2142MODULE_VERSION(DRIVER_VERSION);
2143
85bcc130
PO
2144#ifdef CONFIG_PNP
2145MODULE_PARM_DESC(nopnp, "Scan for device instead of relying on PNP. (default 0)");
2146#endif
1da177e4
LT
2147MODULE_PARM_DESC(io, "I/O base to allocate. Must be 8 byte aligned. (default 0x248)");
2148MODULE_PARM_DESC(irq, "IRQ to allocate. (default 6)");
2149MODULE_PARM_DESC(dma, "DMA channel to allocate. -1 for no DMA. (default 2)");
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