[deliverable/linux.git] / drivers / mtd / chips / Kconfig

menu "RAM/ROM/Flash chip drivers"
	depends on MTD!=n

config MTD_CFI
	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
	select MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface specification was developed by Intel,
	  AMD and other flash manufactures that provides a universal method
	  for probing the capabilities of flash devices. If you wish to
	  support any device that is CFI-compliant, you need to enable this
	  option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	  for more information on CFI.

config MTD_JEDECPROBE
	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
	select MTD_GEN_PROBE
	help
	  This option enables JEDEC-style probing of flash chips which are not
	  compatible with the Common Flash Interface, but will use the common
	  CFI-targeted flash drivers for any chips which are identified which
	  are in fact compatible in all but the probe method. This actually
	  covers most AMD/Fujitsu-compatible chips and also non-CFI
	  Intel chips.

config MTD_GEN_PROBE
	tristate

config MTD_CFI_ADV_OPTIONS
	bool "Flash chip driver advanced configuration options"
	depends on MTD_GEN_PROBE
	help
	  If you need to specify a specific endianness for access to flash
	  chips, or if you wish to reduce the size of the kernel by including
	  support for only specific arrangements of flash chips, say 'Y'. This
	  option does not directly affect the code, but will enable other
	  configuration options which allow you to do so.

	  If unsure, say 'N'.

choice
	prompt "Flash cmd/query data swapping"
	depends on MTD_CFI_ADV_OPTIONS
	default MTD_CFI_NOSWAP
	---help---
	  This option defines the way in which the CPU attempts to arrange
	  data bits when writing the 'magic' commands to the chips. Saying
	  'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	  enabled, means that the CPU will not do any swapping; the chips
	  are expected to be wired to the CPU in 'host-endian' form.
	  Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	  LITTLE_ENDIAN_BYTE, if the bytes are reversed.

config MTD_CFI_NOSWAP
	bool "NO"

config MTD_CFI_BE_BYTE_SWAP
	bool "BIG_ENDIAN_BYTE"

config MTD_CFI_LE_BYTE_SWAP
	bool "LITTLE_ENDIAN_BYTE"

endchoice

config MTD_CFI_GEOMETRY
	bool "Specific CFI Flash geometry selection"
	depends on MTD_CFI_ADV_OPTIONS
	help
	  This option does not affect the code directly, but will enable
	  some other configuration options which would allow you to reduce
	  the size of the kernel by including support for only certain
	  arrangements of CFI chips. If unsure, say 'N' and all options
	  which are supported by the current code will be enabled.

config MTD_MAP_BANK_WIDTH_1
	bool "Support  8-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  8 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_2
	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  16 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_4
	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  32 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_8
	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  64 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_16
	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  128 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_32
	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  256 bits wide, say 'Y'.

config MTD_CFI_I1
	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are not interleaved - i.e. you only have one
	  flash chip addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I2
	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are interleaved in pairs - i.e. you have two
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I4
	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in fours - i.e. you have four
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I8
	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in eights - i.e. you have eight
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_OTP
	bool "Protection Registers aka one-time programmable (OTP) bits"
	depends on MTD_CFI_ADV_OPTIONS
	default n
	help
	  This enables support for reading, writing and locking so called
	  "Protection Registers" present on some flash chips.
	  A subset of them are pre-programmed at the factory with a
	  unique set of values. The rest is user-programmable.

	  The user-programmable Protection Registers contain one-time
	  programmable (OTP) bits; when programmed, register bits cannot be
	  erased. Each Protection Register can be accessed multiple times to
	  program individual bits, as long as the register remains unlocked.

	  Each Protection Register has an associated Lock Register bit. When a
	  Lock Register bit is programmed, the associated Protection Register
	  can only be read; it can no longer be programmed. Additionally,
	  because the Lock Register bits themselves are OTP, when programmed,
	  Lock Register bits cannot be erased. Therefore, when a Protection
	  Register is locked, it cannot be unlocked.

	  This feature should therefore be used with extreme care. Any mistake
	  in the programming of OTP bits will waste them.

config MTD_CFI_INTELEXT
	tristate "Support for Intel/Sharp flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets, used on Intel
	  StrataFlash and other parts.

config MTD_CFI_AMDSTD
	tristate "Support for AMD/Fujitsu/Spansion flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets, used on chips
	  including the AMD Am29LV320.

config MTD_CFI_STAA
	tristate "Support for ST (Advanced Architecture) flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets.

config MTD_CFI_UTIL
	tristate

config MTD_RAM
	tristate "Support for RAM chips in bus mapping"
	help
	  This option enables basic support for RAM chips accessed through
	  a bus mapping driver.

config MTD_ROM
	tristate "Support for ROM chips in bus mapping"
	help
	  This option enables basic support for ROM chips accessed through
	  a bus mapping driver.

config MTD_ABSENT
	tristate "Support for absent chips in bus mapping"
	help
	  This option enables support for a dummy probing driver used to
	  allocated placeholder MTD devices on systems that have socketed
	  or removable media.  Use of this driver as a fallback chip probe
	  preserves the expected registration order of MTD device nodes on
	  the system regardless of media presence.  Device nodes created
	  with this driver will return -ENODEV upon access.

config MTD_XIP
	bool "XIP aware MTD support"
	depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && ARCH_MTD_XIP
	default y if XIP_KERNEL
	help
	  This allows MTD support to work with flash memory which is also
	  used for XIP purposes.  If you're not sure what this is all about
	  then say N.

endmenu
Commit	Line	Data
1da177e4 LT	1	menu "RAM/ROM/Flash chip drivers"
	2	depends on MTD!=n
	3
	4	config MTD_CFI
	5	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
1da177e4	6	select MTD_GEN_PROBE
5e706469	7	select MTD_CFI_UTIL
1da177e4 LT	8	help
	9	The Common Flash Interface specification was developed by Intel,
	10	AMD and other flash manufactures that provides a universal method
	11	for probing the capabilities of flash devices. If you wish to
	12	support any device that is CFI-compliant, you need to enable this
	13	option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	14	for more information on CFI.
	15
	16	config MTD_JEDECPROBE
	17	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
1da177e4 LT	18	select MTD_GEN_PROBE
	19	help
	20	This option enables JEDEC-style probing of flash chips which are not
	21	compatible with the Common Flash Interface, but will use the common
25985edc	22	CFI-targeted flash drivers for any chips which are identified which
1da177e4	23	are in fact compatible in all but the probe method. This actually
8917f6f7 AB	24	covers most AMD/Fujitsu-compatible chips and also non-CFI
8917f6f7 AB	25	Intel chips.
1da177e4 LT	26
	27	config MTD_GEN_PROBE
	28	tristate
	29
	30	config MTD_CFI_ADV_OPTIONS
	31	bool "Flash chip driver advanced configuration options"
	32	depends on MTD_GEN_PROBE
	33	help
	34	If you need to specify a specific endianness for access to flash
	35	chips, or if you wish to reduce the size of the kernel by including
	36	support for only specific arrangements of flash chips, say 'Y'. This
1f948b43	37	option does not directly affect the code, but will enable other
1da177e4 LT	38	configuration options which allow you to do so.
	39
	40	If unsure, say 'N'.
	41
	42	choice
	43	prompt "Flash cmd/query data swapping"
	44	depends on MTD_CFI_ADV_OPTIONS
	45	default MTD_CFI_NOSWAP
1da177e4 LT	46	---help---
	47	This option defines the way in which the CPU attempts to arrange
	48	data bits when writing the 'magic' commands to the chips. Saying
	49	'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	50	enabled, means that the CPU will not do any swapping; the chips
1f948b43	51	are expected to be wired to the CPU in 'host-endian' form.
1da177e4 LT	52	Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	53	LITTLE_ENDIAN_BYTE, if the bytes are reversed.
	54
2e61c3a5 PB	55	config MTD_CFI_NOSWAP
2e61c3a5 PB	56	bool "NO"
1da177e4 LT	57
	58	config MTD_CFI_BE_BYTE_SWAP
	59	bool "BIG_ENDIAN_BYTE"
	60
	61	config MTD_CFI_LE_BYTE_SWAP
	62	bool "LITTLE_ENDIAN_BYTE"
	63
	64	endchoice
	65
	66	config MTD_CFI_GEOMETRY
	67	bool "Specific CFI Flash geometry selection"
	68	depends on MTD_CFI_ADV_OPTIONS
	69	help
1f948b43	70	This option does not affect the code directly, but will enable
1da177e4	71	some other configuration options which would allow you to reduce
1f948b43 TG	72	the size of the kernel by including support for only certain
1f948b43 TG	73	arrangements of CFI chips. If unsure, say 'N' and all options
1da177e4 LT	74	which are supported by the current code will be enabled.
	75
	76	config MTD_MAP_BANK_WIDTH_1
	77	bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
	78	default y
	79	help
	80	If you wish to support CFI devices on a physical bus which is
	81	8 bits wide, say 'Y'.
	82
	83	config MTD_MAP_BANK_WIDTH_2
	84	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	85	default y
	86	help
	87	If you wish to support CFI devices on a physical bus which is
	88	16 bits wide, say 'Y'.
	89
	90	config MTD_MAP_BANK_WIDTH_4
	91	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	92	default y
	93	help
	94	If you wish to support CFI devices on a physical bus which is
	95	32 bits wide, say 'Y'.
	96
	97	config MTD_MAP_BANK_WIDTH_8
	98	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	99	default n
	100	help
	101	If you wish to support CFI devices on a physical bus which is
	102	64 bits wide, say 'Y'.
	103
	104	config MTD_MAP_BANK_WIDTH_16
	105	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	106	default n
	107	help
	108	If you wish to support CFI devices on a physical bus which is
	109	128 bits wide, say 'Y'.
	110
	111	config MTD_MAP_BANK_WIDTH_32
	112	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
	113	default n
	114	help
	115	If you wish to support CFI devices on a physical bus which is
	116	256 bits wide, say 'Y'.
	117
	118	config MTD_CFI_I1
	119	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	120	default y
	121	help
	122	If your flash chips are not interleaved - i.e. you only have one
	123	flash chip addressed by each bus cycle, then say 'Y'.
	124
	125	config MTD_CFI_I2
	126	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	127	default y
	128	help
	129	If your flash chips are interleaved in pairs - i.e. you have two
	130	flash chips addressed by each bus cycle, then say 'Y'.
	131
	132	config MTD_CFI_I4
	133	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	134	default n
	135	help
	136	If your flash chips are interleaved in fours - i.e. you have four
	137	flash chips addressed by each bus cycle, then say 'Y'.
138
139	config MTD_CFI_I8
140	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
141	default n
142	help
143	If your flash chips are interleaved in eights - i.e. you have eight
144	flash chips addressed by each bus cycle, then say 'Y'.
145
f77814dd NP	146	config MTD_OTP
	147	bool "Protection Registers aka one-time programmable (OTP) bits"
	148	depends on MTD_CFI_ADV_OPTIONS
	149	default n
	150	help
	151	This enables support for reading, writing and locking so called
	152	"Protection Registers" present on some flash chips.
	153	A subset of them are pre-programmed at the factory with a
	154	unique set of values. The rest is user-programmable.
	155
	156	The user-programmable Protection Registers contain one-time
	157	programmable (OTP) bits; when programmed, register bits cannot be
	158	erased. Each Protection Register can be accessed multiple times to
	159	program individual bits, as long as the register remains unlocked.
	160
	161	Each Protection Register has an associated Lock Register bit. When a
	162	Lock Register bit is programmed, the associated Protection Register
	163	can only be read; it can no longer be programmed. Additionally,
	164	because the Lock Register bits themselves are OTP, when programmed,
	165	Lock Register bits cannot be erased. Therefore, when a Protection
	166	Register is locked, it cannot be unlocked.
	167
	168	This feature should therefore be used with extreme care. Any mistake
	169	in the programming of OTP bits will waste them.
	170
1da177e4 LT	171	config MTD_CFI_INTELEXT
	172	tristate "Support for Intel/Sharp flash chips"
	173	depends on MTD_GEN_PROBE
	174	select MTD_CFI_UTIL
	175	help
	176	The Common Flash Interface defines a number of different command
	177	sets which a CFI-compliant chip may claim to implement. This code
	178	provides support for one of those command sets, used on Intel
	179	StrataFlash and other parts.
	180
	181	config MTD_CFI_AMDSTD
a0e7229e	182	tristate "Support for AMD/Fujitsu/Spansion flash chips"
1da177e4 LT	183	depends on MTD_GEN_PROBE
	184	select MTD_CFI_UTIL
	185	help
	186	The Common Flash Interface defines a number of different command
	187	sets which a CFI-compliant chip may claim to implement. This code
1f948b43	188	provides support for one of those command sets, used on chips
1da177e4 LT	189	including the AMD Am29LV320.
1da177e4 LT	190
1da177e4 LT	191	config MTD_CFI_STAA
	192	tristate "Support for ST (Advanced Architecture) flash chips"
	193	depends on MTD_GEN_PROBE
	194	select MTD_CFI_UTIL
	195	help
	196	The Common Flash Interface defines a number of different command
	197	sets which a CFI-compliant chip may claim to implement. This code
	198	provides support for one of those command sets.
	199
	200	config MTD_CFI_UTIL
	201	tristate
	202
	203	config MTD_RAM
	204	tristate "Support for RAM chips in bus mapping"
1da177e4	205	help
1f948b43	206	This option enables basic support for RAM chips accessed through
1da177e4 LT	207	a bus mapping driver.
	208
	209	config MTD_ROM
	210	tristate "Support for ROM chips in bus mapping"
1da177e4	211	help
1f948b43	212	This option enables basic support for ROM chips accessed through
1da177e4 LT	213	a bus mapping driver.
	214
	215	config MTD_ABSENT
	216	tristate "Support for absent chips in bus mapping"
1da177e4 LT	217	help
	218	This option enables support for a dummy probing driver used to
	219	allocated placeholder MTD devices on systems that have socketed
	220	or removable media. Use of this driver as a fallback chip probe
	221	preserves the expected registration order of MTD device nodes on
	222	the system regardless of media presence. Device nodes created
	223	with this driver will return -ENODEV upon access.
	224
1da177e4 LT	225	config MTD_XIP
1da177e4 LT	226	bool "XIP aware MTD support"
7b4dd55b	227	depends on !SMP && (MTD_CFI_INTELEXT \|\| MTD_CFI_AMDSTD) && ARCH_MTD_XIP
1da177e4 LT	228	default y if XIP_KERNEL
	229	help
	230	This allows MTD support to work with flash memory which is also
	231	used for XIP purposes. If you're not sure what this is all about
	232	then say N.
	233
	234	endmenu