Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Common Flash Interface support: | |
3 | * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002) | |
4 | * | |
5 | * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp> | |
6 | * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com> | |
02b15e34 | 7 | * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com> |
1da177e4 LT |
8 | * |
9 | * 2_by_8 routines added by Simon Munton | |
10 | * | |
11 | * 4_by_16 work by Carolyn J. Smith | |
12 | * | |
1f948b43 | 13 | * XIP support hooks by Vitaly Wool (based on code for Intel flash |
02b15e34 | 14 | * by Nicolas Pitre) |
1f948b43 | 15 | * |
87e92c06 CM |
16 | * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0 |
17 | * | |
1da177e4 LT |
18 | * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com |
19 | * | |
20 | * This code is GPL | |
1da177e4 LT |
21 | */ |
22 | ||
1da177e4 LT |
23 | #include <linux/module.h> |
24 | #include <linux/types.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/init.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/byteorder.h> | |
30 | ||
31 | #include <linux/errno.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/interrupt.h> | |
eafe1311 | 35 | #include <linux/reboot.h> |
1da177e4 LT |
36 | #include <linux/mtd/map.h> |
37 | #include <linux/mtd/mtd.h> | |
38 | #include <linux/mtd/cfi.h> | |
02b15e34 | 39 | #include <linux/mtd/xip.h> |
1da177e4 LT |
40 | |
41 | #define AMD_BOOTLOC_BUG | |
42 | #define FORCE_WORD_WRITE 0 | |
43 | ||
44 | #define MAX_WORD_RETRIES 3 | |
45 | ||
1da177e4 | 46 | #define SST49LF004B 0x0060 |
89072ef9 | 47 | #define SST49LF040B 0x0050 |
fb4a90bf | 48 | #define SST49LF008A 0x005a |
0165508c | 49 | #define AT49BV6416 0x00d6 |
1da177e4 LT |
50 | |
51 | static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); | |
52 | static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); | |
53 | static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); | |
54 | static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); | |
55 | static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); | |
56 | static void cfi_amdstd_sync (struct mtd_info *); | |
57 | static int cfi_amdstd_suspend (struct mtd_info *); | |
58 | static void cfi_amdstd_resume (struct mtd_info *); | |
eafe1311 | 59 | static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *); |
1da177e4 LT |
60 | static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); |
61 | ||
30ec5a2c IS |
62 | static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, |
63 | size_t *retlen, const u_char *buf); | |
64 | ||
1da177e4 LT |
65 | static void cfi_amdstd_destroy(struct mtd_info *); |
66 | ||
67 | struct mtd_info *cfi_cmdset_0002(struct map_info *, int); | |
68 | static struct mtd_info *cfi_amdstd_setup (struct mtd_info *); | |
69 | ||
70 | static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode); | |
71 | static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr); | |
72 | #include "fwh_lock.h" | |
73 | ||
69423d99 AH |
74 | static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
75 | static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); | |
0165508c | 76 | |
1da177e4 LT |
77 | static struct mtd_chip_driver cfi_amdstd_chipdrv = { |
78 | .probe = NULL, /* Not usable directly */ | |
79 | .destroy = cfi_amdstd_destroy, | |
80 | .name = "cfi_cmdset_0002", | |
81 | .module = THIS_MODULE | |
82 | }; | |
83 | ||
84 | ||
85 | /* #define DEBUG_CFI_FEATURES */ | |
86 | ||
87 | ||
88 | #ifdef DEBUG_CFI_FEATURES | |
89 | static void cfi_tell_features(struct cfi_pri_amdstd *extp) | |
90 | { | |
91 | const char* erase_suspend[3] = { | |
92 | "Not supported", "Read only", "Read/write" | |
93 | }; | |
94 | const char* top_bottom[6] = { | |
95 | "No WP", "8x8KiB sectors at top & bottom, no WP", | |
96 | "Bottom boot", "Top boot", | |
97 | "Uniform, Bottom WP", "Uniform, Top WP" | |
98 | }; | |
99 | ||
100 | printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1); | |
1f948b43 | 101 | printk(" Address sensitive unlock: %s\n", |
1da177e4 LT |
102 | (extp->SiliconRevision & 1) ? "Not required" : "Required"); |
103 | ||
104 | if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend)) | |
105 | printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]); | |
106 | else | |
107 | printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend); | |
108 | ||
109 | if (extp->BlkProt == 0) | |
110 | printk(" Block protection: Not supported\n"); | |
111 | else | |
112 | printk(" Block protection: %d sectors per group\n", extp->BlkProt); | |
113 | ||
114 | ||
115 | printk(" Temporary block unprotect: %s\n", | |
116 | extp->TmpBlkUnprotect ? "Supported" : "Not supported"); | |
117 | printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot); | |
118 | printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps); | |
119 | printk(" Burst mode: %s\n", | |
120 | extp->BurstMode ? "Supported" : "Not supported"); | |
121 | if (extp->PageMode == 0) | |
122 | printk(" Page mode: Not supported\n"); | |
123 | else | |
124 | printk(" Page mode: %d word page\n", extp->PageMode << 2); | |
125 | ||
1f948b43 | 126 | printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n", |
1da177e4 | 127 | extp->VppMin >> 4, extp->VppMin & 0xf); |
1f948b43 | 128 | printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n", |
1da177e4 LT |
129 | extp->VppMax >> 4, extp->VppMax & 0xf); |
130 | ||
131 | if (extp->TopBottom < ARRAY_SIZE(top_bottom)) | |
132 | printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]); | |
133 | else | |
134 | printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom); | |
135 | } | |
136 | #endif | |
137 | ||
138 | #ifdef AMD_BOOTLOC_BUG | |
139 | /* Wheee. Bring me the head of someone at AMD. */ | |
cc318222 | 140 | static void fixup_amd_bootblock(struct mtd_info *mtd) |
1da177e4 LT |
141 | { |
142 | struct map_info *map = mtd->priv; | |
143 | struct cfi_private *cfi = map->fldrv_priv; | |
144 | struct cfi_pri_amdstd *extp = cfi->cmdset_priv; | |
145 | __u8 major = extp->MajorVersion; | |
146 | __u8 minor = extp->MinorVersion; | |
147 | ||
148 | if (((major << 8) | minor) < 0x3131) { | |
149 | /* CFI version 1.0 => don't trust bootloc */ | |
87e92c06 | 150 | |
289c0522 | 151 | pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n", |
87e92c06 CM |
152 | map->name, cfi->mfr, cfi->id); |
153 | ||
154 | /* AFAICS all 29LV400 with a bottom boot block have a device ID | |
155 | * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode. | |
156 | * These were badly detected as they have the 0x80 bit set | |
157 | * so treat them as a special case. | |
158 | */ | |
159 | if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) && | |
160 | ||
161 | /* Macronix added CFI to their 2nd generation | |
162 | * MX29LV400C B/T but AFAICS no other 29LV400 (AMD, | |
163 | * Fujitsu, Spansion, EON, ESI and older Macronix) | |
164 | * has CFI. | |
165 | * | |
166 | * Therefore also check the manufacturer. | |
167 | * This reduces the risk of false detection due to | |
168 | * the 8-bit device ID. | |
169 | */ | |
f3e69c65 | 170 | (cfi->mfr == CFI_MFR_MACRONIX)) { |
289c0522 | 171 | pr_debug("%s: Macronix MX29LV400C with bottom boot block" |
87e92c06 CM |
172 | " detected\n", map->name); |
173 | extp->TopBottom = 2; /* bottom boot */ | |
174 | } else | |
1da177e4 LT |
175 | if (cfi->id & 0x80) { |
176 | printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id); | |
177 | extp->TopBottom = 3; /* top boot */ | |
178 | } else { | |
179 | extp->TopBottom = 2; /* bottom boot */ | |
180 | } | |
87e92c06 | 181 | |
289c0522 | 182 | pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;" |
87e92c06 CM |
183 | " deduced %s from Device ID\n", map->name, major, minor, |
184 | extp->TopBottom == 2 ? "bottom" : "top"); | |
1da177e4 LT |
185 | } |
186 | } | |
187 | #endif | |
188 | ||
cc318222 | 189 | static void fixup_use_write_buffers(struct mtd_info *mtd) |
1da177e4 LT |
190 | { |
191 | struct map_info *map = mtd->priv; | |
192 | struct cfi_private *cfi = map->fldrv_priv; | |
193 | if (cfi->cfiq->BufWriteTimeoutTyp) { | |
289c0522 | 194 | pr_debug("Using buffer write method\n" ); |
3c3c10bb | 195 | mtd->_write = cfi_amdstd_write_buffers; |
1da177e4 LT |
196 | } |
197 | } | |
198 | ||
5b0c5c2c | 199 | /* Atmel chips don't use the same PRI format as AMD chips */ |
cc318222 | 200 | static void fixup_convert_atmel_pri(struct mtd_info *mtd) |
5b0c5c2c HS |
201 | { |
202 | struct map_info *map = mtd->priv; | |
203 | struct cfi_private *cfi = map->fldrv_priv; | |
204 | struct cfi_pri_amdstd *extp = cfi->cmdset_priv; | |
205 | struct cfi_pri_atmel atmel_pri; | |
206 | ||
207 | memcpy(&atmel_pri, extp, sizeof(atmel_pri)); | |
de591dac | 208 | memset((char *)extp + 5, 0, sizeof(*extp) - 5); |
5b0c5c2c HS |
209 | |
210 | if (atmel_pri.Features & 0x02) | |
211 | extp->EraseSuspend = 2; | |
212 | ||
be8f78b8 HS |
213 | /* Some chips got it backwards... */ |
214 | if (cfi->id == AT49BV6416) { | |
215 | if (atmel_pri.BottomBoot) | |
216 | extp->TopBottom = 3; | |
217 | else | |
218 | extp->TopBottom = 2; | |
219 | } else { | |
220 | if (atmel_pri.BottomBoot) | |
221 | extp->TopBottom = 2; | |
222 | else | |
223 | extp->TopBottom = 3; | |
224 | } | |
d10a39d1 HCE |
225 | |
226 | /* burst write mode not supported */ | |
227 | cfi->cfiq->BufWriteTimeoutTyp = 0; | |
228 | cfi->cfiq->BufWriteTimeoutMax = 0; | |
5b0c5c2c HS |
229 | } |
230 | ||
cc318222 | 231 | static void fixup_use_secsi(struct mtd_info *mtd) |
1da177e4 LT |
232 | { |
233 | /* Setup for chips with a secsi area */ | |
3c3c10bb AB |
234 | mtd->_read_user_prot_reg = cfi_amdstd_secsi_read; |
235 | mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read; | |
1da177e4 LT |
236 | } |
237 | ||
cc318222 | 238 | static void fixup_use_erase_chip(struct mtd_info *mtd) |
1da177e4 LT |
239 | { |
240 | struct map_info *map = mtd->priv; | |
241 | struct cfi_private *cfi = map->fldrv_priv; | |
242 | if ((cfi->cfiq->NumEraseRegions == 1) && | |
243 | ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) { | |
3c3c10bb | 244 | mtd->_erase = cfi_amdstd_erase_chip; |
1da177e4 | 245 | } |
1f948b43 | 246 | |
1da177e4 LT |
247 | } |
248 | ||
0165508c HS |
249 | /* |
250 | * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors | |
251 | * locked by default. | |
252 | */ | |
cc318222 | 253 | static void fixup_use_atmel_lock(struct mtd_info *mtd) |
0165508c | 254 | { |
3c3c10bb AB |
255 | mtd->_lock = cfi_atmel_lock; |
256 | mtd->_unlock = cfi_atmel_unlock; | |
e619a75f | 257 | mtd->flags |= MTD_POWERUP_LOCK; |
0165508c HS |
258 | } |
259 | ||
83dcd3bb GL |
260 | static void fixup_old_sst_eraseregion(struct mtd_info *mtd) |
261 | { | |
262 | struct map_info *map = mtd->priv; | |
263 | struct cfi_private *cfi = map->fldrv_priv; | |
264 | ||
265 | /* | |
25985edc | 266 | * These flashes report two separate eraseblock regions based on the |
83dcd3bb GL |
267 | * sector_erase-size and block_erase-size, although they both operate on the |
268 | * same memory. This is not allowed according to CFI, so we just pick the | |
269 | * sector_erase-size. | |
270 | */ | |
271 | cfi->cfiq->NumEraseRegions = 1; | |
272 | } | |
273 | ||
cc318222 | 274 | static void fixup_sst39vf(struct mtd_info *mtd) |
83dcd3bb GL |
275 | { |
276 | struct map_info *map = mtd->priv; | |
277 | struct cfi_private *cfi = map->fldrv_priv; | |
278 | ||
279 | fixup_old_sst_eraseregion(mtd); | |
280 | ||
281 | cfi->addr_unlock1 = 0x5555; | |
282 | cfi->addr_unlock2 = 0x2AAA; | |
283 | } | |
284 | ||
cc318222 | 285 | static void fixup_sst39vf_rev_b(struct mtd_info *mtd) |
5a0563f0 GL |
286 | { |
287 | struct map_info *map = mtd->priv; | |
288 | struct cfi_private *cfi = map->fldrv_priv; | |
289 | ||
290 | fixup_old_sst_eraseregion(mtd); | |
291 | ||
292 | cfi->addr_unlock1 = 0x555; | |
293 | cfi->addr_unlock2 = 0x2AA; | |
08968041 GL |
294 | |
295 | cfi->sector_erase_cmd = CMD(0x50); | |
5a0563f0 GL |
296 | } |
297 | ||
cc318222 | 298 | static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd) |
9fc05fca GL |
299 | { |
300 | struct map_info *map = mtd->priv; | |
301 | struct cfi_private *cfi = map->fldrv_priv; | |
302 | ||
cc318222 | 303 | fixup_sst39vf_rev_b(mtd); |
9fc05fca GL |
304 | |
305 | /* | |
306 | * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where | |
307 | * it should report a size of 8KBytes (0x0020*256). | |
308 | */ | |
309 | cfi->cfiq->EraseRegionInfo[0] = 0x002003ff; | |
310 | pr_warning("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n", mtd->name); | |
311 | } | |
312 | ||
cc318222 | 313 | static void fixup_s29gl064n_sectors(struct mtd_info *mtd) |
70b07255 TP |
314 | { |
315 | struct map_info *map = mtd->priv; | |
316 | struct cfi_private *cfi = map->fldrv_priv; | |
317 | ||
318 | if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) { | |
319 | cfi->cfiq->EraseRegionInfo[0] |= 0x0040; | |
320 | pr_warning("%s: Bad S29GL064N CFI data, adjust from 64 to 128 sectors\n", mtd->name); | |
321 | } | |
322 | } | |
323 | ||
cc318222 | 324 | static void fixup_s29gl032n_sectors(struct mtd_info *mtd) |
70b07255 TP |
325 | { |
326 | struct map_info *map = mtd->priv; | |
327 | struct cfi_private *cfi = map->fldrv_priv; | |
328 | ||
329 | if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) { | |
330 | cfi->cfiq->EraseRegionInfo[1] &= ~0x0040; | |
331 | pr_warning("%s: Bad S29GL032N CFI data, adjust from 127 to 63 sectors\n", mtd->name); | |
332 | } | |
333 | } | |
334 | ||
83dcd3bb GL |
335 | /* Used to fix CFI-Tables of chips without Extended Query Tables */ |
336 | static struct cfi_fixup cfi_nopri_fixup_table[] = { | |
cc318222 GL |
337 | { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */ |
338 | { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */ | |
339 | { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */ | |
340 | { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */ | |
341 | { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */ | |
342 | { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */ | |
343 | { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */ | |
344 | { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */ | |
345 | { 0, 0, NULL } | |
83dcd3bb GL |
346 | }; |
347 | ||
1da177e4 | 348 | static struct cfi_fixup cfi_fixup_table[] = { |
cc318222 | 349 | { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri }, |
1da177e4 | 350 | #ifdef AMD_BOOTLOC_BUG |
cc318222 | 351 | { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock }, |
1065cda8 | 352 | { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock }, |
cc318222 | 353 | { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock }, |
1da177e4 | 354 | #endif |
cc318222 GL |
355 | { CFI_MFR_AMD, 0x0050, fixup_use_secsi }, |
356 | { CFI_MFR_AMD, 0x0053, fixup_use_secsi }, | |
357 | { CFI_MFR_AMD, 0x0055, fixup_use_secsi }, | |
358 | { CFI_MFR_AMD, 0x0056, fixup_use_secsi }, | |
359 | { CFI_MFR_AMD, 0x005C, fixup_use_secsi }, | |
360 | { CFI_MFR_AMD, 0x005F, fixup_use_secsi }, | |
361 | { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors }, | |
362 | { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors }, | |
363 | { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors }, | |
364 | { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors }, | |
365 | { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */ | |
366 | { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */ | |
367 | { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */ | |
368 | { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */ | |
1da177e4 | 369 | #if !FORCE_WORD_WRITE |
cc318222 | 370 | { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers }, |
1da177e4 | 371 | #endif |
cc318222 | 372 | { 0, 0, NULL } |
1da177e4 LT |
373 | }; |
374 | static struct cfi_fixup jedec_fixup_table[] = { | |
cc318222 GL |
375 | { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock }, |
376 | { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock }, | |
377 | { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock }, | |
378 | { 0, 0, NULL } | |
1da177e4 LT |
379 | }; |
380 | ||
381 | static struct cfi_fixup fixup_table[] = { | |
382 | /* The CFI vendor ids and the JEDEC vendor IDs appear | |
383 | * to be common. It is like the devices id's are as | |
384 | * well. This table is to pick all cases where | |
385 | * we know that is the case. | |
386 | */ | |
cc318222 GL |
387 | { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip }, |
388 | { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock }, | |
389 | { 0, 0, NULL } | |
1da177e4 LT |
390 | }; |
391 | ||
392 | ||
fefae48b WG |
393 | static void cfi_fixup_major_minor(struct cfi_private *cfi, |
394 | struct cfi_pri_amdstd *extp) | |
395 | { | |
e6372763 | 396 | if (cfi->mfr == CFI_MFR_SAMSUNG) { |
e8953b73 GL |
397 | if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') || |
398 | (extp->MajorVersion == '3' && extp->MinorVersion == '3')) { | |
e6372763 GL |
399 | /* |
400 | * Samsung K8P2815UQB and K8D6x16UxM chips | |
401 | * report major=0 / minor=0. | |
e8953b73 | 402 | * K8D3x16UxC chips report major=3 / minor=3. |
e6372763 GL |
403 | */ |
404 | printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu" | |
405 | " Extended Query version to 1.%c\n", | |
406 | extp->MinorVersion); | |
407 | extp->MajorVersion = '1'; | |
408 | } | |
409 | } | |
410 | ||
9fc05fca GL |
411 | /* |
412 | * SST 38VF640x chips report major=0xFF / minor=0xFF. | |
413 | */ | |
414 | if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) { | |
415 | extp->MajorVersion = '1'; | |
416 | extp->MinorVersion = '0'; | |
417 | } | |
fefae48b WG |
418 | } |
419 | ||
1da177e4 LT |
420 | struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary) |
421 | { | |
422 | struct cfi_private *cfi = map->fldrv_priv; | |
423 | struct mtd_info *mtd; | |
424 | int i; | |
425 | ||
95b93a0c | 426 | mtd = kzalloc(sizeof(*mtd), GFP_KERNEL); |
1da177e4 LT |
427 | if (!mtd) { |
428 | printk(KERN_WARNING "Failed to allocate memory for MTD device\n"); | |
429 | return NULL; | |
430 | } | |
1da177e4 LT |
431 | mtd->priv = map; |
432 | mtd->type = MTD_NORFLASH; | |
433 | ||
434 | /* Fill in the default mtd operations */ | |
3c3c10bb AB |
435 | mtd->_erase = cfi_amdstd_erase_varsize; |
436 | mtd->_write = cfi_amdstd_write_words; | |
437 | mtd->_read = cfi_amdstd_read; | |
438 | mtd->_sync = cfi_amdstd_sync; | |
439 | mtd->_suspend = cfi_amdstd_suspend; | |
440 | mtd->_resume = cfi_amdstd_resume; | |
1da177e4 LT |
441 | mtd->flags = MTD_CAP_NORFLASH; |
442 | mtd->name = map->name; | |
783ed81f | 443 | mtd->writesize = 1; |
13ce77f4 | 444 | mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize; |
d261c72a | 445 | |
0a32a102 BN |
446 | pr_debug("MTD %s(): write buffer size %d\n", __func__, |
447 | mtd->writebufsize); | |
1da177e4 | 448 | |
3c3c10bb | 449 | mtd->_panic_write = cfi_amdstd_panic_write; |
eafe1311 KC |
450 | mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot; |
451 | ||
1da177e4 LT |
452 | if (cfi->cfi_mode==CFI_MODE_CFI){ |
453 | unsigned char bootloc; | |
1da177e4 LT |
454 | __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR; |
455 | struct cfi_pri_amdstd *extp; | |
456 | ||
457 | extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu"); | |
564b8497 GL |
458 | if (extp) { |
459 | /* | |
460 | * It's a real CFI chip, not one for which the probe | |
461 | * routine faked a CFI structure. | |
462 | */ | |
463 | cfi_fixup_major_minor(cfi, extp); | |
464 | ||
e17f47a1 | 465 | /* |
c9ddab25 | 466 | * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5 |
631dd1a8 JM |
467 | * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19 |
468 | * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf | |
5da19532 | 469 | * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf |
c9ddab25 | 470 | * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf |
e17f47a1 | 471 | */ |
564b8497 | 472 | if (extp->MajorVersion != '1' || |
c9ddab25 | 473 | (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) { |
564b8497 | 474 | printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query " |
e17f47a1 GL |
475 | "version %c.%c (%#02x/%#02x).\n", |
476 | extp->MajorVersion, extp->MinorVersion, | |
477 | extp->MajorVersion, extp->MinorVersion); | |
564b8497 GL |
478 | kfree(extp); |
479 | kfree(mtd); | |
480 | return NULL; | |
481 | } | |
d88f977b | 482 | |
e17f47a1 GL |
483 | printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n", |
484 | extp->MajorVersion, extp->MinorVersion); | |
485 | ||
564b8497 GL |
486 | /* Install our own private info structure */ |
487 | cfi->cmdset_priv = extp; | |
1da177e4 | 488 | |
564b8497 GL |
489 | /* Apply cfi device specific fixups */ |
490 | cfi_fixup(mtd, cfi_fixup_table); | |
1da177e4 LT |
491 | |
492 | #ifdef DEBUG_CFI_FEATURES | |
564b8497 GL |
493 | /* Tell the user about it in lots of lovely detail */ |
494 | cfi_tell_features(extp); | |
1f948b43 | 495 | #endif |
1da177e4 | 496 | |
564b8497 | 497 | bootloc = extp->TopBottom; |
412da2f6 DW |
498 | if ((bootloc < 2) || (bootloc > 5)) { |
499 | printk(KERN_WARNING "%s: CFI contains unrecognised boot " | |
500 | "bank location (%d). Assuming bottom.\n", | |
abab7ebf | 501 | map->name, bootloc); |
564b8497 GL |
502 | bootloc = 2; |
503 | } | |
1da177e4 | 504 | |
564b8497 | 505 | if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) { |
412da2f6 | 506 | printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name); |
1f948b43 | 507 | |
564b8497 GL |
508 | for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) { |
509 | int j = (cfi->cfiq->NumEraseRegions-1)-i; | |
510 | __u32 swap; | |
1f948b43 | 511 | |
564b8497 GL |
512 | swap = cfi->cfiq->EraseRegionInfo[i]; |
513 | cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j]; | |
514 | cfi->cfiq->EraseRegionInfo[j] = swap; | |
515 | } | |
1da177e4 | 516 | } |
564b8497 GL |
517 | /* Set the default CFI lock/unlock addresses */ |
518 | cfi->addr_unlock1 = 0x555; | |
519 | cfi->addr_unlock2 = 0x2aa; | |
520 | } | |
83dcd3bb | 521 | cfi_fixup(mtd, cfi_nopri_fixup_table); |
564b8497 GL |
522 | |
523 | if (!cfi->addr_unlock1 || !cfi->addr_unlock2) { | |
524 | kfree(mtd); | |
525 | return NULL; | |
1da177e4 | 526 | } |
1da177e4 LT |
527 | |
528 | } /* CFI mode */ | |
529 | else if (cfi->cfi_mode == CFI_MODE_JEDEC) { | |
530 | /* Apply jedec specific fixups */ | |
531 | cfi_fixup(mtd, jedec_fixup_table); | |
532 | } | |
533 | /* Apply generic fixups */ | |
534 | cfi_fixup(mtd, fixup_table); | |
535 | ||
536 | for (i=0; i< cfi->numchips; i++) { | |
537 | cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp; | |
538 | cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp; | |
539 | cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp; | |
83d48091 VS |
540 | cfi->chips[i].ref_point_counter = 0; |
541 | init_waitqueue_head(&(cfi->chips[i].wq)); | |
1f948b43 TG |
542 | } |
543 | ||
1da177e4 | 544 | map->fldrv = &cfi_amdstd_chipdrv; |
1f948b43 | 545 | |
1da177e4 LT |
546 | return cfi_amdstd_setup(mtd); |
547 | } | |
80461128 | 548 | struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002"))); |
1e804cec | 549 | struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002"))); |
83ea4ef2 | 550 | EXPORT_SYMBOL_GPL(cfi_cmdset_0002); |
80461128 | 551 | EXPORT_SYMBOL_GPL(cfi_cmdset_0006); |
1e804cec | 552 | EXPORT_SYMBOL_GPL(cfi_cmdset_0701); |
1da177e4 LT |
553 | |
554 | static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd) | |
555 | { | |
556 | struct map_info *map = mtd->priv; | |
557 | struct cfi_private *cfi = map->fldrv_priv; | |
558 | unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave; | |
559 | unsigned long offset = 0; | |
560 | int i,j; | |
561 | ||
1f948b43 | 562 | printk(KERN_NOTICE "number of %s chips: %d\n", |
1da177e4 | 563 | (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips); |
1f948b43 | 564 | /* Select the correct geometry setup */ |
1da177e4 LT |
565 | mtd->size = devsize * cfi->numchips; |
566 | ||
567 | mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips; | |
568 | mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info) | |
569 | * mtd->numeraseregions, GFP_KERNEL); | |
1f948b43 | 570 | if (!mtd->eraseregions) { |
1da177e4 LT |
571 | printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n"); |
572 | goto setup_err; | |
573 | } | |
1f948b43 | 574 | |
1da177e4 LT |
575 | for (i=0; i<cfi->cfiq->NumEraseRegions; i++) { |
576 | unsigned long ernum, ersize; | |
577 | ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave; | |
578 | ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1; | |
1f948b43 | 579 | |
1da177e4 LT |
580 | if (mtd->erasesize < ersize) { |
581 | mtd->erasesize = ersize; | |
582 | } | |
583 | for (j=0; j<cfi->numchips; j++) { | |
584 | mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset; | |
585 | mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize; | |
586 | mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum; | |
587 | } | |
588 | offset += (ersize * ernum); | |
589 | } | |
590 | if (offset != devsize) { | |
591 | /* Argh */ | |
592 | printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize); | |
593 | goto setup_err; | |
594 | } | |
1da177e4 | 595 | |
1da177e4 | 596 | __module_get(THIS_MODULE); |
eafe1311 | 597 | register_reboot_notifier(&mtd->reboot_notifier); |
1da177e4 LT |
598 | return mtd; |
599 | ||
600 | setup_err: | |
17fabf15 JS |
601 | kfree(mtd->eraseregions); |
602 | kfree(mtd); | |
1da177e4 LT |
603 | kfree(cfi->cmdset_priv); |
604 | kfree(cfi->cfiq); | |
605 | return NULL; | |
606 | } | |
607 | ||
608 | /* | |
609 | * Return true if the chip is ready. | |
610 | * | |
611 | * Ready is one of: read mode, query mode, erase-suspend-read mode (in any | |
612 | * non-suspended sector) and is indicated by no toggle bits toggling. | |
613 | * | |
614 | * Note that anything more complicated than checking if no bits are toggling | |
615 | * (including checking DQ5 for an error status) is tricky to get working | |
25985edc LDM |
616 | * correctly and is therefore not done (particularly with interleaved chips |
617 | * as each chip must be checked independently of the others). | |
1da177e4 | 618 | */ |
02b15e34 | 619 | static int __xipram chip_ready(struct map_info *map, unsigned long addr) |
1da177e4 LT |
620 | { |
621 | map_word d, t; | |
622 | ||
623 | d = map_read(map, addr); | |
624 | t = map_read(map, addr); | |
625 | ||
626 | return map_word_equal(map, d, t); | |
627 | } | |
628 | ||
fb4a90bf EB |
629 | /* |
630 | * Return true if the chip is ready and has the correct value. | |
631 | * | |
632 | * Ready is one of: read mode, query mode, erase-suspend-read mode (in any | |
633 | * non-suspended sector) and it is indicated by no bits toggling. | |
634 | * | |
635 | * Error are indicated by toggling bits or bits held with the wrong value, | |
636 | * or with bits toggling. | |
637 | * | |
638 | * Note that anything more complicated than checking if no bits are toggling | |
639 | * (including checking DQ5 for an error status) is tricky to get working | |
25985edc LDM |
640 | * correctly and is therefore not done (particularly with interleaved chips |
641 | * as each chip must be checked independently of the others). | |
fb4a90bf EB |
642 | * |
643 | */ | |
02b15e34 | 644 | static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected) |
fb4a90bf EB |
645 | { |
646 | map_word oldd, curd; | |
647 | ||
648 | oldd = map_read(map, addr); | |
649 | curd = map_read(map, addr); | |
650 | ||
1f948b43 | 651 | return map_word_equal(map, oldd, curd) && |
fb4a90bf EB |
652 | map_word_equal(map, curd, expected); |
653 | } | |
654 | ||
1da177e4 LT |
655 | static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode) |
656 | { | |
657 | DECLARE_WAITQUEUE(wait, current); | |
658 | struct cfi_private *cfi = map->fldrv_priv; | |
659 | unsigned long timeo; | |
660 | struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv; | |
661 | ||
662 | resettime: | |
663 | timeo = jiffies + HZ; | |
664 | retry: | |
665 | switch (chip->state) { | |
666 | ||
667 | case FL_STATUS: | |
668 | for (;;) { | |
669 | if (chip_ready(map, adr)) | |
670 | break; | |
671 | ||
672 | if (time_after(jiffies, timeo)) { | |
673 | printk(KERN_ERR "Waiting for chip to be ready timed out.\n"); | |
1da177e4 LT |
674 | return -EIO; |
675 | } | |
c4e77376 | 676 | mutex_unlock(&chip->mutex); |
1da177e4 | 677 | cfi_udelay(1); |
c4e77376 | 678 | mutex_lock(&chip->mutex); |
1da177e4 LT |
679 | /* Someone else might have been playing with it. */ |
680 | goto retry; | |
681 | } | |
1f948b43 | 682 | |
1da177e4 LT |
683 | case FL_READY: |
684 | case FL_CFI_QUERY: | |
685 | case FL_JEDEC_QUERY: | |
686 | return 0; | |
687 | ||
688 | case FL_ERASING: | |
2695eab9 JT |
689 | if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) || |
690 | !(mode == FL_READY || mode == FL_POINT || | |
691 | (mode == FL_WRITING && (cfip->EraseSuspend & 0x2)))) | |
1da177e4 LT |
692 | goto sleep; |
693 | ||
694 | /* We could check to see if we're trying to access the sector | |
695 | * that is currently being erased. However, no user will try | |
696 | * anything like that so we just wait for the timeout. */ | |
697 | ||
698 | /* Erase suspend */ | |
699 | /* It's harmless to issue the Erase-Suspend and Erase-Resume | |
700 | * commands when the erase algorithm isn't in progress. */ | |
701 | map_write(map, CMD(0xB0), chip->in_progress_block_addr); | |
702 | chip->oldstate = FL_ERASING; | |
703 | chip->state = FL_ERASE_SUSPENDING; | |
704 | chip->erase_suspended = 1; | |
705 | for (;;) { | |
706 | if (chip_ready(map, adr)) | |
707 | break; | |
708 | ||
709 | if (time_after(jiffies, timeo)) { | |
710 | /* Should have suspended the erase by now. | |
711 | * Send an Erase-Resume command as either | |
712 | * there was an error (so leave the erase | |
713 | * routine to recover from it) or we trying to | |
714 | * use the erase-in-progress sector. */ | |
100f2341 | 715 | put_chip(map, chip, adr); |
1da177e4 LT |
716 | printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__); |
717 | return -EIO; | |
718 | } | |
1f948b43 | 719 | |
c4e77376 | 720 | mutex_unlock(&chip->mutex); |
1da177e4 | 721 | cfi_udelay(1); |
c4e77376 | 722 | mutex_lock(&chip->mutex); |
1da177e4 LT |
723 | /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING. |
724 | So we can just loop here. */ | |
725 | } | |
726 | chip->state = FL_READY; | |
727 | return 0; | |
728 | ||
02b15e34 TP |
729 | case FL_XIP_WHILE_ERASING: |
730 | if (mode != FL_READY && mode != FL_POINT && | |
731 | (!cfip || !(cfip->EraseSuspend&2))) | |
732 | goto sleep; | |
733 | chip->oldstate = chip->state; | |
734 | chip->state = FL_READY; | |
735 | return 0; | |
736 | ||
eafe1311 KC |
737 | case FL_SHUTDOWN: |
738 | /* The machine is rebooting */ | |
739 | return -EIO; | |
740 | ||
1da177e4 LT |
741 | case FL_POINT: |
742 | /* Only if there's no operation suspended... */ | |
743 | if (mode == FL_READY && chip->oldstate == FL_READY) | |
744 | return 0; | |
745 | ||
746 | default: | |
747 | sleep: | |
748 | set_current_state(TASK_UNINTERRUPTIBLE); | |
749 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 750 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
751 | schedule(); |
752 | remove_wait_queue(&chip->wq, &wait); | |
c4e77376 | 753 | mutex_lock(&chip->mutex); |
1da177e4 LT |
754 | goto resettime; |
755 | } | |
756 | } | |
757 | ||
758 | ||
759 | static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr) | |
760 | { | |
761 | struct cfi_private *cfi = map->fldrv_priv; | |
762 | ||
763 | switch(chip->oldstate) { | |
764 | case FL_ERASING: | |
08968041 | 765 | map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr); |
1da177e4 LT |
766 | chip->oldstate = FL_READY; |
767 | chip->state = FL_ERASING; | |
768 | break; | |
769 | ||
02b15e34 TP |
770 | case FL_XIP_WHILE_ERASING: |
771 | chip->state = chip->oldstate; | |
772 | chip->oldstate = FL_READY; | |
773 | break; | |
774 | ||
1da177e4 LT |
775 | case FL_READY: |
776 | case FL_STATUS: | |
777 | /* We should really make set_vpp() count, rather than doing this */ | |
778 | DISABLE_VPP(map); | |
779 | break; | |
780 | default: | |
781 | printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate); | |
782 | } | |
783 | wake_up(&chip->wq); | |
784 | } | |
785 | ||
02b15e34 TP |
786 | #ifdef CONFIG_MTD_XIP |
787 | ||
788 | /* | |
789 | * No interrupt what so ever can be serviced while the flash isn't in array | |
790 | * mode. This is ensured by the xip_disable() and xip_enable() functions | |
791 | * enclosing any code path where the flash is known not to be in array mode. | |
792 | * And within a XIP disabled code path, only functions marked with __xipram | |
793 | * may be called and nothing else (it's a good thing to inspect generated | |
794 | * assembly to make sure inline functions were actually inlined and that gcc | |
795 | * didn't emit calls to its own support functions). Also configuring MTD CFI | |
796 | * support to a single buswidth and a single interleave is also recommended. | |
797 | */ | |
f8eb321b | 798 | |
02b15e34 TP |
799 | static void xip_disable(struct map_info *map, struct flchip *chip, |
800 | unsigned long adr) | |
801 | { | |
802 | /* TODO: chips with no XIP use should ignore and return */ | |
803 | (void) map_read(map, adr); /* ensure mmu mapping is up to date */ | |
804 | local_irq_disable(); | |
805 | } | |
806 | ||
807 | static void __xipram xip_enable(struct map_info *map, struct flchip *chip, | |
808 | unsigned long adr) | |
809 | { | |
810 | struct cfi_private *cfi = map->fldrv_priv; | |
811 | ||
812 | if (chip->state != FL_POINT && chip->state != FL_READY) { | |
813 | map_write(map, CMD(0xf0), adr); | |
814 | chip->state = FL_READY; | |
815 | } | |
816 | (void) map_read(map, adr); | |
97f927a4 | 817 | xip_iprefetch(); |
02b15e34 TP |
818 | local_irq_enable(); |
819 | } | |
820 | ||
821 | /* | |
822 | * When a delay is required for the flash operation to complete, the | |
823 | * xip_udelay() function is polling for both the given timeout and pending | |
824 | * (but still masked) hardware interrupts. Whenever there is an interrupt | |
1f948b43 | 825 | * pending then the flash erase operation is suspended, array mode restored |
02b15e34 TP |
826 | * and interrupts unmasked. Task scheduling might also happen at that |
827 | * point. The CPU eventually returns from the interrupt or the call to | |
828 | * schedule() and the suspended flash operation is resumed for the remaining | |
829 | * of the delay period. | |
830 | * | |
831 | * Warning: this function _will_ fool interrupt latency tracing tools. | |
832 | */ | |
833 | ||
834 | static void __xipram xip_udelay(struct map_info *map, struct flchip *chip, | |
835 | unsigned long adr, int usec) | |
836 | { | |
837 | struct cfi_private *cfi = map->fldrv_priv; | |
838 | struct cfi_pri_amdstd *extp = cfi->cmdset_priv; | |
839 | map_word status, OK = CMD(0x80); | |
840 | unsigned long suspended, start = xip_currtime(); | |
841 | flstate_t oldstate; | |
842 | ||
843 | do { | |
844 | cpu_relax(); | |
845 | if (xip_irqpending() && extp && | |
846 | ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) && | |
847 | (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) { | |
848 | /* | |
1f948b43 TG |
849 | * Let's suspend the erase operation when supported. |
850 | * Note that we currently don't try to suspend | |
851 | * interleaved chips if there is already another | |
02b15e34 TP |
852 | * operation suspended (imagine what happens |
853 | * when one chip was already done with the current | |
854 | * operation while another chip suspended it, then | |
855 | * we resume the whole thing at once). Yes, it | |
856 | * can happen! | |
857 | */ | |
858 | map_write(map, CMD(0xb0), adr); | |
859 | usec -= xip_elapsed_since(start); | |
860 | suspended = xip_currtime(); | |
861 | do { | |
862 | if (xip_elapsed_since(suspended) > 100000) { | |
863 | /* | |
864 | * The chip doesn't want to suspend | |
865 | * after waiting for 100 msecs. | |
866 | * This is a critical error but there | |
867 | * is not much we can do here. | |
868 | */ | |
869 | return; | |
870 | } | |
871 | status = map_read(map, adr); | |
872 | } while (!map_word_andequal(map, status, OK, OK)); | |
873 | ||
874 | /* Suspend succeeded */ | |
875 | oldstate = chip->state; | |
876 | if (!map_word_bitsset(map, status, CMD(0x40))) | |
877 | break; | |
878 | chip->state = FL_XIP_WHILE_ERASING; | |
879 | chip->erase_suspended = 1; | |
880 | map_write(map, CMD(0xf0), adr); | |
881 | (void) map_read(map, adr); | |
ca5c23c3 | 882 | xip_iprefetch(); |
02b15e34 | 883 | local_irq_enable(); |
c4e77376 | 884 | mutex_unlock(&chip->mutex); |
ca5c23c3 | 885 | xip_iprefetch(); |
02b15e34 TP |
886 | cond_resched(); |
887 | ||
888 | /* | |
889 | * We're back. However someone else might have | |
890 | * decided to go write to the chip if we are in | |
891 | * a suspended erase state. If so let's wait | |
892 | * until it's done. | |
893 | */ | |
c4e77376 | 894 | mutex_lock(&chip->mutex); |
02b15e34 TP |
895 | while (chip->state != FL_XIP_WHILE_ERASING) { |
896 | DECLARE_WAITQUEUE(wait, current); | |
897 | set_current_state(TASK_UNINTERRUPTIBLE); | |
898 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 899 | mutex_unlock(&chip->mutex); |
02b15e34 TP |
900 | schedule(); |
901 | remove_wait_queue(&chip->wq, &wait); | |
c4e77376 | 902 | mutex_lock(&chip->mutex); |
02b15e34 TP |
903 | } |
904 | /* Disallow XIP again */ | |
905 | local_irq_disable(); | |
906 | ||
907 | /* Resume the write or erase operation */ | |
08968041 | 908 | map_write(map, cfi->sector_erase_cmd, adr); |
02b15e34 TP |
909 | chip->state = oldstate; |
910 | start = xip_currtime(); | |
911 | } else if (usec >= 1000000/HZ) { | |
912 | /* | |
913 | * Try to save on CPU power when waiting delay | |
914 | * is at least a system timer tick period. | |
915 | * No need to be extremely accurate here. | |
916 | */ | |
917 | xip_cpu_idle(); | |
918 | } | |
919 | status = map_read(map, adr); | |
920 | } while (!map_word_andequal(map, status, OK, OK) | |
921 | && xip_elapsed_since(start) < usec); | |
922 | } | |
923 | ||
924 | #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec) | |
925 | ||
926 | /* | |
927 | * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while | |
928 | * the flash is actively programming or erasing since we have to poll for | |
929 | * the operation to complete anyway. We can't do that in a generic way with | |
930 | * a XIP setup so do it before the actual flash operation in this case | |
931 | * and stub it out from INVALIDATE_CACHE_UDELAY. | |
932 | */ | |
933 | #define XIP_INVAL_CACHED_RANGE(map, from, size) \ | |
934 | INVALIDATE_CACHED_RANGE(map, from, size) | |
935 | ||
936 | #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ | |
937 | UDELAY(map, chip, adr, usec) | |
938 | ||
939 | /* | |
940 | * Extra notes: | |
941 | * | |
942 | * Activating this XIP support changes the way the code works a bit. For | |
943 | * example the code to suspend the current process when concurrent access | |
944 | * happens is never executed because xip_udelay() will always return with the | |
945 | * same chip state as it was entered with. This is why there is no care for | |
946 | * the presence of add_wait_queue() or schedule() calls from within a couple | |
947 | * xip_disable()'d areas of code, like in do_erase_oneblock for example. | |
948 | * The queueing and scheduling are always happening within xip_udelay(). | |
949 | * | |
950 | * Similarly, get_chip() and put_chip() just happen to always be executed | |
951 | * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state | |
952 | * is in array mode, therefore never executing many cases therein and not | |
953 | * causing any problem with XIP. | |
954 | */ | |
955 | ||
956 | #else | |
957 | ||
958 | #define xip_disable(map, chip, adr) | |
959 | #define xip_enable(map, chip, adr) | |
960 | #define XIP_INVAL_CACHED_RANGE(x...) | |
961 | ||
962 | #define UDELAY(map, chip, adr, usec) \ | |
963 | do { \ | |
c4e77376 | 964 | mutex_unlock(&chip->mutex); \ |
02b15e34 | 965 | cfi_udelay(usec); \ |
c4e77376 | 966 | mutex_lock(&chip->mutex); \ |
02b15e34 TP |
967 | } while (0) |
968 | ||
969 | #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ | |
970 | do { \ | |
c4e77376 | 971 | mutex_unlock(&chip->mutex); \ |
02b15e34 TP |
972 | INVALIDATE_CACHED_RANGE(map, adr, len); \ |
973 | cfi_udelay(usec); \ | |
c4e77376 | 974 | mutex_lock(&chip->mutex); \ |
02b15e34 TP |
975 | } while (0) |
976 | ||
977 | #endif | |
1da177e4 LT |
978 | |
979 | static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf) | |
980 | { | |
981 | unsigned long cmd_addr; | |
982 | struct cfi_private *cfi = map->fldrv_priv; | |
983 | int ret; | |
984 | ||
985 | adr += chip->start; | |
986 | ||
1f948b43 TG |
987 | /* Ensure cmd read/writes are aligned. */ |
988 | cmd_addr = adr & ~(map_bankwidth(map)-1); | |
1da177e4 | 989 | |
c4e77376 | 990 | mutex_lock(&chip->mutex); |
1da177e4 LT |
991 | ret = get_chip(map, chip, cmd_addr, FL_READY); |
992 | if (ret) { | |
c4e77376 | 993 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
994 | return ret; |
995 | } | |
996 | ||
997 | if (chip->state != FL_POINT && chip->state != FL_READY) { | |
998 | map_write(map, CMD(0xf0), cmd_addr); | |
999 | chip->state = FL_READY; | |
1000 | } | |
1001 | ||
1002 | map_copy_from(map, buf, adr, len); | |
1003 | ||
1004 | put_chip(map, chip, cmd_addr); | |
1005 | ||
c4e77376 | 1006 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1007 | return 0; |
1008 | } | |
1009 | ||
1010 | ||
1011 | static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) | |
1012 | { | |
1013 | struct map_info *map = mtd->priv; | |
1014 | struct cfi_private *cfi = map->fldrv_priv; | |
1015 | unsigned long ofs; | |
1016 | int chipnum; | |
1017 | int ret = 0; | |
1018 | ||
1019 | /* ofs: offset within the first chip that the first read should start */ | |
1020 | ||
1021 | chipnum = (from >> cfi->chipshift); | |
1022 | ofs = from - (chipnum << cfi->chipshift); | |
1023 | ||
1024 | ||
1025 | *retlen = 0; | |
1026 | ||
1027 | while (len) { | |
1028 | unsigned long thislen; | |
1029 | ||
1030 | if (chipnum >= cfi->numchips) | |
1031 | break; | |
1032 | ||
1033 | if ((len + ofs -1) >> cfi->chipshift) | |
1034 | thislen = (1<<cfi->chipshift) - ofs; | |
1035 | else | |
1036 | thislen = len; | |
1037 | ||
1038 | ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf); | |
1039 | if (ret) | |
1040 | break; | |
1041 | ||
1042 | *retlen += thislen; | |
1043 | len -= thislen; | |
1044 | buf += thislen; | |
1045 | ||
1046 | ofs = 0; | |
1047 | chipnum++; | |
1048 | } | |
1049 | return ret; | |
1050 | } | |
1051 | ||
1052 | ||
1053 | static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf) | |
1054 | { | |
1055 | DECLARE_WAITQUEUE(wait, current); | |
1056 | unsigned long timeo = jiffies + HZ; | |
1057 | struct cfi_private *cfi = map->fldrv_priv; | |
1058 | ||
1059 | retry: | |
c4e77376 | 1060 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1061 | |
1062 | if (chip->state != FL_READY){ | |
1da177e4 LT |
1063 | set_current_state(TASK_UNINTERRUPTIBLE); |
1064 | add_wait_queue(&chip->wq, &wait); | |
1f948b43 | 1065 | |
c4e77376 | 1066 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1067 | |
1068 | schedule(); | |
1069 | remove_wait_queue(&chip->wq, &wait); | |
1da177e4 LT |
1070 | timeo = jiffies + HZ; |
1071 | ||
1072 | goto retry; | |
1f948b43 | 1073 | } |
1da177e4 LT |
1074 | |
1075 | adr += chip->start; | |
1076 | ||
1077 | chip->state = FL_READY; | |
1078 | ||
1079 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1080 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1081 | cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1f948b43 | 1082 | |
1da177e4 LT |
1083 | map_copy_from(map, buf, adr, len); |
1084 | ||
1085 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1086 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1087 | cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1088 | cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1f948b43 | 1089 | |
1da177e4 | 1090 | wake_up(&chip->wq); |
c4e77376 | 1091 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1092 | |
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) | |
1097 | { | |
1098 | struct map_info *map = mtd->priv; | |
1099 | struct cfi_private *cfi = map->fldrv_priv; | |
1100 | unsigned long ofs; | |
1101 | int chipnum; | |
1102 | int ret = 0; | |
1103 | ||
1104 | ||
1105 | /* ofs: offset within the first chip that the first read should start */ | |
1106 | ||
1107 | /* 8 secsi bytes per chip */ | |
1108 | chipnum=from>>3; | |
1109 | ofs=from & 7; | |
1110 | ||
1111 | ||
1112 | *retlen = 0; | |
1113 | ||
1114 | while (len) { | |
1115 | unsigned long thislen; | |
1116 | ||
1117 | if (chipnum >= cfi->numchips) | |
1118 | break; | |
1119 | ||
1120 | if ((len + ofs -1) >> 3) | |
1121 | thislen = (1<<3) - ofs; | |
1122 | else | |
1123 | thislen = len; | |
1124 | ||
1125 | ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf); | |
1126 | if (ret) | |
1127 | break; | |
1128 | ||
1129 | *retlen += thislen; | |
1130 | len -= thislen; | |
1131 | buf += thislen; | |
1132 | ||
1133 | ofs = 0; | |
1134 | chipnum++; | |
1135 | } | |
1136 | return ret; | |
1137 | } | |
1138 | ||
1139 | ||
02b15e34 | 1140 | static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum) |
1da177e4 LT |
1141 | { |
1142 | struct cfi_private *cfi = map->fldrv_priv; | |
1143 | unsigned long timeo = jiffies + HZ; | |
1144 | /* | |
1145 | * We use a 1ms + 1 jiffies generic timeout for writes (most devices | |
1146 | * have a max write time of a few hundreds usec). However, we should | |
1147 | * use the maximum timeout value given by the chip at probe time | |
1148 | * instead. Unfortunately, struct flchip does have a field for | |
1149 | * maximum timeout, only for typical which can be far too short | |
1150 | * depending of the conditions. The ' + 1' is to avoid having a | |
1151 | * timeout of 0 jiffies if HZ is smaller than 1000. | |
1152 | */ | |
1153 | unsigned long uWriteTimeout = ( HZ / 1000 ) + 1; | |
1154 | int ret = 0; | |
1155 | map_word oldd; | |
1156 | int retry_cnt = 0; | |
1157 | ||
1158 | adr += chip->start; | |
1159 | ||
c4e77376 | 1160 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1161 | ret = get_chip(map, chip, adr, FL_WRITING); |
1162 | if (ret) { | |
c4e77376 | 1163 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1164 | return ret; |
1165 | } | |
1166 | ||
289c0522 | 1167 | pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", |
1da177e4 LT |
1168 | __func__, adr, datum.x[0] ); |
1169 | ||
1170 | /* | |
1171 | * Check for a NOP for the case when the datum to write is already | |
1172 | * present - it saves time and works around buggy chips that corrupt | |
1173 | * data at other locations when 0xff is written to a location that | |
1174 | * already contains 0xff. | |
1175 | */ | |
1176 | oldd = map_read(map, adr); | |
1177 | if (map_word_equal(map, oldd, datum)) { | |
289c0522 | 1178 | pr_debug("MTD %s(): NOP\n", |
1da177e4 LT |
1179 | __func__); |
1180 | goto op_done; | |
1181 | } | |
1182 | ||
02b15e34 | 1183 | XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map)); |
1da177e4 | 1184 | ENABLE_VPP(map); |
02b15e34 | 1185 | xip_disable(map, chip, adr); |
1da177e4 LT |
1186 | retry: |
1187 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1188 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1189 | cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1190 | map_write(map, datum, adr); | |
1191 | chip->state = FL_WRITING; | |
1192 | ||
02b15e34 TP |
1193 | INVALIDATE_CACHE_UDELAY(map, chip, |
1194 | adr, map_bankwidth(map), | |
1195 | chip->word_write_time); | |
1da177e4 LT |
1196 | |
1197 | /* See comment above for timeout value. */ | |
1f948b43 | 1198 | timeo = jiffies + uWriteTimeout; |
1da177e4 LT |
1199 | for (;;) { |
1200 | if (chip->state != FL_WRITING) { | |
1201 | /* Someone's suspended the write. Sleep */ | |
1202 | DECLARE_WAITQUEUE(wait, current); | |
1203 | ||
1204 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1205 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1206 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1207 | schedule(); |
1208 | remove_wait_queue(&chip->wq, &wait); | |
1209 | timeo = jiffies + (HZ / 2); /* FIXME */ | |
c4e77376 | 1210 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1211 | continue; |
1212 | } | |
1213 | ||
b95f9609 | 1214 | if (time_after(jiffies, timeo) && !chip_ready(map, adr)){ |
02b15e34 | 1215 | xip_enable(map, chip, adr); |
fb4a90bf | 1216 | printk(KERN_WARNING "MTD %s(): software timeout\n", __func__); |
02b15e34 | 1217 | xip_disable(map, chip, adr); |
b95f9609 | 1218 | break; |
fb4a90bf | 1219 | } |
1da177e4 | 1220 | |
b95f9609 KB |
1221 | if (chip_ready(map, adr)) |
1222 | break; | |
1223 | ||
1da177e4 | 1224 | /* Latency issues. Drop the lock, wait a while and retry */ |
02b15e34 | 1225 | UDELAY(map, chip, adr, 1); |
1da177e4 | 1226 | } |
fb4a90bf EB |
1227 | /* Did we succeed? */ |
1228 | if (!chip_good(map, adr, datum)) { | |
1229 | /* reset on all failures. */ | |
1230 | map_write( map, CMD(0xF0), chip->start ); | |
1231 | /* FIXME - should have reset delay before continuing */ | |
1da177e4 | 1232 | |
1f948b43 | 1233 | if (++retry_cnt <= MAX_WORD_RETRIES) |
fb4a90bf | 1234 | goto retry; |
1da177e4 | 1235 | |
fb4a90bf EB |
1236 | ret = -EIO; |
1237 | } | |
02b15e34 | 1238 | xip_enable(map, chip, adr); |
1da177e4 LT |
1239 | op_done: |
1240 | chip->state = FL_READY; | |
1241 | put_chip(map, chip, adr); | |
c4e77376 | 1242 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1243 | |
1244 | return ret; | |
1245 | } | |
1246 | ||
1247 | ||
1248 | static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len, | |
1249 | size_t *retlen, const u_char *buf) | |
1250 | { | |
1251 | struct map_info *map = mtd->priv; | |
1252 | struct cfi_private *cfi = map->fldrv_priv; | |
1253 | int ret = 0; | |
1254 | int chipnum; | |
1255 | unsigned long ofs, chipstart; | |
1256 | DECLARE_WAITQUEUE(wait, current); | |
1257 | ||
1258 | *retlen = 0; | |
1259 | if (!len) | |
1260 | return 0; | |
1261 | ||
1262 | chipnum = to >> cfi->chipshift; | |
1263 | ofs = to - (chipnum << cfi->chipshift); | |
1264 | chipstart = cfi->chips[chipnum].start; | |
1265 | ||
1266 | /* If it's not bus-aligned, do the first byte write */ | |
1267 | if (ofs & (map_bankwidth(map)-1)) { | |
1268 | unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1); | |
1269 | int i = ofs - bus_ofs; | |
1270 | int n = 0; | |
1271 | map_word tmp_buf; | |
1272 | ||
1273 | retry: | |
c4e77376 | 1274 | mutex_lock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1275 | |
1276 | if (cfi->chips[chipnum].state != FL_READY) { | |
1da177e4 LT |
1277 | set_current_state(TASK_UNINTERRUPTIBLE); |
1278 | add_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1279 | ||
c4e77376 | 1280 | mutex_unlock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1281 | |
1282 | schedule(); | |
1283 | remove_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1da177e4 LT |
1284 | goto retry; |
1285 | } | |
1286 | ||
1287 | /* Load 'tmp_buf' with old contents of flash */ | |
1288 | tmp_buf = map_read(map, bus_ofs+chipstart); | |
1289 | ||
c4e77376 | 1290 | mutex_unlock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1291 | |
1292 | /* Number of bytes to copy from buffer */ | |
1293 | n = min_t(int, len, map_bankwidth(map)-i); | |
1f948b43 | 1294 | |
1da177e4 LT |
1295 | tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n); |
1296 | ||
1f948b43 | 1297 | ret = do_write_oneword(map, &cfi->chips[chipnum], |
1da177e4 | 1298 | bus_ofs, tmp_buf); |
1f948b43 | 1299 | if (ret) |
1da177e4 | 1300 | return ret; |
1f948b43 | 1301 | |
1da177e4 LT |
1302 | ofs += n; |
1303 | buf += n; | |
1304 | (*retlen) += n; | |
1305 | len -= n; | |
1306 | ||
1307 | if (ofs >> cfi->chipshift) { | |
1f948b43 | 1308 | chipnum ++; |
1da177e4 LT |
1309 | ofs = 0; |
1310 | if (chipnum == cfi->numchips) | |
1311 | return 0; | |
1312 | } | |
1313 | } | |
1f948b43 | 1314 | |
1da177e4 LT |
1315 | /* We are now aligned, write as much as possible */ |
1316 | while(len >= map_bankwidth(map)) { | |
1317 | map_word datum; | |
1318 | ||
1319 | datum = map_word_load(map, buf); | |
1320 | ||
1321 | ret = do_write_oneword(map, &cfi->chips[chipnum], | |
1322 | ofs, datum); | |
1323 | if (ret) | |
1324 | return ret; | |
1325 | ||
1326 | ofs += map_bankwidth(map); | |
1327 | buf += map_bankwidth(map); | |
1328 | (*retlen) += map_bankwidth(map); | |
1329 | len -= map_bankwidth(map); | |
1330 | ||
1331 | if (ofs >> cfi->chipshift) { | |
1f948b43 | 1332 | chipnum ++; |
1da177e4 LT |
1333 | ofs = 0; |
1334 | if (chipnum == cfi->numchips) | |
1335 | return 0; | |
1336 | chipstart = cfi->chips[chipnum].start; | |
1337 | } | |
1338 | } | |
1339 | ||
1340 | /* Write the trailing bytes if any */ | |
1341 | if (len & (map_bankwidth(map)-1)) { | |
1342 | map_word tmp_buf; | |
1343 | ||
1344 | retry1: | |
c4e77376 | 1345 | mutex_lock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1346 | |
1347 | if (cfi->chips[chipnum].state != FL_READY) { | |
1da177e4 LT |
1348 | set_current_state(TASK_UNINTERRUPTIBLE); |
1349 | add_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1350 | ||
c4e77376 | 1351 | mutex_unlock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1352 | |
1353 | schedule(); | |
1354 | remove_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1da177e4 LT |
1355 | goto retry1; |
1356 | } | |
1357 | ||
1358 | tmp_buf = map_read(map, ofs + chipstart); | |
1359 | ||
c4e77376 | 1360 | mutex_unlock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1361 | |
1362 | tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len); | |
1f948b43 TG |
1363 | |
1364 | ret = do_write_oneword(map, &cfi->chips[chipnum], | |
1da177e4 | 1365 | ofs, tmp_buf); |
1f948b43 | 1366 | if (ret) |
1da177e4 | 1367 | return ret; |
1f948b43 | 1368 | |
1da177e4 LT |
1369 | (*retlen) += len; |
1370 | } | |
1371 | ||
1372 | return 0; | |
1373 | } | |
1374 | ||
1375 | ||
1376 | /* | |
1377 | * FIXME: interleaved mode not tested, and probably not supported! | |
1378 | */ | |
02b15e34 | 1379 | static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, |
1f948b43 | 1380 | unsigned long adr, const u_char *buf, |
02b15e34 | 1381 | int len) |
1da177e4 LT |
1382 | { |
1383 | struct cfi_private *cfi = map->fldrv_priv; | |
1384 | unsigned long timeo = jiffies + HZ; | |
1385 | /* see comments in do_write_oneword() regarding uWriteTimeo. */ | |
1386 | unsigned long uWriteTimeout = ( HZ / 1000 ) + 1; | |
1387 | int ret = -EIO; | |
1388 | unsigned long cmd_adr; | |
1389 | int z, words; | |
1390 | map_word datum; | |
1391 | ||
1392 | adr += chip->start; | |
1393 | cmd_adr = adr; | |
1394 | ||
c4e77376 | 1395 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1396 | ret = get_chip(map, chip, adr, FL_WRITING); |
1397 | if (ret) { | |
c4e77376 | 1398 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1399 | return ret; |
1400 | } | |
1401 | ||
1402 | datum = map_word_load(map, buf); | |
1403 | ||
289c0522 | 1404 | pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", |
1da177e4 LT |
1405 | __func__, adr, datum.x[0] ); |
1406 | ||
02b15e34 | 1407 | XIP_INVAL_CACHED_RANGE(map, adr, len); |
1da177e4 | 1408 | ENABLE_VPP(map); |
02b15e34 | 1409 | xip_disable(map, chip, cmd_adr); |
1f948b43 | 1410 | |
1da177e4 LT |
1411 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); |
1412 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1da177e4 LT |
1413 | |
1414 | /* Write Buffer Load */ | |
1415 | map_write(map, CMD(0x25), cmd_adr); | |
1416 | ||
1417 | chip->state = FL_WRITING_TO_BUFFER; | |
1418 | ||
1419 | /* Write length of data to come */ | |
1420 | words = len / map_bankwidth(map); | |
1421 | map_write(map, CMD(words - 1), cmd_adr); | |
1422 | /* Write data */ | |
1423 | z = 0; | |
1424 | while(z < words * map_bankwidth(map)) { | |
1425 | datum = map_word_load(map, buf); | |
1426 | map_write(map, datum, adr + z); | |
1427 | ||
1428 | z += map_bankwidth(map); | |
1429 | buf += map_bankwidth(map); | |
1430 | } | |
1431 | z -= map_bankwidth(map); | |
1432 | ||
1433 | adr += z; | |
1434 | ||
1435 | /* Write Buffer Program Confirm: GO GO GO */ | |
1436 | map_write(map, CMD(0x29), cmd_adr); | |
1437 | chip->state = FL_WRITING; | |
1438 | ||
02b15e34 TP |
1439 | INVALIDATE_CACHE_UDELAY(map, chip, |
1440 | adr, map_bankwidth(map), | |
1441 | chip->word_write_time); | |
1da177e4 | 1442 | |
1f948b43 TG |
1443 | timeo = jiffies + uWriteTimeout; |
1444 | ||
1da177e4 LT |
1445 | for (;;) { |
1446 | if (chip->state != FL_WRITING) { | |
1447 | /* Someone's suspended the write. Sleep */ | |
1448 | DECLARE_WAITQUEUE(wait, current); | |
1449 | ||
1450 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1451 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1452 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1453 | schedule(); |
1454 | remove_wait_queue(&chip->wq, &wait); | |
1455 | timeo = jiffies + (HZ / 2); /* FIXME */ | |
c4e77376 | 1456 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1457 | continue; |
1458 | } | |
1459 | ||
b95f9609 KB |
1460 | if (time_after(jiffies, timeo) && !chip_ready(map, adr)) |
1461 | break; | |
1462 | ||
02b15e34 TP |
1463 | if (chip_ready(map, adr)) { |
1464 | xip_enable(map, chip, adr); | |
1da177e4 | 1465 | goto op_done; |
02b15e34 | 1466 | } |
1da177e4 LT |
1467 | |
1468 | /* Latency issues. Drop the lock, wait a while and retry */ | |
02b15e34 | 1469 | UDELAY(map, chip, adr, 1); |
1da177e4 LT |
1470 | } |
1471 | ||
1da177e4 LT |
1472 | /* reset on all failures. */ |
1473 | map_write( map, CMD(0xF0), chip->start ); | |
02b15e34 | 1474 | xip_enable(map, chip, adr); |
1da177e4 LT |
1475 | /* FIXME - should have reset delay before continuing */ |
1476 | ||
02b15e34 TP |
1477 | printk(KERN_WARNING "MTD %s(): software timeout\n", |
1478 | __func__ ); | |
1479 | ||
1da177e4 LT |
1480 | ret = -EIO; |
1481 | op_done: | |
1482 | chip->state = FL_READY; | |
1483 | put_chip(map, chip, adr); | |
c4e77376 | 1484 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1485 | |
1486 | return ret; | |
1487 | } | |
1488 | ||
1489 | ||
1490 | static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, | |
1491 | size_t *retlen, const u_char *buf) | |
1492 | { | |
1493 | struct map_info *map = mtd->priv; | |
1494 | struct cfi_private *cfi = map->fldrv_priv; | |
1495 | int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize; | |
1496 | int ret = 0; | |
1497 | int chipnum; | |
1498 | unsigned long ofs; | |
1499 | ||
1500 | *retlen = 0; | |
1501 | if (!len) | |
1502 | return 0; | |
1503 | ||
1504 | chipnum = to >> cfi->chipshift; | |
1505 | ofs = to - (chipnum << cfi->chipshift); | |
1506 | ||
1507 | /* If it's not bus-aligned, do the first word write */ | |
1508 | if (ofs & (map_bankwidth(map)-1)) { | |
1509 | size_t local_len = (-ofs)&(map_bankwidth(map)-1); | |
1510 | if (local_len > len) | |
1511 | local_len = len; | |
1512 | ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), | |
1513 | local_len, retlen, buf); | |
1514 | if (ret) | |
1515 | return ret; | |
1516 | ofs += local_len; | |
1517 | buf += local_len; | |
1518 | len -= local_len; | |
1519 | ||
1520 | if (ofs >> cfi->chipshift) { | |
1521 | chipnum ++; | |
1522 | ofs = 0; | |
1523 | if (chipnum == cfi->numchips) | |
1524 | return 0; | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | /* Write buffer is worth it only if more than one word to write... */ | |
1529 | while (len >= map_bankwidth(map) * 2) { | |
1530 | /* We must not cross write block boundaries */ | |
1531 | int size = wbufsize - (ofs & (wbufsize-1)); | |
1532 | ||
1533 | if (size > len) | |
1534 | size = len; | |
1535 | if (size % map_bankwidth(map)) | |
1536 | size -= size % map_bankwidth(map); | |
1537 | ||
1f948b43 | 1538 | ret = do_write_buffer(map, &cfi->chips[chipnum], |
1da177e4 LT |
1539 | ofs, buf, size); |
1540 | if (ret) | |
1541 | return ret; | |
1542 | ||
1543 | ofs += size; | |
1544 | buf += size; | |
1545 | (*retlen) += size; | |
1546 | len -= size; | |
1547 | ||
1548 | if (ofs >> cfi->chipshift) { | |
1f948b43 | 1549 | chipnum ++; |
1da177e4 LT |
1550 | ofs = 0; |
1551 | if (chipnum == cfi->numchips) | |
1552 | return 0; | |
1553 | } | |
1554 | } | |
1555 | ||
1556 | if (len) { | |
1557 | size_t retlen_dregs = 0; | |
1558 | ||
1559 | ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), | |
1560 | len, &retlen_dregs, buf); | |
1561 | ||
1562 | *retlen += retlen_dregs; | |
1563 | return ret; | |
1564 | } | |
1565 | ||
1566 | return 0; | |
1567 | } | |
1568 | ||
30ec5a2c IS |
1569 | /* |
1570 | * Wait for the flash chip to become ready to write data | |
1571 | * | |
1572 | * This is only called during the panic_write() path. When panic_write() | |
1573 | * is called, the kernel is in the process of a panic, and will soon be | |
1574 | * dead. Therefore we don't take any locks, and attempt to get access | |
1575 | * to the chip as soon as possible. | |
1576 | */ | |
1577 | static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip, | |
1578 | unsigned long adr) | |
1579 | { | |
1580 | struct cfi_private *cfi = map->fldrv_priv; | |
1581 | int retries = 10; | |
1582 | int i; | |
1583 | ||
1584 | /* | |
1585 | * If the driver thinks the chip is idle, and no toggle bits | |
1586 | * are changing, then the chip is actually idle for sure. | |
1587 | */ | |
1588 | if (chip->state == FL_READY && chip_ready(map, adr)) | |
1589 | return 0; | |
1590 | ||
1591 | /* | |
1592 | * Try several times to reset the chip and then wait for it | |
1593 | * to become idle. The upper limit of a few milliseconds of | |
1594 | * delay isn't a big problem: the kernel is dying anyway. It | |
1595 | * is more important to save the messages. | |
1596 | */ | |
1597 | while (retries > 0) { | |
1598 | const unsigned long timeo = (HZ / 1000) + 1; | |
1599 | ||
1600 | /* send the reset command */ | |
1601 | map_write(map, CMD(0xF0), chip->start); | |
1602 | ||
1603 | /* wait for the chip to become ready */ | |
1604 | for (i = 0; i < jiffies_to_usecs(timeo); i++) { | |
1605 | if (chip_ready(map, adr)) | |
1606 | return 0; | |
1607 | ||
1608 | udelay(1); | |
1609 | } | |
1610 | } | |
1611 | ||
1612 | /* the chip never became ready */ | |
1613 | return -EBUSY; | |
1614 | } | |
1615 | ||
1616 | /* | |
1617 | * Write out one word of data to a single flash chip during a kernel panic | |
1618 | * | |
1619 | * This is only called during the panic_write() path. When panic_write() | |
1620 | * is called, the kernel is in the process of a panic, and will soon be | |
1621 | * dead. Therefore we don't take any locks, and attempt to get access | |
1622 | * to the chip as soon as possible. | |
1623 | * | |
1624 | * The implementation of this routine is intentionally similar to | |
1625 | * do_write_oneword(), in order to ease code maintenance. | |
1626 | */ | |
1627 | static int do_panic_write_oneword(struct map_info *map, struct flchip *chip, | |
1628 | unsigned long adr, map_word datum) | |
1629 | { | |
1630 | const unsigned long uWriteTimeout = (HZ / 1000) + 1; | |
1631 | struct cfi_private *cfi = map->fldrv_priv; | |
1632 | int retry_cnt = 0; | |
1633 | map_word oldd; | |
1634 | int ret = 0; | |
1635 | int i; | |
1636 | ||
1637 | adr += chip->start; | |
1638 | ||
1639 | ret = cfi_amdstd_panic_wait(map, chip, adr); | |
1640 | if (ret) | |
1641 | return ret; | |
1642 | ||
1643 | pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n", | |
1644 | __func__, adr, datum.x[0]); | |
1645 | ||
1646 | /* | |
1647 | * Check for a NOP for the case when the datum to write is already | |
1648 | * present - it saves time and works around buggy chips that corrupt | |
1649 | * data at other locations when 0xff is written to a location that | |
1650 | * already contains 0xff. | |
1651 | */ | |
1652 | oldd = map_read(map, adr); | |
1653 | if (map_word_equal(map, oldd, datum)) { | |
1654 | pr_debug("MTD %s(): NOP\n", __func__); | |
1655 | goto op_done; | |
1656 | } | |
1657 | ||
1658 | ENABLE_VPP(map); | |
1659 | ||
1660 | retry: | |
1661 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1662 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1663 | cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1664 | map_write(map, datum, adr); | |
1665 | ||
1666 | for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) { | |
1667 | if (chip_ready(map, adr)) | |
1668 | break; | |
1669 | ||
1670 | udelay(1); | |
1671 | } | |
1672 | ||
1673 | if (!chip_good(map, adr, datum)) { | |
1674 | /* reset on all failures. */ | |
1675 | map_write(map, CMD(0xF0), chip->start); | |
1676 | /* FIXME - should have reset delay before continuing */ | |
1677 | ||
1678 | if (++retry_cnt <= MAX_WORD_RETRIES) | |
1679 | goto retry; | |
1680 | ||
1681 | ret = -EIO; | |
1682 | } | |
1683 | ||
1684 | op_done: | |
1685 | DISABLE_VPP(map); | |
1686 | return ret; | |
1687 | } | |
1688 | ||
1689 | /* | |
1690 | * Write out some data during a kernel panic | |
1691 | * | |
1692 | * This is used by the mtdoops driver to save the dying messages from a | |
1693 | * kernel which has panic'd. | |
1694 | * | |
1695 | * This routine ignores all of the locking used throughout the rest of the | |
1696 | * driver, in order to ensure that the data gets written out no matter what | |
1697 | * state this driver (and the flash chip itself) was in when the kernel crashed. | |
1698 | * | |
1699 | * The implementation of this routine is intentionally similar to | |
1700 | * cfi_amdstd_write_words(), in order to ease code maintenance. | |
1701 | */ | |
1702 | static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, | |
1703 | size_t *retlen, const u_char *buf) | |
1704 | { | |
1705 | struct map_info *map = mtd->priv; | |
1706 | struct cfi_private *cfi = map->fldrv_priv; | |
1707 | unsigned long ofs, chipstart; | |
1708 | int ret = 0; | |
1709 | int chipnum; | |
1710 | ||
1711 | *retlen = 0; | |
1712 | if (!len) | |
1713 | return 0; | |
1714 | ||
1715 | chipnum = to >> cfi->chipshift; | |
1716 | ofs = to - (chipnum << cfi->chipshift); | |
1717 | chipstart = cfi->chips[chipnum].start; | |
1718 | ||
1719 | /* If it's not bus aligned, do the first byte write */ | |
1720 | if (ofs & (map_bankwidth(map) - 1)) { | |
1721 | unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1); | |
1722 | int i = ofs - bus_ofs; | |
1723 | int n = 0; | |
1724 | map_word tmp_buf; | |
1725 | ||
1726 | ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs); | |
1727 | if (ret) | |
1728 | return ret; | |
1729 | ||
1730 | /* Load 'tmp_buf' with old contents of flash */ | |
1731 | tmp_buf = map_read(map, bus_ofs + chipstart); | |
1732 | ||
1733 | /* Number of bytes to copy from buffer */ | |
1734 | n = min_t(int, len, map_bankwidth(map) - i); | |
1735 | ||
1736 | tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n); | |
1737 | ||
1738 | ret = do_panic_write_oneword(map, &cfi->chips[chipnum], | |
1739 | bus_ofs, tmp_buf); | |
1740 | if (ret) | |
1741 | return ret; | |
1742 | ||
1743 | ofs += n; | |
1744 | buf += n; | |
1745 | (*retlen) += n; | |
1746 | len -= n; | |
1747 | ||
1748 | if (ofs >> cfi->chipshift) { | |
1749 | chipnum++; | |
1750 | ofs = 0; | |
1751 | if (chipnum == cfi->numchips) | |
1752 | return 0; | |
1753 | } | |
1754 | } | |
1755 | ||
1756 | /* We are now aligned, write as much as possible */ | |
1757 | while (len >= map_bankwidth(map)) { | |
1758 | map_word datum; | |
1759 | ||
1760 | datum = map_word_load(map, buf); | |
1761 | ||
1762 | ret = do_panic_write_oneword(map, &cfi->chips[chipnum], | |
1763 | ofs, datum); | |
1764 | if (ret) | |
1765 | return ret; | |
1766 | ||
1767 | ofs += map_bankwidth(map); | |
1768 | buf += map_bankwidth(map); | |
1769 | (*retlen) += map_bankwidth(map); | |
1770 | len -= map_bankwidth(map); | |
1771 | ||
1772 | if (ofs >> cfi->chipshift) { | |
1773 | chipnum++; | |
1774 | ofs = 0; | |
1775 | if (chipnum == cfi->numchips) | |
1776 | return 0; | |
1777 | ||
1778 | chipstart = cfi->chips[chipnum].start; | |
1779 | } | |
1780 | } | |
1781 | ||
1782 | /* Write the trailing bytes if any */ | |
1783 | if (len & (map_bankwidth(map) - 1)) { | |
1784 | map_word tmp_buf; | |
1785 | ||
1786 | ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs); | |
1787 | if (ret) | |
1788 | return ret; | |
1789 | ||
1790 | tmp_buf = map_read(map, ofs + chipstart); | |
1791 | ||
1792 | tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len); | |
1793 | ||
1794 | ret = do_panic_write_oneword(map, &cfi->chips[chipnum], | |
1795 | ofs, tmp_buf); | |
1796 | if (ret) | |
1797 | return ret; | |
1798 | ||
1799 | (*retlen) += len; | |
1800 | } | |
1801 | ||
1802 | return 0; | |
1803 | } | |
1804 | ||
1da177e4 LT |
1805 | |
1806 | /* | |
1807 | * Handle devices with one erase region, that only implement | |
1808 | * the chip erase command. | |
1809 | */ | |
02b15e34 | 1810 | static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip) |
1da177e4 LT |
1811 | { |
1812 | struct cfi_private *cfi = map->fldrv_priv; | |
1813 | unsigned long timeo = jiffies + HZ; | |
1814 | unsigned long int adr; | |
1815 | DECLARE_WAITQUEUE(wait, current); | |
1816 | int ret = 0; | |
1817 | ||
1818 | adr = cfi->addr_unlock1; | |
1819 | ||
c4e77376 | 1820 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1821 | ret = get_chip(map, chip, adr, FL_WRITING); |
1822 | if (ret) { | |
c4e77376 | 1823 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1824 | return ret; |
1825 | } | |
1826 | ||
289c0522 | 1827 | pr_debug("MTD %s(): ERASE 0x%.8lx\n", |
1da177e4 LT |
1828 | __func__, chip->start ); |
1829 | ||
02b15e34 | 1830 | XIP_INVAL_CACHED_RANGE(map, adr, map->size); |
1da177e4 | 1831 | ENABLE_VPP(map); |
02b15e34 TP |
1832 | xip_disable(map, chip, adr); |
1833 | ||
1da177e4 LT |
1834 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); |
1835 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1836 | cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1837 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1838 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1839 | cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1840 | ||
1841 | chip->state = FL_ERASING; | |
1842 | chip->erase_suspended = 0; | |
1843 | chip->in_progress_block_addr = adr; | |
1844 | ||
02b15e34 TP |
1845 | INVALIDATE_CACHE_UDELAY(map, chip, |
1846 | adr, map->size, | |
1847 | chip->erase_time*500); | |
1da177e4 LT |
1848 | |
1849 | timeo = jiffies + (HZ*20); | |
1850 | ||
1851 | for (;;) { | |
1852 | if (chip->state != FL_ERASING) { | |
1853 | /* Someone's suspended the erase. Sleep */ | |
1854 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1855 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1856 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1857 | schedule(); |
1858 | remove_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1859 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1860 | continue; |
1861 | } | |
1862 | if (chip->erase_suspended) { | |
1863 | /* This erase was suspended and resumed. | |
1864 | Adjust the timeout */ | |
1865 | timeo = jiffies + (HZ*20); /* FIXME */ | |
1866 | chip->erase_suspended = 0; | |
1867 | } | |
1868 | ||
1869 | if (chip_ready(map, adr)) | |
fb4a90bf | 1870 | break; |
1da177e4 | 1871 | |
fb4a90bf EB |
1872 | if (time_after(jiffies, timeo)) { |
1873 | printk(KERN_WARNING "MTD %s(): software timeout\n", | |
1874 | __func__ ); | |
1da177e4 | 1875 | break; |
fb4a90bf | 1876 | } |
1da177e4 LT |
1877 | |
1878 | /* Latency issues. Drop the lock, wait a while and retry */ | |
02b15e34 | 1879 | UDELAY(map, chip, adr, 1000000/HZ); |
1da177e4 | 1880 | } |
fb4a90bf EB |
1881 | /* Did we succeed? */ |
1882 | if (!chip_good(map, adr, map_word_ff(map))) { | |
1883 | /* reset on all failures. */ | |
1884 | map_write( map, CMD(0xF0), chip->start ); | |
1885 | /* FIXME - should have reset delay before continuing */ | |
1da177e4 | 1886 | |
fb4a90bf EB |
1887 | ret = -EIO; |
1888 | } | |
1da177e4 | 1889 | |
1da177e4 | 1890 | chip->state = FL_READY; |
02b15e34 | 1891 | xip_enable(map, chip, adr); |
1da177e4 | 1892 | put_chip(map, chip, adr); |
c4e77376 | 1893 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1894 | |
1895 | return ret; | |
1896 | } | |
1897 | ||
1898 | ||
02b15e34 | 1899 | static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk) |
1da177e4 LT |
1900 | { |
1901 | struct cfi_private *cfi = map->fldrv_priv; | |
1902 | unsigned long timeo = jiffies + HZ; | |
1903 | DECLARE_WAITQUEUE(wait, current); | |
1904 | int ret = 0; | |
1905 | ||
1906 | adr += chip->start; | |
1907 | ||
c4e77376 | 1908 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1909 | ret = get_chip(map, chip, adr, FL_ERASING); |
1910 | if (ret) { | |
c4e77376 | 1911 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1912 | return ret; |
1913 | } | |
1914 | ||
289c0522 | 1915 | pr_debug("MTD %s(): ERASE 0x%.8lx\n", |
1da177e4 LT |
1916 | __func__, adr ); |
1917 | ||
02b15e34 | 1918 | XIP_INVAL_CACHED_RANGE(map, adr, len); |
1da177e4 | 1919 | ENABLE_VPP(map); |
02b15e34 TP |
1920 | xip_disable(map, chip, adr); |
1921 | ||
1da177e4 LT |
1922 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); |
1923 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1924 | cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1925 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1926 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
08968041 | 1927 | map_write(map, cfi->sector_erase_cmd, adr); |
1da177e4 LT |
1928 | |
1929 | chip->state = FL_ERASING; | |
1930 | chip->erase_suspended = 0; | |
1931 | chip->in_progress_block_addr = adr; | |
02b15e34 TP |
1932 | |
1933 | INVALIDATE_CACHE_UDELAY(map, chip, | |
1934 | adr, len, | |
1935 | chip->erase_time*500); | |
1da177e4 LT |
1936 | |
1937 | timeo = jiffies + (HZ*20); | |
1938 | ||
1939 | for (;;) { | |
1940 | if (chip->state != FL_ERASING) { | |
1941 | /* Someone's suspended the erase. Sleep */ | |
1942 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1943 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1944 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1945 | schedule(); |
1946 | remove_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1947 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1948 | continue; |
1949 | } | |
1950 | if (chip->erase_suspended) { | |
1951 | /* This erase was suspended and resumed. | |
1952 | Adjust the timeout */ | |
1953 | timeo = jiffies + (HZ*20); /* FIXME */ | |
1954 | chip->erase_suspended = 0; | |
1955 | } | |
1956 | ||
02b15e34 TP |
1957 | if (chip_ready(map, adr)) { |
1958 | xip_enable(map, chip, adr); | |
fb4a90bf | 1959 | break; |
02b15e34 | 1960 | } |
1da177e4 | 1961 | |
fb4a90bf | 1962 | if (time_after(jiffies, timeo)) { |
02b15e34 | 1963 | xip_enable(map, chip, adr); |
fb4a90bf EB |
1964 | printk(KERN_WARNING "MTD %s(): software timeout\n", |
1965 | __func__ ); | |
1da177e4 | 1966 | break; |
fb4a90bf | 1967 | } |
1da177e4 LT |
1968 | |
1969 | /* Latency issues. Drop the lock, wait a while and retry */ | |
02b15e34 | 1970 | UDELAY(map, chip, adr, 1000000/HZ); |
1da177e4 | 1971 | } |
fb4a90bf | 1972 | /* Did we succeed? */ |
22fd9a87 | 1973 | if (!chip_good(map, adr, map_word_ff(map))) { |
fb4a90bf EB |
1974 | /* reset on all failures. */ |
1975 | map_write( map, CMD(0xF0), chip->start ); | |
1976 | /* FIXME - should have reset delay before continuing */ | |
1977 | ||
1978 | ret = -EIO; | |
1979 | } | |
1da177e4 | 1980 | |
1da177e4 LT |
1981 | chip->state = FL_READY; |
1982 | put_chip(map, chip, adr); | |
c4e77376 | 1983 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1984 | return ret; |
1985 | } | |
1986 | ||
1987 | ||
ce0f33ad | 1988 | static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 LT |
1989 | { |
1990 | unsigned long ofs, len; | |
1991 | int ret; | |
1992 | ||
1993 | ofs = instr->addr; | |
1994 | len = instr->len; | |
1995 | ||
1996 | ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL); | |
1997 | if (ret) | |
1998 | return ret; | |
1999 | ||
2000 | instr->state = MTD_ERASE_DONE; | |
2001 | mtd_erase_callback(instr); | |
1f948b43 | 2002 | |
1da177e4 LT |
2003 | return 0; |
2004 | } | |
2005 | ||
2006 | ||
2007 | static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr) | |
2008 | { | |
2009 | struct map_info *map = mtd->priv; | |
2010 | struct cfi_private *cfi = map->fldrv_priv; | |
2011 | int ret = 0; | |
2012 | ||
2013 | if (instr->addr != 0) | |
2014 | return -EINVAL; | |
2015 | ||
2016 | if (instr->len != mtd->size) | |
2017 | return -EINVAL; | |
2018 | ||
2019 | ret = do_erase_chip(map, &cfi->chips[0]); | |
2020 | if (ret) | |
2021 | return ret; | |
2022 | ||
2023 | instr->state = MTD_ERASE_DONE; | |
2024 | mtd_erase_callback(instr); | |
1f948b43 | 2025 | |
1da177e4 LT |
2026 | return 0; |
2027 | } | |
2028 | ||
0165508c HS |
2029 | static int do_atmel_lock(struct map_info *map, struct flchip *chip, |
2030 | unsigned long adr, int len, void *thunk) | |
2031 | { | |
2032 | struct cfi_private *cfi = map->fldrv_priv; | |
2033 | int ret; | |
2034 | ||
c4e77376 | 2035 | mutex_lock(&chip->mutex); |
0165508c HS |
2036 | ret = get_chip(map, chip, adr + chip->start, FL_LOCKING); |
2037 | if (ret) | |
2038 | goto out_unlock; | |
2039 | chip->state = FL_LOCKING; | |
2040 | ||
0a32a102 | 2041 | pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len); |
0165508c HS |
2042 | |
2043 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, | |
2044 | cfi->device_type, NULL); | |
2045 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, | |
2046 | cfi->device_type, NULL); | |
2047 | cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, | |
2048 | cfi->device_type, NULL); | |
2049 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, | |
2050 | cfi->device_type, NULL); | |
2051 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, | |
2052 | cfi->device_type, NULL); | |
2053 | map_write(map, CMD(0x40), chip->start + adr); | |
2054 | ||
2055 | chip->state = FL_READY; | |
2056 | put_chip(map, chip, adr + chip->start); | |
2057 | ret = 0; | |
2058 | ||
2059 | out_unlock: | |
c4e77376 | 2060 | mutex_unlock(&chip->mutex); |
0165508c HS |
2061 | return ret; |
2062 | } | |
2063 | ||
2064 | static int do_atmel_unlock(struct map_info *map, struct flchip *chip, | |
2065 | unsigned long adr, int len, void *thunk) | |
2066 | { | |
2067 | struct cfi_private *cfi = map->fldrv_priv; | |
2068 | int ret; | |
2069 | ||
c4e77376 | 2070 | mutex_lock(&chip->mutex); |
0165508c HS |
2071 | ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING); |
2072 | if (ret) | |
2073 | goto out_unlock; | |
2074 | chip->state = FL_UNLOCKING; | |
2075 | ||
0a32a102 | 2076 | pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len); |
0165508c HS |
2077 | |
2078 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, | |
2079 | cfi->device_type, NULL); | |
2080 | map_write(map, CMD(0x70), adr); | |
2081 | ||
2082 | chip->state = FL_READY; | |
2083 | put_chip(map, chip, adr + chip->start); | |
2084 | ret = 0; | |
2085 | ||
2086 | out_unlock: | |
c4e77376 | 2087 | mutex_unlock(&chip->mutex); |
0165508c HS |
2088 | return ret; |
2089 | } | |
2090 | ||
69423d99 | 2091 | static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
0165508c HS |
2092 | { |
2093 | return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL); | |
2094 | } | |
2095 | ||
69423d99 | 2096 | static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
0165508c HS |
2097 | { |
2098 | return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL); | |
2099 | } | |
2100 | ||
1da177e4 LT |
2101 | |
2102 | static void cfi_amdstd_sync (struct mtd_info *mtd) | |
2103 | { | |
2104 | struct map_info *map = mtd->priv; | |
2105 | struct cfi_private *cfi = map->fldrv_priv; | |
2106 | int i; | |
2107 | struct flchip *chip; | |
2108 | int ret = 0; | |
2109 | DECLARE_WAITQUEUE(wait, current); | |
2110 | ||
2111 | for (i=0; !ret && i<cfi->numchips; i++) { | |
2112 | chip = &cfi->chips[i]; | |
2113 | ||
2114 | retry: | |
c4e77376 | 2115 | mutex_lock(&chip->mutex); |
1da177e4 LT |
2116 | |
2117 | switch(chip->state) { | |
2118 | case FL_READY: | |
2119 | case FL_STATUS: | |
2120 | case FL_CFI_QUERY: | |
2121 | case FL_JEDEC_QUERY: | |
2122 | chip->oldstate = chip->state; | |
2123 | chip->state = FL_SYNCING; | |
1f948b43 | 2124 | /* No need to wake_up() on this state change - |
1da177e4 LT |
2125 | * as the whole point is that nobody can do anything |
2126 | * with the chip now anyway. | |
2127 | */ | |
2128 | case FL_SYNCING: | |
c4e77376 | 2129 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
2130 | break; |
2131 | ||
2132 | default: | |
2133 | /* Not an idle state */ | |
f8e30e44 | 2134 | set_current_state(TASK_UNINTERRUPTIBLE); |
1da177e4 | 2135 | add_wait_queue(&chip->wq, &wait); |
1f948b43 | 2136 | |
c4e77376 | 2137 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
2138 | |
2139 | schedule(); | |
2140 | ||
2141 | remove_wait_queue(&chip->wq, &wait); | |
1f948b43 | 2142 | |
1da177e4 LT |
2143 | goto retry; |
2144 | } | |
2145 | } | |
2146 | ||
2147 | /* Unlock the chips again */ | |
2148 | ||
2149 | for (i--; i >=0; i--) { | |
2150 | chip = &cfi->chips[i]; | |
2151 | ||
c4e77376 | 2152 | mutex_lock(&chip->mutex); |
1f948b43 | 2153 | |
1da177e4 LT |
2154 | if (chip->state == FL_SYNCING) { |
2155 | chip->state = chip->oldstate; | |
2156 | wake_up(&chip->wq); | |
2157 | } | |
c4e77376 | 2158 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
2159 | } |
2160 | } | |
2161 | ||
2162 | ||
2163 | static int cfi_amdstd_suspend(struct mtd_info *mtd) | |
2164 | { | |
2165 | struct map_info *map = mtd->priv; | |
2166 | struct cfi_private *cfi = map->fldrv_priv; | |
2167 | int i; | |
2168 | struct flchip *chip; | |
2169 | int ret = 0; | |
2170 | ||
2171 | for (i=0; !ret && i<cfi->numchips; i++) { | |
2172 | chip = &cfi->chips[i]; | |
2173 | ||
c4e77376 | 2174 | mutex_lock(&chip->mutex); |
1da177e4 LT |
2175 | |
2176 | switch(chip->state) { | |
2177 | case FL_READY: | |
2178 | case FL_STATUS: | |
2179 | case FL_CFI_QUERY: | |
2180 | case FL_JEDEC_QUERY: | |
2181 | chip->oldstate = chip->state; | |
2182 | chip->state = FL_PM_SUSPENDED; | |
1f948b43 | 2183 | /* No need to wake_up() on this state change - |
1da177e4 LT |
2184 | * as the whole point is that nobody can do anything |
2185 | * with the chip now anyway. | |
2186 | */ | |
2187 | case FL_PM_SUSPENDED: | |
2188 | break; | |
2189 | ||
2190 | default: | |
2191 | ret = -EAGAIN; | |
2192 | break; | |
2193 | } | |
c4e77376 | 2194 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
2195 | } |
2196 | ||
2197 | /* Unlock the chips again */ | |
2198 | ||
2199 | if (ret) { | |
2200 | for (i--; i >=0; i--) { | |
2201 | chip = &cfi->chips[i]; | |
2202 | ||
c4e77376 | 2203 | mutex_lock(&chip->mutex); |
1f948b43 | 2204 | |
1da177e4 LT |
2205 | if (chip->state == FL_PM_SUSPENDED) { |
2206 | chip->state = chip->oldstate; | |
2207 | wake_up(&chip->wq); | |
2208 | } | |
c4e77376 | 2209 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
2210 | } |
2211 | } | |
1f948b43 | 2212 | |
1da177e4 LT |
2213 | return ret; |
2214 | } | |
2215 | ||
2216 | ||
2217 | static void cfi_amdstd_resume(struct mtd_info *mtd) | |
2218 | { | |
2219 | struct map_info *map = mtd->priv; | |
2220 | struct cfi_private *cfi = map->fldrv_priv; | |
2221 | int i; | |
2222 | struct flchip *chip; | |
2223 | ||
2224 | for (i=0; i<cfi->numchips; i++) { | |
1f948b43 | 2225 | |
1da177e4 LT |
2226 | chip = &cfi->chips[i]; |
2227 | ||
c4e77376 | 2228 | mutex_lock(&chip->mutex); |
1f948b43 | 2229 | |
1da177e4 LT |
2230 | if (chip->state == FL_PM_SUSPENDED) { |
2231 | chip->state = FL_READY; | |
2232 | map_write(map, CMD(0xF0), chip->start); | |
2233 | wake_up(&chip->wq); | |
2234 | } | |
2235 | else | |
2236 | printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n"); | |
2237 | ||
c4e77376 | 2238 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
2239 | } |
2240 | } | |
2241 | ||
eafe1311 KC |
2242 | |
2243 | /* | |
2244 | * Ensure that the flash device is put back into read array mode before | |
2245 | * unloading the driver or rebooting. On some systems, rebooting while | |
2246 | * the flash is in query/program/erase mode will prevent the CPU from | |
2247 | * fetching the bootloader code, requiring a hard reset or power cycle. | |
2248 | */ | |
2249 | static int cfi_amdstd_reset(struct mtd_info *mtd) | |
2250 | { | |
2251 | struct map_info *map = mtd->priv; | |
2252 | struct cfi_private *cfi = map->fldrv_priv; | |
2253 | int i, ret; | |
2254 | struct flchip *chip; | |
2255 | ||
2256 | for (i = 0; i < cfi->numchips; i++) { | |
2257 | ||
2258 | chip = &cfi->chips[i]; | |
2259 | ||
2260 | mutex_lock(&chip->mutex); | |
2261 | ||
2262 | ret = get_chip(map, chip, chip->start, FL_SHUTDOWN); | |
2263 | if (!ret) { | |
2264 | map_write(map, CMD(0xF0), chip->start); | |
2265 | chip->state = FL_SHUTDOWN; | |
2266 | put_chip(map, chip, chip->start); | |
2267 | } | |
2268 | ||
2269 | mutex_unlock(&chip->mutex); | |
2270 | } | |
2271 | ||
2272 | return 0; | |
2273 | } | |
2274 | ||
2275 | ||
2276 | static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val, | |
2277 | void *v) | |
2278 | { | |
2279 | struct mtd_info *mtd; | |
2280 | ||
2281 | mtd = container_of(nb, struct mtd_info, reboot_notifier); | |
2282 | cfi_amdstd_reset(mtd); | |
2283 | return NOTIFY_DONE; | |
2284 | } | |
2285 | ||
2286 | ||
1da177e4 LT |
2287 | static void cfi_amdstd_destroy(struct mtd_info *mtd) |
2288 | { | |
2289 | struct map_info *map = mtd->priv; | |
2290 | struct cfi_private *cfi = map->fldrv_priv; | |
fa671646 | 2291 | |
eafe1311 KC |
2292 | cfi_amdstd_reset(mtd); |
2293 | unregister_reboot_notifier(&mtd->reboot_notifier); | |
1da177e4 LT |
2294 | kfree(cfi->cmdset_priv); |
2295 | kfree(cfi->cfiq); | |
2296 | kfree(cfi); | |
2297 | kfree(mtd->eraseregions); | |
2298 | } | |
2299 | ||
1da177e4 LT |
2300 | MODULE_LICENSE("GPL"); |
2301 | MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al."); | |
2302 | MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips"); | |
80461128 | 2303 | MODULE_ALIAS("cfi_cmdset_0006"); |
1e804cec | 2304 | MODULE_ALIAS("cfi_cmdset_0701"); |