Commit | Line | Data |
---|---|---|
1f948b43 | 1 | /* |
1da177e4 LT |
2 | Common Flash Interface probe code. |
3 | (C) 2000 Red Hat. GPL'd. | |
1da177e4 LT |
4 | */ |
5 | ||
1da177e4 LT |
6 | #include <linux/module.h> |
7 | #include <linux/types.h> | |
8 | #include <linux/kernel.h> | |
9 | #include <linux/init.h> | |
10 | #include <asm/io.h> | |
11 | #include <asm/byteorder.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/interrupt.h> | |
15 | ||
16 | #include <linux/mtd/xip.h> | |
17 | #include <linux/mtd/map.h> | |
18 | #include <linux/mtd/cfi.h> | |
19 | #include <linux/mtd/gen_probe.h> | |
20 | ||
1f948b43 | 21 | //#define DEBUG_CFI |
1da177e4 LT |
22 | |
23 | #ifdef DEBUG_CFI | |
24 | static void print_cfi_ident(struct cfi_ident *); | |
25 | #endif | |
26 | ||
27 | static int cfi_probe_chip(struct map_info *map, __u32 base, | |
28 | unsigned long *chip_map, struct cfi_private *cfi); | |
29 | static int cfi_chip_setup(struct map_info *map, struct cfi_private *cfi); | |
30 | ||
31 | struct mtd_info *cfi_probe(struct map_info *map); | |
32 | ||
33 | #ifdef CONFIG_MTD_XIP | |
34 | ||
35 | /* only needed for short periods, so this is rather simple */ | |
36 | #define xip_disable() local_irq_disable() | |
37 | ||
38 | #define xip_allowed(base, map) \ | |
39 | do { \ | |
40 | (void) map_read(map, base); \ | |
ca5c23c3 | 41 | xip_iprefetch(); \ |
1da177e4 LT |
42 | local_irq_enable(); \ |
43 | } while (0) | |
44 | ||
45 | #define xip_enable(base, map, cfi) \ | |
46 | do { \ | |
c314dfdc | 47 | cfi_qry_mode_off(base, map, cfi); \ |
1da177e4 LT |
48 | xip_allowed(base, map); \ |
49 | } while (0) | |
50 | ||
51 | #define xip_disable_qry(base, map, cfi) \ | |
52 | do { \ | |
53 | xip_disable(); \ | |
c314dfdc | 54 | cfi_qry_mode_on(base, map, cfi); \ |
1da177e4 LT |
55 | } while (0) |
56 | ||
57 | #else | |
58 | ||
59 | #define xip_disable() do { } while (0) | |
60 | #define xip_allowed(base, map) do { } while (0) | |
61 | #define xip_enable(base, map, cfi) do { } while (0) | |
62 | #define xip_disable_qry(base, map, cfi) do { } while (0) | |
63 | ||
64 | #endif | |
65 | ||
66 | /* check for QRY. | |
67 | in: interleave,type,mode | |
68 | ret: table index, <0 for error | |
69 | */ | |
1da177e4 LT |
70 | |
71 | static int __xipram cfi_probe_chip(struct map_info *map, __u32 base, | |
72 | unsigned long *chip_map, struct cfi_private *cfi) | |
73 | { | |
74 | int i; | |
1f948b43 | 75 | |
1da177e4 LT |
76 | if ((base + 0) >= map->size) { |
77 | printk(KERN_NOTICE | |
78 | "Probe at base[0x00](0x%08lx) past the end of the map(0x%08lx)\n", | |
79 | (unsigned long)base, map->size -1); | |
80 | return 0; | |
81 | } | |
82 | if ((base + 0xff) >= map->size) { | |
83 | printk(KERN_NOTICE | |
84 | "Probe at base[0x55](0x%08lx) past the end of the map(0x%08lx)\n", | |
85 | (unsigned long)base + 0x55, map->size -1); | |
86 | return 0; | |
87 | } | |
88 | ||
89 | xip_disable(); | |
c314dfdc | 90 | if (!cfi_qry_mode_on(base, map, cfi)) { |
1da177e4 LT |
91 | xip_enable(base, map, cfi); |
92 | return 0; | |
93 | } | |
94 | ||
95 | if (!cfi->numchips) { | |
1f948b43 | 96 | /* This is the first time we're called. Set up the CFI |
1da177e4 LT |
97 | stuff accordingly and return */ |
98 | return cfi_chip_setup(map, cfi); | |
99 | } | |
100 | ||
101 | /* Check each previous chip to see if it's an alias */ | |
102 | for (i=0; i < (base >> cfi->chipshift); i++) { | |
103 | unsigned long start; | |
104 | if(!test_bit(i, chip_map)) { | |
105 | /* Skip location; no valid chip at this address */ | |
1f948b43 | 106 | continue; |
1da177e4 LT |
107 | } |
108 | start = i << cfi->chipshift; | |
109 | /* This chip should be in read mode if it's one | |
110 | we've already touched. */ | |
c314dfdc | 111 | if (cfi_qry_present(map, start, cfi)) { |
1f948b43 | 112 | /* Eep. This chip also had the QRY marker. |
1da177e4 | 113 | * Is it an alias for the new one? */ |
c314dfdc | 114 | cfi_qry_mode_off(start, map, cfi); |
1da177e4 LT |
115 | |
116 | /* If the QRY marker goes away, it's an alias */ | |
c314dfdc | 117 | if (!cfi_qry_present(map, start, cfi)) { |
1da177e4 LT |
118 | xip_allowed(base, map); |
119 | printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", | |
120 | map->name, base, start); | |
121 | return 0; | |
122 | } | |
1f948b43 | 123 | /* Yes, it's actually got QRY for data. Most |
1da177e4 LT |
124 | * unfortunate. Stick the new chip in read mode |
125 | * too and if it's the same, assume it's an alias. */ | |
126 | /* FIXME: Use other modes to do a proper check */ | |
c314dfdc | 127 | cfi_qry_mode_off(base, map, cfi); |
1f948b43 | 128 | |
c314dfdc | 129 | if (cfi_qry_present(map, base, cfi)) { |
1da177e4 LT |
130 | xip_allowed(base, map); |
131 | printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", | |
132 | map->name, base, start); | |
133 | return 0; | |
134 | } | |
135 | } | |
136 | } | |
1f948b43 | 137 | |
1da177e4 LT |
138 | /* OK, if we got to here, then none of the previous chips appear to |
139 | be aliases for the current one. */ | |
140 | set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */ | |
141 | cfi->numchips++; | |
1f948b43 | 142 | |
1da177e4 | 143 | /* Put it back into Read Mode */ |
c314dfdc | 144 | cfi_qry_mode_off(base, map, cfi); |
1da177e4 LT |
145 | xip_allowed(base, map); |
146 | ||
147 | printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n", | |
148 | map->name, cfi->interleave, cfi->device_type*8, base, | |
149 | map->bankwidth*8); | |
1f948b43 | 150 | |
1da177e4 LT |
151 | return 1; |
152 | } | |
153 | ||
1f948b43 | 154 | static int __xipram cfi_chip_setup(struct map_info *map, |
1da177e4 LT |
155 | struct cfi_private *cfi) |
156 | { | |
157 | int ofs_factor = cfi->interleave*cfi->device_type; | |
158 | __u32 base = 0; | |
159 | int num_erase_regions = cfi_read_query(map, base + (0x10 + 28)*ofs_factor); | |
160 | int i; | |
ad7026fe | 161 | int addr_unlock1 = 0x555, addr_unlock2 = 0x2AA; |
1da177e4 LT |
162 | |
163 | xip_enable(base, map, cfi); | |
164 | #ifdef DEBUG_CFI | |
165 | printk("Number of erase regions: %d\n", num_erase_regions); | |
166 | #endif | |
167 | if (!num_erase_regions) | |
168 | return 0; | |
169 | ||
170 | cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL); | |
171 | if (!cfi->cfiq) { | |
172 | printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name); | |
173 | return 0; | |
174 | } | |
1f948b43 TG |
175 | |
176 | memset(cfi->cfiq,0,sizeof(struct cfi_ident)); | |
177 | ||
1da177e4 | 178 | cfi->cfi_mode = CFI_MODE_CFI; |
1f948b43 | 179 | |
1da177e4 LT |
180 | /* Read the CFI info structure */ |
181 | xip_disable_qry(base, map, cfi); | |
182 | for (i=0; i<(sizeof(struct cfi_ident) + num_erase_regions * 4); i++) | |
183 | ((unsigned char *)cfi->cfiq)[i] = cfi_read_query(map,base + (0x10 + i)*ofs_factor); | |
184 | ||
1da177e4 LT |
185 | /* Do any necessary byteswapping */ |
186 | cfi->cfiq->P_ID = le16_to_cpu(cfi->cfiq->P_ID); | |
187 | ||
188 | cfi->cfiq->P_ADR = le16_to_cpu(cfi->cfiq->P_ADR); | |
189 | cfi->cfiq->A_ID = le16_to_cpu(cfi->cfiq->A_ID); | |
190 | cfi->cfiq->A_ADR = le16_to_cpu(cfi->cfiq->A_ADR); | |
191 | cfi->cfiq->InterfaceDesc = le16_to_cpu(cfi->cfiq->InterfaceDesc); | |
192 | cfi->cfiq->MaxBufWriteSize = le16_to_cpu(cfi->cfiq->MaxBufWriteSize); | |
193 | ||
194 | #ifdef DEBUG_CFI | |
195 | /* Dump the information therein */ | |
196 | print_cfi_ident(cfi->cfiq); | |
197 | #endif | |
198 | ||
199 | for (i=0; i<cfi->cfiq->NumEraseRegions; i++) { | |
200 | cfi->cfiq->EraseRegionInfo[i] = le32_to_cpu(cfi->cfiq->EraseRegionInfo[i]); | |
1f948b43 TG |
201 | |
202 | #ifdef DEBUG_CFI | |
1da177e4 | 203 | printk(" Erase Region #%d: BlockSize 0x%4.4X bytes, %d blocks\n", |
1f948b43 | 204 | i, (cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff, |
1da177e4 LT |
205 | (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1); |
206 | #endif | |
207 | } | |
208 | ||
8473044d GL |
209 | /* |
210 | * Note we put the device back into Read Mode BEFORE going into Auto | |
211 | * Select Mode, as some devices support nesting of modes, others | |
212 | * don't. This way should always work. | |
213 | * On cmdset 0001 the writes of 0xaa and 0x55 are not needed, and | |
214 | * so should be treated as nops or illegal (and so put the device | |
215 | * back into Read Mode, which is a nop in this case). | |
216 | */ | |
217 | cfi_send_gen_cmd(0xf0, 0, base, map, cfi, cfi->device_type, NULL); | |
ad7026fe GL |
218 | cfi_send_gen_cmd(0xaa, addr_unlock1, base, map, cfi, cfi->device_type, NULL); |
219 | cfi_send_gen_cmd(0x55, addr_unlock2, base, map, cfi, cfi->device_type, NULL); | |
220 | cfi_send_gen_cmd(0x90, addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
8473044d GL |
221 | cfi->mfr = cfi_read_query16(map, base); |
222 | cfi->id = cfi_read_query16(map, base + ofs_factor); | |
223 | ||
224 | /* Get AMD/Spansion extended JEDEC ID */ | |
225 | if (cfi->mfr == CFI_MFR_AMD && (cfi->id & 0xff) == 0x7e) | |
226 | cfi->id = cfi_read_query(map, base + 0xe * ofs_factor) << 8 | | |
227 | cfi_read_query(map, base + 0xf * ofs_factor); | |
228 | ||
229 | /* Put it back into Read Mode */ | |
230 | cfi_qry_mode_off(base, map, cfi); | |
231 | xip_allowed(base, map); | |
232 | ||
1da177e4 LT |
233 | printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n", |
234 | map->name, cfi->interleave, cfi->device_type*8, base, | |
235 | map->bankwidth*8); | |
236 | ||
237 | return 1; | |
238 | } | |
239 | ||
240 | #ifdef DEBUG_CFI | |
1f948b43 | 241 | static char *vendorname(__u16 vendor) |
1da177e4 LT |
242 | { |
243 | switch (vendor) { | |
244 | case P_ID_NONE: | |
245 | return "None"; | |
1f948b43 | 246 | |
1da177e4 LT |
247 | case P_ID_INTEL_EXT: |
248 | return "Intel/Sharp Extended"; | |
1f948b43 | 249 | |
1da177e4 LT |
250 | case P_ID_AMD_STD: |
251 | return "AMD/Fujitsu Standard"; | |
1f948b43 | 252 | |
1da177e4 LT |
253 | case P_ID_INTEL_STD: |
254 | return "Intel/Sharp Standard"; | |
1f948b43 | 255 | |
1da177e4 LT |
256 | case P_ID_AMD_EXT: |
257 | return "AMD/Fujitsu Extended"; | |
258 | ||
259 | case P_ID_WINBOND: | |
260 | return "Winbond Standard"; | |
1f948b43 | 261 | |
1da177e4 LT |
262 | case P_ID_ST_ADV: |
263 | return "ST Advanced"; | |
264 | ||
265 | case P_ID_MITSUBISHI_STD: | |
266 | return "Mitsubishi Standard"; | |
1f948b43 | 267 | |
1da177e4 LT |
268 | case P_ID_MITSUBISHI_EXT: |
269 | return "Mitsubishi Extended"; | |
270 | ||
271 | case P_ID_SST_PAGE: | |
272 | return "SST Page Write"; | |
273 | ||
274 | case P_ID_INTEL_PERFORMANCE: | |
275 | return "Intel Performance Code"; | |
1f948b43 | 276 | |
1da177e4 LT |
277 | case P_ID_INTEL_DATA: |
278 | return "Intel Data"; | |
1f948b43 | 279 | |
1da177e4 LT |
280 | case P_ID_RESERVED: |
281 | return "Not Allowed / Reserved for Future Use"; | |
1f948b43 | 282 | |
1da177e4 LT |
283 | default: |
284 | return "Unknown"; | |
285 | } | |
286 | } | |
287 | ||
288 | ||
289 | static void print_cfi_ident(struct cfi_ident *cfip) | |
290 | { | |
291 | #if 0 | |
292 | if (cfip->qry[0] != 'Q' || cfip->qry[1] != 'R' || cfip->qry[2] != 'Y') { | |
293 | printk("Invalid CFI ident structure.\n"); | |
294 | return; | |
1f948b43 TG |
295 | } |
296 | #endif | |
1da177e4 LT |
297 | printk("Primary Vendor Command Set: %4.4X (%s)\n", cfip->P_ID, vendorname(cfip->P_ID)); |
298 | if (cfip->P_ADR) | |
299 | printk("Primary Algorithm Table at %4.4X\n", cfip->P_ADR); | |
300 | else | |
301 | printk("No Primary Algorithm Table\n"); | |
1f948b43 | 302 | |
1da177e4 LT |
303 | printk("Alternative Vendor Command Set: %4.4X (%s)\n", cfip->A_ID, vendorname(cfip->A_ID)); |
304 | if (cfip->A_ADR) | |
305 | printk("Alternate Algorithm Table at %4.4X\n", cfip->A_ADR); | |
306 | else | |
307 | printk("No Alternate Algorithm Table\n"); | |
1f948b43 TG |
308 | |
309 | ||
1da177e4 LT |
310 | printk("Vcc Minimum: %2d.%d V\n", cfip->VccMin >> 4, cfip->VccMin & 0xf); |
311 | printk("Vcc Maximum: %2d.%d V\n", cfip->VccMax >> 4, cfip->VccMax & 0xf); | |
312 | if (cfip->VppMin) { | |
313 | printk("Vpp Minimum: %2d.%d V\n", cfip->VppMin >> 4, cfip->VppMin & 0xf); | |
314 | printk("Vpp Maximum: %2d.%d V\n", cfip->VppMax >> 4, cfip->VppMax & 0xf); | |
315 | } | |
316 | else | |
317 | printk("No Vpp line\n"); | |
1f948b43 | 318 | |
151e7659 DW |
319 | printk("Typical byte/word write timeout: %d µs\n", 1<<cfip->WordWriteTimeoutTyp); |
320 | printk("Maximum byte/word write timeout: %d µs\n", (1<<cfip->WordWriteTimeoutMax) * (1<<cfip->WordWriteTimeoutTyp)); | |
1f948b43 | 321 | |
1da177e4 | 322 | if (cfip->BufWriteTimeoutTyp || cfip->BufWriteTimeoutMax) { |
151e7659 DW |
323 | printk("Typical full buffer write timeout: %d µs\n", 1<<cfip->BufWriteTimeoutTyp); |
324 | printk("Maximum full buffer write timeout: %d µs\n", (1<<cfip->BufWriteTimeoutMax) * (1<<cfip->BufWriteTimeoutTyp)); | |
1da177e4 LT |
325 | } |
326 | else | |
327 | printk("Full buffer write not supported\n"); | |
1f948b43 | 328 | |
1da177e4 LT |
329 | printk("Typical block erase timeout: %d ms\n", 1<<cfip->BlockEraseTimeoutTyp); |
330 | printk("Maximum block erase timeout: %d ms\n", (1<<cfip->BlockEraseTimeoutMax) * (1<<cfip->BlockEraseTimeoutTyp)); | |
331 | if (cfip->ChipEraseTimeoutTyp || cfip->ChipEraseTimeoutMax) { | |
1f948b43 | 332 | printk("Typical chip erase timeout: %d ms\n", 1<<cfip->ChipEraseTimeoutTyp); |
1da177e4 LT |
333 | printk("Maximum chip erase timeout: %d ms\n", (1<<cfip->ChipEraseTimeoutMax) * (1<<cfip->ChipEraseTimeoutTyp)); |
334 | } | |
335 | else | |
336 | printk("Chip erase not supported\n"); | |
1f948b43 | 337 | |
1da177e4 LT |
338 | printk("Device size: 0x%X bytes (%d MiB)\n", 1 << cfip->DevSize, 1<< (cfip->DevSize - 20)); |
339 | printk("Flash Device Interface description: 0x%4.4X\n", cfip->InterfaceDesc); | |
340 | switch(cfip->InterfaceDesc) { | |
de7921f0 | 341 | case CFI_INTERFACE_X8_ASYNC: |
1da177e4 LT |
342 | printk(" - x8-only asynchronous interface\n"); |
343 | break; | |
1f948b43 | 344 | |
de7921f0 | 345 | case CFI_INTERFACE_X16_ASYNC: |
1da177e4 LT |
346 | printk(" - x16-only asynchronous interface\n"); |
347 | break; | |
1f948b43 | 348 | |
de7921f0 | 349 | case CFI_INTERFACE_X8_BY_X16_ASYNC: |
1da177e4 LT |
350 | printk(" - supports x8 and x16 via BYTE# with asynchronous interface\n"); |
351 | break; | |
1f948b43 | 352 | |
de7921f0 | 353 | case CFI_INTERFACE_X32_ASYNC: |
1da177e4 LT |
354 | printk(" - x32-only asynchronous interface\n"); |
355 | break; | |
1f948b43 | 356 | |
de7921f0 | 357 | case CFI_INTERFACE_X16_BY_X32_ASYNC: |
1da177e4 LT |
358 | printk(" - supports x16 and x32 via Word# with asynchronous interface\n"); |
359 | break; | |
1f948b43 | 360 | |
de7921f0 | 361 | case CFI_INTERFACE_NOT_ALLOWED: |
1da177e4 LT |
362 | printk(" - Not Allowed / Reserved\n"); |
363 | break; | |
1f948b43 | 364 | |
1da177e4 LT |
365 | default: |
366 | printk(" - Unknown\n"); | |
367 | break; | |
368 | } | |
1f948b43 | 369 | |
1da177e4 LT |
370 | printk("Max. bytes in buffer write: 0x%x\n", 1<< cfip->MaxBufWriteSize); |
371 | printk("Number of Erase Block Regions: %d\n", cfip->NumEraseRegions); | |
1f948b43 | 372 | |
1da177e4 LT |
373 | } |
374 | #endif /* DEBUG_CFI */ | |
375 | ||
376 | static struct chip_probe cfi_chip_probe = { | |
377 | .name = "CFI", | |
378 | .probe_chip = cfi_probe_chip | |
379 | }; | |
380 | ||
381 | struct mtd_info *cfi_probe(struct map_info *map) | |
382 | { | |
383 | /* | |
384 | * Just use the generic probe stuff to call our CFI-specific | |
385 | * chip_probe routine in all the possible permutations, etc. | |
386 | */ | |
387 | return mtd_do_chip_probe(map, &cfi_chip_probe); | |
388 | } | |
389 | ||
390 | static struct mtd_chip_driver cfi_chipdrv = { | |
391 | .probe = cfi_probe, | |
392 | .name = "cfi_probe", | |
393 | .module = THIS_MODULE | |
394 | }; | |
395 | ||
2b9175c1 | 396 | static int __init cfi_probe_init(void) |
1da177e4 LT |
397 | { |
398 | register_mtd_chip_driver(&cfi_chipdrv); | |
399 | return 0; | |
400 | } | |
401 | ||
402 | static void __exit cfi_probe_exit(void) | |
403 | { | |
404 | unregister_mtd_chip_driver(&cfi_chipdrv); | |
405 | } | |
406 | ||
407 | module_init(cfi_probe_init); | |
408 | module_exit(cfi_probe_exit); | |
409 | ||
410 | MODULE_LICENSE("GPL"); | |
411 | MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org> et al."); | |
412 | MODULE_DESCRIPTION("Probe code for CFI-compliant flash chips"); |