Commit | Line | Data |
---|---|---|
1f948b43 | 1 | /* |
1da177e4 LT |
2 | Common Flash Interface probe code. |
3 | (C) 2000 Red Hat. GPL'd. | |
1da177e4 LT |
4 | See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5) |
5 | for the standard this probe goes back to. | |
6 | ||
7 | Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com | |
8 | */ | |
9 | ||
1da177e4 LT |
10 | #include <linux/module.h> |
11 | #include <linux/init.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <asm/io.h> | |
15 | #include <asm/byteorder.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/interrupt.h> | |
1da177e4 LT |
19 | |
20 | #include <linux/mtd/mtd.h> | |
21 | #include <linux/mtd/map.h> | |
22 | #include <linux/mtd/cfi.h> | |
23 | #include <linux/mtd/gen_probe.h> | |
24 | ||
1da177e4 | 25 | /* AMD */ |
4a22442f | 26 | #define AM29DL800BB 0x22CB |
1da177e4 LT |
27 | #define AM29DL800BT 0x224A |
28 | ||
29 | #define AM29F800BB 0x2258 | |
30 | #define AM29F800BT 0x22D6 | |
31 | #define AM29LV400BB 0x22BA | |
32 | #define AM29LV400BT 0x22B9 | |
33 | #define AM29LV800BB 0x225B | |
34 | #define AM29LV800BT 0x22DA | |
35 | #define AM29LV160DT 0x22C4 | |
36 | #define AM29LV160DB 0x2249 | |
37 | #define AM29F017D 0x003D | |
38 | #define AM29F016D 0x00AD | |
39 | #define AM29F080 0x00D5 | |
40 | #define AM29F040 0x00A4 | |
41 | #define AM29LV040B 0x004F | |
42 | #define AM29F032B 0x0041 | |
43 | #define AM29F002T 0x00B0 | |
8fd310a1 MR |
44 | #define AM29SL800DB 0x226B |
45 | #define AM29SL800DT 0x22EA | |
1da177e4 LT |
46 | |
47 | /* Atmel */ | |
48 | #define AT49BV512 0x0003 | |
49 | #define AT29LV512 0x003d | |
50 | #define AT49BV16X 0x00C0 | |
51 | #define AT49BV16XT 0x00C2 | |
52 | #define AT49BV32X 0x00C8 | |
53 | #define AT49BV32XT 0x00C9 | |
54 | ||
1b0b30ac MR |
55 | /* Eon */ |
56 | #define EN29SL800BB 0x226B | |
57 | #define EN29SL800BT 0x22EA | |
58 | ||
1da177e4 LT |
59 | /* Fujitsu */ |
60 | #define MBM29F040C 0x00A4 | |
c9856e39 | 61 | #define MBM29F800BA 0x2258 |
1da177e4 LT |
62 | #define MBM29LV650UE 0x22D7 |
63 | #define MBM29LV320TE 0x22F6 | |
64 | #define MBM29LV320BE 0x22F9 | |
65 | #define MBM29LV160TE 0x22C4 | |
66 | #define MBM29LV160BE 0x2249 | |
67 | #define MBM29LV800BA 0x225B | |
68 | #define MBM29LV800TA 0x22DA | |
69 | #define MBM29LV400TC 0x22B9 | |
70 | #define MBM29LV400BC 0x22BA | |
71 | ||
72 | /* Hyundai */ | |
73 | #define HY29F002T 0x00B0 | |
74 | ||
75 | /* Intel */ | |
76 | #define I28F004B3T 0x00d4 | |
77 | #define I28F004B3B 0x00d5 | |
78 | #define I28F400B3T 0x8894 | |
79 | #define I28F400B3B 0x8895 | |
80 | #define I28F008S5 0x00a6 | |
81 | #define I28F016S5 0x00a0 | |
82 | #define I28F008SA 0x00a2 | |
83 | #define I28F008B3T 0x00d2 | |
84 | #define I28F008B3B 0x00d3 | |
85 | #define I28F800B3T 0x8892 | |
86 | #define I28F800B3B 0x8893 | |
87 | #define I28F016S3 0x00aa | |
88 | #define I28F016B3T 0x00d0 | |
89 | #define I28F016B3B 0x00d1 | |
90 | #define I28F160B3T 0x8890 | |
91 | #define I28F160B3B 0x8891 | |
92 | #define I28F320B3T 0x8896 | |
93 | #define I28F320B3B 0x8897 | |
94 | #define I28F640B3T 0x8898 | |
95 | #define I28F640B3B 0x8899 | |
b4c8c8cf SR |
96 | #define I28F640C3B 0x88CD |
97 | #define I28F160F3T 0x88F3 | |
98 | #define I28F160F3B 0x88F4 | |
99 | #define I28F160C3T 0x88C2 | |
100 | #define I28F160C3B 0x88C3 | |
1da177e4 LT |
101 | #define I82802AB 0x00ad |
102 | #define I82802AC 0x00ac | |
103 | ||
104 | /* Macronix */ | |
105 | #define MX29LV040C 0x004F | |
106 | #define MX29LV160T 0x22C4 | |
107 | #define MX29LV160B 0x2249 | |
c4e6952f | 108 | #define MX29F040 0x00A4 |
1da177e4 LT |
109 | #define MX29F016 0x00AD |
110 | #define MX29F002T 0x00B0 | |
111 | #define MX29F004T 0x0045 | |
112 | #define MX29F004B 0x0046 | |
113 | ||
114 | /* NEC */ | |
115 | #define UPD29F064115 0x221C | |
116 | ||
117 | /* PMC */ | |
118 | #define PM49FL002 0x006D | |
119 | #define PM49FL004 0x006E | |
120 | #define PM49FL008 0x006A | |
121 | ||
a63ec1b7 | 122 | /* Sharp */ |
fe2f4c8e | 123 | #define LH28F640BF 0x00B0 |
a63ec1b7 | 124 | |
1da177e4 | 125 | /* ST - www.st.com */ |
c9856e39 | 126 | #define M29F800AB 0x0058 |
db5432db LM |
127 | #define M29W800DT 0x22D7 |
128 | #define M29W800DB 0x225B | |
30d6a24e GF |
129 | #define M29W400DT 0x00EE |
130 | #define M29W400DB 0x00EF | |
1da177e4 LT |
131 | #define M29W160DT 0x22C4 |
132 | #define M29W160DB 0x2249 | |
133 | #define M29W040B 0x00E3 | |
134 | #define M50FW040 0x002C | |
135 | #define M50FW080 0x002D | |
136 | #define M50FW016 0x002E | |
137 | #define M50LPW080 0x002F | |
deb1a5f1 NC |
138 | #define M50FLW080A 0x0080 |
139 | #define M50FLW080B 0x0081 | |
e1070211 | 140 | #define PSD4256G6V 0x00e9 |
1da177e4 LT |
141 | |
142 | /* SST */ | |
143 | #define SST29EE020 0x0010 | |
144 | #define SST29LE020 0x0012 | |
145 | #define SST29EE512 0x005d | |
146 | #define SST29LE512 0x003d | |
147 | #define SST39LF800 0x2781 | |
148 | #define SST39LF160 0x2782 | |
88ec7c50 | 149 | #define SST39VF1601 0x234b |
bd50a0ff | 150 | #define SST39VF3201 0x235b |
087acaf1 WS |
151 | #define SST39WF1601 0x274b |
152 | #define SST39WF1602 0x274a | |
1da177e4 LT |
153 | #define SST39LF512 0x00D4 |
154 | #define SST39LF010 0x00D5 | |
155 | #define SST39LF020 0x00D6 | |
156 | #define SST39LF040 0x00D7 | |
157 | #define SST39SF010A 0x00B5 | |
158 | #define SST39SF020A 0x00B6 | |
a0645ce9 | 159 | #define SST39SF040 0x00B7 |
1da177e4 | 160 | #define SST49LF004B 0x0060 |
89072ef9 | 161 | #define SST49LF040B 0x0050 |
1da177e4 LT |
162 | #define SST49LF008A 0x005a |
163 | #define SST49LF030A 0x001C | |
164 | #define SST49LF040A 0x0051 | |
165 | #define SST49LF080A 0x005B | |
1b0a062b | 166 | #define SST36VF3203 0x7354 |
1da177e4 LT |
167 | |
168 | /* Toshiba */ | |
169 | #define TC58FVT160 0x00C2 | |
170 | #define TC58FVB160 0x0043 | |
171 | #define TC58FVT321 0x009A | |
172 | #define TC58FVB321 0x009C | |
173 | #define TC58FVT641 0x0093 | |
174 | #define TC58FVB641 0x0095 | |
175 | ||
176 | /* Winbond */ | |
177 | #define W49V002A 0x00b0 | |
178 | ||
179 | ||
180 | /* | |
181 | * Unlock address sets for AMD command sets. | |
182 | * Intel command sets use the MTD_UADDR_UNNECESSARY. | |
183 | * Each identifier, except MTD_UADDR_UNNECESSARY, and | |
184 | * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[]. | |
185 | * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure | |
186 | * initialization need not require initializing all of the | |
187 | * unlock addresses for all bit widths. | |
188 | */ | |
189 | enum uaddr { | |
190 | MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */ | |
191 | MTD_UADDR_0x0555_0x02AA, | |
192 | MTD_UADDR_0x0555_0x0AAA, | |
193 | MTD_UADDR_0x5555_0x2AAA, | |
e1070211 | 194 | MTD_UADDR_0x0AAA_0x0554, |
1da177e4 | 195 | MTD_UADDR_0x0AAA_0x0555, |
ca6f12c6 | 196 | MTD_UADDR_0xAAAA_0x5555, |
1da177e4 LT |
197 | MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */ |
198 | MTD_UADDR_UNNECESSARY, /* Does not require any address */ | |
199 | }; | |
200 | ||
201 | ||
202 | struct unlock_addr { | |
5d3cce3b DW |
203 | uint32_t addr1; |
204 | uint32_t addr2; | |
1da177e4 LT |
205 | }; |
206 | ||
207 | ||
208 | /* | |
209 | * I don't like the fact that the first entry in unlock_addrs[] | |
210 | * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore, | |
211 | * should not be used. The problem is that structures with | |
212 | * initializers have extra fields initialized to 0. It is _very_ | |
3ad2f3fb | 213 | * desirable to have the unlock address entries for unsupported |
1da177e4 LT |
214 | * data widths automatically initialized - that means that |
215 | * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here | |
216 | * must go unused. | |
217 | */ | |
218 | static const struct unlock_addr unlock_addrs[] = { | |
219 | [MTD_UADDR_NOT_SUPPORTED] = { | |
220 | .addr1 = 0xffff, | |
221 | .addr2 = 0xffff | |
222 | }, | |
223 | ||
224 | [MTD_UADDR_0x0555_0x02AA] = { | |
225 | .addr1 = 0x0555, | |
226 | .addr2 = 0x02aa | |
227 | }, | |
228 | ||
229 | [MTD_UADDR_0x0555_0x0AAA] = { | |
230 | .addr1 = 0x0555, | |
231 | .addr2 = 0x0aaa | |
232 | }, | |
233 | ||
234 | [MTD_UADDR_0x5555_0x2AAA] = { | |
235 | .addr1 = 0x5555, | |
236 | .addr2 = 0x2aaa | |
237 | }, | |
238 | ||
e1070211 MF |
239 | [MTD_UADDR_0x0AAA_0x0554] = { |
240 | .addr1 = 0x0AAA, | |
241 | .addr2 = 0x0554 | |
242 | }, | |
243 | ||
1da177e4 LT |
244 | [MTD_UADDR_0x0AAA_0x0555] = { |
245 | .addr1 = 0x0AAA, | |
246 | .addr2 = 0x0555 | |
247 | }, | |
248 | ||
ca6f12c6 AN |
249 | [MTD_UADDR_0xAAAA_0x5555] = { |
250 | .addr1 = 0xaaaa, | |
251 | .addr2 = 0x5555 | |
252 | }, | |
253 | ||
1da177e4 LT |
254 | [MTD_UADDR_DONT_CARE] = { |
255 | .addr1 = 0x0000, /* Doesn't matter which address */ | |
256 | .addr2 = 0x0000 /* is used - must be last entry */ | |
257 | }, | |
258 | ||
259 | [MTD_UADDR_UNNECESSARY] = { | |
260 | .addr1 = 0x0000, | |
261 | .addr2 = 0x0000 | |
262 | } | |
263 | }; | |
264 | ||
1da177e4 | 265 | struct amd_flash_info { |
1da177e4 | 266 | const char *name; |
5d3cce3b DW |
267 | const uint16_t mfr_id; |
268 | const uint16_t dev_id; | |
269 | const uint8_t dev_size; | |
270 | const uint8_t nr_regions; | |
271 | const uint16_t cmd_set; | |
272 | const uint32_t regions[6]; | |
273 | const uint8_t devtypes; /* Bitmask for x8, x16 etc. */ | |
274 | const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */ | |
1da177e4 LT |
275 | }; |
276 | ||
277 | #define ERASEINFO(size,blocks) (size<<8)|(blocks-1) | |
278 | ||
279 | #define SIZE_64KiB 16 | |
280 | #define SIZE_128KiB 17 | |
281 | #define SIZE_256KiB 18 | |
282 | #define SIZE_512KiB 19 | |
283 | #define SIZE_1MiB 20 | |
284 | #define SIZE_2MiB 21 | |
285 | #define SIZE_4MiB 22 | |
286 | #define SIZE_8MiB 23 | |
287 | ||
288 | ||
289 | /* | |
290 | * Please keep this list ordered by manufacturer! | |
291 | * Fortunately, the list isn't searched often and so a | |
292 | * slow, linear search isn't so bad. | |
293 | */ | |
294 | static const struct amd_flash_info jedec_table[] = { | |
295 | { | |
ae731822 | 296 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
297 | .dev_id = AM29F032B, |
298 | .name = "AMD AM29F032B", | |
5d3cce3b DW |
299 | .uaddr = MTD_UADDR_0x0555_0x02AA, |
300 | .devtypes = CFI_DEVICETYPE_X8, | |
301 | .dev_size = SIZE_4MiB, | |
302 | .cmd_set = P_ID_AMD_STD, | |
303 | .nr_regions = 1, | |
1da177e4 LT |
304 | .regions = { |
305 | ERASEINFO(0x10000,64) | |
306 | } | |
307 | }, { | |
ae731822 | 308 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
309 | .dev_id = AM29LV160DT, |
310 | .name = "AMD AM29LV160DT", | |
5d3cce3b DW |
311 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
312 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
313 | .dev_size = SIZE_2MiB, |
314 | .cmd_set = P_ID_AMD_STD, | |
315 | .nr_regions = 4, | |
1da177e4 LT |
316 | .regions = { |
317 | ERASEINFO(0x10000,31), | |
318 | ERASEINFO(0x08000,1), | |
319 | ERASEINFO(0x02000,2), | |
320 | ERASEINFO(0x04000,1) | |
321 | } | |
322 | }, { | |
ae731822 | 323 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
324 | .dev_id = AM29LV160DB, |
325 | .name = "AMD AM29LV160DB", | |
5d3cce3b DW |
326 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
327 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
328 | .dev_size = SIZE_2MiB, |
329 | .cmd_set = P_ID_AMD_STD, | |
330 | .nr_regions = 4, | |
1da177e4 LT |
331 | .regions = { |
332 | ERASEINFO(0x04000,1), | |
333 | ERASEINFO(0x02000,2), | |
334 | ERASEINFO(0x08000,1), | |
335 | ERASEINFO(0x10000,31) | |
336 | } | |
337 | }, { | |
ae731822 | 338 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
339 | .dev_id = AM29LV400BB, |
340 | .name = "AMD AM29LV400BB", | |
5d3cce3b DW |
341 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
342 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
343 | .dev_size = SIZE_512KiB, |
344 | .cmd_set = P_ID_AMD_STD, | |
345 | .nr_regions = 4, | |
1da177e4 LT |
346 | .regions = { |
347 | ERASEINFO(0x04000,1), | |
348 | ERASEINFO(0x02000,2), | |
349 | ERASEINFO(0x08000,1), | |
350 | ERASEINFO(0x10000,7) | |
351 | } | |
352 | }, { | |
ae731822 | 353 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
354 | .dev_id = AM29LV400BT, |
355 | .name = "AMD AM29LV400BT", | |
5d3cce3b DW |
356 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
357 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
358 | .dev_size = SIZE_512KiB, |
359 | .cmd_set = P_ID_AMD_STD, | |
360 | .nr_regions = 4, | |
1da177e4 LT |
361 | .regions = { |
362 | ERASEINFO(0x10000,7), | |
363 | ERASEINFO(0x08000,1), | |
364 | ERASEINFO(0x02000,2), | |
365 | ERASEINFO(0x04000,1) | |
366 | } | |
367 | }, { | |
ae731822 | 368 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
369 | .dev_id = AM29LV800BB, |
370 | .name = "AMD AM29LV800BB", | |
5d3cce3b DW |
371 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
372 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
373 | .dev_size = SIZE_1MiB, |
374 | .cmd_set = P_ID_AMD_STD, | |
375 | .nr_regions = 4, | |
1da177e4 LT |
376 | .regions = { |
377 | ERASEINFO(0x04000,1), | |
378 | ERASEINFO(0x02000,2), | |
379 | ERASEINFO(0x08000,1), | |
380 | ERASEINFO(0x10000,15), | |
381 | } | |
382 | }, { | |
383 | /* add DL */ | |
ae731822 | 384 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
385 | .dev_id = AM29DL800BB, |
386 | .name = "AMD AM29DL800BB", | |
5d3cce3b DW |
387 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
388 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
389 | .dev_size = SIZE_1MiB, |
390 | .cmd_set = P_ID_AMD_STD, | |
391 | .nr_regions = 6, | |
1da177e4 LT |
392 | .regions = { |
393 | ERASEINFO(0x04000,1), | |
394 | ERASEINFO(0x08000,1), | |
395 | ERASEINFO(0x02000,4), | |
396 | ERASEINFO(0x08000,1), | |
397 | ERASEINFO(0x04000,1), | |
398 | ERASEINFO(0x10000,14) | |
399 | } | |
400 | }, { | |
ae731822 | 401 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
402 | .dev_id = AM29DL800BT, |
403 | .name = "AMD AM29DL800BT", | |
5d3cce3b DW |
404 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
405 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
406 | .dev_size = SIZE_1MiB, |
407 | .cmd_set = P_ID_AMD_STD, | |
408 | .nr_regions = 6, | |
1da177e4 LT |
409 | .regions = { |
410 | ERASEINFO(0x10000,14), | |
411 | ERASEINFO(0x04000,1), | |
412 | ERASEINFO(0x08000,1), | |
413 | ERASEINFO(0x02000,4), | |
414 | ERASEINFO(0x08000,1), | |
415 | ERASEINFO(0x04000,1) | |
416 | } | |
417 | }, { | |
ae731822 | 418 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
419 | .dev_id = AM29F800BB, |
420 | .name = "AMD AM29F800BB", | |
5d3cce3b DW |
421 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
422 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
423 | .dev_size = SIZE_1MiB, |
424 | .cmd_set = P_ID_AMD_STD, | |
425 | .nr_regions = 4, | |
1da177e4 LT |
426 | .regions = { |
427 | ERASEINFO(0x04000,1), | |
428 | ERASEINFO(0x02000,2), | |
429 | ERASEINFO(0x08000,1), | |
430 | ERASEINFO(0x10000,15), | |
431 | } | |
432 | }, { | |
ae731822 | 433 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
434 | .dev_id = AM29LV800BT, |
435 | .name = "AMD AM29LV800BT", | |
5d3cce3b DW |
436 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
437 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
438 | .dev_size = SIZE_1MiB, |
439 | .cmd_set = P_ID_AMD_STD, | |
440 | .nr_regions = 4, | |
1da177e4 LT |
441 | .regions = { |
442 | ERASEINFO(0x10000,15), | |
443 | ERASEINFO(0x08000,1), | |
444 | ERASEINFO(0x02000,2), | |
445 | ERASEINFO(0x04000,1) | |
446 | } | |
447 | }, { | |
ae731822 | 448 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
449 | .dev_id = AM29F800BT, |
450 | .name = "AMD AM29F800BT", | |
5d3cce3b DW |
451 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
452 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
453 | .dev_size = SIZE_1MiB, |
454 | .cmd_set = P_ID_AMD_STD, | |
455 | .nr_regions = 4, | |
1da177e4 LT |
456 | .regions = { |
457 | ERASEINFO(0x10000,15), | |
458 | ERASEINFO(0x08000,1), | |
459 | ERASEINFO(0x02000,2), | |
460 | ERASEINFO(0x04000,1) | |
461 | } | |
462 | }, { | |
ae731822 | 463 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
464 | .dev_id = AM29F017D, |
465 | .name = "AMD AM29F017D", | |
5d3cce3b DW |
466 | .devtypes = CFI_DEVICETYPE_X8, |
467 | .uaddr = MTD_UADDR_DONT_CARE, | |
468 | .dev_size = SIZE_2MiB, | |
469 | .cmd_set = P_ID_AMD_STD, | |
470 | .nr_regions = 1, | |
1da177e4 LT |
471 | .regions = { |
472 | ERASEINFO(0x10000,32), | |
473 | } | |
474 | }, { | |
ae731822 | 475 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
476 | .dev_id = AM29F016D, |
477 | .name = "AMD AM29F016D", | |
5d3cce3b DW |
478 | .devtypes = CFI_DEVICETYPE_X8, |
479 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
480 | .dev_size = SIZE_2MiB, | |
481 | .cmd_set = P_ID_AMD_STD, | |
482 | .nr_regions = 1, | |
1da177e4 LT |
483 | .regions = { |
484 | ERASEINFO(0x10000,32), | |
485 | } | |
486 | }, { | |
ae731822 | 487 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
488 | .dev_id = AM29F080, |
489 | .name = "AMD AM29F080", | |
5d3cce3b DW |
490 | .devtypes = CFI_DEVICETYPE_X8, |
491 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
492 | .dev_size = SIZE_1MiB, | |
493 | .cmd_set = P_ID_AMD_STD, | |
494 | .nr_regions = 1, | |
1da177e4 LT |
495 | .regions = { |
496 | ERASEINFO(0x10000,16), | |
497 | } | |
498 | }, { | |
ae731822 | 499 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
500 | .dev_id = AM29F040, |
501 | .name = "AMD AM29F040", | |
5d3cce3b DW |
502 | .devtypes = CFI_DEVICETYPE_X8, |
503 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
504 | .dev_size = SIZE_512KiB, | |
505 | .cmd_set = P_ID_AMD_STD, | |
506 | .nr_regions = 1, | |
1da177e4 LT |
507 | .regions = { |
508 | ERASEINFO(0x10000,8), | |
509 | } | |
510 | }, { | |
ae731822 | 511 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
512 | .dev_id = AM29LV040B, |
513 | .name = "AMD AM29LV040B", | |
5d3cce3b DW |
514 | .devtypes = CFI_DEVICETYPE_X8, |
515 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
516 | .dev_size = SIZE_512KiB, | |
517 | .cmd_set = P_ID_AMD_STD, | |
518 | .nr_regions = 1, | |
1da177e4 LT |
519 | .regions = { |
520 | ERASEINFO(0x10000,8), | |
521 | } | |
522 | }, { | |
ae731822 | 523 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
524 | .dev_id = AM29F002T, |
525 | .name = "AMD AM29F002T", | |
5d3cce3b DW |
526 | .devtypes = CFI_DEVICETYPE_X8, |
527 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
528 | .dev_size = SIZE_256KiB, | |
529 | .cmd_set = P_ID_AMD_STD, | |
530 | .nr_regions = 4, | |
1da177e4 LT |
531 | .regions = { |
532 | ERASEINFO(0x10000,3), | |
533 | ERASEINFO(0x08000,1), | |
534 | ERASEINFO(0x02000,2), | |
535 | ERASEINFO(0x04000,1), | |
536 | } | |
8fd310a1 | 537 | }, { |
ae731822 | 538 | .mfr_id = CFI_MFR_AMD, |
8fd310a1 MR |
539 | .dev_id = AM29SL800DT, |
540 | .name = "AMD AM29SL800DT", | |
541 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
542 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
543 | .dev_size = SIZE_1MiB, | |
544 | .cmd_set = P_ID_AMD_STD, | |
545 | .nr_regions = 4, | |
546 | .regions = { | |
547 | ERASEINFO(0x10000,15), | |
548 | ERASEINFO(0x08000,1), | |
549 | ERASEINFO(0x02000,2), | |
550 | ERASEINFO(0x04000,1), | |
551 | } | |
552 | }, { | |
ae731822 | 553 | .mfr_id = CFI_MFR_AMD, |
8fd310a1 MR |
554 | .dev_id = AM29SL800DB, |
555 | .name = "AMD AM29SL800DB", | |
556 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
557 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
558 | .dev_size = SIZE_1MiB, | |
559 | .cmd_set = P_ID_AMD_STD, | |
560 | .nr_regions = 4, | |
561 | .regions = { | |
562 | ERASEINFO(0x04000,1), | |
563 | ERASEINFO(0x02000,2), | |
564 | ERASEINFO(0x08000,1), | |
565 | ERASEINFO(0x10000,15), | |
566 | } | |
1da177e4 | 567 | }, { |
ae731822 | 568 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
569 | .dev_id = AT49BV512, |
570 | .name = "Atmel AT49BV512", | |
5d3cce3b DW |
571 | .devtypes = CFI_DEVICETYPE_X8, |
572 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
573 | .dev_size = SIZE_64KiB, | |
574 | .cmd_set = P_ID_AMD_STD, | |
575 | .nr_regions = 1, | |
1da177e4 LT |
576 | .regions = { |
577 | ERASEINFO(0x10000,1) | |
578 | } | |
579 | }, { | |
ae731822 | 580 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
581 | .dev_id = AT29LV512, |
582 | .name = "Atmel AT29LV512", | |
5d3cce3b DW |
583 | .devtypes = CFI_DEVICETYPE_X8, |
584 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
585 | .dev_size = SIZE_64KiB, | |
586 | .cmd_set = P_ID_AMD_STD, | |
587 | .nr_regions = 1, | |
1da177e4 LT |
588 | .regions = { |
589 | ERASEINFO(0x80,256), | |
590 | ERASEINFO(0x80,256) | |
591 | } | |
592 | }, { | |
ae731822 | 593 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
594 | .dev_id = AT49BV16X, |
595 | .name = "Atmel AT49BV16X", | |
5d3cce3b | 596 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 597 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
598 | .dev_size = SIZE_2MiB, |
599 | .cmd_set = P_ID_AMD_STD, | |
600 | .nr_regions = 2, | |
1da177e4 LT |
601 | .regions = { |
602 | ERASEINFO(0x02000,8), | |
603 | ERASEINFO(0x10000,31) | |
604 | } | |
605 | }, { | |
ae731822 | 606 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
607 | .dev_id = AT49BV16XT, |
608 | .name = "Atmel AT49BV16XT", | |
5d3cce3b | 609 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 610 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
611 | .dev_size = SIZE_2MiB, |
612 | .cmd_set = P_ID_AMD_STD, | |
613 | .nr_regions = 2, | |
1da177e4 LT |
614 | .regions = { |
615 | ERASEINFO(0x10000,31), | |
616 | ERASEINFO(0x02000,8) | |
617 | } | |
618 | }, { | |
ae731822 | 619 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
620 | .dev_id = AT49BV32X, |
621 | .name = "Atmel AT49BV32X", | |
5d3cce3b | 622 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 623 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
624 | .dev_size = SIZE_4MiB, |
625 | .cmd_set = P_ID_AMD_STD, | |
626 | .nr_regions = 2, | |
1da177e4 LT |
627 | .regions = { |
628 | ERASEINFO(0x02000,8), | |
629 | ERASEINFO(0x10000,63) | |
630 | } | |
631 | }, { | |
ae731822 | 632 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
633 | .dev_id = AT49BV32XT, |
634 | .name = "Atmel AT49BV32XT", | |
5d3cce3b | 635 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 636 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
637 | .dev_size = SIZE_4MiB, |
638 | .cmd_set = P_ID_AMD_STD, | |
639 | .nr_regions = 2, | |
1da177e4 LT |
640 | .regions = { |
641 | ERASEINFO(0x10000,63), | |
642 | ERASEINFO(0x02000,8) | |
643 | } | |
1b0b30ac | 644 | }, { |
ae731822 | 645 | .mfr_id = CFI_MFR_EON, |
1b0b30ac MR |
646 | .dev_id = EN29SL800BT, |
647 | .name = "Eon EN29SL800BT", | |
648 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
649 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
650 | .dev_size = SIZE_1MiB, | |
651 | .cmd_set = P_ID_AMD_STD, | |
652 | .nr_regions = 4, | |
653 | .regions = { | |
654 | ERASEINFO(0x10000,15), | |
655 | ERASEINFO(0x08000,1), | |
656 | ERASEINFO(0x02000,2), | |
657 | ERASEINFO(0x04000,1), | |
658 | } | |
659 | }, { | |
ae731822 | 660 | .mfr_id = CFI_MFR_EON, |
1b0b30ac MR |
661 | .dev_id = EN29SL800BB, |
662 | .name = "Eon EN29SL800BB", | |
663 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
664 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
665 | .dev_size = SIZE_1MiB, | |
666 | .cmd_set = P_ID_AMD_STD, | |
667 | .nr_regions = 4, | |
668 | .regions = { | |
669 | ERASEINFO(0x04000,1), | |
670 | ERASEINFO(0x02000,2), | |
671 | ERASEINFO(0x08000,1), | |
672 | ERASEINFO(0x10000,15), | |
673 | } | |
1da177e4 | 674 | }, { |
ae731822 | 675 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
676 | .dev_id = MBM29F040C, |
677 | .name = "Fujitsu MBM29F040C", | |
5d3cce3b DW |
678 | .devtypes = CFI_DEVICETYPE_X8, |
679 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
680 | .dev_size = SIZE_512KiB, | |
681 | .cmd_set = P_ID_AMD_STD, | |
682 | .nr_regions = 1, | |
1da177e4 LT |
683 | .regions = { |
684 | ERASEINFO(0x10000,8) | |
685 | } | |
c9856e39 | 686 | }, { |
ae731822 | 687 | .mfr_id = CFI_MFR_FUJITSU, |
c9856e39 PDM |
688 | .dev_id = MBM29F800BA, |
689 | .name = "Fujitsu MBM29F800BA", | |
5d3cce3b DW |
690 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
691 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
692 | .dev_size = SIZE_1MiB, |
693 | .cmd_set = P_ID_AMD_STD, | |
694 | .nr_regions = 4, | |
c9856e39 PDM |
695 | .regions = { |
696 | ERASEINFO(0x04000,1), | |
697 | ERASEINFO(0x02000,2), | |
698 | ERASEINFO(0x08000,1), | |
699 | ERASEINFO(0x10000,15), | |
700 | } | |
1da177e4 | 701 | }, { |
ae731822 | 702 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
703 | .dev_id = MBM29LV650UE, |
704 | .name = "Fujitsu MBM29LV650UE", | |
5d3cce3b DW |
705 | .devtypes = CFI_DEVICETYPE_X8, |
706 | .uaddr = MTD_UADDR_DONT_CARE, | |
707 | .dev_size = SIZE_8MiB, | |
708 | .cmd_set = P_ID_AMD_STD, | |
709 | .nr_regions = 1, | |
1da177e4 LT |
710 | .regions = { |
711 | ERASEINFO(0x10000,128) | |
712 | } | |
713 | }, { | |
ae731822 | 714 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
715 | .dev_id = MBM29LV320TE, |
716 | .name = "Fujitsu MBM29LV320TE", | |
5d3cce3b DW |
717 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
718 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
719 | .dev_size = SIZE_4MiB, |
720 | .cmd_set = P_ID_AMD_STD, | |
721 | .nr_regions = 2, | |
1da177e4 LT |
722 | .regions = { |
723 | ERASEINFO(0x10000,63), | |
724 | ERASEINFO(0x02000,8) | |
725 | } | |
726 | }, { | |
ae731822 | 727 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
728 | .dev_id = MBM29LV320BE, |
729 | .name = "Fujitsu MBM29LV320BE", | |
5d3cce3b DW |
730 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
731 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
732 | .dev_size = SIZE_4MiB, |
733 | .cmd_set = P_ID_AMD_STD, | |
734 | .nr_regions = 2, | |
1da177e4 LT |
735 | .regions = { |
736 | ERASEINFO(0x02000,8), | |
737 | ERASEINFO(0x10000,63) | |
738 | } | |
739 | }, { | |
ae731822 | 740 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
741 | .dev_id = MBM29LV160TE, |
742 | .name = "Fujitsu MBM29LV160TE", | |
5d3cce3b DW |
743 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
744 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
745 | .dev_size = SIZE_2MiB, |
746 | .cmd_set = P_ID_AMD_STD, | |
747 | .nr_regions = 4, | |
1da177e4 LT |
748 | .regions = { |
749 | ERASEINFO(0x10000,31), | |
750 | ERASEINFO(0x08000,1), | |
751 | ERASEINFO(0x02000,2), | |
752 | ERASEINFO(0x04000,1) | |
753 | } | |
754 | }, { | |
ae731822 | 755 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
756 | .dev_id = MBM29LV160BE, |
757 | .name = "Fujitsu MBM29LV160BE", | |
5d3cce3b DW |
758 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
759 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
760 | .dev_size = SIZE_2MiB, |
761 | .cmd_set = P_ID_AMD_STD, | |
762 | .nr_regions = 4, | |
1da177e4 LT |
763 | .regions = { |
764 | ERASEINFO(0x04000,1), | |
765 | ERASEINFO(0x02000,2), | |
766 | ERASEINFO(0x08000,1), | |
767 | ERASEINFO(0x10000,31) | |
768 | } | |
769 | }, { | |
ae731822 | 770 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
771 | .dev_id = MBM29LV800BA, |
772 | .name = "Fujitsu MBM29LV800BA", | |
5d3cce3b DW |
773 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
774 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
775 | .dev_size = SIZE_1MiB, |
776 | .cmd_set = P_ID_AMD_STD, | |
777 | .nr_regions = 4, | |
1da177e4 LT |
778 | .regions = { |
779 | ERASEINFO(0x04000,1), | |
780 | ERASEINFO(0x02000,2), | |
781 | ERASEINFO(0x08000,1), | |
782 | ERASEINFO(0x10000,15) | |
783 | } | |
784 | }, { | |
ae731822 | 785 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
786 | .dev_id = MBM29LV800TA, |
787 | .name = "Fujitsu MBM29LV800TA", | |
5d3cce3b DW |
788 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
789 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
790 | .dev_size = SIZE_1MiB, |
791 | .cmd_set = P_ID_AMD_STD, | |
792 | .nr_regions = 4, | |
1da177e4 LT |
793 | .regions = { |
794 | ERASEINFO(0x10000,15), | |
795 | ERASEINFO(0x08000,1), | |
796 | ERASEINFO(0x02000,2), | |
797 | ERASEINFO(0x04000,1) | |
798 | } | |
799 | }, { | |
ae731822 | 800 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
801 | .dev_id = MBM29LV400BC, |
802 | .name = "Fujitsu MBM29LV400BC", | |
5d3cce3b DW |
803 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
804 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
805 | .dev_size = SIZE_512KiB, |
806 | .cmd_set = P_ID_AMD_STD, | |
807 | .nr_regions = 4, | |
1da177e4 LT |
808 | .regions = { |
809 | ERASEINFO(0x04000,1), | |
810 | ERASEINFO(0x02000,2), | |
811 | ERASEINFO(0x08000,1), | |
812 | ERASEINFO(0x10000,7) | |
813 | } | |
814 | }, { | |
ae731822 | 815 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
816 | .dev_id = MBM29LV400TC, |
817 | .name = "Fujitsu MBM29LV400TC", | |
5d3cce3b DW |
818 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
819 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
820 | .dev_size = SIZE_512KiB, |
821 | .cmd_set = P_ID_AMD_STD, | |
822 | .nr_regions = 4, | |
1da177e4 LT |
823 | .regions = { |
824 | ERASEINFO(0x10000,7), | |
825 | ERASEINFO(0x08000,1), | |
826 | ERASEINFO(0x02000,2), | |
827 | ERASEINFO(0x04000,1) | |
828 | } | |
829 | }, { | |
ae731822 | 830 | .mfr_id = CFI_MFR_HYUNDAI, |
1da177e4 LT |
831 | .dev_id = HY29F002T, |
832 | .name = "Hyundai HY29F002T", | |
5d3cce3b DW |
833 | .devtypes = CFI_DEVICETYPE_X8, |
834 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
835 | .dev_size = SIZE_256KiB, | |
836 | .cmd_set = P_ID_AMD_STD, | |
837 | .nr_regions = 4, | |
1da177e4 LT |
838 | .regions = { |
839 | ERASEINFO(0x10000,3), | |
840 | ERASEINFO(0x08000,1), | |
841 | ERASEINFO(0x02000,2), | |
842 | ERASEINFO(0x04000,1), | |
843 | } | |
844 | }, { | |
ae731822 | 845 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
846 | .dev_id = I28F004B3B, |
847 | .name = "Intel 28F004B3B", | |
5d3cce3b DW |
848 | .devtypes = CFI_DEVICETYPE_X8, |
849 | .uaddr = MTD_UADDR_UNNECESSARY, | |
850 | .dev_size = SIZE_512KiB, | |
851 | .cmd_set = P_ID_INTEL_STD, | |
852 | .nr_regions = 2, | |
1da177e4 LT |
853 | .regions = { |
854 | ERASEINFO(0x02000, 8), | |
855 | ERASEINFO(0x10000, 7), | |
856 | } | |
857 | }, { | |
ae731822 | 858 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
859 | .dev_id = I28F004B3T, |
860 | .name = "Intel 28F004B3T", | |
5d3cce3b DW |
861 | .devtypes = CFI_DEVICETYPE_X8, |
862 | .uaddr = MTD_UADDR_UNNECESSARY, | |
863 | .dev_size = SIZE_512KiB, | |
864 | .cmd_set = P_ID_INTEL_STD, | |
865 | .nr_regions = 2, | |
1da177e4 LT |
866 | .regions = { |
867 | ERASEINFO(0x10000, 7), | |
868 | ERASEINFO(0x02000, 8), | |
869 | } | |
870 | }, { | |
ae731822 | 871 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
872 | .dev_id = I28F400B3B, |
873 | .name = "Intel 28F400B3B", | |
5d3cce3b DW |
874 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
875 | .uaddr = MTD_UADDR_UNNECESSARY, | |
5d3cce3b DW |
876 | .dev_size = SIZE_512KiB, |
877 | .cmd_set = P_ID_INTEL_STD, | |
878 | .nr_regions = 2, | |
1da177e4 LT |
879 | .regions = { |
880 | ERASEINFO(0x02000, 8), | |
881 | ERASEINFO(0x10000, 7), | |
882 | } | |
883 | }, { | |
ae731822 | 884 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
885 | .dev_id = I28F400B3T, |
886 | .name = "Intel 28F400B3T", | |
5d3cce3b DW |
887 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
888 | .uaddr = MTD_UADDR_UNNECESSARY, | |
5d3cce3b DW |
889 | .dev_size = SIZE_512KiB, |
890 | .cmd_set = P_ID_INTEL_STD, | |
891 | .nr_regions = 2, | |
1da177e4 LT |
892 | .regions = { |
893 | ERASEINFO(0x10000, 7), | |
894 | ERASEINFO(0x02000, 8), | |
895 | } | |
896 | }, { | |
ae731822 | 897 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
898 | .dev_id = I28F008B3B, |
899 | .name = "Intel 28F008B3B", | |
5d3cce3b DW |
900 | .devtypes = CFI_DEVICETYPE_X8, |
901 | .uaddr = MTD_UADDR_UNNECESSARY, | |
902 | .dev_size = SIZE_1MiB, | |
903 | .cmd_set = P_ID_INTEL_STD, | |
904 | .nr_regions = 2, | |
1da177e4 LT |
905 | .regions = { |
906 | ERASEINFO(0x02000, 8), | |
907 | ERASEINFO(0x10000, 15), | |
908 | } | |
909 | }, { | |
ae731822 | 910 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
911 | .dev_id = I28F008B3T, |
912 | .name = "Intel 28F008B3T", | |
5d3cce3b DW |
913 | .devtypes = CFI_DEVICETYPE_X8, |
914 | .uaddr = MTD_UADDR_UNNECESSARY, | |
915 | .dev_size = SIZE_1MiB, | |
916 | .cmd_set = P_ID_INTEL_STD, | |
917 | .nr_regions = 2, | |
1da177e4 LT |
918 | .regions = { |
919 | ERASEINFO(0x10000, 15), | |
920 | ERASEINFO(0x02000, 8), | |
921 | } | |
922 | }, { | |
ae731822 | 923 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
924 | .dev_id = I28F008S5, |
925 | .name = "Intel 28F008S5", | |
5d3cce3b DW |
926 | .devtypes = CFI_DEVICETYPE_X8, |
927 | .uaddr = MTD_UADDR_UNNECESSARY, | |
928 | .dev_size = SIZE_1MiB, | |
929 | .cmd_set = P_ID_INTEL_EXT, | |
930 | .nr_regions = 1, | |
1da177e4 LT |
931 | .regions = { |
932 | ERASEINFO(0x10000,16), | |
933 | } | |
934 | }, { | |
ae731822 | 935 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
936 | .dev_id = I28F016S5, |
937 | .name = "Intel 28F016S5", | |
5d3cce3b DW |
938 | .devtypes = CFI_DEVICETYPE_X8, |
939 | .uaddr = MTD_UADDR_UNNECESSARY, | |
940 | .dev_size = SIZE_2MiB, | |
941 | .cmd_set = P_ID_INTEL_EXT, | |
942 | .nr_regions = 1, | |
1da177e4 LT |
943 | .regions = { |
944 | ERASEINFO(0x10000,32), | |
945 | } | |
946 | }, { | |
ae731822 | 947 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
948 | .dev_id = I28F008SA, |
949 | .name = "Intel 28F008SA", | |
5d3cce3b DW |
950 | .devtypes = CFI_DEVICETYPE_X8, |
951 | .uaddr = MTD_UADDR_UNNECESSARY, | |
952 | .dev_size = SIZE_1MiB, | |
953 | .cmd_set = P_ID_INTEL_STD, | |
954 | .nr_regions = 1, | |
1da177e4 LT |
955 | .regions = { |
956 | ERASEINFO(0x10000, 16), | |
957 | } | |
958 | }, { | |
ae731822 | 959 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
960 | .dev_id = I28F800B3B, |
961 | .name = "Intel 28F800B3B", | |
5d3cce3b DW |
962 | .devtypes = CFI_DEVICETYPE_X16, |
963 | .uaddr = MTD_UADDR_UNNECESSARY, | |
964 | .dev_size = SIZE_1MiB, | |
965 | .cmd_set = P_ID_INTEL_STD, | |
966 | .nr_regions = 2, | |
1da177e4 LT |
967 | .regions = { |
968 | ERASEINFO(0x02000, 8), | |
969 | ERASEINFO(0x10000, 15), | |
970 | } | |
971 | }, { | |
ae731822 | 972 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
973 | .dev_id = I28F800B3T, |
974 | .name = "Intel 28F800B3T", | |
5d3cce3b DW |
975 | .devtypes = CFI_DEVICETYPE_X16, |
976 | .uaddr = MTD_UADDR_UNNECESSARY, | |
977 | .dev_size = SIZE_1MiB, | |
978 | .cmd_set = P_ID_INTEL_STD, | |
979 | .nr_regions = 2, | |
1da177e4 LT |
980 | .regions = { |
981 | ERASEINFO(0x10000, 15), | |
982 | ERASEINFO(0x02000, 8), | |
983 | } | |
984 | }, { | |
ae731822 | 985 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
986 | .dev_id = I28F016B3B, |
987 | .name = "Intel 28F016B3B", | |
5d3cce3b DW |
988 | .devtypes = CFI_DEVICETYPE_X8, |
989 | .uaddr = MTD_UADDR_UNNECESSARY, | |
990 | .dev_size = SIZE_2MiB, | |
991 | .cmd_set = P_ID_INTEL_STD, | |
992 | .nr_regions = 2, | |
1da177e4 LT |
993 | .regions = { |
994 | ERASEINFO(0x02000, 8), | |
995 | ERASEINFO(0x10000, 31), | |
996 | } | |
997 | }, { | |
ae731822 | 998 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
999 | .dev_id = I28F016S3, |
1000 | .name = "Intel I28F016S3", | |
5d3cce3b DW |
1001 | .devtypes = CFI_DEVICETYPE_X8, |
1002 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1003 | .dev_size = SIZE_2MiB, | |
1004 | .cmd_set = P_ID_INTEL_STD, | |
1005 | .nr_regions = 1, | |
1da177e4 LT |
1006 | .regions = { |
1007 | ERASEINFO(0x10000, 32), | |
1008 | } | |
1009 | }, { | |
ae731822 | 1010 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1011 | .dev_id = I28F016B3T, |
1012 | .name = "Intel 28F016B3T", | |
5d3cce3b DW |
1013 | .devtypes = CFI_DEVICETYPE_X8, |
1014 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1015 | .dev_size = SIZE_2MiB, | |
1016 | .cmd_set = P_ID_INTEL_STD, | |
1017 | .nr_regions = 2, | |
1da177e4 LT |
1018 | .regions = { |
1019 | ERASEINFO(0x10000, 31), | |
1020 | ERASEINFO(0x02000, 8), | |
1021 | } | |
1022 | }, { | |
ae731822 | 1023 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1024 | .dev_id = I28F160B3B, |
1025 | .name = "Intel 28F160B3B", | |
5d3cce3b DW |
1026 | .devtypes = CFI_DEVICETYPE_X16, |
1027 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1028 | .dev_size = SIZE_2MiB, | |
1029 | .cmd_set = P_ID_INTEL_STD, | |
1030 | .nr_regions = 2, | |
1da177e4 LT |
1031 | .regions = { |
1032 | ERASEINFO(0x02000, 8), | |
1033 | ERASEINFO(0x10000, 31), | |
1034 | } | |
1035 | }, { | |
ae731822 | 1036 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1037 | .dev_id = I28F160B3T, |
1038 | .name = "Intel 28F160B3T", | |
5d3cce3b DW |
1039 | .devtypes = CFI_DEVICETYPE_X16, |
1040 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1041 | .dev_size = SIZE_2MiB, | |
1042 | .cmd_set = P_ID_INTEL_STD, | |
1043 | .nr_regions = 2, | |
1da177e4 LT |
1044 | .regions = { |
1045 | ERASEINFO(0x10000, 31), | |
1046 | ERASEINFO(0x02000, 8), | |
1047 | } | |
1048 | }, { | |
ae731822 | 1049 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1050 | .dev_id = I28F320B3B, |
1051 | .name = "Intel 28F320B3B", | |
5d3cce3b DW |
1052 | .devtypes = CFI_DEVICETYPE_X16, |
1053 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1054 | .dev_size = SIZE_4MiB, | |
1055 | .cmd_set = P_ID_INTEL_STD, | |
1056 | .nr_regions = 2, | |
1da177e4 LT |
1057 | .regions = { |
1058 | ERASEINFO(0x02000, 8), | |
1059 | ERASEINFO(0x10000, 63), | |
1060 | } | |
1061 | }, { | |
ae731822 | 1062 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1063 | .dev_id = I28F320B3T, |
1064 | .name = "Intel 28F320B3T", | |
5d3cce3b DW |
1065 | .devtypes = CFI_DEVICETYPE_X16, |
1066 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1067 | .dev_size = SIZE_4MiB, | |
1068 | .cmd_set = P_ID_INTEL_STD, | |
1069 | .nr_regions = 2, | |
1da177e4 LT |
1070 | .regions = { |
1071 | ERASEINFO(0x10000, 63), | |
1072 | ERASEINFO(0x02000, 8), | |
1073 | } | |
1074 | }, { | |
ae731822 | 1075 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1076 | .dev_id = I28F640B3B, |
1077 | .name = "Intel 28F640B3B", | |
5d3cce3b DW |
1078 | .devtypes = CFI_DEVICETYPE_X16, |
1079 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1080 | .dev_size = SIZE_8MiB, | |
1081 | .cmd_set = P_ID_INTEL_STD, | |
1082 | .nr_regions = 2, | |
1da177e4 LT |
1083 | .regions = { |
1084 | ERASEINFO(0x02000, 8), | |
1085 | ERASEINFO(0x10000, 127), | |
1086 | } | |
1087 | }, { | |
ae731822 | 1088 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1089 | .dev_id = I28F640B3T, |
1090 | .name = "Intel 28F640B3T", | |
5d3cce3b DW |
1091 | .devtypes = CFI_DEVICETYPE_X16, |
1092 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1093 | .dev_size = SIZE_8MiB, | |
1094 | .cmd_set = P_ID_INTEL_STD, | |
1095 | .nr_regions = 2, | |
1da177e4 LT |
1096 | .regions = { |
1097 | ERASEINFO(0x10000, 127), | |
1098 | ERASEINFO(0x02000, 8), | |
1099 | } | |
b4c8c8cf | 1100 | }, { |
ae731822 | 1101 | .mfr_id = CFI_MFR_INTEL, |
b4c8c8cf SR |
1102 | .dev_id = I28F640C3B, |
1103 | .name = "Intel 28F640C3B", | |
1104 | .devtypes = CFI_DEVICETYPE_X16, | |
1105 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1106 | .dev_size = SIZE_8MiB, | |
1107 | .cmd_set = P_ID_INTEL_STD, | |
1108 | .nr_regions = 2, | |
1109 | .regions = { | |
1110 | ERASEINFO(0x02000, 8), | |
1111 | ERASEINFO(0x10000, 127), | |
1112 | } | |
1da177e4 | 1113 | }, { |
ae731822 | 1114 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1115 | .dev_id = I82802AB, |
1116 | .name = "Intel 82802AB", | |
5d3cce3b DW |
1117 | .devtypes = CFI_DEVICETYPE_X8, |
1118 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1119 | .dev_size = SIZE_512KiB, | |
1120 | .cmd_set = P_ID_INTEL_EXT, | |
1121 | .nr_regions = 1, | |
1da177e4 LT |
1122 | .regions = { |
1123 | ERASEINFO(0x10000,8), | |
1124 | } | |
1125 | }, { | |
ae731822 | 1126 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1127 | .dev_id = I82802AC, |
1128 | .name = "Intel 82802AC", | |
5d3cce3b DW |
1129 | .devtypes = CFI_DEVICETYPE_X8, |
1130 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1131 | .dev_size = SIZE_1MiB, | |
1132 | .cmd_set = P_ID_INTEL_EXT, | |
1133 | .nr_regions = 1, | |
1da177e4 LT |
1134 | .regions = { |
1135 | ERASEINFO(0x10000,16), | |
1136 | } | |
1137 | }, { | |
ae731822 | 1138 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1139 | .dev_id = MX29LV040C, |
1140 | .name = "Macronix MX29LV040C", | |
5d3cce3b DW |
1141 | .devtypes = CFI_DEVICETYPE_X8, |
1142 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1143 | .dev_size = SIZE_512KiB, | |
1144 | .cmd_set = P_ID_AMD_STD, | |
1145 | .nr_regions = 1, | |
1da177e4 LT |
1146 | .regions = { |
1147 | ERASEINFO(0x10000,8), | |
1148 | } | |
1149 | }, { | |
ae731822 | 1150 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1151 | .dev_id = MX29LV160T, |
1152 | .name = "MXIC MX29LV160T", | |
5d3cce3b DW |
1153 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1154 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1155 | .dev_size = SIZE_2MiB, |
1156 | .cmd_set = P_ID_AMD_STD, | |
1157 | .nr_regions = 4, | |
1da177e4 LT |
1158 | .regions = { |
1159 | ERASEINFO(0x10000,31), | |
1160 | ERASEINFO(0x08000,1), | |
1161 | ERASEINFO(0x02000,2), | |
1162 | ERASEINFO(0x04000,1) | |
1163 | } | |
1164 | }, { | |
ae731822 | 1165 | .mfr_id = CFI_MFR_NEC, |
1da177e4 LT |
1166 | .dev_id = UPD29F064115, |
1167 | .name = "NEC uPD29F064115", | |
9aff1b1a HI |
1168 | .devtypes = CFI_DEVICETYPE_X16, |
1169 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
5d3cce3b DW |
1170 | .dev_size = SIZE_8MiB, |
1171 | .cmd_set = P_ID_AMD_STD, | |
1172 | .nr_regions = 3, | |
1da177e4 LT |
1173 | .regions = { |
1174 | ERASEINFO(0x2000,8), | |
1175 | ERASEINFO(0x10000,126), | |
1176 | ERASEINFO(0x2000,8), | |
1177 | } | |
1178 | }, { | |
ae731822 | 1179 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1180 | .dev_id = MX29LV160B, |
1181 | .name = "MXIC MX29LV160B", | |
5d3cce3b DW |
1182 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1183 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1184 | .dev_size = SIZE_2MiB, |
1185 | .cmd_set = P_ID_AMD_STD, | |
1186 | .nr_regions = 4, | |
1da177e4 LT |
1187 | .regions = { |
1188 | ERASEINFO(0x04000,1), | |
1189 | ERASEINFO(0x02000,2), | |
1190 | ERASEINFO(0x08000,1), | |
1191 | ERASEINFO(0x10000,31) | |
1192 | } | |
1193 | }, { | |
ae731822 | 1194 | .mfr_id = CFI_MFR_MACRONIX, |
c4e6952f TY |
1195 | .dev_id = MX29F040, |
1196 | .name = "Macronix MX29F040", | |
5d3cce3b DW |
1197 | .devtypes = CFI_DEVICETYPE_X8, |
1198 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1199 | .dev_size = SIZE_512KiB, | |
1200 | .cmd_set = P_ID_AMD_STD, | |
1201 | .nr_regions = 1, | |
c4e6952f TY |
1202 | .regions = { |
1203 | ERASEINFO(0x10000,8), | |
1204 | } | |
35d086b1 | 1205 | }, { |
ae731822 | 1206 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1207 | .dev_id = MX29F016, |
1208 | .name = "Macronix MX29F016", | |
5d3cce3b DW |
1209 | .devtypes = CFI_DEVICETYPE_X8, |
1210 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1211 | .dev_size = SIZE_2MiB, | |
1212 | .cmd_set = P_ID_AMD_STD, | |
1213 | .nr_regions = 1, | |
1da177e4 LT |
1214 | .regions = { |
1215 | ERASEINFO(0x10000,32), | |
1216 | } | |
35d086b1 | 1217 | }, { |
ae731822 | 1218 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1219 | .dev_id = MX29F004T, |
1220 | .name = "Macronix MX29F004T", | |
5d3cce3b DW |
1221 | .devtypes = CFI_DEVICETYPE_X8, |
1222 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1223 | .dev_size = SIZE_512KiB, | |
1224 | .cmd_set = P_ID_AMD_STD, | |
1225 | .nr_regions = 4, | |
1da177e4 LT |
1226 | .regions = { |
1227 | ERASEINFO(0x10000,7), | |
1228 | ERASEINFO(0x08000,1), | |
1229 | ERASEINFO(0x02000,2), | |
1230 | ERASEINFO(0x04000,1), | |
1231 | } | |
35d086b1 | 1232 | }, { |
ae731822 | 1233 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1234 | .dev_id = MX29F004B, |
1235 | .name = "Macronix MX29F004B", | |
5d3cce3b DW |
1236 | .devtypes = CFI_DEVICETYPE_X8, |
1237 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1238 | .dev_size = SIZE_512KiB, | |
1239 | .cmd_set = P_ID_AMD_STD, | |
1240 | .nr_regions = 4, | |
1da177e4 LT |
1241 | .regions = { |
1242 | ERASEINFO(0x04000,1), | |
1243 | ERASEINFO(0x02000,2), | |
1244 | ERASEINFO(0x08000,1), | |
1245 | ERASEINFO(0x10000,7), | |
1246 | } | |
1247 | }, { | |
ae731822 | 1248 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1249 | .dev_id = MX29F002T, |
1250 | .name = "Macronix MX29F002T", | |
5d3cce3b DW |
1251 | .devtypes = CFI_DEVICETYPE_X8, |
1252 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1253 | .dev_size = SIZE_256KiB, | |
1254 | .cmd_set = P_ID_AMD_STD, | |
1255 | .nr_regions = 4, | |
1da177e4 LT |
1256 | .regions = { |
1257 | ERASEINFO(0x10000,3), | |
1258 | ERASEINFO(0x08000,1), | |
1259 | ERASEINFO(0x02000,2), | |
1260 | ERASEINFO(0x04000,1), | |
1261 | } | |
1262 | }, { | |
ae731822 | 1263 | .mfr_id = CFI_MFR_PMC, |
1da177e4 LT |
1264 | .dev_id = PM49FL002, |
1265 | .name = "PMC Pm49FL002", | |
5d3cce3b DW |
1266 | .devtypes = CFI_DEVICETYPE_X8, |
1267 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1268 | .dev_size = SIZE_256KiB, | |
1269 | .cmd_set = P_ID_AMD_STD, | |
1270 | .nr_regions = 1, | |
1da177e4 LT |
1271 | .regions = { |
1272 | ERASEINFO( 0x01000, 64 ) | |
1273 | } | |
1274 | }, { | |
ae731822 | 1275 | .mfr_id = CFI_MFR_PMC, |
1da177e4 LT |
1276 | .dev_id = PM49FL004, |
1277 | .name = "PMC Pm49FL004", | |
5d3cce3b DW |
1278 | .devtypes = CFI_DEVICETYPE_X8, |
1279 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1280 | .dev_size = SIZE_512KiB, | |
1281 | .cmd_set = P_ID_AMD_STD, | |
1282 | .nr_regions = 1, | |
1da177e4 LT |
1283 | .regions = { |
1284 | ERASEINFO( 0x01000, 128 ) | |
1285 | } | |
1286 | }, { | |
ae731822 | 1287 | .mfr_id = CFI_MFR_PMC, |
1da177e4 LT |
1288 | .dev_id = PM49FL008, |
1289 | .name = "PMC Pm49FL008", | |
5d3cce3b DW |
1290 | .devtypes = CFI_DEVICETYPE_X8, |
1291 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1292 | .dev_size = SIZE_1MiB, | |
1293 | .cmd_set = P_ID_AMD_STD, | |
1294 | .nr_regions = 1, | |
1da177e4 LT |
1295 | .regions = { |
1296 | ERASEINFO( 0x01000, 256 ) | |
1297 | } | |
a63ec1b7 | 1298 | }, { |
ae731822 | 1299 | .mfr_id = CFI_MFR_SHARP, |
a63ec1b7 PM |
1300 | .dev_id = LH28F640BF, |
1301 | .name = "LH28F640BF", | |
fe2f4c8e | 1302 | .devtypes = CFI_DEVICETYPE_X16, |
5d3cce3b | 1303 | .uaddr = MTD_UADDR_UNNECESSARY, |
fe2f4c8e AA |
1304 | .dev_size = SIZE_8MiB, |
1305 | .cmd_set = P_ID_INTEL_EXT, | |
1306 | .nr_regions = 2, | |
5d3cce3b | 1307 | .regions = { |
fe2f4c8e AA |
1308 | ERASEINFO(0x10000, 127), |
1309 | ERASEINFO(0x02000, 8), | |
a63ec1b7 | 1310 | } |
35d086b1 | 1311 | }, { |
ae731822 | 1312 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1313 | .dev_id = SST39LF512, |
1314 | .name = "SST 39LF512", | |
5d3cce3b DW |
1315 | .devtypes = CFI_DEVICETYPE_X8, |
1316 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1317 | .dev_size = SIZE_64KiB, | |
1318 | .cmd_set = P_ID_AMD_STD, | |
1319 | .nr_regions = 1, | |
1da177e4 LT |
1320 | .regions = { |
1321 | ERASEINFO(0x01000,16), | |
1322 | } | |
35d086b1 | 1323 | }, { |
ae731822 | 1324 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1325 | .dev_id = SST39LF010, |
1326 | .name = "SST 39LF010", | |
5d3cce3b DW |
1327 | .devtypes = CFI_DEVICETYPE_X8, |
1328 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1329 | .dev_size = SIZE_128KiB, | |
1330 | .cmd_set = P_ID_AMD_STD, | |
1331 | .nr_regions = 1, | |
1da177e4 LT |
1332 | .regions = { |
1333 | ERASEINFO(0x01000,32), | |
1334 | } | |
35d086b1 | 1335 | }, { |
ae731822 | 1336 | .mfr_id = CFI_MFR_SST, |
7d84b627 | 1337 | .dev_id = SST29EE020, |
1da177e4 | 1338 | .name = "SST 29EE020", |
5d3cce3b DW |
1339 | .devtypes = CFI_DEVICETYPE_X8, |
1340 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1341 | .dev_size = SIZE_256KiB, | |
1342 | .cmd_set = P_ID_SST_PAGE, | |
1343 | .nr_regions = 1, | |
1344 | .regions = {ERASEINFO(0x01000,64), | |
1345 | } | |
1346 | }, { | |
7d84b627 | 1347 | .mfr_id = CFI_MFR_SST, |
1da177e4 | 1348 | .dev_id = SST29LE020, |
7d84b627 | 1349 | .name = "SST 29LE020", |
5d3cce3b DW |
1350 | .devtypes = CFI_DEVICETYPE_X8, |
1351 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1352 | .dev_size = SIZE_256KiB, | |
1353 | .cmd_set = P_ID_SST_PAGE, | |
1354 | .nr_regions = 1, | |
1355 | .regions = {ERASEINFO(0x01000,64), | |
1356 | } | |
1da177e4 | 1357 | }, { |
ae731822 | 1358 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1359 | .dev_id = SST39LF020, |
1360 | .name = "SST 39LF020", | |
5d3cce3b DW |
1361 | .devtypes = CFI_DEVICETYPE_X8, |
1362 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1363 | .dev_size = SIZE_256KiB, | |
1364 | .cmd_set = P_ID_AMD_STD, | |
1365 | .nr_regions = 1, | |
1da177e4 LT |
1366 | .regions = { |
1367 | ERASEINFO(0x01000,64), | |
1368 | } | |
35d086b1 | 1369 | }, { |
ae731822 | 1370 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1371 | .dev_id = SST39LF040, |
1372 | .name = "SST 39LF040", | |
5d3cce3b DW |
1373 | .devtypes = CFI_DEVICETYPE_X8, |
1374 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1375 | .dev_size = SIZE_512KiB, | |
1376 | .cmd_set = P_ID_AMD_STD, | |
1377 | .nr_regions = 1, | |
1da177e4 LT |
1378 | .regions = { |
1379 | ERASEINFO(0x01000,128), | |
1380 | } | |
35d086b1 | 1381 | }, { |
ae731822 | 1382 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1383 | .dev_id = SST39SF010A, |
1384 | .name = "SST 39SF010A", | |
5d3cce3b DW |
1385 | .devtypes = CFI_DEVICETYPE_X8, |
1386 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1387 | .dev_size = SIZE_128KiB, | |
1388 | .cmd_set = P_ID_AMD_STD, | |
1389 | .nr_regions = 1, | |
1da177e4 LT |
1390 | .regions = { |
1391 | ERASEINFO(0x01000,32), | |
1392 | } | |
35d086b1 | 1393 | }, { |
ae731822 | 1394 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1395 | .dev_id = SST39SF020A, |
1396 | .name = "SST 39SF020A", | |
5d3cce3b DW |
1397 | .devtypes = CFI_DEVICETYPE_X8, |
1398 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1399 | .dev_size = SIZE_256KiB, | |
1400 | .cmd_set = P_ID_AMD_STD, | |
1401 | .nr_regions = 1, | |
1da177e4 LT |
1402 | .regions = { |
1403 | ERASEINFO(0x01000,64), | |
1404 | } | |
a0645ce9 | 1405 | }, { |
ae731822 | 1406 | .mfr_id = CFI_MFR_SST, |
a0645ce9 MM |
1407 | .dev_id = SST39SF040, |
1408 | .name = "SST 39SF040", | |
1409 | .devtypes = CFI_DEVICETYPE_X8, | |
1410 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1411 | .dev_size = SIZE_512KiB, | |
1412 | .cmd_set = P_ID_AMD_STD, | |
1413 | .nr_regions = 1, | |
1414 | .regions = { | |
1415 | ERASEINFO(0x01000,128), | |
1416 | } | |
1da177e4 | 1417 | }, { |
ae731822 | 1418 | .mfr_id = CFI_MFR_SST, |
5d3cce3b DW |
1419 | .dev_id = SST49LF040B, |
1420 | .name = "SST 49LF040B", | |
1421 | .devtypes = CFI_DEVICETYPE_X8, | |
1422 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1423 | .dev_size = SIZE_512KiB, | |
1424 | .cmd_set = P_ID_AMD_STD, | |
1425 | .nr_regions = 1, | |
1426 | .regions = { | |
89072ef9 RJ |
1427 | ERASEINFO(0x01000,128), |
1428 | } | |
1429 | }, { | |
1430 | ||
ae731822 | 1431 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1432 | .dev_id = SST49LF004B, |
1433 | .name = "SST 49LF004B", | |
5d3cce3b DW |
1434 | .devtypes = CFI_DEVICETYPE_X8, |
1435 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1436 | .dev_size = SIZE_512KiB, | |
1437 | .cmd_set = P_ID_AMD_STD, | |
1438 | .nr_regions = 1, | |
1da177e4 LT |
1439 | .regions = { |
1440 | ERASEINFO(0x01000,128), | |
1441 | } | |
1442 | }, { | |
ae731822 | 1443 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1444 | .dev_id = SST49LF008A, |
1445 | .name = "SST 49LF008A", | |
5d3cce3b DW |
1446 | .devtypes = CFI_DEVICETYPE_X8, |
1447 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1448 | .dev_size = SIZE_1MiB, | |
1449 | .cmd_set = P_ID_AMD_STD, | |
1450 | .nr_regions = 1, | |
1da177e4 LT |
1451 | .regions = { |
1452 | ERASEINFO(0x01000,256), | |
1453 | } | |
1454 | }, { | |
ae731822 | 1455 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1456 | .dev_id = SST49LF030A, |
1457 | .name = "SST 49LF030A", | |
5d3cce3b DW |
1458 | .devtypes = CFI_DEVICETYPE_X8, |
1459 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1460 | .dev_size = SIZE_512KiB, | |
1461 | .cmd_set = P_ID_AMD_STD, | |
1462 | .nr_regions = 1, | |
1da177e4 LT |
1463 | .regions = { |
1464 | ERASEINFO(0x01000,96), | |
1465 | } | |
1466 | }, { | |
ae731822 | 1467 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1468 | .dev_id = SST49LF040A, |
1469 | .name = "SST 49LF040A", | |
5d3cce3b DW |
1470 | .devtypes = CFI_DEVICETYPE_X8, |
1471 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1472 | .dev_size = SIZE_512KiB, | |
1473 | .cmd_set = P_ID_AMD_STD, | |
1474 | .nr_regions = 1, | |
1da177e4 LT |
1475 | .regions = { |
1476 | ERASEINFO(0x01000,128), | |
1477 | } | |
1478 | }, { | |
ae731822 | 1479 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1480 | .dev_id = SST49LF080A, |
1481 | .name = "SST 49LF080A", | |
5d3cce3b DW |
1482 | .devtypes = CFI_DEVICETYPE_X8, |
1483 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1484 | .dev_size = SIZE_1MiB, | |
1485 | .cmd_set = P_ID_AMD_STD, | |
1486 | .nr_regions = 1, | |
1da177e4 LT |
1487 | .regions = { |
1488 | ERASEINFO(0x01000,256), | |
1489 | } | |
1490 | }, { | |
ae731822 | 1491 | .mfr_id = CFI_MFR_SST, /* should be CFI */ |
5d3cce3b DW |
1492 | .dev_id = SST39LF160, |
1493 | .name = "SST 39LF160", | |
ca6f12c6 AN |
1494 | .devtypes = CFI_DEVICETYPE_X16, |
1495 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
5d3cce3b DW |
1496 | .dev_size = SIZE_2MiB, |
1497 | .cmd_set = P_ID_AMD_STD, | |
1498 | .nr_regions = 2, | |
1499 | .regions = { | |
1500 | ERASEINFO(0x1000,256), | |
1501 | ERASEINFO(0x1000,256) | |
1502 | } | |
1503 | }, { | |
ae731822 | 1504 | .mfr_id = CFI_MFR_SST, /* should be CFI */ |
5d3cce3b DW |
1505 | .dev_id = SST39VF1601, |
1506 | .name = "SST 39VF1601", | |
ca6f12c6 AN |
1507 | .devtypes = CFI_DEVICETYPE_X16, |
1508 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
5d3cce3b DW |
1509 | .dev_size = SIZE_2MiB, |
1510 | .cmd_set = P_ID_AMD_STD, | |
1511 | .nr_regions = 2, | |
1512 | .regions = { | |
1513 | ERASEINFO(0x1000,256), | |
1514 | ERASEINFO(0x1000,256) | |
1515 | } | |
087acaf1 WS |
1516 | }, { |
1517 | /* CFI is broken: reports AMD_STD, but needs custom uaddr */ | |
1518 | .mfr_id = CFI_MFR_SST, | |
1519 | .dev_id = SST39WF1601, | |
1520 | .name = "SST 39WF1601", | |
1521 | .devtypes = CFI_DEVICETYPE_X16, | |
1522 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
1523 | .dev_size = SIZE_2MiB, | |
1524 | .cmd_set = P_ID_AMD_STD, | |
1525 | .nr_regions = 2, | |
1526 | .regions = { | |
1527 | ERASEINFO(0x1000,256), | |
1528 | ERASEINFO(0x1000,256) | |
1529 | } | |
1530 | }, { | |
1531 | /* CFI is broken: reports AMD_STD, but needs custom uaddr */ | |
1532 | .mfr_id = CFI_MFR_SST, | |
1533 | .dev_id = SST39WF1602, | |
1534 | .name = "SST 39WF1602", | |
1535 | .devtypes = CFI_DEVICETYPE_X16, | |
1536 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
1537 | .dev_size = SIZE_2MiB, | |
1538 | .cmd_set = P_ID_AMD_STD, | |
1539 | .nr_regions = 2, | |
1540 | .regions = { | |
1541 | ERASEINFO(0x1000,256), | |
1542 | ERASEINFO(0x1000,256) | |
1543 | } | |
bd50a0ff | 1544 | }, { |
ae731822 | 1545 | .mfr_id = CFI_MFR_SST, /* should be CFI */ |
bd50a0ff YY |
1546 | .dev_id = SST39VF3201, |
1547 | .name = "SST 39VF3201", | |
1548 | .devtypes = CFI_DEVICETYPE_X16, | |
1549 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
1550 | .dev_size = SIZE_4MiB, | |
1551 | .cmd_set = P_ID_AMD_STD, | |
1552 | .nr_regions = 4, | |
1553 | .regions = { | |
1554 | ERASEINFO(0x1000,256), | |
1555 | ERASEINFO(0x1000,256), | |
1556 | ERASEINFO(0x1000,256), | |
1557 | ERASEINFO(0x1000,256) | |
1558 | } | |
1b0a062b | 1559 | }, { |
ae731822 | 1560 | .mfr_id = CFI_MFR_SST, |
1b0a062b AD |
1561 | .dev_id = SST36VF3203, |
1562 | .name = "SST 36VF3203", | |
1563 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
1564 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
1565 | .dev_size = SIZE_4MiB, | |
1566 | .cmd_set = P_ID_AMD_STD, | |
1567 | .nr_regions = 1, | |
1568 | .regions = { | |
1569 | ERASEINFO(0x10000,64), | |
1570 | } | |
c9856e39 | 1571 | }, { |
ae731822 | 1572 | .mfr_id = CFI_MFR_ST, |
c9856e39 PDM |
1573 | .dev_id = M29F800AB, |
1574 | .name = "ST M29F800AB", | |
5d3cce3b DW |
1575 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1576 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1577 | .dev_size = SIZE_1MiB, |
1578 | .cmd_set = P_ID_AMD_STD, | |
1579 | .nr_regions = 4, | |
c9856e39 PDM |
1580 | .regions = { |
1581 | ERASEINFO(0x04000,1), | |
1582 | ERASEINFO(0x02000,2), | |
1583 | ERASEINFO(0x08000,1), | |
1584 | ERASEINFO(0x10000,15), | |
1585 | } | |
35d086b1 | 1586 | }, { |
ae731822 | 1587 | .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */ |
1da177e4 LT |
1588 | .dev_id = M29W800DT, |
1589 | .name = "ST M29W800DT", | |
5d3cce3b | 1590 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
db5432db | 1591 | .uaddr = MTD_UADDR_0x0AAA_0x0555, |
5d3cce3b DW |
1592 | .dev_size = SIZE_1MiB, |
1593 | .cmd_set = P_ID_AMD_STD, | |
1594 | .nr_regions = 4, | |
1da177e4 LT |
1595 | .regions = { |
1596 | ERASEINFO(0x10000,15), | |
1597 | ERASEINFO(0x08000,1), | |
1598 | ERASEINFO(0x02000,2), | |
1599 | ERASEINFO(0x04000,1) | |
1600 | } | |
1601 | }, { | |
ae731822 | 1602 | .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */ |
1da177e4 LT |
1603 | .dev_id = M29W800DB, |
1604 | .name = "ST M29W800DB", | |
5d3cce3b | 1605 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
db5432db | 1606 | .uaddr = MTD_UADDR_0x0AAA_0x0555, |
5d3cce3b DW |
1607 | .dev_size = SIZE_1MiB, |
1608 | .cmd_set = P_ID_AMD_STD, | |
1609 | .nr_regions = 4, | |
1da177e4 LT |
1610 | .regions = { |
1611 | ERASEINFO(0x04000,1), | |
1612 | ERASEINFO(0x02000,2), | |
1613 | ERASEINFO(0x08000,1), | |
1614 | ERASEINFO(0x10000,15) | |
1615 | } | |
30d6a24e | 1616 | }, { |
ae731822 | 1617 | .mfr_id = CFI_MFR_ST, |
30d6a24e GF |
1618 | .dev_id = M29W400DT, |
1619 | .name = "ST M29W400DT", | |
1620 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
1621 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
1622 | .dev_size = SIZE_512KiB, | |
1623 | .cmd_set = P_ID_AMD_STD, | |
1624 | .nr_regions = 4, | |
1625 | .regions = { | |
1626 | ERASEINFO(0x04000,7), | |
1627 | ERASEINFO(0x02000,1), | |
1628 | ERASEINFO(0x08000,2), | |
1629 | ERASEINFO(0x10000,1) | |
1630 | } | |
1631 | }, { | |
ae731822 | 1632 | .mfr_id = CFI_MFR_ST, |
30d6a24e GF |
1633 | .dev_id = M29W400DB, |
1634 | .name = "ST M29W400DB", | |
1635 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
1636 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
1637 | .dev_size = SIZE_512KiB, | |
1638 | .cmd_set = P_ID_AMD_STD, | |
1639 | .nr_regions = 4, | |
1640 | .regions = { | |
1641 | ERASEINFO(0x04000,1), | |
1642 | ERASEINFO(0x02000,2), | |
1643 | ERASEINFO(0x08000,1), | |
1644 | ERASEINFO(0x10000,7) | |
1645 | } | |
1da177e4 | 1646 | }, { |
ae731822 | 1647 | .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */ |
1da177e4 LT |
1648 | .dev_id = M29W160DT, |
1649 | .name = "ST M29W160DT", | |
5d3cce3b | 1650 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 1651 | .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ |
5d3cce3b DW |
1652 | .dev_size = SIZE_2MiB, |
1653 | .cmd_set = P_ID_AMD_STD, | |
1654 | .nr_regions = 4, | |
1da177e4 LT |
1655 | .regions = { |
1656 | ERASEINFO(0x10000,31), | |
1657 | ERASEINFO(0x08000,1), | |
1658 | ERASEINFO(0x02000,2), | |
1659 | ERASEINFO(0x04000,1) | |
1660 | } | |
1661 | }, { | |
ae731822 | 1662 | .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */ |
1da177e4 LT |
1663 | .dev_id = M29W160DB, |
1664 | .name = "ST M29W160DB", | |
5d3cce3b | 1665 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 1666 | .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ |
5d3cce3b DW |
1667 | .dev_size = SIZE_2MiB, |
1668 | .cmd_set = P_ID_AMD_STD, | |
1669 | .nr_regions = 4, | |
1da177e4 LT |
1670 | .regions = { |
1671 | ERASEINFO(0x04000,1), | |
1672 | ERASEINFO(0x02000,2), | |
1673 | ERASEINFO(0x08000,1), | |
1674 | ERASEINFO(0x10000,31) | |
1675 | } | |
35d086b1 | 1676 | }, { |
ae731822 | 1677 | .mfr_id = CFI_MFR_ST, |
1da177e4 LT |
1678 | .dev_id = M29W040B, |
1679 | .name = "ST M29W040B", | |
5d3cce3b DW |
1680 | .devtypes = CFI_DEVICETYPE_X8, |
1681 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1682 | .dev_size = SIZE_512KiB, | |
1683 | .cmd_set = P_ID_AMD_STD, | |
1684 | .nr_regions = 1, | |
1da177e4 LT |
1685 | .regions = { |
1686 | ERASEINFO(0x10000,8), | |
1687 | } | |
35d086b1 | 1688 | }, { |
ae731822 | 1689 | .mfr_id = CFI_MFR_ST, |
1da177e4 LT |
1690 | .dev_id = M50FW040, |
1691 | .name = "ST M50FW040", | |
5d3cce3b DW |
1692 | .devtypes = CFI_DEVICETYPE_X8, |
1693 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1694 | .dev_size = SIZE_512KiB, | |
1695 | .cmd_set = P_ID_INTEL_EXT, | |
1696 | .nr_regions = 1, | |
1da177e4 LT |
1697 | .regions = { |
1698 | ERASEINFO(0x10000,8), | |
1699 | } | |
35d086b1 | 1700 | }, { |
ae731822 | 1701 | .mfr_id = CFI_MFR_ST, |
1da177e4 LT |
1702 | .dev_id = M50FW080, |
1703 | .name = "ST M50FW080", | |
5d3cce3b DW |
1704 | .devtypes = CFI_DEVICETYPE_X8, |
1705 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1706 | .dev_size = SIZE_1MiB, | |
1707 | .cmd_set = P_ID_INTEL_EXT, | |
1708 | .nr_regions = 1, | |
1da177e4 LT |
1709 | .regions = { |
1710 | ERASEINFO(0x10000,16), | |
1711 | } | |
35d086b1 | 1712 | }, { |
ae731822 | 1713 | .mfr_id = CFI_MFR_ST, |
1da177e4 LT |
1714 | .dev_id = M50FW016, |
1715 | .name = "ST M50FW016", | |
5d3cce3b DW |
1716 | .devtypes = CFI_DEVICETYPE_X8, |
1717 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1718 | .dev_size = SIZE_2MiB, | |
1719 | .cmd_set = P_ID_INTEL_EXT, | |
1720 | .nr_regions = 1, | |
1da177e4 LT |
1721 | .regions = { |
1722 | ERASEINFO(0x10000,32), | |
1723 | } | |
1724 | }, { | |
ae731822 | 1725 | .mfr_id = CFI_MFR_ST, |
1da177e4 LT |
1726 | .dev_id = M50LPW080, |
1727 | .name = "ST M50LPW080", | |
5d3cce3b DW |
1728 | .devtypes = CFI_DEVICETYPE_X8, |
1729 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1730 | .dev_size = SIZE_1MiB, | |
1731 | .cmd_set = P_ID_INTEL_EXT, | |
1732 | .nr_regions = 1, | |
1da177e4 LT |
1733 | .regions = { |
1734 | ERASEINFO(0x10000,16), | |
deb1a5f1 NC |
1735 | }, |
1736 | }, { | |
ae731822 | 1737 | .mfr_id = CFI_MFR_ST, |
deb1a5f1 NC |
1738 | .dev_id = M50FLW080A, |
1739 | .name = "ST M50FLW080A", | |
1740 | .devtypes = CFI_DEVICETYPE_X8, | |
1741 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1742 | .dev_size = SIZE_1MiB, | |
1743 | .cmd_set = P_ID_INTEL_EXT, | |
1744 | .nr_regions = 4, | |
1745 | .regions = { | |
1746 | ERASEINFO(0x1000,16), | |
1747 | ERASEINFO(0x10000,13), | |
1748 | ERASEINFO(0x1000,16), | |
1749 | ERASEINFO(0x1000,16), | |
1750 | } | |
1751 | }, { | |
ae731822 | 1752 | .mfr_id = CFI_MFR_ST, |
deb1a5f1 NC |
1753 | .dev_id = M50FLW080B, |
1754 | .name = "ST M50FLW080B", | |
1755 | .devtypes = CFI_DEVICETYPE_X8, | |
1756 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1757 | .dev_size = SIZE_1MiB, | |
1758 | .cmd_set = P_ID_INTEL_EXT, | |
1759 | .nr_regions = 4, | |
1760 | .regions = { | |
1761 | ERASEINFO(0x1000,16), | |
1762 | ERASEINFO(0x1000,16), | |
1763 | ERASEINFO(0x10000,13), | |
1764 | ERASEINFO(0x1000,16), | |
1da177e4 | 1765 | } |
e1070211 | 1766 | }, { |
ae731822 | 1767 | .mfr_id = 0xff00 | CFI_MFR_ST, |
e1070211 MF |
1768 | .dev_id = 0xff00 | PSD4256G6V, |
1769 | .name = "ST PSD4256G6V", | |
1770 | .devtypes = CFI_DEVICETYPE_X16, | |
1771 | .uaddr = MTD_UADDR_0x0AAA_0x0554, | |
1772 | .dev_size = SIZE_1MiB, | |
1773 | .cmd_set = P_ID_AMD_STD, | |
1774 | .nr_regions = 1, | |
1775 | .regions = { | |
1776 | ERASEINFO(0x10000,16), | |
1777 | } | |
1da177e4 | 1778 | }, { |
ae731822 | 1779 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1780 | .dev_id = TC58FVT160, |
1781 | .name = "Toshiba TC58FVT160", | |
5d3cce3b DW |
1782 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1783 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1784 | .dev_size = SIZE_2MiB, |
1785 | .cmd_set = P_ID_AMD_STD, | |
1786 | .nr_regions = 4, | |
1da177e4 LT |
1787 | .regions = { |
1788 | ERASEINFO(0x10000,31), | |
1789 | ERASEINFO(0x08000,1), | |
1790 | ERASEINFO(0x02000,2), | |
1791 | ERASEINFO(0x04000,1) | |
1792 | } | |
1793 | }, { | |
ae731822 | 1794 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1795 | .dev_id = TC58FVB160, |
1796 | .name = "Toshiba TC58FVB160", | |
5d3cce3b DW |
1797 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1798 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1799 | .dev_size = SIZE_2MiB, |
1800 | .cmd_set = P_ID_AMD_STD, | |
1801 | .nr_regions = 4, | |
1da177e4 LT |
1802 | .regions = { |
1803 | ERASEINFO(0x04000,1), | |
1804 | ERASEINFO(0x02000,2), | |
1805 | ERASEINFO(0x08000,1), | |
1806 | ERASEINFO(0x10000,31) | |
1807 | } | |
1808 | }, { | |
ae731822 | 1809 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1810 | .dev_id = TC58FVB321, |
1811 | .name = "Toshiba TC58FVB321", | |
5d3cce3b DW |
1812 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1813 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1814 | .dev_size = SIZE_4MiB, |
1815 | .cmd_set = P_ID_AMD_STD, | |
1816 | .nr_regions = 2, | |
1da177e4 LT |
1817 | .regions = { |
1818 | ERASEINFO(0x02000,8), | |
1819 | ERASEINFO(0x10000,63) | |
1820 | } | |
1821 | }, { | |
ae731822 | 1822 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1823 | .dev_id = TC58FVT321, |
1824 | .name = "Toshiba TC58FVT321", | |
5d3cce3b DW |
1825 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1826 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1827 | .dev_size = SIZE_4MiB, |
1828 | .cmd_set = P_ID_AMD_STD, | |
1829 | .nr_regions = 2, | |
1da177e4 LT |
1830 | .regions = { |
1831 | ERASEINFO(0x10000,63), | |
1832 | ERASEINFO(0x02000,8) | |
1833 | } | |
1834 | }, { | |
ae731822 | 1835 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1836 | .dev_id = TC58FVB641, |
1837 | .name = "Toshiba TC58FVB641", | |
5d3cce3b DW |
1838 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1839 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1840 | .dev_size = SIZE_8MiB, |
1841 | .cmd_set = P_ID_AMD_STD, | |
1842 | .nr_regions = 2, | |
1da177e4 LT |
1843 | .regions = { |
1844 | ERASEINFO(0x02000,8), | |
1845 | ERASEINFO(0x10000,127) | |
1846 | } | |
1847 | }, { | |
ae731822 | 1848 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1849 | .dev_id = TC58FVT641, |
1850 | .name = "Toshiba TC58FVT641", | |
5d3cce3b DW |
1851 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1852 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1853 | .dev_size = SIZE_8MiB, |
1854 | .cmd_set = P_ID_AMD_STD, | |
1855 | .nr_regions = 2, | |
1da177e4 LT |
1856 | .regions = { |
1857 | ERASEINFO(0x10000,127), | |
1858 | ERASEINFO(0x02000,8) | |
1859 | } | |
1860 | }, { | |
ae731822 | 1861 | .mfr_id = CFI_MFR_WINBOND, |
1da177e4 LT |
1862 | .dev_id = W49V002A, |
1863 | .name = "Winbond W49V002A", | |
5d3cce3b DW |
1864 | .devtypes = CFI_DEVICETYPE_X8, |
1865 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1866 | .dev_size = SIZE_256KiB, | |
1867 | .cmd_set = P_ID_AMD_STD, | |
1868 | .nr_regions = 4, | |
1da177e4 LT |
1869 | .regions = { |
1870 | ERASEINFO(0x10000, 3), | |
1871 | ERASEINFO(0x08000, 1), | |
1872 | ERASEINFO(0x02000, 2), | |
1873 | ERASEINFO(0x04000, 1), | |
1874 | } | |
1875 | } | |
1876 | }; | |
1877 | ||
5d3cce3b | 1878 | static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base, |
1da177e4 LT |
1879 | struct cfi_private *cfi) |
1880 | { | |
1881 | map_word result; | |
1882 | unsigned long mask; | |
5c9c11e1 MR |
1883 | int bank = 0; |
1884 | ||
1885 | /* According to JEDEC "Standard Manufacturer's Identification Code" | |
1886 | * (http://www.jedec.org/download/search/jep106W.pdf) | |
1887 | * several first banks can contain 0x7f instead of actual ID | |
1888 | */ | |
1889 | do { | |
467622ef | 1890 | uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi); |
5c9c11e1 MR |
1891 | mask = (1 << (cfi->device_type * 8)) - 1; |
1892 | result = map_read(map, base + ofs); | |
1893 | bank++; | |
ae731822 | 1894 | } while ((result.x[0] & mask) == CFI_MFR_CONTINUATION); |
5c9c11e1 | 1895 | |
1da177e4 LT |
1896 | return result.x[0] & mask; |
1897 | } | |
1898 | ||
5d3cce3b | 1899 | static inline u32 jedec_read_id(struct map_info *map, uint32_t base, |
1da177e4 LT |
1900 | struct cfi_private *cfi) |
1901 | { | |
1902 | map_word result; | |
1903 | unsigned long mask; | |
467622ef | 1904 | u32 ofs = cfi_build_cmd_addr(1, map, cfi); |
1da177e4 LT |
1905 | mask = (1 << (cfi->device_type * 8)) -1; |
1906 | result = map_read(map, base + ofs); | |
1907 | return result.x[0] & mask; | |
1908 | } | |
1909 | ||
53d88553 | 1910 | static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi) |
1da177e4 LT |
1911 | { |
1912 | /* Reset */ | |
1913 | ||
1914 | /* after checking the datasheets for SST, MACRONIX and ATMEL | |
1915 | * (oh and incidentaly the jedec spec - 3.5.3.3) the reset | |
1916 | * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at | |
1917 | * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips | |
7854d3f7 | 1918 | * as they will ignore the writes and don't care what address |
1da177e4 | 1919 | * the F0 is written to */ |
cec80bf2 | 1920 | if (cfi->addr_unlock1) { |
289c0522 | 1921 | pr_debug( "reset unlock called %x %x \n", |
1da177e4 LT |
1922 | cfi->addr_unlock1,cfi->addr_unlock2); |
1923 | cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
1924 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); | |
1925 | } | |
1926 | ||
1927 | cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
cec80bf2 | 1928 | /* Some misdesigned Intel chips do not respond for 0xF0 for a reset, |
1da177e4 LT |
1929 | * so ensure we're in read mode. Send both the Intel and the AMD command |
1930 | * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so | |
1931 | * this should be safe. | |
1f948b43 | 1932 | */ |
1da177e4 LT |
1933 | cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); |
1934 | /* FIXME - should have reset delay before continuing */ | |
1935 | } | |
1936 | ||
1937 | ||
ceabebb2 | 1938 | static int cfi_jedec_setup(struct map_info *map, struct cfi_private *cfi, int index) |
1da177e4 LT |
1939 | { |
1940 | int i,num_erase_regions; | |
5d3cce3b DW |
1941 | uint8_t uaddr; |
1942 | ||
efba2e31 | 1943 | if (!(jedec_table[index].devtypes & cfi->device_type)) { |
289c0522 | 1944 | pr_debug("Rejecting potential %s with incompatible %d-bit device type\n", |
efba2e31 | 1945 | jedec_table[index].name, 4 * (1<<cfi->device_type)); |
5d3cce3b DW |
1946 | return 0; |
1947 | } | |
1da177e4 | 1948 | |
5d3cce3b | 1949 | printk(KERN_INFO "Found: %s\n",jedec_table[index].name); |
1da177e4 | 1950 | |
5d3cce3b | 1951 | num_erase_regions = jedec_table[index].nr_regions; |
1f948b43 | 1952 | |
efba2e31 AP |
1953 | cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL); |
1954 | if (!cfi->cfiq) { | |
1da177e4 LT |
1955 | //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name); |
1956 | return 0; | |
1957 | } | |
1958 | ||
efba2e31 | 1959 | memset(cfi->cfiq, 0, sizeof(struct cfi_ident)); |
1da177e4 | 1960 | |
efba2e31 AP |
1961 | cfi->cfiq->P_ID = jedec_table[index].cmd_set; |
1962 | cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions; | |
1963 | cfi->cfiq->DevSize = jedec_table[index].dev_size; | |
1964 | cfi->cfi_mode = CFI_MODE_JEDEC; | |
ceabebb2 | 1965 | cfi->sector_erase_cmd = CMD(0x30); |
1da177e4 LT |
1966 | |
1967 | for (i=0; i<num_erase_regions; i++){ | |
efba2e31 | 1968 | cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i]; |
1da177e4 | 1969 | } |
efba2e31 | 1970 | cfi->cmdset_priv = NULL; |
1da177e4 LT |
1971 | |
1972 | /* This may be redundant for some cases, but it doesn't hurt */ | |
efba2e31 AP |
1973 | cfi->mfr = jedec_table[index].mfr_id; |
1974 | cfi->id = jedec_table[index].dev_id; | |
1da177e4 | 1975 | |
5d3cce3b | 1976 | uaddr = jedec_table[index].uaddr; |
1da177e4 | 1977 | |
cec80bf2 DW |
1978 | /* The table has unlock addresses in _bytes_, and we try not to let |
1979 | our brains explode when we see the datasheets talking about address | |
1980 | lines numbered from A-1 to A18. The CFI table has unlock addresses | |
1981 | in device-words according to the mode the device is connected in */ | |
efba2e31 AP |
1982 | cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / cfi->device_type; |
1983 | cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / cfi->device_type; | |
1da177e4 | 1984 | |
7d84b627 | 1985 | return 1; /* ok */ |
1da177e4 LT |
1986 | } |
1987 | ||
1988 | ||
1989 | /* | |
f33686b5 | 1990 | * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing |
1da177e4 LT |
1991 | * the mapped address, unlock addresses, and proper chip ID. This function |
1992 | * attempts to minimize errors. It is doubtfull that this probe will ever | |
1993 | * be perfect - consequently there should be some module parameters that | |
1994 | * could be manually specified to force the chip info. | |
1995 | */ | |
5d3cce3b | 1996 | static inline int jedec_match( uint32_t base, |
1da177e4 LT |
1997 | struct map_info *map, |
1998 | struct cfi_private *cfi, | |
1999 | const struct amd_flash_info *finfo ) | |
2000 | { | |
2001 | int rc = 0; /* failure until all tests pass */ | |
2002 | u32 mfr, id; | |
5d3cce3b | 2003 | uint8_t uaddr; |
1da177e4 LT |
2004 | |
2005 | /* | |
2006 | * The IDs must match. For X16 and X32 devices operating in | |
2007 | * a lower width ( X8 or X16 ), the device ID's are usually just | |
2008 | * the lower byte(s) of the larger device ID for wider mode. If | |
2009 | * a part is found that doesn't fit this assumption (device id for | |
2010 | * smaller width mode is completely unrealated to full-width mode) | |
2011 | * then the jedec_table[] will have to be augmented with the IDs | |
2012 | * for different widths. | |
2013 | */ | |
2014 | switch (cfi->device_type) { | |
2015 | case CFI_DEVICETYPE_X8: | |
5d3cce3b DW |
2016 | mfr = (uint8_t)finfo->mfr_id; |
2017 | id = (uint8_t)finfo->dev_id; | |
011b2a36 BD |
2018 | |
2019 | /* bjd: it seems that if we do this, we can end up | |
2020 | * detecting 16bit flashes as an 8bit device, even though | |
2021 | * there aren't. | |
2022 | */ | |
2023 | if (finfo->dev_id > 0xff) { | |
289c0522 | 2024 | pr_debug("%s(): ID is not 8bit\n", |
011b2a36 BD |
2025 | __func__); |
2026 | goto match_done; | |
2027 | } | |
1da177e4 LT |
2028 | break; |
2029 | case CFI_DEVICETYPE_X16: | |
5d3cce3b DW |
2030 | mfr = (uint16_t)finfo->mfr_id; |
2031 | id = (uint16_t)finfo->dev_id; | |
1da177e4 LT |
2032 | break; |
2033 | case CFI_DEVICETYPE_X32: | |
5d3cce3b DW |
2034 | mfr = (uint16_t)finfo->mfr_id; |
2035 | id = (uint32_t)finfo->dev_id; | |
1da177e4 LT |
2036 | break; |
2037 | default: | |
2038 | printk(KERN_WARNING | |
2039 | "MTD %s(): Unsupported device type %d\n", | |
2040 | __func__, cfi->device_type); | |
2041 | goto match_done; | |
2042 | } | |
2043 | if ( cfi->mfr != mfr || cfi->id != id ) { | |
2044 | goto match_done; | |
2045 | } | |
2046 | ||
2047 | /* the part size must fit in the memory window */ | |
289c0522 | 2048 | pr_debug("MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n", |
5d3cce3b DW |
2049 | __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) ); |
2050 | if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) { | |
289c0522 | 2051 | pr_debug("MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n", |
1da177e4 | 2052 | __func__, finfo->mfr_id, finfo->dev_id, |
5d3cce3b | 2053 | 1 << finfo->dev_size ); |
1da177e4 LT |
2054 | goto match_done; |
2055 | } | |
2056 | ||
5d3cce3b | 2057 | if (! (finfo->devtypes & cfi->device_type)) |
1da177e4 | 2058 | goto match_done; |
5d3cce3b DW |
2059 | |
2060 | uaddr = finfo->uaddr; | |
1da177e4 | 2061 | |
289c0522 | 2062 | pr_debug("MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n", |
1da177e4 LT |
2063 | __func__, cfi->addr_unlock1, cfi->addr_unlock2 ); |
2064 | if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr | |
cec80bf2 DW |
2065 | && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 || |
2066 | unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) { | |
289c0522 | 2067 | pr_debug("MTD %s(): 0x%.4x 0x%.4x did not match\n", |
1da177e4 LT |
2068 | __func__, |
2069 | unlock_addrs[uaddr].addr1, | |
2070 | unlock_addrs[uaddr].addr2); | |
2071 | goto match_done; | |
2072 | } | |
2073 | ||
2074 | /* | |
25985edc | 2075 | * Make sure the ID's disappear when the device is taken out of |
1da177e4 LT |
2076 | * ID mode. The only time this should fail when it should succeed |
2077 | * is when the ID's are written as data to the same | |
2078 | * addresses. For this rare and unfortunate case the chip | |
2079 | * cannot be probed correctly. | |
2080 | * FIXME - write a driver that takes all of the chip info as | |
2081 | * module parameters, doesn't probe but forces a load. | |
2082 | */ | |
289c0522 | 2083 | pr_debug("MTD %s(): check ID's disappear when not in ID mode\n", |
1da177e4 LT |
2084 | __func__ ); |
2085 | jedec_reset( base, map, cfi ); | |
2086 | mfr = jedec_read_mfr( map, base, cfi ); | |
2087 | id = jedec_read_id( map, base, cfi ); | |
2088 | if ( mfr == cfi->mfr && id == cfi->id ) { | |
289c0522 | 2089 | pr_debug("MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n" |
1da177e4 LT |
2090 | "You might need to manually specify JEDEC parameters.\n", |
2091 | __func__, cfi->mfr, cfi->id ); | |
2092 | goto match_done; | |
2093 | } | |
2094 | ||
2095 | /* all tests passed - mark as success */ | |
2096 | rc = 1; | |
2097 | ||
2098 | /* | |
2099 | * Put the device back in ID mode - only need to do this if we | |
2100 | * were truly frobbing a real device. | |
2101 | */ | |
289c0522 | 2102 | pr_debug("MTD %s(): return to ID mode\n", __func__ ); |
cec80bf2 | 2103 | if (cfi->addr_unlock1) { |
1da177e4 LT |
2104 | cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); |
2105 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); | |
2106 | } | |
2107 | cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
2108 | /* FIXME - should have a delay before continuing */ | |
2109 | ||
1f948b43 | 2110 | match_done: |
1da177e4 LT |
2111 | return rc; |
2112 | } | |
2113 | ||
2114 | ||
2115 | static int jedec_probe_chip(struct map_info *map, __u32 base, | |
2116 | unsigned long *chip_map, struct cfi_private *cfi) | |
2117 | { | |
2118 | int i; | |
2119 | enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED; | |
2120 | u32 probe_offset1, probe_offset2; | |
2121 | ||
2122 | retry: | |
2123 | if (!cfi->numchips) { | |
2124 | uaddr_idx++; | |
2125 | ||
2126 | if (MTD_UADDR_UNNECESSARY == uaddr_idx) | |
2127 | return 0; | |
2128 | ||
cec80bf2 DW |
2129 | cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type; |
2130 | cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type; | |
1da177e4 LT |
2131 | } |
2132 | ||
2133 | /* Make certain we aren't probing past the end of map */ | |
2134 | if (base >= map->size) { | |
2135 | printk(KERN_NOTICE | |
2136 | "Probe at base(0x%08x) past the end of the map(0x%08lx)\n", | |
2137 | base, map->size -1); | |
2138 | return 0; | |
1f948b43 | 2139 | |
1da177e4 LT |
2140 | } |
2141 | /* Ensure the unlock addresses we try stay inside the map */ | |
467622ef EB |
2142 | probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, map, cfi); |
2143 | probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, map, cfi); | |
1da177e4 LT |
2144 | if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || |
2145 | ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) | |
1da177e4 | 2146 | goto retry; |
1f948b43 | 2147 | |
1da177e4 LT |
2148 | /* Reset */ |
2149 | jedec_reset(base, map, cfi); | |
2150 | ||
2151 | /* Autoselect Mode */ | |
2152 | if(cfi->addr_unlock1) { | |
2153 | cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
2154 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); | |
2155 | } | |
2156 | cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
2157 | /* FIXME - should have a delay before continuing */ | |
2158 | ||
2159 | if (!cfi->numchips) { | |
1f948b43 | 2160 | /* This is the first time we're called. Set up the CFI |
1da177e4 | 2161 | stuff accordingly and return */ |
1f948b43 | 2162 | |
1da177e4 LT |
2163 | cfi->mfr = jedec_read_mfr(map, base, cfi); |
2164 | cfi->id = jedec_read_id(map, base, cfi); | |
289c0522 | 2165 | pr_debug("Search for id:(%02x %02x) interleave(%d) type(%d)\n", |
1da177e4 | 2166 | cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type); |
87d10f3c | 2167 | for (i = 0; i < ARRAY_SIZE(jedec_table); i++) { |
1da177e4 | 2168 | if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) { |
289c0522 | 2169 | pr_debug("MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n", |
1da177e4 LT |
2170 | __func__, cfi->mfr, cfi->id, |
2171 | cfi->addr_unlock1, cfi->addr_unlock2 ); | |
ceabebb2 | 2172 | if (!cfi_jedec_setup(map, cfi, i)) |
1da177e4 LT |
2173 | return 0; |
2174 | goto ok_out; | |
2175 | } | |
2176 | } | |
2177 | goto retry; | |
2178 | } else { | |
5d3cce3b DW |
2179 | uint16_t mfr; |
2180 | uint16_t id; | |
1da177e4 LT |
2181 | |
2182 | /* Make sure it is a chip of the same manufacturer and id */ | |
2183 | mfr = jedec_read_mfr(map, base, cfi); | |
2184 | id = jedec_read_id(map, base, cfi); | |
2185 | ||
2186 | if ((mfr != cfi->mfr) || (id != cfi->id)) { | |
2187 | printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n", | |
2188 | map->name, mfr, id, base); | |
2189 | jedec_reset(base, map, cfi); | |
2190 | return 0; | |
2191 | } | |
2192 | } | |
1f948b43 | 2193 | |
1da177e4 LT |
2194 | /* Check each previous chip locations to see if it's an alias */ |
2195 | for (i=0; i < (base >> cfi->chipshift); i++) { | |
2196 | unsigned long start; | |
2197 | if(!test_bit(i, chip_map)) { | |
2198 | continue; /* Skip location; no valid chip at this address */ | |
2199 | } | |
2200 | start = i << cfi->chipshift; | |
2201 | if (jedec_read_mfr(map, start, cfi) == cfi->mfr && | |
2202 | jedec_read_id(map, start, cfi) == cfi->id) { | |
2203 | /* Eep. This chip also looks like it's in autoselect mode. | |
2204 | Is it an alias for the new one? */ | |
2205 | jedec_reset(start, map, cfi); | |
2206 | ||
2207 | /* If the device IDs go away, it's an alias */ | |
2208 | if (jedec_read_mfr(map, base, cfi) != cfi->mfr || | |
2209 | jedec_read_id(map, base, cfi) != cfi->id) { | |
2210 | printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", | |
2211 | map->name, base, start); | |
2212 | return 0; | |
2213 | } | |
1f948b43 | 2214 | |
1da177e4 LT |
2215 | /* Yes, it's actually got the device IDs as data. Most |
2216 | * unfortunate. Stick the new chip in read mode | |
2217 | * too and if it's the same, assume it's an alias. */ | |
2218 | /* FIXME: Use other modes to do a proper check */ | |
2219 | jedec_reset(base, map, cfi); | |
2220 | if (jedec_read_mfr(map, base, cfi) == cfi->mfr && | |
2221 | jedec_read_id(map, base, cfi) == cfi->id) { | |
2222 | printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", | |
2223 | map->name, base, start); | |
2224 | return 0; | |
2225 | } | |
2226 | } | |
2227 | } | |
1f948b43 | 2228 | |
1da177e4 LT |
2229 | /* OK, if we got to here, then none of the previous chips appear to |
2230 | be aliases for the current one. */ | |
2231 | set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */ | |
2232 | cfi->numchips++; | |
1f948b43 | 2233 | |
1da177e4 LT |
2234 | ok_out: |
2235 | /* Put it back into Read Mode */ | |
2236 | jedec_reset(base, map, cfi); | |
2237 | ||
2238 | printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n", | |
1f948b43 | 2239 | map->name, cfi_interleave(cfi), cfi->device_type*8, base, |
1da177e4 | 2240 | map->bankwidth*8); |
1f948b43 | 2241 | |
1da177e4 LT |
2242 | return 1; |
2243 | } | |
2244 | ||
2245 | static struct chip_probe jedec_chip_probe = { | |
2246 | .name = "JEDEC", | |
2247 | .probe_chip = jedec_probe_chip | |
2248 | }; | |
2249 | ||
2250 | static struct mtd_info *jedec_probe(struct map_info *map) | |
2251 | { | |
2252 | /* | |
2253 | * Just use the generic probe stuff to call our CFI-specific | |
2254 | * chip_probe routine in all the possible permutations, etc. | |
2255 | */ | |
2256 | return mtd_do_chip_probe(map, &jedec_chip_probe); | |
2257 | } | |
2258 | ||
2259 | static struct mtd_chip_driver jedec_chipdrv = { | |
2260 | .probe = jedec_probe, | |
2261 | .name = "jedec_probe", | |
2262 | .module = THIS_MODULE | |
2263 | }; | |
2264 | ||
2265 | static int __init jedec_probe_init(void) | |
2266 | { | |
2267 | register_mtd_chip_driver(&jedec_chipdrv); | |
2268 | return 0; | |
2269 | } | |
2270 | ||
2271 | static void __exit jedec_probe_exit(void) | |
2272 | { | |
2273 | unregister_mtd_chip_driver(&jedec_chipdrv); | |
2274 | } | |
2275 | ||
2276 | module_init(jedec_probe_init); | |
2277 | module_exit(jedec_probe_exit); | |
2278 | ||
2279 | MODULE_LICENSE("GPL"); | |
2280 | MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al."); | |
2281 | MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips"); |