Commit | Line | Data |
---|---|---|
1f948b43 | 1 | /* |
1da177e4 LT |
2 | Common Flash Interface probe code. |
3 | (C) 2000 Red Hat. GPL'd. | |
1f948b43 | 4 | $Id: jedec_probe.c,v 1.66 2005/11/07 11:14:23 gleixner Exp $ |
1da177e4 LT |
5 | See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5) |
6 | for the standard this probe goes back to. | |
7 | ||
8 | Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com | |
9 | */ | |
10 | ||
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <asm/io.h> | |
16 | #include <asm/byteorder.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/interrupt.h> | |
1da177e4 LT |
20 | |
21 | #include <linux/mtd/mtd.h> | |
22 | #include <linux/mtd/map.h> | |
23 | #include <linux/mtd/cfi.h> | |
24 | #include <linux/mtd/gen_probe.h> | |
25 | ||
26 | /* Manufacturers */ | |
27 | #define MANUFACTURER_AMD 0x0001 | |
28 | #define MANUFACTURER_ATMEL 0x001f | |
29 | #define MANUFACTURER_FUJITSU 0x0004 | |
30 | #define MANUFACTURER_HYUNDAI 0x00AD | |
31 | #define MANUFACTURER_INTEL 0x0089 | |
32 | #define MANUFACTURER_MACRONIX 0x00C2 | |
33 | #define MANUFACTURER_NEC 0x0010 | |
34 | #define MANUFACTURER_PMC 0x009D | |
a63ec1b7 | 35 | #define MANUFACTURER_SHARP 0x00b0 |
1da177e4 LT |
36 | #define MANUFACTURER_SST 0x00BF |
37 | #define MANUFACTURER_ST 0x0020 | |
38 | #define MANUFACTURER_TOSHIBA 0x0098 | |
39 | #define MANUFACTURER_WINBOND 0x00da | |
40 | ||
41 | ||
42 | /* AMD */ | |
43 | #define AM29DL800BB 0x22C8 | |
44 | #define AM29DL800BT 0x224A | |
45 | ||
46 | #define AM29F800BB 0x2258 | |
47 | #define AM29F800BT 0x22D6 | |
48 | #define AM29LV400BB 0x22BA | |
49 | #define AM29LV400BT 0x22B9 | |
50 | #define AM29LV800BB 0x225B | |
51 | #define AM29LV800BT 0x22DA | |
52 | #define AM29LV160DT 0x22C4 | |
53 | #define AM29LV160DB 0x2249 | |
54 | #define AM29F017D 0x003D | |
55 | #define AM29F016D 0x00AD | |
56 | #define AM29F080 0x00D5 | |
57 | #define AM29F040 0x00A4 | |
58 | #define AM29LV040B 0x004F | |
59 | #define AM29F032B 0x0041 | |
60 | #define AM29F002T 0x00B0 | |
61 | ||
62 | /* Atmel */ | |
63 | #define AT49BV512 0x0003 | |
64 | #define AT29LV512 0x003d | |
65 | #define AT49BV16X 0x00C0 | |
66 | #define AT49BV16XT 0x00C2 | |
67 | #define AT49BV32X 0x00C8 | |
68 | #define AT49BV32XT 0x00C9 | |
69 | ||
70 | /* Fujitsu */ | |
71 | #define MBM29F040C 0x00A4 | |
c9856e39 | 72 | #define MBM29F800BA 0x2258 |
1da177e4 LT |
73 | #define MBM29LV650UE 0x22D7 |
74 | #define MBM29LV320TE 0x22F6 | |
75 | #define MBM29LV320BE 0x22F9 | |
76 | #define MBM29LV160TE 0x22C4 | |
77 | #define MBM29LV160BE 0x2249 | |
78 | #define MBM29LV800BA 0x225B | |
79 | #define MBM29LV800TA 0x22DA | |
80 | #define MBM29LV400TC 0x22B9 | |
81 | #define MBM29LV400BC 0x22BA | |
82 | ||
83 | /* Hyundai */ | |
84 | #define HY29F002T 0x00B0 | |
85 | ||
86 | /* Intel */ | |
87 | #define I28F004B3T 0x00d4 | |
88 | #define I28F004B3B 0x00d5 | |
89 | #define I28F400B3T 0x8894 | |
90 | #define I28F400B3B 0x8895 | |
91 | #define I28F008S5 0x00a6 | |
92 | #define I28F016S5 0x00a0 | |
93 | #define I28F008SA 0x00a2 | |
94 | #define I28F008B3T 0x00d2 | |
95 | #define I28F008B3B 0x00d3 | |
96 | #define I28F800B3T 0x8892 | |
97 | #define I28F800B3B 0x8893 | |
98 | #define I28F016S3 0x00aa | |
99 | #define I28F016B3T 0x00d0 | |
100 | #define I28F016B3B 0x00d1 | |
101 | #define I28F160B3T 0x8890 | |
102 | #define I28F160B3B 0x8891 | |
103 | #define I28F320B3T 0x8896 | |
104 | #define I28F320B3B 0x8897 | |
105 | #define I28F640B3T 0x8898 | |
106 | #define I28F640B3B 0x8899 | |
107 | #define I82802AB 0x00ad | |
108 | #define I82802AC 0x00ac | |
109 | ||
110 | /* Macronix */ | |
111 | #define MX29LV040C 0x004F | |
112 | #define MX29LV160T 0x22C4 | |
113 | #define MX29LV160B 0x2249 | |
c4e6952f | 114 | #define MX29F040 0x00A4 |
1da177e4 LT |
115 | #define MX29F016 0x00AD |
116 | #define MX29F002T 0x00B0 | |
117 | #define MX29F004T 0x0045 | |
118 | #define MX29F004B 0x0046 | |
119 | ||
120 | /* NEC */ | |
121 | #define UPD29F064115 0x221C | |
122 | ||
123 | /* PMC */ | |
124 | #define PM49FL002 0x006D | |
125 | #define PM49FL004 0x006E | |
126 | #define PM49FL008 0x006A | |
127 | ||
a63ec1b7 PM |
128 | /* Sharp */ |
129 | #define LH28F640BF 0x00b0 | |
130 | ||
1da177e4 | 131 | /* ST - www.st.com */ |
c9856e39 | 132 | #define M29F800AB 0x0058 |
1da177e4 LT |
133 | #define M29W800DT 0x00D7 |
134 | #define M29W800DB 0x005B | |
30d6a24e GF |
135 | #define M29W400DT 0x00EE |
136 | #define M29W400DB 0x00EF | |
1da177e4 LT |
137 | #define M29W160DT 0x22C4 |
138 | #define M29W160DB 0x2249 | |
139 | #define M29W040B 0x00E3 | |
140 | #define M50FW040 0x002C | |
141 | #define M50FW080 0x002D | |
142 | #define M50FW016 0x002E | |
143 | #define M50LPW080 0x002F | |
144 | ||
145 | /* SST */ | |
146 | #define SST29EE020 0x0010 | |
147 | #define SST29LE020 0x0012 | |
148 | #define SST29EE512 0x005d | |
149 | #define SST29LE512 0x003d | |
150 | #define SST39LF800 0x2781 | |
151 | #define SST39LF160 0x2782 | |
88ec7c50 | 152 | #define SST39VF1601 0x234b |
1da177e4 LT |
153 | #define SST39LF512 0x00D4 |
154 | #define SST39LF010 0x00D5 | |
155 | #define SST39LF020 0x00D6 | |
156 | #define SST39LF040 0x00D7 | |
157 | #define SST39SF010A 0x00B5 | |
158 | #define SST39SF020A 0x00B6 | |
159 | #define SST49LF004B 0x0060 | |
89072ef9 | 160 | #define SST49LF040B 0x0050 |
1da177e4 LT |
161 | #define SST49LF008A 0x005a |
162 | #define SST49LF030A 0x001C | |
163 | #define SST49LF040A 0x0051 | |
164 | #define SST49LF080A 0x005B | |
165 | ||
166 | /* Toshiba */ | |
167 | #define TC58FVT160 0x00C2 | |
168 | #define TC58FVB160 0x0043 | |
169 | #define TC58FVT321 0x009A | |
170 | #define TC58FVB321 0x009C | |
171 | #define TC58FVT641 0x0093 | |
172 | #define TC58FVB641 0x0095 | |
173 | ||
174 | /* Winbond */ | |
175 | #define W49V002A 0x00b0 | |
176 | ||
177 | ||
178 | /* | |
179 | * Unlock address sets for AMD command sets. | |
180 | * Intel command sets use the MTD_UADDR_UNNECESSARY. | |
181 | * Each identifier, except MTD_UADDR_UNNECESSARY, and | |
182 | * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[]. | |
183 | * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure | |
184 | * initialization need not require initializing all of the | |
185 | * unlock addresses for all bit widths. | |
186 | */ | |
187 | enum uaddr { | |
188 | MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */ | |
189 | MTD_UADDR_0x0555_0x02AA, | |
190 | MTD_UADDR_0x0555_0x0AAA, | |
191 | MTD_UADDR_0x5555_0x2AAA, | |
192 | MTD_UADDR_0x0AAA_0x0555, | |
193 | MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */ | |
194 | MTD_UADDR_UNNECESSARY, /* Does not require any address */ | |
195 | }; | |
196 | ||
197 | ||
198 | struct unlock_addr { | |
5d3cce3b DW |
199 | uint32_t addr1; |
200 | uint32_t addr2; | |
1da177e4 LT |
201 | }; |
202 | ||
203 | ||
204 | /* | |
205 | * I don't like the fact that the first entry in unlock_addrs[] | |
206 | * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore, | |
207 | * should not be used. The problem is that structures with | |
208 | * initializers have extra fields initialized to 0. It is _very_ | |
209 | * desireable to have the unlock address entries for unsupported | |
210 | * data widths automatically initialized - that means that | |
211 | * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here | |
212 | * must go unused. | |
213 | */ | |
214 | static const struct unlock_addr unlock_addrs[] = { | |
215 | [MTD_UADDR_NOT_SUPPORTED] = { | |
216 | .addr1 = 0xffff, | |
217 | .addr2 = 0xffff | |
218 | }, | |
219 | ||
220 | [MTD_UADDR_0x0555_0x02AA] = { | |
221 | .addr1 = 0x0555, | |
222 | .addr2 = 0x02aa | |
223 | }, | |
224 | ||
225 | [MTD_UADDR_0x0555_0x0AAA] = { | |
226 | .addr1 = 0x0555, | |
227 | .addr2 = 0x0aaa | |
228 | }, | |
229 | ||
230 | [MTD_UADDR_0x5555_0x2AAA] = { | |
231 | .addr1 = 0x5555, | |
232 | .addr2 = 0x2aaa | |
233 | }, | |
234 | ||
235 | [MTD_UADDR_0x0AAA_0x0555] = { | |
236 | .addr1 = 0x0AAA, | |
237 | .addr2 = 0x0555 | |
238 | }, | |
239 | ||
240 | [MTD_UADDR_DONT_CARE] = { | |
241 | .addr1 = 0x0000, /* Doesn't matter which address */ | |
242 | .addr2 = 0x0000 /* is used - must be last entry */ | |
243 | }, | |
244 | ||
245 | [MTD_UADDR_UNNECESSARY] = { | |
246 | .addr1 = 0x0000, | |
247 | .addr2 = 0x0000 | |
248 | } | |
249 | }; | |
250 | ||
1da177e4 | 251 | struct amd_flash_info { |
1da177e4 | 252 | const char *name; |
5d3cce3b DW |
253 | const uint16_t mfr_id; |
254 | const uint16_t dev_id; | |
255 | const uint8_t dev_size; | |
256 | const uint8_t nr_regions; | |
257 | const uint16_t cmd_set; | |
258 | const uint32_t regions[6]; | |
259 | const uint8_t devtypes; /* Bitmask for x8, x16 etc. */ | |
260 | const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */ | |
1da177e4 LT |
261 | }; |
262 | ||
263 | #define ERASEINFO(size,blocks) (size<<8)|(blocks-1) | |
264 | ||
265 | #define SIZE_64KiB 16 | |
266 | #define SIZE_128KiB 17 | |
267 | #define SIZE_256KiB 18 | |
268 | #define SIZE_512KiB 19 | |
269 | #define SIZE_1MiB 20 | |
270 | #define SIZE_2MiB 21 | |
271 | #define SIZE_4MiB 22 | |
272 | #define SIZE_8MiB 23 | |
273 | ||
274 | ||
275 | /* | |
276 | * Please keep this list ordered by manufacturer! | |
277 | * Fortunately, the list isn't searched often and so a | |
278 | * slow, linear search isn't so bad. | |
279 | */ | |
280 | static const struct amd_flash_info jedec_table[] = { | |
281 | { | |
282 | .mfr_id = MANUFACTURER_AMD, | |
283 | .dev_id = AM29F032B, | |
284 | .name = "AMD AM29F032B", | |
5d3cce3b DW |
285 | .uaddr = MTD_UADDR_0x0555_0x02AA, |
286 | .devtypes = CFI_DEVICETYPE_X8, | |
287 | .dev_size = SIZE_4MiB, | |
288 | .cmd_set = P_ID_AMD_STD, | |
289 | .nr_regions = 1, | |
1da177e4 LT |
290 | .regions = { |
291 | ERASEINFO(0x10000,64) | |
292 | } | |
293 | }, { | |
294 | .mfr_id = MANUFACTURER_AMD, | |
295 | .dev_id = AM29LV160DT, | |
296 | .name = "AMD AM29LV160DT", | |
5d3cce3b DW |
297 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
298 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
299 | .dev_size = SIZE_2MiB, |
300 | .cmd_set = P_ID_AMD_STD, | |
301 | .nr_regions = 4, | |
1da177e4 LT |
302 | .regions = { |
303 | ERASEINFO(0x10000,31), | |
304 | ERASEINFO(0x08000,1), | |
305 | ERASEINFO(0x02000,2), | |
306 | ERASEINFO(0x04000,1) | |
307 | } | |
308 | }, { | |
309 | .mfr_id = MANUFACTURER_AMD, | |
310 | .dev_id = AM29LV160DB, | |
311 | .name = "AMD AM29LV160DB", | |
5d3cce3b DW |
312 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
313 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
314 | .dev_size = SIZE_2MiB, |
315 | .cmd_set = P_ID_AMD_STD, | |
316 | .nr_regions = 4, | |
1da177e4 LT |
317 | .regions = { |
318 | ERASEINFO(0x04000,1), | |
319 | ERASEINFO(0x02000,2), | |
320 | ERASEINFO(0x08000,1), | |
321 | ERASEINFO(0x10000,31) | |
322 | } | |
323 | }, { | |
324 | .mfr_id = MANUFACTURER_AMD, | |
325 | .dev_id = AM29LV400BB, | |
326 | .name = "AMD AM29LV400BB", | |
5d3cce3b DW |
327 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
328 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
329 | .dev_size = SIZE_512KiB, |
330 | .cmd_set = P_ID_AMD_STD, | |
331 | .nr_regions = 4, | |
1da177e4 LT |
332 | .regions = { |
333 | ERASEINFO(0x04000,1), | |
334 | ERASEINFO(0x02000,2), | |
335 | ERASEINFO(0x08000,1), | |
336 | ERASEINFO(0x10000,7) | |
337 | } | |
338 | }, { | |
339 | .mfr_id = MANUFACTURER_AMD, | |
340 | .dev_id = AM29LV400BT, | |
341 | .name = "AMD AM29LV400BT", | |
5d3cce3b DW |
342 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
343 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
344 | .dev_size = SIZE_512KiB, |
345 | .cmd_set = P_ID_AMD_STD, | |
346 | .nr_regions = 4, | |
1da177e4 LT |
347 | .regions = { |
348 | ERASEINFO(0x10000,7), | |
349 | ERASEINFO(0x08000,1), | |
350 | ERASEINFO(0x02000,2), | |
351 | ERASEINFO(0x04000,1) | |
352 | } | |
353 | }, { | |
354 | .mfr_id = MANUFACTURER_AMD, | |
355 | .dev_id = AM29LV800BB, | |
356 | .name = "AMD AM29LV800BB", | |
5d3cce3b DW |
357 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
358 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
359 | .dev_size = SIZE_1MiB, |
360 | .cmd_set = P_ID_AMD_STD, | |
361 | .nr_regions = 4, | |
1da177e4 LT |
362 | .regions = { |
363 | ERASEINFO(0x04000,1), | |
364 | ERASEINFO(0x02000,2), | |
365 | ERASEINFO(0x08000,1), | |
366 | ERASEINFO(0x10000,15), | |
367 | } | |
368 | }, { | |
369 | /* add DL */ | |
370 | .mfr_id = MANUFACTURER_AMD, | |
371 | .dev_id = AM29DL800BB, | |
372 | .name = "AMD AM29DL800BB", | |
5d3cce3b DW |
373 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
374 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
375 | .dev_size = SIZE_1MiB, |
376 | .cmd_set = P_ID_AMD_STD, | |
377 | .nr_regions = 6, | |
1da177e4 LT |
378 | .regions = { |
379 | ERASEINFO(0x04000,1), | |
380 | ERASEINFO(0x08000,1), | |
381 | ERASEINFO(0x02000,4), | |
382 | ERASEINFO(0x08000,1), | |
383 | ERASEINFO(0x04000,1), | |
384 | ERASEINFO(0x10000,14) | |
385 | } | |
386 | }, { | |
387 | .mfr_id = MANUFACTURER_AMD, | |
388 | .dev_id = AM29DL800BT, | |
389 | .name = "AMD AM29DL800BT", | |
5d3cce3b DW |
390 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
391 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
392 | .dev_size = SIZE_1MiB, |
393 | .cmd_set = P_ID_AMD_STD, | |
394 | .nr_regions = 6, | |
1da177e4 LT |
395 | .regions = { |
396 | ERASEINFO(0x10000,14), | |
397 | ERASEINFO(0x04000,1), | |
398 | ERASEINFO(0x08000,1), | |
399 | ERASEINFO(0x02000,4), | |
400 | ERASEINFO(0x08000,1), | |
401 | ERASEINFO(0x04000,1) | |
402 | } | |
403 | }, { | |
404 | .mfr_id = MANUFACTURER_AMD, | |
405 | .dev_id = AM29F800BB, | |
406 | .name = "AMD AM29F800BB", | |
5d3cce3b DW |
407 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
408 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
409 | .dev_size = SIZE_1MiB, |
410 | .cmd_set = P_ID_AMD_STD, | |
411 | .nr_regions = 4, | |
1da177e4 LT |
412 | .regions = { |
413 | ERASEINFO(0x04000,1), | |
414 | ERASEINFO(0x02000,2), | |
415 | ERASEINFO(0x08000,1), | |
416 | ERASEINFO(0x10000,15), | |
417 | } | |
418 | }, { | |
419 | .mfr_id = MANUFACTURER_AMD, | |
420 | .dev_id = AM29LV800BT, | |
421 | .name = "AMD AM29LV800BT", | |
5d3cce3b DW |
422 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
423 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
424 | .dev_size = SIZE_1MiB, |
425 | .cmd_set = P_ID_AMD_STD, | |
426 | .nr_regions = 4, | |
1da177e4 LT |
427 | .regions = { |
428 | ERASEINFO(0x10000,15), | |
429 | ERASEINFO(0x08000,1), | |
430 | ERASEINFO(0x02000,2), | |
431 | ERASEINFO(0x04000,1) | |
432 | } | |
433 | }, { | |
434 | .mfr_id = MANUFACTURER_AMD, | |
435 | .dev_id = AM29F800BT, | |
436 | .name = "AMD AM29F800BT", | |
5d3cce3b DW |
437 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
438 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
439 | .dev_size = SIZE_1MiB, |
440 | .cmd_set = P_ID_AMD_STD, | |
441 | .nr_regions = 4, | |
1da177e4 LT |
442 | .regions = { |
443 | ERASEINFO(0x10000,15), | |
444 | ERASEINFO(0x08000,1), | |
445 | ERASEINFO(0x02000,2), | |
446 | ERASEINFO(0x04000,1) | |
447 | } | |
448 | }, { | |
449 | .mfr_id = MANUFACTURER_AMD, | |
450 | .dev_id = AM29F017D, | |
451 | .name = "AMD AM29F017D", | |
5d3cce3b DW |
452 | .devtypes = CFI_DEVICETYPE_X8, |
453 | .uaddr = MTD_UADDR_DONT_CARE, | |
454 | .dev_size = SIZE_2MiB, | |
455 | .cmd_set = P_ID_AMD_STD, | |
456 | .nr_regions = 1, | |
1da177e4 LT |
457 | .regions = { |
458 | ERASEINFO(0x10000,32), | |
459 | } | |
460 | }, { | |
461 | .mfr_id = MANUFACTURER_AMD, | |
462 | .dev_id = AM29F016D, | |
463 | .name = "AMD AM29F016D", | |
5d3cce3b DW |
464 | .devtypes = CFI_DEVICETYPE_X8, |
465 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
466 | .dev_size = SIZE_2MiB, | |
467 | .cmd_set = P_ID_AMD_STD, | |
468 | .nr_regions = 1, | |
1da177e4 LT |
469 | .regions = { |
470 | ERASEINFO(0x10000,32), | |
471 | } | |
472 | }, { | |
473 | .mfr_id = MANUFACTURER_AMD, | |
474 | .dev_id = AM29F080, | |
475 | .name = "AMD AM29F080", | |
5d3cce3b DW |
476 | .devtypes = CFI_DEVICETYPE_X8, |
477 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
478 | .dev_size = SIZE_1MiB, | |
479 | .cmd_set = P_ID_AMD_STD, | |
480 | .nr_regions = 1, | |
1da177e4 LT |
481 | .regions = { |
482 | ERASEINFO(0x10000,16), | |
483 | } | |
484 | }, { | |
485 | .mfr_id = MANUFACTURER_AMD, | |
486 | .dev_id = AM29F040, | |
487 | .name = "AMD AM29F040", | |
5d3cce3b DW |
488 | .devtypes = CFI_DEVICETYPE_X8, |
489 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
490 | .dev_size = SIZE_512KiB, | |
491 | .cmd_set = P_ID_AMD_STD, | |
492 | .nr_regions = 1, | |
1da177e4 LT |
493 | .regions = { |
494 | ERASEINFO(0x10000,8), | |
495 | } | |
496 | }, { | |
497 | .mfr_id = MANUFACTURER_AMD, | |
498 | .dev_id = AM29LV040B, | |
499 | .name = "AMD AM29LV040B", | |
5d3cce3b DW |
500 | .devtypes = CFI_DEVICETYPE_X8, |
501 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
502 | .dev_size = SIZE_512KiB, | |
503 | .cmd_set = P_ID_AMD_STD, | |
504 | .nr_regions = 1, | |
1da177e4 LT |
505 | .regions = { |
506 | ERASEINFO(0x10000,8), | |
507 | } | |
508 | }, { | |
509 | .mfr_id = MANUFACTURER_AMD, | |
510 | .dev_id = AM29F002T, | |
511 | .name = "AMD AM29F002T", | |
5d3cce3b DW |
512 | .devtypes = CFI_DEVICETYPE_X8, |
513 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
514 | .dev_size = SIZE_256KiB, | |
515 | .cmd_set = P_ID_AMD_STD, | |
516 | .nr_regions = 4, | |
1da177e4 LT |
517 | .regions = { |
518 | ERASEINFO(0x10000,3), | |
519 | ERASEINFO(0x08000,1), | |
520 | ERASEINFO(0x02000,2), | |
521 | ERASEINFO(0x04000,1), | |
522 | } | |
523 | }, { | |
524 | .mfr_id = MANUFACTURER_ATMEL, | |
525 | .dev_id = AT49BV512, | |
526 | .name = "Atmel AT49BV512", | |
5d3cce3b DW |
527 | .devtypes = CFI_DEVICETYPE_X8, |
528 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
529 | .dev_size = SIZE_64KiB, | |
530 | .cmd_set = P_ID_AMD_STD, | |
531 | .nr_regions = 1, | |
1da177e4 LT |
532 | .regions = { |
533 | ERASEINFO(0x10000,1) | |
534 | } | |
535 | }, { | |
536 | .mfr_id = MANUFACTURER_ATMEL, | |
537 | .dev_id = AT29LV512, | |
538 | .name = "Atmel AT29LV512", | |
5d3cce3b DW |
539 | .devtypes = CFI_DEVICETYPE_X8, |
540 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
541 | .dev_size = SIZE_64KiB, | |
542 | .cmd_set = P_ID_AMD_STD, | |
543 | .nr_regions = 1, | |
1da177e4 LT |
544 | .regions = { |
545 | ERASEINFO(0x80,256), | |
546 | ERASEINFO(0x80,256) | |
547 | } | |
548 | }, { | |
549 | .mfr_id = MANUFACTURER_ATMEL, | |
550 | .dev_id = AT49BV16X, | |
551 | .name = "Atmel AT49BV16X", | |
5d3cce3b | 552 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 553 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
554 | .dev_size = SIZE_2MiB, |
555 | .cmd_set = P_ID_AMD_STD, | |
556 | .nr_regions = 2, | |
1da177e4 LT |
557 | .regions = { |
558 | ERASEINFO(0x02000,8), | |
559 | ERASEINFO(0x10000,31) | |
560 | } | |
561 | }, { | |
562 | .mfr_id = MANUFACTURER_ATMEL, | |
563 | .dev_id = AT49BV16XT, | |
564 | .name = "Atmel AT49BV16XT", | |
5d3cce3b | 565 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 566 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
567 | .dev_size = SIZE_2MiB, |
568 | .cmd_set = P_ID_AMD_STD, | |
569 | .nr_regions = 2, | |
1da177e4 LT |
570 | .regions = { |
571 | ERASEINFO(0x10000,31), | |
572 | ERASEINFO(0x02000,8) | |
573 | } | |
574 | }, { | |
575 | .mfr_id = MANUFACTURER_ATMEL, | |
576 | .dev_id = AT49BV32X, | |
577 | .name = "Atmel AT49BV32X", | |
5d3cce3b | 578 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 579 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
580 | .dev_size = SIZE_4MiB, |
581 | .cmd_set = P_ID_AMD_STD, | |
582 | .nr_regions = 2, | |
1da177e4 LT |
583 | .regions = { |
584 | ERASEINFO(0x02000,8), | |
585 | ERASEINFO(0x10000,63) | |
586 | } | |
587 | }, { | |
588 | .mfr_id = MANUFACTURER_ATMEL, | |
589 | .dev_id = AT49BV32XT, | |
590 | .name = "Atmel AT49BV32XT", | |
5d3cce3b | 591 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 592 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
593 | .dev_size = SIZE_4MiB, |
594 | .cmd_set = P_ID_AMD_STD, | |
595 | .nr_regions = 2, | |
1da177e4 LT |
596 | .regions = { |
597 | ERASEINFO(0x10000,63), | |
598 | ERASEINFO(0x02000,8) | |
599 | } | |
600 | }, { | |
601 | .mfr_id = MANUFACTURER_FUJITSU, | |
602 | .dev_id = MBM29F040C, | |
603 | .name = "Fujitsu MBM29F040C", | |
5d3cce3b DW |
604 | .devtypes = CFI_DEVICETYPE_X8, |
605 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
606 | .dev_size = SIZE_512KiB, | |
607 | .cmd_set = P_ID_AMD_STD, | |
608 | .nr_regions = 1, | |
1da177e4 LT |
609 | .regions = { |
610 | ERASEINFO(0x10000,8) | |
611 | } | |
c9856e39 PDM |
612 | }, { |
613 | .mfr_id = MANUFACTURER_FUJITSU, | |
614 | .dev_id = MBM29F800BA, | |
615 | .name = "Fujitsu MBM29F800BA", | |
5d3cce3b DW |
616 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
617 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
618 | .dev_size = SIZE_1MiB, |
619 | .cmd_set = P_ID_AMD_STD, | |
620 | .nr_regions = 4, | |
c9856e39 PDM |
621 | .regions = { |
622 | ERASEINFO(0x04000,1), | |
623 | ERASEINFO(0x02000,2), | |
624 | ERASEINFO(0x08000,1), | |
625 | ERASEINFO(0x10000,15), | |
626 | } | |
1da177e4 LT |
627 | }, { |
628 | .mfr_id = MANUFACTURER_FUJITSU, | |
629 | .dev_id = MBM29LV650UE, | |
630 | .name = "Fujitsu MBM29LV650UE", | |
5d3cce3b DW |
631 | .devtypes = CFI_DEVICETYPE_X8, |
632 | .uaddr = MTD_UADDR_DONT_CARE, | |
633 | .dev_size = SIZE_8MiB, | |
634 | .cmd_set = P_ID_AMD_STD, | |
635 | .nr_regions = 1, | |
1da177e4 LT |
636 | .regions = { |
637 | ERASEINFO(0x10000,128) | |
638 | } | |
639 | }, { | |
640 | .mfr_id = MANUFACTURER_FUJITSU, | |
641 | .dev_id = MBM29LV320TE, | |
642 | .name = "Fujitsu MBM29LV320TE", | |
5d3cce3b DW |
643 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
644 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
645 | .dev_size = SIZE_4MiB, |
646 | .cmd_set = P_ID_AMD_STD, | |
647 | .nr_regions = 2, | |
1da177e4 LT |
648 | .regions = { |
649 | ERASEINFO(0x10000,63), | |
650 | ERASEINFO(0x02000,8) | |
651 | } | |
652 | }, { | |
653 | .mfr_id = MANUFACTURER_FUJITSU, | |
654 | .dev_id = MBM29LV320BE, | |
655 | .name = "Fujitsu MBM29LV320BE", | |
5d3cce3b DW |
656 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
657 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
658 | .dev_size = SIZE_4MiB, |
659 | .cmd_set = P_ID_AMD_STD, | |
660 | .nr_regions = 2, | |
1da177e4 LT |
661 | .regions = { |
662 | ERASEINFO(0x02000,8), | |
663 | ERASEINFO(0x10000,63) | |
664 | } | |
665 | }, { | |
666 | .mfr_id = MANUFACTURER_FUJITSU, | |
667 | .dev_id = MBM29LV160TE, | |
668 | .name = "Fujitsu MBM29LV160TE", | |
5d3cce3b DW |
669 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
670 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
671 | .dev_size = SIZE_2MiB, |
672 | .cmd_set = P_ID_AMD_STD, | |
673 | .nr_regions = 4, | |
1da177e4 LT |
674 | .regions = { |
675 | ERASEINFO(0x10000,31), | |
676 | ERASEINFO(0x08000,1), | |
677 | ERASEINFO(0x02000,2), | |
678 | ERASEINFO(0x04000,1) | |
679 | } | |
680 | }, { | |
681 | .mfr_id = MANUFACTURER_FUJITSU, | |
682 | .dev_id = MBM29LV160BE, | |
683 | .name = "Fujitsu MBM29LV160BE", | |
5d3cce3b DW |
684 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
685 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
686 | .dev_size = SIZE_2MiB, |
687 | .cmd_set = P_ID_AMD_STD, | |
688 | .nr_regions = 4, | |
1da177e4 LT |
689 | .regions = { |
690 | ERASEINFO(0x04000,1), | |
691 | ERASEINFO(0x02000,2), | |
692 | ERASEINFO(0x08000,1), | |
693 | ERASEINFO(0x10000,31) | |
694 | } | |
695 | }, { | |
696 | .mfr_id = MANUFACTURER_FUJITSU, | |
697 | .dev_id = MBM29LV800BA, | |
698 | .name = "Fujitsu MBM29LV800BA", | |
5d3cce3b DW |
699 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
700 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
701 | .dev_size = SIZE_1MiB, |
702 | .cmd_set = P_ID_AMD_STD, | |
703 | .nr_regions = 4, | |
1da177e4 LT |
704 | .regions = { |
705 | ERASEINFO(0x04000,1), | |
706 | ERASEINFO(0x02000,2), | |
707 | ERASEINFO(0x08000,1), | |
708 | ERASEINFO(0x10000,15) | |
709 | } | |
710 | }, { | |
711 | .mfr_id = MANUFACTURER_FUJITSU, | |
712 | .dev_id = MBM29LV800TA, | |
713 | .name = "Fujitsu MBM29LV800TA", | |
5d3cce3b DW |
714 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
715 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
716 | .dev_size = SIZE_1MiB, |
717 | .cmd_set = P_ID_AMD_STD, | |
718 | .nr_regions = 4, | |
1da177e4 LT |
719 | .regions = { |
720 | ERASEINFO(0x10000,15), | |
721 | ERASEINFO(0x08000,1), | |
722 | ERASEINFO(0x02000,2), | |
723 | ERASEINFO(0x04000,1) | |
724 | } | |
725 | }, { | |
726 | .mfr_id = MANUFACTURER_FUJITSU, | |
727 | .dev_id = MBM29LV400BC, | |
728 | .name = "Fujitsu MBM29LV400BC", | |
5d3cce3b DW |
729 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
730 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
731 | .dev_size = SIZE_512KiB, |
732 | .cmd_set = P_ID_AMD_STD, | |
733 | .nr_regions = 4, | |
1da177e4 LT |
734 | .regions = { |
735 | ERASEINFO(0x04000,1), | |
736 | ERASEINFO(0x02000,2), | |
737 | ERASEINFO(0x08000,1), | |
738 | ERASEINFO(0x10000,7) | |
739 | } | |
740 | }, { | |
741 | .mfr_id = MANUFACTURER_FUJITSU, | |
742 | .dev_id = MBM29LV400TC, | |
743 | .name = "Fujitsu MBM29LV400TC", | |
5d3cce3b DW |
744 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
745 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
746 | .dev_size = SIZE_512KiB, |
747 | .cmd_set = P_ID_AMD_STD, | |
748 | .nr_regions = 4, | |
1da177e4 LT |
749 | .regions = { |
750 | ERASEINFO(0x10000,7), | |
751 | ERASEINFO(0x08000,1), | |
752 | ERASEINFO(0x02000,2), | |
753 | ERASEINFO(0x04000,1) | |
754 | } | |
755 | }, { | |
756 | .mfr_id = MANUFACTURER_HYUNDAI, | |
757 | .dev_id = HY29F002T, | |
758 | .name = "Hyundai HY29F002T", | |
5d3cce3b DW |
759 | .devtypes = CFI_DEVICETYPE_X8, |
760 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
761 | .dev_size = SIZE_256KiB, | |
762 | .cmd_set = P_ID_AMD_STD, | |
763 | .nr_regions = 4, | |
1da177e4 LT |
764 | .regions = { |
765 | ERASEINFO(0x10000,3), | |
766 | ERASEINFO(0x08000,1), | |
767 | ERASEINFO(0x02000,2), | |
768 | ERASEINFO(0x04000,1), | |
769 | } | |
770 | }, { | |
771 | .mfr_id = MANUFACTURER_INTEL, | |
772 | .dev_id = I28F004B3B, | |
773 | .name = "Intel 28F004B3B", | |
5d3cce3b DW |
774 | .devtypes = CFI_DEVICETYPE_X8, |
775 | .uaddr = MTD_UADDR_UNNECESSARY, | |
776 | .dev_size = SIZE_512KiB, | |
777 | .cmd_set = P_ID_INTEL_STD, | |
778 | .nr_regions = 2, | |
1da177e4 LT |
779 | .regions = { |
780 | ERASEINFO(0x02000, 8), | |
781 | ERASEINFO(0x10000, 7), | |
782 | } | |
783 | }, { | |
784 | .mfr_id = MANUFACTURER_INTEL, | |
785 | .dev_id = I28F004B3T, | |
786 | .name = "Intel 28F004B3T", | |
5d3cce3b DW |
787 | .devtypes = CFI_DEVICETYPE_X8, |
788 | .uaddr = MTD_UADDR_UNNECESSARY, | |
789 | .dev_size = SIZE_512KiB, | |
790 | .cmd_set = P_ID_INTEL_STD, | |
791 | .nr_regions = 2, | |
1da177e4 LT |
792 | .regions = { |
793 | ERASEINFO(0x10000, 7), | |
794 | ERASEINFO(0x02000, 8), | |
795 | } | |
796 | }, { | |
797 | .mfr_id = MANUFACTURER_INTEL, | |
798 | .dev_id = I28F400B3B, | |
799 | .name = "Intel 28F400B3B", | |
5d3cce3b DW |
800 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
801 | .uaddr = MTD_UADDR_UNNECESSARY, | |
5d3cce3b DW |
802 | .dev_size = SIZE_512KiB, |
803 | .cmd_set = P_ID_INTEL_STD, | |
804 | .nr_regions = 2, | |
1da177e4 LT |
805 | .regions = { |
806 | ERASEINFO(0x02000, 8), | |
807 | ERASEINFO(0x10000, 7), | |
808 | } | |
809 | }, { | |
810 | .mfr_id = MANUFACTURER_INTEL, | |
811 | .dev_id = I28F400B3T, | |
812 | .name = "Intel 28F400B3T", | |
5d3cce3b DW |
813 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
814 | .uaddr = MTD_UADDR_UNNECESSARY, | |
5d3cce3b DW |
815 | .dev_size = SIZE_512KiB, |
816 | .cmd_set = P_ID_INTEL_STD, | |
817 | .nr_regions = 2, | |
1da177e4 LT |
818 | .regions = { |
819 | ERASEINFO(0x10000, 7), | |
820 | ERASEINFO(0x02000, 8), | |
821 | } | |
822 | }, { | |
823 | .mfr_id = MANUFACTURER_INTEL, | |
824 | .dev_id = I28F008B3B, | |
825 | .name = "Intel 28F008B3B", | |
5d3cce3b DW |
826 | .devtypes = CFI_DEVICETYPE_X8, |
827 | .uaddr = MTD_UADDR_UNNECESSARY, | |
828 | .dev_size = SIZE_1MiB, | |
829 | .cmd_set = P_ID_INTEL_STD, | |
830 | .nr_regions = 2, | |
1da177e4 LT |
831 | .regions = { |
832 | ERASEINFO(0x02000, 8), | |
833 | ERASEINFO(0x10000, 15), | |
834 | } | |
835 | }, { | |
836 | .mfr_id = MANUFACTURER_INTEL, | |
837 | .dev_id = I28F008B3T, | |
838 | .name = "Intel 28F008B3T", | |
5d3cce3b DW |
839 | .devtypes = CFI_DEVICETYPE_X8, |
840 | .uaddr = MTD_UADDR_UNNECESSARY, | |
841 | .dev_size = SIZE_1MiB, | |
842 | .cmd_set = P_ID_INTEL_STD, | |
843 | .nr_regions = 2, | |
1da177e4 LT |
844 | .regions = { |
845 | ERASEINFO(0x10000, 15), | |
846 | ERASEINFO(0x02000, 8), | |
847 | } | |
848 | }, { | |
849 | .mfr_id = MANUFACTURER_INTEL, | |
850 | .dev_id = I28F008S5, | |
851 | .name = "Intel 28F008S5", | |
5d3cce3b DW |
852 | .devtypes = CFI_DEVICETYPE_X8, |
853 | .uaddr = MTD_UADDR_UNNECESSARY, | |
854 | .dev_size = SIZE_1MiB, | |
855 | .cmd_set = P_ID_INTEL_EXT, | |
856 | .nr_regions = 1, | |
1da177e4 LT |
857 | .regions = { |
858 | ERASEINFO(0x10000,16), | |
859 | } | |
860 | }, { | |
861 | .mfr_id = MANUFACTURER_INTEL, | |
862 | .dev_id = I28F016S5, | |
863 | .name = "Intel 28F016S5", | |
5d3cce3b DW |
864 | .devtypes = CFI_DEVICETYPE_X8, |
865 | .uaddr = MTD_UADDR_UNNECESSARY, | |
866 | .dev_size = SIZE_2MiB, | |
867 | .cmd_set = P_ID_INTEL_EXT, | |
868 | .nr_regions = 1, | |
1da177e4 LT |
869 | .regions = { |
870 | ERASEINFO(0x10000,32), | |
871 | } | |
872 | }, { | |
873 | .mfr_id = MANUFACTURER_INTEL, | |
874 | .dev_id = I28F008SA, | |
875 | .name = "Intel 28F008SA", | |
5d3cce3b DW |
876 | .devtypes = CFI_DEVICETYPE_X8, |
877 | .uaddr = MTD_UADDR_UNNECESSARY, | |
878 | .dev_size = SIZE_1MiB, | |
879 | .cmd_set = P_ID_INTEL_STD, | |
880 | .nr_regions = 1, | |
1da177e4 LT |
881 | .regions = { |
882 | ERASEINFO(0x10000, 16), | |
883 | } | |
884 | }, { | |
885 | .mfr_id = MANUFACTURER_INTEL, | |
886 | .dev_id = I28F800B3B, | |
887 | .name = "Intel 28F800B3B", | |
5d3cce3b DW |
888 | .devtypes = CFI_DEVICETYPE_X16, |
889 | .uaddr = MTD_UADDR_UNNECESSARY, | |
890 | .dev_size = SIZE_1MiB, | |
891 | .cmd_set = P_ID_INTEL_STD, | |
892 | .nr_regions = 2, | |
1da177e4 LT |
893 | .regions = { |
894 | ERASEINFO(0x02000, 8), | |
895 | ERASEINFO(0x10000, 15), | |
896 | } | |
897 | }, { | |
898 | .mfr_id = MANUFACTURER_INTEL, | |
899 | .dev_id = I28F800B3T, | |
900 | .name = "Intel 28F800B3T", | |
5d3cce3b DW |
901 | .devtypes = CFI_DEVICETYPE_X16, |
902 | .uaddr = MTD_UADDR_UNNECESSARY, | |
903 | .dev_size = SIZE_1MiB, | |
904 | .cmd_set = P_ID_INTEL_STD, | |
905 | .nr_regions = 2, | |
1da177e4 LT |
906 | .regions = { |
907 | ERASEINFO(0x10000, 15), | |
908 | ERASEINFO(0x02000, 8), | |
909 | } | |
910 | }, { | |
911 | .mfr_id = MANUFACTURER_INTEL, | |
912 | .dev_id = I28F016B3B, | |
913 | .name = "Intel 28F016B3B", | |
5d3cce3b DW |
914 | .devtypes = CFI_DEVICETYPE_X8, |
915 | .uaddr = MTD_UADDR_UNNECESSARY, | |
916 | .dev_size = SIZE_2MiB, | |
917 | .cmd_set = P_ID_INTEL_STD, | |
918 | .nr_regions = 2, | |
1da177e4 LT |
919 | .regions = { |
920 | ERASEINFO(0x02000, 8), | |
921 | ERASEINFO(0x10000, 31), | |
922 | } | |
923 | }, { | |
924 | .mfr_id = MANUFACTURER_INTEL, | |
925 | .dev_id = I28F016S3, | |
926 | .name = "Intel I28F016S3", | |
5d3cce3b DW |
927 | .devtypes = CFI_DEVICETYPE_X8, |
928 | .uaddr = MTD_UADDR_UNNECESSARY, | |
929 | .dev_size = SIZE_2MiB, | |
930 | .cmd_set = P_ID_INTEL_STD, | |
931 | .nr_regions = 1, | |
1da177e4 LT |
932 | .regions = { |
933 | ERASEINFO(0x10000, 32), | |
934 | } | |
935 | }, { | |
936 | .mfr_id = MANUFACTURER_INTEL, | |
937 | .dev_id = I28F016B3T, | |
938 | .name = "Intel 28F016B3T", | |
5d3cce3b DW |
939 | .devtypes = CFI_DEVICETYPE_X8, |
940 | .uaddr = MTD_UADDR_UNNECESSARY, | |
941 | .dev_size = SIZE_2MiB, | |
942 | .cmd_set = P_ID_INTEL_STD, | |
943 | .nr_regions = 2, | |
1da177e4 LT |
944 | .regions = { |
945 | ERASEINFO(0x10000, 31), | |
946 | ERASEINFO(0x02000, 8), | |
947 | } | |
948 | }, { | |
949 | .mfr_id = MANUFACTURER_INTEL, | |
950 | .dev_id = I28F160B3B, | |
951 | .name = "Intel 28F160B3B", | |
5d3cce3b DW |
952 | .devtypes = CFI_DEVICETYPE_X16, |
953 | .uaddr = MTD_UADDR_UNNECESSARY, | |
954 | .dev_size = SIZE_2MiB, | |
955 | .cmd_set = P_ID_INTEL_STD, | |
956 | .nr_regions = 2, | |
1da177e4 LT |
957 | .regions = { |
958 | ERASEINFO(0x02000, 8), | |
959 | ERASEINFO(0x10000, 31), | |
960 | } | |
961 | }, { | |
962 | .mfr_id = MANUFACTURER_INTEL, | |
963 | .dev_id = I28F160B3T, | |
964 | .name = "Intel 28F160B3T", | |
5d3cce3b DW |
965 | .devtypes = CFI_DEVICETYPE_X16, |
966 | .uaddr = MTD_UADDR_UNNECESSARY, | |
967 | .dev_size = SIZE_2MiB, | |
968 | .cmd_set = P_ID_INTEL_STD, | |
969 | .nr_regions = 2, | |
1da177e4 LT |
970 | .regions = { |
971 | ERASEINFO(0x10000, 31), | |
972 | ERASEINFO(0x02000, 8), | |
973 | } | |
974 | }, { | |
975 | .mfr_id = MANUFACTURER_INTEL, | |
976 | .dev_id = I28F320B3B, | |
977 | .name = "Intel 28F320B3B", | |
5d3cce3b DW |
978 | .devtypes = CFI_DEVICETYPE_X16, |
979 | .uaddr = MTD_UADDR_UNNECESSARY, | |
980 | .dev_size = SIZE_4MiB, | |
981 | .cmd_set = P_ID_INTEL_STD, | |
982 | .nr_regions = 2, | |
1da177e4 LT |
983 | .regions = { |
984 | ERASEINFO(0x02000, 8), | |
985 | ERASEINFO(0x10000, 63), | |
986 | } | |
987 | }, { | |
988 | .mfr_id = MANUFACTURER_INTEL, | |
989 | .dev_id = I28F320B3T, | |
990 | .name = "Intel 28F320B3T", | |
5d3cce3b DW |
991 | .devtypes = CFI_DEVICETYPE_X16, |
992 | .uaddr = MTD_UADDR_UNNECESSARY, | |
993 | .dev_size = SIZE_4MiB, | |
994 | .cmd_set = P_ID_INTEL_STD, | |
995 | .nr_regions = 2, | |
1da177e4 LT |
996 | .regions = { |
997 | ERASEINFO(0x10000, 63), | |
998 | ERASEINFO(0x02000, 8), | |
999 | } | |
1000 | }, { | |
1001 | .mfr_id = MANUFACTURER_INTEL, | |
1002 | .dev_id = I28F640B3B, | |
1003 | .name = "Intel 28F640B3B", | |
5d3cce3b DW |
1004 | .devtypes = CFI_DEVICETYPE_X16, |
1005 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1006 | .dev_size = SIZE_8MiB, | |
1007 | .cmd_set = P_ID_INTEL_STD, | |
1008 | .nr_regions = 2, | |
1da177e4 LT |
1009 | .regions = { |
1010 | ERASEINFO(0x02000, 8), | |
1011 | ERASEINFO(0x10000, 127), | |
1012 | } | |
1013 | }, { | |
1014 | .mfr_id = MANUFACTURER_INTEL, | |
1015 | .dev_id = I28F640B3T, | |
1016 | .name = "Intel 28F640B3T", | |
5d3cce3b DW |
1017 | .devtypes = CFI_DEVICETYPE_X16, |
1018 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1019 | .dev_size = SIZE_8MiB, | |
1020 | .cmd_set = P_ID_INTEL_STD, | |
1021 | .nr_regions = 2, | |
1da177e4 LT |
1022 | .regions = { |
1023 | ERASEINFO(0x10000, 127), | |
1024 | ERASEINFO(0x02000, 8), | |
1025 | } | |
1026 | }, { | |
1027 | .mfr_id = MANUFACTURER_INTEL, | |
1028 | .dev_id = I82802AB, | |
1029 | .name = "Intel 82802AB", | |
5d3cce3b DW |
1030 | .devtypes = CFI_DEVICETYPE_X8, |
1031 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1032 | .dev_size = SIZE_512KiB, | |
1033 | .cmd_set = P_ID_INTEL_EXT, | |
1034 | .nr_regions = 1, | |
1da177e4 LT |
1035 | .regions = { |
1036 | ERASEINFO(0x10000,8), | |
1037 | } | |
1038 | }, { | |
1039 | .mfr_id = MANUFACTURER_INTEL, | |
1040 | .dev_id = I82802AC, | |
1041 | .name = "Intel 82802AC", | |
5d3cce3b DW |
1042 | .devtypes = CFI_DEVICETYPE_X8, |
1043 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1044 | .dev_size = SIZE_1MiB, | |
1045 | .cmd_set = P_ID_INTEL_EXT, | |
1046 | .nr_regions = 1, | |
1da177e4 LT |
1047 | .regions = { |
1048 | ERASEINFO(0x10000,16), | |
1049 | } | |
1050 | }, { | |
1051 | .mfr_id = MANUFACTURER_MACRONIX, | |
1052 | .dev_id = MX29LV040C, | |
1053 | .name = "Macronix MX29LV040C", | |
5d3cce3b DW |
1054 | .devtypes = CFI_DEVICETYPE_X8, |
1055 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1056 | .dev_size = SIZE_512KiB, | |
1057 | .cmd_set = P_ID_AMD_STD, | |
1058 | .nr_regions = 1, | |
1da177e4 LT |
1059 | .regions = { |
1060 | ERASEINFO(0x10000,8), | |
1061 | } | |
1062 | }, { | |
1063 | .mfr_id = MANUFACTURER_MACRONIX, | |
1064 | .dev_id = MX29LV160T, | |
1065 | .name = "MXIC MX29LV160T", | |
5d3cce3b DW |
1066 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1067 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1068 | .dev_size = SIZE_2MiB, |
1069 | .cmd_set = P_ID_AMD_STD, | |
1070 | .nr_regions = 4, | |
1da177e4 LT |
1071 | .regions = { |
1072 | ERASEINFO(0x10000,31), | |
1073 | ERASEINFO(0x08000,1), | |
1074 | ERASEINFO(0x02000,2), | |
1075 | ERASEINFO(0x04000,1) | |
1076 | } | |
1077 | }, { | |
1078 | .mfr_id = MANUFACTURER_NEC, | |
1079 | .dev_id = UPD29F064115, | |
1080 | .name = "NEC uPD29F064115", | |
5d3cce3b | 1081 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 1082 | .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ |
5d3cce3b DW |
1083 | .dev_size = SIZE_8MiB, |
1084 | .cmd_set = P_ID_AMD_STD, | |
1085 | .nr_regions = 3, | |
1da177e4 LT |
1086 | .regions = { |
1087 | ERASEINFO(0x2000,8), | |
1088 | ERASEINFO(0x10000,126), | |
1089 | ERASEINFO(0x2000,8), | |
1090 | } | |
1091 | }, { | |
1092 | .mfr_id = MANUFACTURER_MACRONIX, | |
1093 | .dev_id = MX29LV160B, | |
1094 | .name = "MXIC MX29LV160B", | |
5d3cce3b DW |
1095 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1096 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1097 | .dev_size = SIZE_2MiB, |
1098 | .cmd_set = P_ID_AMD_STD, | |
1099 | .nr_regions = 4, | |
1da177e4 LT |
1100 | .regions = { |
1101 | ERASEINFO(0x04000,1), | |
1102 | ERASEINFO(0x02000,2), | |
1103 | ERASEINFO(0x08000,1), | |
1104 | ERASEINFO(0x10000,31) | |
1105 | } | |
1106 | }, { | |
c4e6952f TY |
1107 | .mfr_id = MANUFACTURER_MACRONIX, |
1108 | .dev_id = MX29F040, | |
1109 | .name = "Macronix MX29F040", | |
5d3cce3b DW |
1110 | .devtypes = CFI_DEVICETYPE_X8, |
1111 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1112 | .dev_size = SIZE_512KiB, | |
1113 | .cmd_set = P_ID_AMD_STD, | |
1114 | .nr_regions = 1, | |
c4e6952f TY |
1115 | .regions = { |
1116 | ERASEINFO(0x10000,8), | |
1117 | } | |
1118 | }, { | |
1da177e4 LT |
1119 | .mfr_id = MANUFACTURER_MACRONIX, |
1120 | .dev_id = MX29F016, | |
1121 | .name = "Macronix MX29F016", | |
5d3cce3b DW |
1122 | .devtypes = CFI_DEVICETYPE_X8, |
1123 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1124 | .dev_size = SIZE_2MiB, | |
1125 | .cmd_set = P_ID_AMD_STD, | |
1126 | .nr_regions = 1, | |
1da177e4 LT |
1127 | .regions = { |
1128 | ERASEINFO(0x10000,32), | |
1129 | } | |
1130 | }, { | |
1131 | .mfr_id = MANUFACTURER_MACRONIX, | |
1132 | .dev_id = MX29F004T, | |
1133 | .name = "Macronix MX29F004T", | |
5d3cce3b DW |
1134 | .devtypes = CFI_DEVICETYPE_X8, |
1135 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1136 | .dev_size = SIZE_512KiB, | |
1137 | .cmd_set = P_ID_AMD_STD, | |
1138 | .nr_regions = 4, | |
1da177e4 LT |
1139 | .regions = { |
1140 | ERASEINFO(0x10000,7), | |
1141 | ERASEINFO(0x08000,1), | |
1142 | ERASEINFO(0x02000,2), | |
1143 | ERASEINFO(0x04000,1), | |
1144 | } | |
1145 | }, { | |
1146 | .mfr_id = MANUFACTURER_MACRONIX, | |
1147 | .dev_id = MX29F004B, | |
1148 | .name = "Macronix MX29F004B", | |
5d3cce3b DW |
1149 | .devtypes = CFI_DEVICETYPE_X8, |
1150 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1151 | .dev_size = SIZE_512KiB, | |
1152 | .cmd_set = P_ID_AMD_STD, | |
1153 | .nr_regions = 4, | |
1da177e4 LT |
1154 | .regions = { |
1155 | ERASEINFO(0x04000,1), | |
1156 | ERASEINFO(0x02000,2), | |
1157 | ERASEINFO(0x08000,1), | |
1158 | ERASEINFO(0x10000,7), | |
1159 | } | |
1160 | }, { | |
1161 | .mfr_id = MANUFACTURER_MACRONIX, | |
1162 | .dev_id = MX29F002T, | |
1163 | .name = "Macronix MX29F002T", | |
5d3cce3b DW |
1164 | .devtypes = CFI_DEVICETYPE_X8, |
1165 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1166 | .dev_size = SIZE_256KiB, | |
1167 | .cmd_set = P_ID_AMD_STD, | |
1168 | .nr_regions = 4, | |
1da177e4 LT |
1169 | .regions = { |
1170 | ERASEINFO(0x10000,3), | |
1171 | ERASEINFO(0x08000,1), | |
1172 | ERASEINFO(0x02000,2), | |
1173 | ERASEINFO(0x04000,1), | |
1174 | } | |
1175 | }, { | |
1176 | .mfr_id = MANUFACTURER_PMC, | |
1177 | .dev_id = PM49FL002, | |
1178 | .name = "PMC Pm49FL002", | |
5d3cce3b DW |
1179 | .devtypes = CFI_DEVICETYPE_X8, |
1180 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1181 | .dev_size = SIZE_256KiB, | |
1182 | .cmd_set = P_ID_AMD_STD, | |
1183 | .nr_regions = 1, | |
1da177e4 LT |
1184 | .regions = { |
1185 | ERASEINFO( 0x01000, 64 ) | |
1186 | } | |
1187 | }, { | |
1188 | .mfr_id = MANUFACTURER_PMC, | |
1189 | .dev_id = PM49FL004, | |
1190 | .name = "PMC Pm49FL004", | |
5d3cce3b DW |
1191 | .devtypes = CFI_DEVICETYPE_X8, |
1192 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1193 | .dev_size = SIZE_512KiB, | |
1194 | .cmd_set = P_ID_AMD_STD, | |
1195 | .nr_regions = 1, | |
1da177e4 LT |
1196 | .regions = { |
1197 | ERASEINFO( 0x01000, 128 ) | |
1198 | } | |
1199 | }, { | |
1200 | .mfr_id = MANUFACTURER_PMC, | |
1201 | .dev_id = PM49FL008, | |
1202 | .name = "PMC Pm49FL008", | |
5d3cce3b DW |
1203 | .devtypes = CFI_DEVICETYPE_X8, |
1204 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1205 | .dev_size = SIZE_1MiB, | |
1206 | .cmd_set = P_ID_AMD_STD, | |
1207 | .nr_regions = 1, | |
1da177e4 LT |
1208 | .regions = { |
1209 | ERASEINFO( 0x01000, 256 ) | |
1210 | } | |
a63ec1b7 PM |
1211 | }, { |
1212 | .mfr_id = MANUFACTURER_SHARP, | |
1213 | .dev_id = LH28F640BF, | |
1214 | .name = "LH28F640BF", | |
5d3cce3b DW |
1215 | .devtypes = CFI_DEVICETYPE_X8, |
1216 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1217 | .dev_size = SIZE_4MiB, | |
1218 | .cmd_set = P_ID_INTEL_STD, | |
1219 | .nr_regions = 1, | |
1220 | .regions = { | |
a63ec1b7 PM |
1221 | ERASEINFO(0x40000,16), |
1222 | } | |
1da177e4 LT |
1223 | }, { |
1224 | .mfr_id = MANUFACTURER_SST, | |
1225 | .dev_id = SST39LF512, | |
1226 | .name = "SST 39LF512", | |
5d3cce3b DW |
1227 | .devtypes = CFI_DEVICETYPE_X8, |
1228 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1229 | .dev_size = SIZE_64KiB, | |
1230 | .cmd_set = P_ID_AMD_STD, | |
1231 | .nr_regions = 1, | |
1da177e4 LT |
1232 | .regions = { |
1233 | ERASEINFO(0x01000,16), | |
1234 | } | |
1235 | }, { | |
1236 | .mfr_id = MANUFACTURER_SST, | |
1237 | .dev_id = SST39LF010, | |
1238 | .name = "SST 39LF010", | |
5d3cce3b DW |
1239 | .devtypes = CFI_DEVICETYPE_X8, |
1240 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1241 | .dev_size = SIZE_128KiB, | |
1242 | .cmd_set = P_ID_AMD_STD, | |
1243 | .nr_regions = 1, | |
1da177e4 LT |
1244 | .regions = { |
1245 | ERASEINFO(0x01000,32), | |
1246 | } | |
1247 | }, { | |
1248 | .mfr_id = MANUFACTURER_SST, | |
1249 | .dev_id = SST29EE020, | |
1250 | .name = "SST 29EE020", | |
5d3cce3b DW |
1251 | .devtypes = CFI_DEVICETYPE_X8, |
1252 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1253 | .dev_size = SIZE_256KiB, | |
1254 | .cmd_set = P_ID_SST_PAGE, | |
1255 | .nr_regions = 1, | |
1256 | .regions = {ERASEINFO(0x01000,64), | |
1257 | } | |
1258 | }, { | |
1da177e4 LT |
1259 | .mfr_id = MANUFACTURER_SST, |
1260 | .dev_id = SST29LE020, | |
1261 | .name = "SST 29LE020", | |
5d3cce3b DW |
1262 | .devtypes = CFI_DEVICETYPE_X8, |
1263 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1264 | .dev_size = SIZE_256KiB, | |
1265 | .cmd_set = P_ID_SST_PAGE, | |
1266 | .nr_regions = 1, | |
1267 | .regions = {ERASEINFO(0x01000,64), | |
1268 | } | |
1da177e4 LT |
1269 | }, { |
1270 | .mfr_id = MANUFACTURER_SST, | |
1271 | .dev_id = SST39LF020, | |
1272 | .name = "SST 39LF020", | |
5d3cce3b DW |
1273 | .devtypes = CFI_DEVICETYPE_X8, |
1274 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1275 | .dev_size = SIZE_256KiB, | |
1276 | .cmd_set = P_ID_AMD_STD, | |
1277 | .nr_regions = 1, | |
1da177e4 LT |
1278 | .regions = { |
1279 | ERASEINFO(0x01000,64), | |
1280 | } | |
1281 | }, { | |
1282 | .mfr_id = MANUFACTURER_SST, | |
1283 | .dev_id = SST39LF040, | |
1284 | .name = "SST 39LF040", | |
5d3cce3b DW |
1285 | .devtypes = CFI_DEVICETYPE_X8, |
1286 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1287 | .dev_size = SIZE_512KiB, | |
1288 | .cmd_set = P_ID_AMD_STD, | |
1289 | .nr_regions = 1, | |
1da177e4 LT |
1290 | .regions = { |
1291 | ERASEINFO(0x01000,128), | |
1292 | } | |
1293 | }, { | |
1294 | .mfr_id = MANUFACTURER_SST, | |
1295 | .dev_id = SST39SF010A, | |
1296 | .name = "SST 39SF010A", | |
5d3cce3b DW |
1297 | .devtypes = CFI_DEVICETYPE_X8, |
1298 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1299 | .dev_size = SIZE_128KiB, | |
1300 | .cmd_set = P_ID_AMD_STD, | |
1301 | .nr_regions = 1, | |
1da177e4 LT |
1302 | .regions = { |
1303 | ERASEINFO(0x01000,32), | |
1304 | } | |
1305 | }, { | |
1306 | .mfr_id = MANUFACTURER_SST, | |
1307 | .dev_id = SST39SF020A, | |
1308 | .name = "SST 39SF020A", | |
5d3cce3b DW |
1309 | .devtypes = CFI_DEVICETYPE_X8, |
1310 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1311 | .dev_size = SIZE_256KiB, | |
1312 | .cmd_set = P_ID_AMD_STD, | |
1313 | .nr_regions = 1, | |
1da177e4 LT |
1314 | .regions = { |
1315 | ERASEINFO(0x01000,64), | |
1316 | } | |
1317 | }, { | |
89072ef9 | 1318 | .mfr_id = MANUFACTURER_SST, |
5d3cce3b DW |
1319 | .dev_id = SST49LF040B, |
1320 | .name = "SST 49LF040B", | |
1321 | .devtypes = CFI_DEVICETYPE_X8, | |
1322 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1323 | .dev_size = SIZE_512KiB, | |
1324 | .cmd_set = P_ID_AMD_STD, | |
1325 | .nr_regions = 1, | |
1326 | .regions = { | |
89072ef9 RJ |
1327 | ERASEINFO(0x01000,128), |
1328 | } | |
1329 | }, { | |
1330 | ||
1da177e4 LT |
1331 | .mfr_id = MANUFACTURER_SST, |
1332 | .dev_id = SST49LF004B, | |
1333 | .name = "SST 49LF004B", | |
5d3cce3b DW |
1334 | .devtypes = CFI_DEVICETYPE_X8, |
1335 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1336 | .dev_size = SIZE_512KiB, | |
1337 | .cmd_set = P_ID_AMD_STD, | |
1338 | .nr_regions = 1, | |
1da177e4 LT |
1339 | .regions = { |
1340 | ERASEINFO(0x01000,128), | |
1341 | } | |
1342 | }, { | |
1343 | .mfr_id = MANUFACTURER_SST, | |
1344 | .dev_id = SST49LF008A, | |
1345 | .name = "SST 49LF008A", | |
5d3cce3b DW |
1346 | .devtypes = CFI_DEVICETYPE_X8, |
1347 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1348 | .dev_size = SIZE_1MiB, | |
1349 | .cmd_set = P_ID_AMD_STD, | |
1350 | .nr_regions = 1, | |
1da177e4 LT |
1351 | .regions = { |
1352 | ERASEINFO(0x01000,256), | |
1353 | } | |
1354 | }, { | |
1355 | .mfr_id = MANUFACTURER_SST, | |
1356 | .dev_id = SST49LF030A, | |
1357 | .name = "SST 49LF030A", | |
5d3cce3b DW |
1358 | .devtypes = CFI_DEVICETYPE_X8, |
1359 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1360 | .dev_size = SIZE_512KiB, | |
1361 | .cmd_set = P_ID_AMD_STD, | |
1362 | .nr_regions = 1, | |
1da177e4 LT |
1363 | .regions = { |
1364 | ERASEINFO(0x01000,96), | |
1365 | } | |
1366 | }, { | |
1367 | .mfr_id = MANUFACTURER_SST, | |
1368 | .dev_id = SST49LF040A, | |
1369 | .name = "SST 49LF040A", | |
5d3cce3b DW |
1370 | .devtypes = CFI_DEVICETYPE_X8, |
1371 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1372 | .dev_size = SIZE_512KiB, | |
1373 | .cmd_set = P_ID_AMD_STD, | |
1374 | .nr_regions = 1, | |
1da177e4 LT |
1375 | .regions = { |
1376 | ERASEINFO(0x01000,128), | |
1377 | } | |
1378 | }, { | |
1379 | .mfr_id = MANUFACTURER_SST, | |
1380 | .dev_id = SST49LF080A, | |
1381 | .name = "SST 49LF080A", | |
5d3cce3b DW |
1382 | .devtypes = CFI_DEVICETYPE_X8, |
1383 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1384 | .dev_size = SIZE_1MiB, | |
1385 | .cmd_set = P_ID_AMD_STD, | |
1386 | .nr_regions = 1, | |
1da177e4 LT |
1387 | .regions = { |
1388 | ERASEINFO(0x01000,256), | |
1389 | } | |
1390 | }, { | |
5d3cce3b DW |
1391 | .mfr_id = MANUFACTURER_SST, /* should be CFI */ |
1392 | .dev_id = SST39LF160, | |
1393 | .name = "SST 39LF160", | |
1394 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
cec80bf2 | 1395 | .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ |
5d3cce3b DW |
1396 | .dev_size = SIZE_2MiB, |
1397 | .cmd_set = P_ID_AMD_STD, | |
1398 | .nr_regions = 2, | |
1399 | .regions = { | |
1400 | ERASEINFO(0x1000,256), | |
1401 | ERASEINFO(0x1000,256) | |
1402 | } | |
1403 | }, { | |
1404 | .mfr_id = MANUFACTURER_SST, /* should be CFI */ | |
1405 | .dev_id = SST39VF1601, | |
1406 | .name = "SST 39VF1601", | |
1407 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
cec80bf2 | 1408 | .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ |
5d3cce3b DW |
1409 | .dev_size = SIZE_2MiB, |
1410 | .cmd_set = P_ID_AMD_STD, | |
1411 | .nr_regions = 2, | |
1412 | .regions = { | |
1413 | ERASEINFO(0x1000,256), | |
1414 | ERASEINFO(0x1000,256) | |
1415 | } | |
c9856e39 PDM |
1416 | }, { |
1417 | .mfr_id = MANUFACTURER_ST, | |
1418 | .dev_id = M29F800AB, | |
1419 | .name = "ST M29F800AB", | |
5d3cce3b DW |
1420 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1421 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1422 | .dev_size = SIZE_1MiB, |
1423 | .cmd_set = P_ID_AMD_STD, | |
1424 | .nr_regions = 4, | |
c9856e39 PDM |
1425 | .regions = { |
1426 | ERASEINFO(0x04000,1), | |
1427 | ERASEINFO(0x02000,2), | |
1428 | ERASEINFO(0x08000,1), | |
1429 | ERASEINFO(0x10000,15), | |
1430 | } | |
1da177e4 LT |
1431 | }, { |
1432 | .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ | |
1433 | .dev_id = M29W800DT, | |
1434 | .name = "ST M29W800DT", | |
5d3cce3b | 1435 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 1436 | .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ |
5d3cce3b DW |
1437 | .dev_size = SIZE_1MiB, |
1438 | .cmd_set = P_ID_AMD_STD, | |
1439 | .nr_regions = 4, | |
1da177e4 LT |
1440 | .regions = { |
1441 | ERASEINFO(0x10000,15), | |
1442 | ERASEINFO(0x08000,1), | |
1443 | ERASEINFO(0x02000,2), | |
1444 | ERASEINFO(0x04000,1) | |
1445 | } | |
1446 | }, { | |
1447 | .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ | |
1448 | .dev_id = M29W800DB, | |
1449 | .name = "ST M29W800DB", | |
5d3cce3b | 1450 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 1451 | .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ |
5d3cce3b DW |
1452 | .dev_size = SIZE_1MiB, |
1453 | .cmd_set = P_ID_AMD_STD, | |
1454 | .nr_regions = 4, | |
1da177e4 LT |
1455 | .regions = { |
1456 | ERASEINFO(0x04000,1), | |
1457 | ERASEINFO(0x02000,2), | |
1458 | ERASEINFO(0x08000,1), | |
1459 | ERASEINFO(0x10000,15) | |
1460 | } | |
30d6a24e GF |
1461 | }, { |
1462 | .mfr_id = MANUFACTURER_ST, | |
1463 | .dev_id = M29W400DT, | |
1464 | .name = "ST M29W400DT", | |
1465 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
1466 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
1467 | .dev_size = SIZE_512KiB, | |
1468 | .cmd_set = P_ID_AMD_STD, | |
1469 | .nr_regions = 4, | |
1470 | .regions = { | |
1471 | ERASEINFO(0x04000,7), | |
1472 | ERASEINFO(0x02000,1), | |
1473 | ERASEINFO(0x08000,2), | |
1474 | ERASEINFO(0x10000,1) | |
1475 | } | |
1476 | }, { | |
1477 | .mfr_id = MANUFACTURER_ST, | |
1478 | .dev_id = M29W400DB, | |
1479 | .name = "ST M29W400DB", | |
1480 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
1481 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
1482 | .dev_size = SIZE_512KiB, | |
1483 | .cmd_set = P_ID_AMD_STD, | |
1484 | .nr_regions = 4, | |
1485 | .regions = { | |
1486 | ERASEINFO(0x04000,1), | |
1487 | ERASEINFO(0x02000,2), | |
1488 | ERASEINFO(0x08000,1), | |
1489 | ERASEINFO(0x10000,7) | |
1490 | } | |
1da177e4 LT |
1491 | }, { |
1492 | .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ | |
1493 | .dev_id = M29W160DT, | |
1494 | .name = "ST M29W160DT", | |
5d3cce3b | 1495 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 1496 | .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ |
5d3cce3b DW |
1497 | .dev_size = SIZE_2MiB, |
1498 | .cmd_set = P_ID_AMD_STD, | |
1499 | .nr_regions = 4, | |
1da177e4 LT |
1500 | .regions = { |
1501 | ERASEINFO(0x10000,31), | |
1502 | ERASEINFO(0x08000,1), | |
1503 | ERASEINFO(0x02000,2), | |
1504 | ERASEINFO(0x04000,1) | |
1505 | } | |
1506 | }, { | |
1507 | .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ | |
1508 | .dev_id = M29W160DB, | |
1509 | .name = "ST M29W160DB", | |
5d3cce3b | 1510 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 1511 | .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ |
5d3cce3b DW |
1512 | .dev_size = SIZE_2MiB, |
1513 | .cmd_set = P_ID_AMD_STD, | |
1514 | .nr_regions = 4, | |
1da177e4 LT |
1515 | .regions = { |
1516 | ERASEINFO(0x04000,1), | |
1517 | ERASEINFO(0x02000,2), | |
1518 | ERASEINFO(0x08000,1), | |
1519 | ERASEINFO(0x10000,31) | |
1520 | } | |
1521 | }, { | |
1522 | .mfr_id = MANUFACTURER_ST, | |
1523 | .dev_id = M29W040B, | |
1524 | .name = "ST M29W040B", | |
5d3cce3b DW |
1525 | .devtypes = CFI_DEVICETYPE_X8, |
1526 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1527 | .dev_size = SIZE_512KiB, | |
1528 | .cmd_set = P_ID_AMD_STD, | |
1529 | .nr_regions = 1, | |
1da177e4 LT |
1530 | .regions = { |
1531 | ERASEINFO(0x10000,8), | |
1532 | } | |
1533 | }, { | |
1534 | .mfr_id = MANUFACTURER_ST, | |
1535 | .dev_id = M50FW040, | |
1536 | .name = "ST M50FW040", | |
5d3cce3b DW |
1537 | .devtypes = CFI_DEVICETYPE_X8, |
1538 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1539 | .dev_size = SIZE_512KiB, | |
1540 | .cmd_set = P_ID_INTEL_EXT, | |
1541 | .nr_regions = 1, | |
1da177e4 LT |
1542 | .regions = { |
1543 | ERASEINFO(0x10000,8), | |
1544 | } | |
1545 | }, { | |
1546 | .mfr_id = MANUFACTURER_ST, | |
1547 | .dev_id = M50FW080, | |
1548 | .name = "ST M50FW080", | |
5d3cce3b DW |
1549 | .devtypes = CFI_DEVICETYPE_X8, |
1550 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1551 | .dev_size = SIZE_1MiB, | |
1552 | .cmd_set = P_ID_INTEL_EXT, | |
1553 | .nr_regions = 1, | |
1da177e4 LT |
1554 | .regions = { |
1555 | ERASEINFO(0x10000,16), | |
1556 | } | |
1557 | }, { | |
1558 | .mfr_id = MANUFACTURER_ST, | |
1559 | .dev_id = M50FW016, | |
1560 | .name = "ST M50FW016", | |
5d3cce3b DW |
1561 | .devtypes = CFI_DEVICETYPE_X8, |
1562 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1563 | .dev_size = SIZE_2MiB, | |
1564 | .cmd_set = P_ID_INTEL_EXT, | |
1565 | .nr_regions = 1, | |
1da177e4 LT |
1566 | .regions = { |
1567 | ERASEINFO(0x10000,32), | |
1568 | } | |
1569 | }, { | |
1570 | .mfr_id = MANUFACTURER_ST, | |
1571 | .dev_id = M50LPW080, | |
1572 | .name = "ST M50LPW080", | |
5d3cce3b DW |
1573 | .devtypes = CFI_DEVICETYPE_X8, |
1574 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1575 | .dev_size = SIZE_1MiB, | |
1576 | .cmd_set = P_ID_INTEL_EXT, | |
1577 | .nr_regions = 1, | |
1da177e4 LT |
1578 | .regions = { |
1579 | ERASEINFO(0x10000,16), | |
1580 | } | |
1581 | }, { | |
1582 | .mfr_id = MANUFACTURER_TOSHIBA, | |
1583 | .dev_id = TC58FVT160, | |
1584 | .name = "Toshiba TC58FVT160", | |
5d3cce3b DW |
1585 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1586 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1587 | .dev_size = SIZE_2MiB, |
1588 | .cmd_set = P_ID_AMD_STD, | |
1589 | .nr_regions = 4, | |
1da177e4 LT |
1590 | .regions = { |
1591 | ERASEINFO(0x10000,31), | |
1592 | ERASEINFO(0x08000,1), | |
1593 | ERASEINFO(0x02000,2), | |
1594 | ERASEINFO(0x04000,1) | |
1595 | } | |
1596 | }, { | |
1597 | .mfr_id = MANUFACTURER_TOSHIBA, | |
1598 | .dev_id = TC58FVB160, | |
1599 | .name = "Toshiba TC58FVB160", | |
5d3cce3b DW |
1600 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1601 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1602 | .dev_size = SIZE_2MiB, |
1603 | .cmd_set = P_ID_AMD_STD, | |
1604 | .nr_regions = 4, | |
1da177e4 LT |
1605 | .regions = { |
1606 | ERASEINFO(0x04000,1), | |
1607 | ERASEINFO(0x02000,2), | |
1608 | ERASEINFO(0x08000,1), | |
1609 | ERASEINFO(0x10000,31) | |
1610 | } | |
1611 | }, { | |
1612 | .mfr_id = MANUFACTURER_TOSHIBA, | |
1613 | .dev_id = TC58FVB321, | |
1614 | .name = "Toshiba TC58FVB321", | |
5d3cce3b DW |
1615 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1616 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1617 | .dev_size = SIZE_4MiB, |
1618 | .cmd_set = P_ID_AMD_STD, | |
1619 | .nr_regions = 2, | |
1da177e4 LT |
1620 | .regions = { |
1621 | ERASEINFO(0x02000,8), | |
1622 | ERASEINFO(0x10000,63) | |
1623 | } | |
1624 | }, { | |
1625 | .mfr_id = MANUFACTURER_TOSHIBA, | |
1626 | .dev_id = TC58FVT321, | |
1627 | .name = "Toshiba TC58FVT321", | |
5d3cce3b DW |
1628 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1629 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1630 | .dev_size = SIZE_4MiB, |
1631 | .cmd_set = P_ID_AMD_STD, | |
1632 | .nr_regions = 2, | |
1da177e4 LT |
1633 | .regions = { |
1634 | ERASEINFO(0x10000,63), | |
1635 | ERASEINFO(0x02000,8) | |
1636 | } | |
1637 | }, { | |
1638 | .mfr_id = MANUFACTURER_TOSHIBA, | |
1639 | .dev_id = TC58FVB641, | |
1640 | .name = "Toshiba TC58FVB641", | |
5d3cce3b DW |
1641 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1642 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1643 | .dev_size = SIZE_8MiB, |
1644 | .cmd_set = P_ID_AMD_STD, | |
1645 | .nr_regions = 2, | |
1da177e4 LT |
1646 | .regions = { |
1647 | ERASEINFO(0x02000,8), | |
1648 | ERASEINFO(0x10000,127) | |
1649 | } | |
1650 | }, { | |
1651 | .mfr_id = MANUFACTURER_TOSHIBA, | |
1652 | .dev_id = TC58FVT641, | |
1653 | .name = "Toshiba TC58FVT641", | |
5d3cce3b DW |
1654 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1655 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1656 | .dev_size = SIZE_8MiB, |
1657 | .cmd_set = P_ID_AMD_STD, | |
1658 | .nr_regions = 2, | |
1da177e4 LT |
1659 | .regions = { |
1660 | ERASEINFO(0x10000,127), | |
1661 | ERASEINFO(0x02000,8) | |
1662 | } | |
1663 | }, { | |
1664 | .mfr_id = MANUFACTURER_WINBOND, | |
1665 | .dev_id = W49V002A, | |
1666 | .name = "Winbond W49V002A", | |
5d3cce3b DW |
1667 | .devtypes = CFI_DEVICETYPE_X8, |
1668 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1669 | .dev_size = SIZE_256KiB, | |
1670 | .cmd_set = P_ID_AMD_STD, | |
1671 | .nr_regions = 4, | |
1da177e4 LT |
1672 | .regions = { |
1673 | ERASEINFO(0x10000, 3), | |
1674 | ERASEINFO(0x08000, 1), | |
1675 | ERASEINFO(0x02000, 2), | |
1676 | ERASEINFO(0x04000, 1), | |
1677 | } | |
1678 | } | |
1679 | }; | |
1680 | ||
5d3cce3b | 1681 | static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base, |
1da177e4 LT |
1682 | struct cfi_private *cfi) |
1683 | { | |
1684 | map_word result; | |
1685 | unsigned long mask; | |
1686 | u32 ofs = cfi_build_cmd_addr(0, cfi_interleave(cfi), cfi->device_type); | |
1687 | mask = (1 << (cfi->device_type * 8)) -1; | |
1688 | result = map_read(map, base + ofs); | |
1689 | return result.x[0] & mask; | |
1690 | } | |
1691 | ||
5d3cce3b | 1692 | static inline u32 jedec_read_id(struct map_info *map, uint32_t base, |
1da177e4 LT |
1693 | struct cfi_private *cfi) |
1694 | { | |
1695 | map_word result; | |
1696 | unsigned long mask; | |
1697 | u32 ofs = cfi_build_cmd_addr(1, cfi_interleave(cfi), cfi->device_type); | |
1698 | mask = (1 << (cfi->device_type * 8)) -1; | |
1699 | result = map_read(map, base + ofs); | |
1700 | return result.x[0] & mask; | |
1701 | } | |
1702 | ||
53d88553 | 1703 | static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi) |
1da177e4 LT |
1704 | { |
1705 | /* Reset */ | |
1706 | ||
1707 | /* after checking the datasheets for SST, MACRONIX and ATMEL | |
1708 | * (oh and incidentaly the jedec spec - 3.5.3.3) the reset | |
1709 | * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at | |
1710 | * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips | |
1711 | * as they will ignore the writes and dont care what address | |
1712 | * the F0 is written to */ | |
cec80bf2 | 1713 | if (cfi->addr_unlock1) { |
1da177e4 LT |
1714 | DEBUG( MTD_DEBUG_LEVEL3, |
1715 | "reset unlock called %x %x \n", | |
1716 | cfi->addr_unlock1,cfi->addr_unlock2); | |
1717 | cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
1718 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); | |
1719 | } | |
1720 | ||
1721 | cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
cec80bf2 | 1722 | /* Some misdesigned Intel chips do not respond for 0xF0 for a reset, |
1da177e4 LT |
1723 | * so ensure we're in read mode. Send both the Intel and the AMD command |
1724 | * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so | |
1725 | * this should be safe. | |
1f948b43 | 1726 | */ |
1da177e4 LT |
1727 | cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); |
1728 | /* FIXME - should have reset delay before continuing */ | |
1729 | } | |
1730 | ||
1731 | ||
1da177e4 LT |
1732 | static int cfi_jedec_setup(struct cfi_private *p_cfi, int index) |
1733 | { | |
1734 | int i,num_erase_regions; | |
5d3cce3b DW |
1735 | uint8_t uaddr; |
1736 | ||
1737 | if (! (jedec_table[index].devtypes & p_cfi->device_type)) { | |
1738 | DEBUG(MTD_DEBUG_LEVEL1, "Rejecting potential %s with incompatible %d-bit device type\n", | |
1739 | jedec_table[index].name, 4 * (1<<p_cfi->device_type)); | |
1740 | return 0; | |
1741 | } | |
1da177e4 | 1742 | |
5d3cce3b | 1743 | printk(KERN_INFO "Found: %s\n",jedec_table[index].name); |
1da177e4 | 1744 | |
5d3cce3b | 1745 | num_erase_regions = jedec_table[index].nr_regions; |
1f948b43 | 1746 | |
1da177e4 LT |
1747 | p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL); |
1748 | if (!p_cfi->cfiq) { | |
1749 | //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name); | |
1750 | return 0; | |
1751 | } | |
1752 | ||
1f948b43 | 1753 | memset(p_cfi->cfiq,0,sizeof(struct cfi_ident)); |
1da177e4 | 1754 | |
5d3cce3b DW |
1755 | p_cfi->cfiq->P_ID = jedec_table[index].cmd_set; |
1756 | p_cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions; | |
1757 | p_cfi->cfiq->DevSize = jedec_table[index].dev_size; | |
1da177e4 LT |
1758 | p_cfi->cfi_mode = CFI_MODE_JEDEC; |
1759 | ||
1760 | for (i=0; i<num_erase_regions; i++){ | |
1761 | p_cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i]; | |
1762 | } | |
1763 | p_cfi->cmdset_priv = NULL; | |
1764 | ||
1765 | /* This may be redundant for some cases, but it doesn't hurt */ | |
1766 | p_cfi->mfr = jedec_table[index].mfr_id; | |
1767 | p_cfi->id = jedec_table[index].dev_id; | |
1768 | ||
5d3cce3b | 1769 | uaddr = jedec_table[index].uaddr; |
1da177e4 | 1770 | |
cec80bf2 DW |
1771 | /* The table has unlock addresses in _bytes_, and we try not to let |
1772 | our brains explode when we see the datasheets talking about address | |
1773 | lines numbered from A-1 to A18. The CFI table has unlock addresses | |
1774 | in device-words according to the mode the device is connected in */ | |
1775 | p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / p_cfi->device_type; | |
1776 | p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / p_cfi->device_type; | |
1da177e4 LT |
1777 | |
1778 | return 1; /* ok */ | |
1779 | } | |
1780 | ||
1781 | ||
1782 | /* | |
f33686b5 | 1783 | * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing |
1da177e4 LT |
1784 | * the mapped address, unlock addresses, and proper chip ID. This function |
1785 | * attempts to minimize errors. It is doubtfull that this probe will ever | |
1786 | * be perfect - consequently there should be some module parameters that | |
1787 | * could be manually specified to force the chip info. | |
1788 | */ | |
5d3cce3b | 1789 | static inline int jedec_match( uint32_t base, |
1da177e4 LT |
1790 | struct map_info *map, |
1791 | struct cfi_private *cfi, | |
1792 | const struct amd_flash_info *finfo ) | |
1793 | { | |
1794 | int rc = 0; /* failure until all tests pass */ | |
1795 | u32 mfr, id; | |
5d3cce3b | 1796 | uint8_t uaddr; |
1da177e4 LT |
1797 | |
1798 | /* | |
1799 | * The IDs must match. For X16 and X32 devices operating in | |
1800 | * a lower width ( X8 or X16 ), the device ID's are usually just | |
1801 | * the lower byte(s) of the larger device ID for wider mode. If | |
1802 | * a part is found that doesn't fit this assumption (device id for | |
1803 | * smaller width mode is completely unrealated to full-width mode) | |
1804 | * then the jedec_table[] will have to be augmented with the IDs | |
1805 | * for different widths. | |
1806 | */ | |
1807 | switch (cfi->device_type) { | |
1808 | case CFI_DEVICETYPE_X8: | |
5d3cce3b DW |
1809 | mfr = (uint8_t)finfo->mfr_id; |
1810 | id = (uint8_t)finfo->dev_id; | |
011b2a36 BD |
1811 | |
1812 | /* bjd: it seems that if we do this, we can end up | |
1813 | * detecting 16bit flashes as an 8bit device, even though | |
1814 | * there aren't. | |
1815 | */ | |
1816 | if (finfo->dev_id > 0xff) { | |
1817 | DEBUG( MTD_DEBUG_LEVEL3, "%s(): ID is not 8bit\n", | |
1818 | __func__); | |
1819 | goto match_done; | |
1820 | } | |
1da177e4 LT |
1821 | break; |
1822 | case CFI_DEVICETYPE_X16: | |
5d3cce3b DW |
1823 | mfr = (uint16_t)finfo->mfr_id; |
1824 | id = (uint16_t)finfo->dev_id; | |
1da177e4 LT |
1825 | break; |
1826 | case CFI_DEVICETYPE_X32: | |
5d3cce3b DW |
1827 | mfr = (uint16_t)finfo->mfr_id; |
1828 | id = (uint32_t)finfo->dev_id; | |
1da177e4 LT |
1829 | break; |
1830 | default: | |
1831 | printk(KERN_WARNING | |
1832 | "MTD %s(): Unsupported device type %d\n", | |
1833 | __func__, cfi->device_type); | |
1834 | goto match_done; | |
1835 | } | |
1836 | if ( cfi->mfr != mfr || cfi->id != id ) { | |
1837 | goto match_done; | |
1838 | } | |
1839 | ||
1840 | /* the part size must fit in the memory window */ | |
1841 | DEBUG( MTD_DEBUG_LEVEL3, | |
1842 | "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n", | |
5d3cce3b DW |
1843 | __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) ); |
1844 | if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) { | |
1da177e4 LT |
1845 | DEBUG( MTD_DEBUG_LEVEL3, |
1846 | "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n", | |
1847 | __func__, finfo->mfr_id, finfo->dev_id, | |
5d3cce3b | 1848 | 1 << finfo->dev_size ); |
1da177e4 LT |
1849 | goto match_done; |
1850 | } | |
1851 | ||
5d3cce3b | 1852 | if (! (finfo->devtypes & cfi->device_type)) |
1da177e4 | 1853 | goto match_done; |
5d3cce3b DW |
1854 | |
1855 | uaddr = finfo->uaddr; | |
1da177e4 LT |
1856 | |
1857 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n", | |
1858 | __func__, cfi->addr_unlock1, cfi->addr_unlock2 ); | |
1859 | if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr | |
cec80bf2 DW |
1860 | && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 || |
1861 | unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) { | |
1da177e4 LT |
1862 | DEBUG( MTD_DEBUG_LEVEL3, |
1863 | "MTD %s(): 0x%.4x 0x%.4x did not match\n", | |
1864 | __func__, | |
1865 | unlock_addrs[uaddr].addr1, | |
1866 | unlock_addrs[uaddr].addr2); | |
1867 | goto match_done; | |
1868 | } | |
1869 | ||
1870 | /* | |
1871 | * Make sure the ID's dissappear when the device is taken out of | |
1872 | * ID mode. The only time this should fail when it should succeed | |
1873 | * is when the ID's are written as data to the same | |
1874 | * addresses. For this rare and unfortunate case the chip | |
1875 | * cannot be probed correctly. | |
1876 | * FIXME - write a driver that takes all of the chip info as | |
1877 | * module parameters, doesn't probe but forces a load. | |
1878 | */ | |
1879 | DEBUG( MTD_DEBUG_LEVEL3, | |
1880 | "MTD %s(): check ID's disappear when not in ID mode\n", | |
1881 | __func__ ); | |
1882 | jedec_reset( base, map, cfi ); | |
1883 | mfr = jedec_read_mfr( map, base, cfi ); | |
1884 | id = jedec_read_id( map, base, cfi ); | |
1885 | if ( mfr == cfi->mfr && id == cfi->id ) { | |
1886 | DEBUG( MTD_DEBUG_LEVEL3, | |
1887 | "MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n" | |
1888 | "You might need to manually specify JEDEC parameters.\n", | |
1889 | __func__, cfi->mfr, cfi->id ); | |
1890 | goto match_done; | |
1891 | } | |
1892 | ||
1893 | /* all tests passed - mark as success */ | |
1894 | rc = 1; | |
1895 | ||
1896 | /* | |
1897 | * Put the device back in ID mode - only need to do this if we | |
1898 | * were truly frobbing a real device. | |
1899 | */ | |
1900 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ ); | |
cec80bf2 | 1901 | if (cfi->addr_unlock1) { |
1da177e4 LT |
1902 | cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); |
1903 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); | |
1904 | } | |
1905 | cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
1906 | /* FIXME - should have a delay before continuing */ | |
1907 | ||
1f948b43 | 1908 | match_done: |
1da177e4 LT |
1909 | return rc; |
1910 | } | |
1911 | ||
1912 | ||
1913 | static int jedec_probe_chip(struct map_info *map, __u32 base, | |
1914 | unsigned long *chip_map, struct cfi_private *cfi) | |
1915 | { | |
1916 | int i; | |
1917 | enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED; | |
1918 | u32 probe_offset1, probe_offset2; | |
1919 | ||
1920 | retry: | |
1921 | if (!cfi->numchips) { | |
1922 | uaddr_idx++; | |
1923 | ||
1924 | if (MTD_UADDR_UNNECESSARY == uaddr_idx) | |
1925 | return 0; | |
1926 | ||
cec80bf2 DW |
1927 | cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type; |
1928 | cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type; | |
1da177e4 LT |
1929 | } |
1930 | ||
1931 | /* Make certain we aren't probing past the end of map */ | |
1932 | if (base >= map->size) { | |
1933 | printk(KERN_NOTICE | |
1934 | "Probe at base(0x%08x) past the end of the map(0x%08lx)\n", | |
1935 | base, map->size -1); | |
1936 | return 0; | |
1f948b43 | 1937 | |
1da177e4 LT |
1938 | } |
1939 | /* Ensure the unlock addresses we try stay inside the map */ | |
5d3cce3b | 1940 | probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, cfi_interleave(cfi), cfi->device_type); |
f6f0f818 | 1941 | probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, cfi_interleave(cfi), cfi->device_type); |
1da177e4 LT |
1942 | if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || |
1943 | ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) | |
1da177e4 | 1944 | goto retry; |
1f948b43 | 1945 | |
1da177e4 LT |
1946 | /* Reset */ |
1947 | jedec_reset(base, map, cfi); | |
1948 | ||
1949 | /* Autoselect Mode */ | |
1950 | if(cfi->addr_unlock1) { | |
1951 | cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
1952 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); | |
1953 | } | |
1954 | cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
1955 | /* FIXME - should have a delay before continuing */ | |
1956 | ||
1957 | if (!cfi->numchips) { | |
1f948b43 | 1958 | /* This is the first time we're called. Set up the CFI |
1da177e4 | 1959 | stuff accordingly and return */ |
1f948b43 | 1960 | |
1da177e4 LT |
1961 | cfi->mfr = jedec_read_mfr(map, base, cfi); |
1962 | cfi->id = jedec_read_id(map, base, cfi); | |
1963 | DEBUG(MTD_DEBUG_LEVEL3, | |
1f948b43 | 1964 | "Search for id:(%02x %02x) interleave(%d) type(%d)\n", |
1da177e4 | 1965 | cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type); |
87d10f3c | 1966 | for (i = 0; i < ARRAY_SIZE(jedec_table); i++) { |
1da177e4 LT |
1967 | if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) { |
1968 | DEBUG( MTD_DEBUG_LEVEL3, | |
1969 | "MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n", | |
1970 | __func__, cfi->mfr, cfi->id, | |
1971 | cfi->addr_unlock1, cfi->addr_unlock2 ); | |
1972 | if (!cfi_jedec_setup(cfi, i)) | |
1973 | return 0; | |
1974 | goto ok_out; | |
1975 | } | |
1976 | } | |
1977 | goto retry; | |
1978 | } else { | |
5d3cce3b DW |
1979 | uint16_t mfr; |
1980 | uint16_t id; | |
1da177e4 LT |
1981 | |
1982 | /* Make sure it is a chip of the same manufacturer and id */ | |
1983 | mfr = jedec_read_mfr(map, base, cfi); | |
1984 | id = jedec_read_id(map, base, cfi); | |
1985 | ||
1986 | if ((mfr != cfi->mfr) || (id != cfi->id)) { | |
1987 | printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n", | |
1988 | map->name, mfr, id, base); | |
1989 | jedec_reset(base, map, cfi); | |
1990 | return 0; | |
1991 | } | |
1992 | } | |
1f948b43 | 1993 | |
1da177e4 LT |
1994 | /* Check each previous chip locations to see if it's an alias */ |
1995 | for (i=0; i < (base >> cfi->chipshift); i++) { | |
1996 | unsigned long start; | |
1997 | if(!test_bit(i, chip_map)) { | |
1998 | continue; /* Skip location; no valid chip at this address */ | |
1999 | } | |
2000 | start = i << cfi->chipshift; | |
2001 | if (jedec_read_mfr(map, start, cfi) == cfi->mfr && | |
2002 | jedec_read_id(map, start, cfi) == cfi->id) { | |
2003 | /* Eep. This chip also looks like it's in autoselect mode. | |
2004 | Is it an alias for the new one? */ | |
2005 | jedec_reset(start, map, cfi); | |
2006 | ||
2007 | /* If the device IDs go away, it's an alias */ | |
2008 | if (jedec_read_mfr(map, base, cfi) != cfi->mfr || | |
2009 | jedec_read_id(map, base, cfi) != cfi->id) { | |
2010 | printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", | |
2011 | map->name, base, start); | |
2012 | return 0; | |
2013 | } | |
1f948b43 | 2014 | |
1da177e4 LT |
2015 | /* Yes, it's actually got the device IDs as data. Most |
2016 | * unfortunate. Stick the new chip in read mode | |
2017 | * too and if it's the same, assume it's an alias. */ | |
2018 | /* FIXME: Use other modes to do a proper check */ | |
2019 | jedec_reset(base, map, cfi); | |
2020 | if (jedec_read_mfr(map, base, cfi) == cfi->mfr && | |
2021 | jedec_read_id(map, base, cfi) == cfi->id) { | |
2022 | printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", | |
2023 | map->name, base, start); | |
2024 | return 0; | |
2025 | } | |
2026 | } | |
2027 | } | |
1f948b43 | 2028 | |
1da177e4 LT |
2029 | /* OK, if we got to here, then none of the previous chips appear to |
2030 | be aliases for the current one. */ | |
2031 | set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */ | |
2032 | cfi->numchips++; | |
1f948b43 | 2033 | |
1da177e4 LT |
2034 | ok_out: |
2035 | /* Put it back into Read Mode */ | |
2036 | jedec_reset(base, map, cfi); | |
2037 | ||
2038 | printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n", | |
1f948b43 | 2039 | map->name, cfi_interleave(cfi), cfi->device_type*8, base, |
1da177e4 | 2040 | map->bankwidth*8); |
1f948b43 | 2041 | |
1da177e4 LT |
2042 | return 1; |
2043 | } | |
2044 | ||
2045 | static struct chip_probe jedec_chip_probe = { | |
2046 | .name = "JEDEC", | |
2047 | .probe_chip = jedec_probe_chip | |
2048 | }; | |
2049 | ||
2050 | static struct mtd_info *jedec_probe(struct map_info *map) | |
2051 | { | |
2052 | /* | |
2053 | * Just use the generic probe stuff to call our CFI-specific | |
2054 | * chip_probe routine in all the possible permutations, etc. | |
2055 | */ | |
2056 | return mtd_do_chip_probe(map, &jedec_chip_probe); | |
2057 | } | |
2058 | ||
2059 | static struct mtd_chip_driver jedec_chipdrv = { | |
2060 | .probe = jedec_probe, | |
2061 | .name = "jedec_probe", | |
2062 | .module = THIS_MODULE | |
2063 | }; | |
2064 | ||
2065 | static int __init jedec_probe_init(void) | |
2066 | { | |
2067 | register_mtd_chip_driver(&jedec_chipdrv); | |
2068 | return 0; | |
2069 | } | |
2070 | ||
2071 | static void __exit jedec_probe_exit(void) | |
2072 | { | |
2073 | unregister_mtd_chip_driver(&jedec_chipdrv); | |
2074 | } | |
2075 | ||
2076 | module_init(jedec_probe_init); | |
2077 | module_exit(jedec_probe_exit); | |
2078 | ||
2079 | MODULE_LICENSE("GPL"); | |
2080 | MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al."); | |
2081 | MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips"); |