Commit | Line | Data |
---|---|---|
2f9f7628 | 1 | /* |
fa0a8c71 | 2 | * MTD SPI driver for ST M25Pxx (and similar) serial flash chips |
2f9f7628 ML |
3 | * |
4 | * Author: Mike Lavender, mike@steroidmicros.com | |
5 | * | |
6 | * Copyright (c) 2005, Intec Automation Inc. | |
7 | * | |
8 | * Some parts are based on lart.c by Abraham Van Der Merwe | |
9 | * | |
10 | * Cleaned up and generalized based on mtd_dataflash.c | |
11 | * | |
12 | * This code is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
9d2c4f3f AV |
19 | #include <linux/err.h> |
20 | #include <linux/errno.h> | |
2f9f7628 ML |
21 | #include <linux/module.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/interrupt.h> | |
7d5230ea | 24 | #include <linux/mutex.h> |
d85316ac | 25 | #include <linux/math64.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
d43c36dc | 27 | #include <linux/sched.h> |
b34bc037 | 28 | #include <linux/mod_devicetable.h> |
7d5230ea | 29 | |
aa084653 | 30 | #include <linux/mtd/cfi.h> |
2f9f7628 ML |
31 | #include <linux/mtd/mtd.h> |
32 | #include <linux/mtd/partitions.h> | |
5f949137 | 33 | #include <linux/of_platform.h> |
7d5230ea | 34 | |
2f9f7628 ML |
35 | #include <linux/spi/spi.h> |
36 | #include <linux/spi/flash.h> | |
37 | ||
2f9f7628 | 38 | /* Flash opcodes. */ |
fa0a8c71 DB |
39 | #define OPCODE_WREN 0x06 /* Write enable */ |
40 | #define OPCODE_RDSR 0x05 /* Read status register */ | |
72289824 | 41 | #define OPCODE_WRSR 0x01 /* Write status register 1 byte */ |
2230b76b | 42 | #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ |
fa0a8c71 DB |
43 | #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ |
44 | #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ | |
7854643a | 45 | #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ |
6c3b8897 | 46 | #define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ |
02d087db | 47 | #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ |
7854643a | 48 | #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ |
02d087db | 49 | #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ |
2f9f7628 ML |
50 | #define OPCODE_RDID 0x9f /* Read JEDEC ID */ |
51 | ||
87c9511f BN |
52 | /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ |
53 | #define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ | |
54 | #define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ | |
55 | #define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ | |
56 | #define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ | |
57 | ||
49aac4ae GY |
58 | /* Used for SST flashes only. */ |
59 | #define OPCODE_BP 0x02 /* Byte program */ | |
60 | #define OPCODE_WRDI 0x04 /* Write disable */ | |
61 | #define OPCODE_AAI_WP 0xad /* Auto address increment word program */ | |
62 | ||
caddab0f | 63 | /* Used for Macronix and Winbond flashes. */ |
4b7f7422 KC |
64 | #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ |
65 | #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ | |
66 | ||
baa9ae3c KC |
67 | /* Used for Spansion flashes only. */ |
68 | #define OPCODE_BRWR 0x17 /* Bank register write */ | |
69 | ||
2f9f7628 ML |
70 | /* Status Register bits. */ |
71 | #define SR_WIP 1 /* Write in progress */ | |
72 | #define SR_WEL 2 /* Write enable latch */ | |
fa0a8c71 | 73 | /* meaning of other SR_* bits may differ between vendors */ |
2f9f7628 ML |
74 | #define SR_BP0 4 /* Block protect 0 */ |
75 | #define SR_BP1 8 /* Block protect 1 */ | |
76 | #define SR_BP2 0x10 /* Block protect 2 */ | |
77 | #define SR_SRWD 0x80 /* SR write protect */ | |
78 | ||
79 | /* Define max times to check status register before we give up. */ | |
89bb871e | 80 | #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ |
4b7f7422 | 81 | #define MAX_CMD_SIZE 5 |
2f9f7628 | 82 | |
aa084653 KC |
83 | #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16) |
84 | ||
2f9f7628 ML |
85 | /****************************************************************************/ |
86 | ||
87 | struct m25p { | |
88 | struct spi_device *spi; | |
7d5230ea | 89 | struct mutex lock; |
2f9f7628 | 90 | struct mtd_info mtd; |
837479d2 AV |
91 | u16 page_size; |
92 | u16 addr_width; | |
fa0a8c71 | 93 | u8 erase_opcode; |
87c9511f BN |
94 | u8 read_opcode; |
95 | u8 program_opcode; | |
61c3506c | 96 | u8 *command; |
12ad2be9 | 97 | bool fast_read; |
2f9f7628 ML |
98 | }; |
99 | ||
100 | static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) | |
101 | { | |
102 | return container_of(mtd, struct m25p, mtd); | |
103 | } | |
104 | ||
105 | /****************************************************************************/ | |
106 | ||
107 | /* | |
108 | * Internal helper functions | |
109 | */ | |
110 | ||
111 | /* | |
112 | * Read the status register, returning its value in the location | |
113 | * Return the status register value. | |
114 | * Returns negative if error occurred. | |
115 | */ | |
116 | static int read_sr(struct m25p *flash) | |
117 | { | |
118 | ssize_t retval; | |
119 | u8 code = OPCODE_RDSR; | |
120 | u8 val; | |
121 | ||
122 | retval = spi_write_then_read(flash->spi, &code, 1, &val, 1); | |
123 | ||
124 | if (retval < 0) { | |
125 | dev_err(&flash->spi->dev, "error %d reading SR\n", | |
126 | (int) retval); | |
127 | return retval; | |
128 | } | |
129 | ||
130 | return val; | |
131 | } | |
132 | ||
72289824 MH |
133 | /* |
134 | * Write status register 1 byte | |
135 | * Returns negative if error occurred. | |
136 | */ | |
137 | static int write_sr(struct m25p *flash, u8 val) | |
138 | { | |
139 | flash->command[0] = OPCODE_WRSR; | |
140 | flash->command[1] = val; | |
141 | ||
142 | return spi_write(flash->spi, flash->command, 2); | |
143 | } | |
2f9f7628 ML |
144 | |
145 | /* | |
146 | * Set write enable latch with Write Enable command. | |
147 | * Returns negative if error occurred. | |
148 | */ | |
149 | static inline int write_enable(struct m25p *flash) | |
150 | { | |
151 | u8 code = OPCODE_WREN; | |
152 | ||
8a1a6272 | 153 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); |
2f9f7628 ML |
154 | } |
155 | ||
49aac4ae GY |
156 | /* |
157 | * Send write disble instruction to the chip. | |
158 | */ | |
159 | static inline int write_disable(struct m25p *flash) | |
160 | { | |
161 | u8 code = OPCODE_WRDI; | |
162 | ||
163 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); | |
164 | } | |
2f9f7628 | 165 | |
4b7f7422 KC |
166 | /* |
167 | * Enable/disable 4-byte addressing mode. | |
168 | */ | |
baa9ae3c | 169 | static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable) |
4b7f7422 | 170 | { |
2b468ef0 EDB |
171 | int status; |
172 | bool need_wren = false; | |
173 | ||
baa9ae3c | 174 | switch (JEDEC_MFR(jedec_id)) { |
eedeac3c | 175 | case CFI_MFR_ST: /* Micron, actually */ |
2b468ef0 EDB |
176 | /* Some Micron need WREN command; all will accept it */ |
177 | need_wren = true; | |
178 | case CFI_MFR_MACRONIX: | |
0aa87b75 | 179 | case 0xEF /* winbond */: |
2b468ef0 EDB |
180 | if (need_wren) |
181 | write_enable(flash); | |
182 | ||
baa9ae3c | 183 | flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B; |
2b468ef0 EDB |
184 | status = spi_write(flash->spi, flash->command, 1); |
185 | ||
186 | if (need_wren) | |
187 | write_disable(flash); | |
188 | ||
189 | return status; | |
baa9ae3c KC |
190 | default: |
191 | /* Spansion style */ | |
192 | flash->command[0] = OPCODE_BRWR; | |
193 | flash->command[1] = enable << 7; | |
194 | return spi_write(flash->spi, flash->command, 2); | |
195 | } | |
4b7f7422 KC |
196 | } |
197 | ||
2f9f7628 ML |
198 | /* |
199 | * Service routine to read status register until ready, or timeout occurs. | |
200 | * Returns non-zero if error. | |
201 | */ | |
202 | static int wait_till_ready(struct m25p *flash) | |
203 | { | |
cd1a6de7 | 204 | unsigned long deadline; |
2f9f7628 ML |
205 | int sr; |
206 | ||
cd1a6de7 PH |
207 | deadline = jiffies + MAX_READY_WAIT_JIFFIES; |
208 | ||
209 | do { | |
2f9f7628 ML |
210 | if ((sr = read_sr(flash)) < 0) |
211 | break; | |
212 | else if (!(sr & SR_WIP)) | |
213 | return 0; | |
214 | ||
cd1a6de7 PH |
215 | cond_resched(); |
216 | ||
217 | } while (!time_after_eq(jiffies, deadline)); | |
2f9f7628 ML |
218 | |
219 | return 1; | |
220 | } | |
221 | ||
faff3750 CG |
222 | /* |
223 | * Erase the whole flash memory | |
224 | * | |
225 | * Returns 0 if successful, non-zero otherwise. | |
226 | */ | |
7854643a | 227 | static int erase_chip(struct m25p *flash) |
faff3750 | 228 | { |
0a32a102 BN |
229 | pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__, |
230 | (long long)(flash->mtd.size >> 10)); | |
faff3750 CG |
231 | |
232 | /* Wait until finished previous write command. */ | |
233 | if (wait_till_ready(flash)) | |
234 | return 1; | |
235 | ||
236 | /* Send write enable, then erase commands. */ | |
237 | write_enable(flash); | |
238 | ||
239 | /* Set up command buffer. */ | |
7854643a | 240 | flash->command[0] = OPCODE_CHIP_ERASE; |
faff3750 CG |
241 | |
242 | spi_write(flash->spi, flash->command, 1); | |
243 | ||
244 | return 0; | |
245 | } | |
2f9f7628 | 246 | |
837479d2 AV |
247 | static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd) |
248 | { | |
249 | /* opcode is in cmd[0] */ | |
250 | cmd[1] = addr >> (flash->addr_width * 8 - 8); | |
251 | cmd[2] = addr >> (flash->addr_width * 8 - 16); | |
252 | cmd[3] = addr >> (flash->addr_width * 8 - 24); | |
4b7f7422 | 253 | cmd[4] = addr >> (flash->addr_width * 8 - 32); |
837479d2 AV |
254 | } |
255 | ||
256 | static int m25p_cmdsz(struct m25p *flash) | |
257 | { | |
258 | return 1 + flash->addr_width; | |
259 | } | |
260 | ||
2f9f7628 ML |
261 | /* |
262 | * Erase one sector of flash memory at offset ``offset'' which is any | |
263 | * address within the sector which should be erased. | |
264 | * | |
265 | * Returns 0 if successful, non-zero otherwise. | |
266 | */ | |
267 | static int erase_sector(struct m25p *flash, u32 offset) | |
268 | { | |
0a32a102 BN |
269 | pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev), |
270 | __func__, flash->mtd.erasesize / 1024, offset); | |
2f9f7628 ML |
271 | |
272 | /* Wait until finished previous write command. */ | |
273 | if (wait_till_ready(flash)) | |
274 | return 1; | |
275 | ||
276 | /* Send write enable, then erase commands. */ | |
277 | write_enable(flash); | |
278 | ||
279 | /* Set up command buffer. */ | |
fa0a8c71 | 280 | flash->command[0] = flash->erase_opcode; |
837479d2 | 281 | m25p_addr2cmd(flash, offset, flash->command); |
2f9f7628 | 282 | |
837479d2 | 283 | spi_write(flash->spi, flash->command, m25p_cmdsz(flash)); |
2f9f7628 ML |
284 | |
285 | return 0; | |
286 | } | |
287 | ||
288 | /****************************************************************************/ | |
289 | ||
290 | /* | |
291 | * MTD implementation | |
292 | */ | |
293 | ||
294 | /* | |
295 | * Erase an address range on the flash chip. The address range may extend | |
296 | * one or more erase sectors. Return an error is there is a problem erasing. | |
297 | */ | |
298 | static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) | |
299 | { | |
300 | struct m25p *flash = mtd_to_m25p(mtd); | |
301 | u32 addr,len; | |
d85316ac | 302 | uint32_t rem; |
2f9f7628 | 303 | |
0a32a102 BN |
304 | pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev), |
305 | __func__, (long long)instr->addr, | |
306 | (long long)instr->len); | |
2f9f7628 | 307 | |
d85316ac AB |
308 | div_u64_rem(instr->len, mtd->erasesize, &rem); |
309 | if (rem) | |
2f9f7628 | 310 | return -EINVAL; |
2f9f7628 ML |
311 | |
312 | addr = instr->addr; | |
313 | len = instr->len; | |
314 | ||
7d5230ea | 315 | mutex_lock(&flash->lock); |
2f9f7628 | 316 | |
7854643a | 317 | /* whole-chip erase? */ |
3f33b0aa SF |
318 | if (len == flash->mtd.size) { |
319 | if (erase_chip(flash)) { | |
320 | instr->state = MTD_ERASE_FAILED; | |
321 | mutex_unlock(&flash->lock); | |
322 | return -EIO; | |
323 | } | |
7854643a CG |
324 | |
325 | /* REVISIT in some cases we could speed up erasing large regions | |
326 | * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up | |
327 | * to use "small sector erase", but that's not always optimal. | |
328 | */ | |
329 | ||
330 | /* "sector"-at-a-time erase */ | |
faff3750 CG |
331 | } else { |
332 | while (len) { | |
333 | if (erase_sector(flash, addr)) { | |
334 | instr->state = MTD_ERASE_FAILED; | |
335 | mutex_unlock(&flash->lock); | |
336 | return -EIO; | |
337 | } | |
338 | ||
339 | addr += mtd->erasesize; | |
340 | len -= mtd->erasesize; | |
2f9f7628 | 341 | } |
2f9f7628 ML |
342 | } |
343 | ||
7d5230ea | 344 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
345 | |
346 | instr->state = MTD_ERASE_DONE; | |
347 | mtd_erase_callback(instr); | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
352 | /* | |
353 | * Read an address range from the flash chip. The address range | |
354 | * may be any size provided it is within the physical boundaries. | |
355 | */ | |
356 | static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, | |
357 | size_t *retlen, u_char *buf) | |
358 | { | |
359 | struct m25p *flash = mtd_to_m25p(mtd); | |
360 | struct spi_transfer t[2]; | |
361 | struct spi_message m; | |
12ad2be9 | 362 | uint8_t opcode; |
2f9f7628 | 363 | |
0a32a102 BN |
364 | pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev), |
365 | __func__, (u32)from, len); | |
2f9f7628 | 366 | |
8275c642 VW |
367 | spi_message_init(&m); |
368 | memset(t, 0, (sizeof t)); | |
369 | ||
2230b76b BW |
370 | /* NOTE: |
371 | * OPCODE_FAST_READ (if available) is faster. | |
372 | * Should add 1 byte DUMMY_BYTE. | |
373 | */ | |
8275c642 | 374 | t[0].tx_buf = flash->command; |
12ad2be9 | 375 | t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0); |
8275c642 VW |
376 | spi_message_add_tail(&t[0], &m); |
377 | ||
378 | t[1].rx_buf = buf; | |
379 | t[1].len = len; | |
380 | spi_message_add_tail(&t[1], &m); | |
381 | ||
7d5230ea | 382 | mutex_lock(&flash->lock); |
2f9f7628 ML |
383 | |
384 | /* Wait till previous write/erase is done. */ | |
385 | if (wait_till_ready(flash)) { | |
386 | /* REVISIT status return?? */ | |
7d5230ea | 387 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
388 | return 1; |
389 | } | |
390 | ||
fa0a8c71 DB |
391 | /* FIXME switch to OPCODE_FAST_READ. It's required for higher |
392 | * clocks; and at this writing, every chip this driver handles | |
393 | * supports that opcode. | |
394 | */ | |
2f9f7628 ML |
395 | |
396 | /* Set up the write data buffer. */ | |
87c9511f | 397 | opcode = flash->read_opcode; |
12ad2be9 | 398 | flash->command[0] = opcode; |
837479d2 | 399 | m25p_addr2cmd(flash, from, flash->command); |
2f9f7628 | 400 | |
2f9f7628 ML |
401 | spi_sync(flash->spi, &m); |
402 | ||
12ad2be9 MV |
403 | *retlen = m.actual_length - m25p_cmdsz(flash) - |
404 | (flash->fast_read ? 1 : 0); | |
2f9f7628 | 405 | |
7d5230ea | 406 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
407 | |
408 | return 0; | |
409 | } | |
410 | ||
411 | /* | |
412 | * Write an address range to the flash chip. Data must be written in | |
413 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
414 | * it is within the physical boundaries. | |
415 | */ | |
416 | static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, | |
417 | size_t *retlen, const u_char *buf) | |
418 | { | |
419 | struct m25p *flash = mtd_to_m25p(mtd); | |
420 | u32 page_offset, page_size; | |
421 | struct spi_transfer t[2]; | |
422 | struct spi_message m; | |
423 | ||
0a32a102 BN |
424 | pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev), |
425 | __func__, (u32)to, len); | |
2f9f7628 | 426 | |
8275c642 VW |
427 | spi_message_init(&m); |
428 | memset(t, 0, (sizeof t)); | |
429 | ||
430 | t[0].tx_buf = flash->command; | |
837479d2 | 431 | t[0].len = m25p_cmdsz(flash); |
8275c642 VW |
432 | spi_message_add_tail(&t[0], &m); |
433 | ||
434 | t[1].tx_buf = buf; | |
435 | spi_message_add_tail(&t[1], &m); | |
436 | ||
7d5230ea | 437 | mutex_lock(&flash->lock); |
2f9f7628 ML |
438 | |
439 | /* Wait until finished previous write command. */ | |
bc018863 CG |
440 | if (wait_till_ready(flash)) { |
441 | mutex_unlock(&flash->lock); | |
2f9f7628 | 442 | return 1; |
bc018863 | 443 | } |
2f9f7628 ML |
444 | |
445 | write_enable(flash); | |
446 | ||
2f9f7628 | 447 | /* Set up the opcode in the write buffer. */ |
87c9511f | 448 | flash->command[0] = flash->program_opcode; |
837479d2 | 449 | m25p_addr2cmd(flash, to, flash->command); |
2f9f7628 | 450 | |
837479d2 | 451 | page_offset = to & (flash->page_size - 1); |
2f9f7628 ML |
452 | |
453 | /* do all the bytes fit onto one page? */ | |
837479d2 | 454 | if (page_offset + len <= flash->page_size) { |
2f9f7628 ML |
455 | t[1].len = len; |
456 | ||
457 | spi_sync(flash->spi, &m); | |
458 | ||
837479d2 | 459 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 ML |
460 | } else { |
461 | u32 i; | |
462 | ||
463 | /* the size of data remaining on the first page */ | |
837479d2 | 464 | page_size = flash->page_size - page_offset; |
2f9f7628 | 465 | |
2f9f7628 ML |
466 | t[1].len = page_size; |
467 | spi_sync(flash->spi, &m); | |
468 | ||
837479d2 | 469 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 | 470 | |
837479d2 | 471 | /* write everything in flash->page_size chunks */ |
2f9f7628 ML |
472 | for (i = page_size; i < len; i += page_size) { |
473 | page_size = len - i; | |
837479d2 AV |
474 | if (page_size > flash->page_size) |
475 | page_size = flash->page_size; | |
2f9f7628 ML |
476 | |
477 | /* write the next page to flash */ | |
837479d2 | 478 | m25p_addr2cmd(flash, to + i, flash->command); |
2f9f7628 ML |
479 | |
480 | t[1].tx_buf = buf + i; | |
481 | t[1].len = page_size; | |
482 | ||
483 | wait_till_ready(flash); | |
484 | ||
485 | write_enable(flash); | |
486 | ||
487 | spi_sync(flash->spi, &m); | |
488 | ||
b06cd21e | 489 | *retlen += m.actual_length - m25p_cmdsz(flash); |
7d5230ea DB |
490 | } |
491 | } | |
2f9f7628 | 492 | |
7d5230ea | 493 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
494 | |
495 | return 0; | |
496 | } | |
497 | ||
49aac4ae GY |
498 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, |
499 | size_t *retlen, const u_char *buf) | |
500 | { | |
501 | struct m25p *flash = mtd_to_m25p(mtd); | |
502 | struct spi_transfer t[2]; | |
503 | struct spi_message m; | |
504 | size_t actual; | |
505 | int cmd_sz, ret; | |
506 | ||
0a32a102 BN |
507 | pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev), |
508 | __func__, (u32)to, len); | |
dcf12463 | 509 | |
49aac4ae GY |
510 | spi_message_init(&m); |
511 | memset(t, 0, (sizeof t)); | |
512 | ||
513 | t[0].tx_buf = flash->command; | |
837479d2 | 514 | t[0].len = m25p_cmdsz(flash); |
49aac4ae GY |
515 | spi_message_add_tail(&t[0], &m); |
516 | ||
517 | t[1].tx_buf = buf; | |
518 | spi_message_add_tail(&t[1], &m); | |
519 | ||
520 | mutex_lock(&flash->lock); | |
521 | ||
522 | /* Wait until finished previous write command. */ | |
523 | ret = wait_till_ready(flash); | |
524 | if (ret) | |
525 | goto time_out; | |
526 | ||
527 | write_enable(flash); | |
528 | ||
529 | actual = to % 2; | |
530 | /* Start write from odd address. */ | |
531 | if (actual) { | |
532 | flash->command[0] = OPCODE_BP; | |
837479d2 | 533 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
534 | |
535 | /* write one byte. */ | |
536 | t[1].len = 1; | |
537 | spi_sync(flash->spi, &m); | |
538 | ret = wait_till_ready(flash); | |
539 | if (ret) | |
540 | goto time_out; | |
837479d2 | 541 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
542 | } |
543 | to += actual; | |
544 | ||
545 | flash->command[0] = OPCODE_AAI_WP; | |
837479d2 | 546 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
547 | |
548 | /* Write out most of the data here. */ | |
837479d2 | 549 | cmd_sz = m25p_cmdsz(flash); |
49aac4ae GY |
550 | for (; actual < len - 1; actual += 2) { |
551 | t[0].len = cmd_sz; | |
552 | /* write two bytes. */ | |
553 | t[1].len = 2; | |
554 | t[1].tx_buf = buf + actual; | |
555 | ||
556 | spi_sync(flash->spi, &m); | |
557 | ret = wait_till_ready(flash); | |
558 | if (ret) | |
559 | goto time_out; | |
560 | *retlen += m.actual_length - cmd_sz; | |
561 | cmd_sz = 1; | |
562 | to += 2; | |
563 | } | |
564 | write_disable(flash); | |
565 | ret = wait_till_ready(flash); | |
566 | if (ret) | |
567 | goto time_out; | |
568 | ||
569 | /* Write out trailing byte if it exists. */ | |
570 | if (actual != len) { | |
571 | write_enable(flash); | |
572 | flash->command[0] = OPCODE_BP; | |
837479d2 AV |
573 | m25p_addr2cmd(flash, to, flash->command); |
574 | t[0].len = m25p_cmdsz(flash); | |
49aac4ae GY |
575 | t[1].len = 1; |
576 | t[1].tx_buf = buf + actual; | |
577 | ||
578 | spi_sync(flash->spi, &m); | |
579 | ret = wait_till_ready(flash); | |
580 | if (ret) | |
581 | goto time_out; | |
837479d2 | 582 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
583 | write_disable(flash); |
584 | } | |
585 | ||
586 | time_out: | |
587 | mutex_unlock(&flash->lock); | |
588 | return ret; | |
589 | } | |
2f9f7628 | 590 | |
972e1b7b AB |
591 | static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
592 | { | |
593 | struct m25p *flash = mtd_to_m25p(mtd); | |
594 | uint32_t offset = ofs; | |
595 | uint8_t status_old, status_new; | |
596 | int res = 0; | |
597 | ||
598 | mutex_lock(&flash->lock); | |
599 | /* Wait until finished previous command */ | |
600 | if (wait_till_ready(flash)) { | |
601 | res = 1; | |
602 | goto err; | |
603 | } | |
604 | ||
605 | status_old = read_sr(flash); | |
606 | ||
607 | if (offset < flash->mtd.size-(flash->mtd.size/2)) | |
608 | status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0; | |
609 | else if (offset < flash->mtd.size-(flash->mtd.size/4)) | |
610 | status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; | |
611 | else if (offset < flash->mtd.size-(flash->mtd.size/8)) | |
612 | status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; | |
613 | else if (offset < flash->mtd.size-(flash->mtd.size/16)) | |
614 | status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2; | |
615 | else if (offset < flash->mtd.size-(flash->mtd.size/32)) | |
616 | status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; | |
617 | else if (offset < flash->mtd.size-(flash->mtd.size/64)) | |
618 | status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1; | |
619 | else | |
620 | status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0; | |
621 | ||
622 | /* Only modify protection if it will not unlock other areas */ | |
623 | if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) > | |
624 | (status_old&(SR_BP2|SR_BP1|SR_BP0))) { | |
625 | write_enable(flash); | |
626 | if (write_sr(flash, status_new) < 0) { | |
627 | res = 1; | |
628 | goto err; | |
629 | } | |
630 | } | |
631 | ||
632 | err: mutex_unlock(&flash->lock); | |
633 | return res; | |
634 | } | |
635 | ||
636 | static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
637 | { | |
638 | struct m25p *flash = mtd_to_m25p(mtd); | |
639 | uint32_t offset = ofs; | |
640 | uint8_t status_old, status_new; | |
641 | int res = 0; | |
642 | ||
643 | mutex_lock(&flash->lock); | |
644 | /* Wait until finished previous command */ | |
645 | if (wait_till_ready(flash)) { | |
646 | res = 1; | |
647 | goto err; | |
648 | } | |
649 | ||
650 | status_old = read_sr(flash); | |
651 | ||
652 | if (offset+len > flash->mtd.size-(flash->mtd.size/64)) | |
653 | status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0); | |
654 | else if (offset+len > flash->mtd.size-(flash->mtd.size/32)) | |
655 | status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0; | |
656 | else if (offset+len > flash->mtd.size-(flash->mtd.size/16)) | |
657 | status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1; | |
658 | else if (offset+len > flash->mtd.size-(flash->mtd.size/8)) | |
659 | status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; | |
660 | else if (offset+len > flash->mtd.size-(flash->mtd.size/4)) | |
661 | status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2; | |
662 | else if (offset+len > flash->mtd.size-(flash->mtd.size/2)) | |
663 | status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; | |
664 | else | |
665 | status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; | |
666 | ||
667 | /* Only modify protection if it will not lock other areas */ | |
668 | if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) < | |
669 | (status_old&(SR_BP2|SR_BP1|SR_BP0))) { | |
670 | write_enable(flash); | |
671 | if (write_sr(flash, status_new) < 0) { | |
672 | res = 1; | |
673 | goto err; | |
674 | } | |
675 | } | |
676 | ||
677 | err: mutex_unlock(&flash->lock); | |
678 | return res; | |
679 | } | |
680 | ||
2f9f7628 ML |
681 | /****************************************************************************/ |
682 | ||
683 | /* | |
684 | * SPI device driver setup and teardown | |
685 | */ | |
686 | ||
687 | struct flash_info { | |
fa0a8c71 DB |
688 | /* JEDEC id zero means "no ID" (most older chips); otherwise it has |
689 | * a high byte of zero plus three data bytes: the manufacturer id, | |
690 | * then a two byte device id. | |
691 | */ | |
692 | u32 jedec_id; | |
d0e8c47c | 693 | u16 ext_id; |
fa0a8c71 DB |
694 | |
695 | /* The size listed here is what works with OPCODE_SE, which isn't | |
696 | * necessarily called a "sector" by the vendor. | |
697 | */ | |
2f9f7628 | 698 | unsigned sector_size; |
fa0a8c71 DB |
699 | u16 n_sectors; |
700 | ||
837479d2 AV |
701 | u16 page_size; |
702 | u16 addr_width; | |
703 | ||
fa0a8c71 DB |
704 | u16 flags; |
705 | #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ | |
837479d2 | 706 | #define M25P_NO_ERASE 0x02 /* No erase command needed */ |
e534ee4f | 707 | #define SST_WRITE 0x04 /* use SST byte programming */ |
58146992 | 708 | #define M25P_NO_FR 0x08 /* Can't do fastread */ |
6c3b8897 | 709 | #define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */ |
2f9f7628 ML |
710 | }; |
711 | ||
b34bc037 AV |
712 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
713 | ((kernel_ulong_t)&(struct flash_info) { \ | |
714 | .jedec_id = (_jedec_id), \ | |
715 | .ext_id = (_ext_id), \ | |
716 | .sector_size = (_sector_size), \ | |
717 | .n_sectors = (_n_sectors), \ | |
837479d2 | 718 | .page_size = 256, \ |
b34bc037 AV |
719 | .flags = (_flags), \ |
720 | }) | |
fa0a8c71 | 721 | |
7e7d83b3 | 722 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ |
837479d2 AV |
723 | ((kernel_ulong_t)&(struct flash_info) { \ |
724 | .sector_size = (_sector_size), \ | |
725 | .n_sectors = (_n_sectors), \ | |
726 | .page_size = (_page_size), \ | |
727 | .addr_width = (_addr_width), \ | |
7e7d83b3 | 728 | .flags = (_flags), \ |
837479d2 | 729 | }) |
fa0a8c71 DB |
730 | |
731 | /* NOTE: double check command sets and memory organization when you add | |
732 | * more flash chips. This current list focusses on newer chips, which | |
733 | * have been converging on command sets which including JEDEC ID. | |
734 | */ | |
b34bc037 | 735 | static const struct spi_device_id m25p_ids[] = { |
fa0a8c71 | 736 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
b34bc037 AV |
737 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, |
738 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
fa0a8c71 | 739 | |
b34bc037 | 740 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, |
ada766e9 | 741 | { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, |
b34bc037 | 742 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, |
fa0a8c71 | 743 | |
b34bc037 AV |
744 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, |
745 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
746 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
8fffed8c | 747 | { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, |
fa0a8c71 | 748 | |
a5b2d76d CL |
749 | { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, |
750 | ||
37a23c20 GJ |
751 | /* EON -- en25xxx */ |
752 | { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, | |
60845e72 | 753 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, |
86a9893d | 754 | { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, |
60845e72 | 755 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, |
58d864ed | 756 | { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, |
6b75152b | 757 | { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, |
60845e72 | 758 | |
5ca11ca7 | 759 | /* Everspin */ |
58146992 | 760 | { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, M25P_NO_ERASE | M25P_NO_FR) }, |
a3d7ee9f | 761 | { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, M25P_NO_ERASE | M25P_NO_FR) }, |
5ca11ca7 | 762 | |
55bf75b7 MS |
763 | /* GigaDevice */ |
764 | { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) }, | |
765 | { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) }, | |
766 | ||
f80e521c GJ |
767 | /* Intel/Numonyx -- xxxs33b */ |
768 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, | |
769 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, | |
770 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, | |
771 | ||
ab1ff210 | 772 | /* Macronix */ |
bb08bc10 | 773 | { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, |
df0094d7 | 774 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, |
6175f4a1 | 775 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, |
9c76b4e5 | 776 | { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, |
b34bc037 AV |
777 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) }, |
778 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) }, | |
779 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, | |
780 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
4b7f7422 | 781 | { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, |
ac622f58 | 782 | { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, |
f9952754 | 783 | { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) }, |
ab1ff210 | 784 | |
8da28681 | 785 | /* Micron */ |
e66e280c | 786 | { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) }, |
98a9e245 LW |
787 | { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) }, |
788 | { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) }, | |
8da28681 VD |
789 | { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) }, |
790 | ||
6c3b8897 MS |
791 | /* PMC */ |
792 | { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, | |
793 | { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) }, | |
794 | { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) }, | |
795 | ||
fa0a8c71 DB |
796 | /* Spansion -- single (large) sector size only, at least |
797 | * for the chips listed here (without boot sectors). | |
798 | */ | |
b277f77e MV |
799 | { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) }, |
800 | { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) }, | |
baa9ae3c KC |
801 | { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, |
802 | { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) }, | |
3d2d2b65 KC |
803 | { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) }, |
804 | { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, | |
b34bc037 AV |
805 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, |
806 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
807 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) }, | |
808 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) }, | |
8bb8b85f MV |
809 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
810 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
811 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
812 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
813 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, | |
f2df1ae3 GH |
814 | { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, |
815 | { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
fa0a8c71 DB |
816 | |
817 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
e534ee4f KM |
818 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, |
819 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, | |
820 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, | |
821 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, | |
89134055 | 822 | { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, |
e534ee4f KM |
823 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, |
824 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, | |
825 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, | |
826 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, | |
fa0a8c71 DB |
827 | |
828 | /* ST Microelectronics -- newer production may have feature updates */ | |
b34bc037 AV |
829 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, |
830 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
831 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
832 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
833 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
834 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
835 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
836 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
837 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
4800399e | 838 | { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) }, |
b34bc037 | 839 | |
f7b00090 AV |
840 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, |
841 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, | |
842 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, | |
843 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, | |
844 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, | |
845 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, | |
846 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, | |
847 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, | |
848 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, | |
849 | ||
b34bc037 AV |
850 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, |
851 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
852 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
853 | ||
943b35a6 | 854 | { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, |
b34bc037 AV |
855 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, |
856 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
fa0a8c71 | 857 | |
16004f36 KC |
858 | { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, |
859 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, | |
860 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, | |
861 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, | |
d8f90b2c | 862 | |
02d087db | 863 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ |
b34bc037 AV |
864 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
865 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
866 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
867 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
868 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
869 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
0af18d27 | 870 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, |
9d6367f4 | 871 | { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) }, |
b34bc037 | 872 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
d2ac467a | 873 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, |
4b6ff7af | 874 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, |
4fba37ae | 875 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
9b7ef60c | 876 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, |
001c33ab | 877 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, |
0aa87b75 | 878 | { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) }, |
837479d2 AV |
879 | |
880 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
58146992 SH |
881 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1, M25P_NO_ERASE | M25P_NO_FR) }, |
882 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2, M25P_NO_ERASE | M25P_NO_FR) }, | |
883 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) }, | |
884 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) }, | |
885 | { "cat25128", CAT25_INFO(2048, 8, 64, 2, M25P_NO_ERASE | M25P_NO_FR) }, | |
b34bc037 | 886 | { }, |
2f9f7628 | 887 | }; |
b34bc037 | 888 | MODULE_DEVICE_TABLE(spi, m25p_ids); |
2f9f7628 | 889 | |
06f25510 | 890 | static const struct spi_device_id *jedec_probe(struct spi_device *spi) |
fa0a8c71 DB |
891 | { |
892 | int tmp; | |
893 | u8 code = OPCODE_RDID; | |
daa84735 | 894 | u8 id[5]; |
fa0a8c71 | 895 | u32 jedec; |
d0e8c47c | 896 | u16 ext_jedec; |
fa0a8c71 DB |
897 | struct flash_info *info; |
898 | ||
899 | /* JEDEC also defines an optional "extended device information" | |
900 | * string for after vendor-specific data, after the three bytes | |
901 | * we use here. Supporting some chips might require using it. | |
902 | */ | |
daa84735 | 903 | tmp = spi_write_then_read(spi, &code, 1, id, 5); |
fa0a8c71 | 904 | if (tmp < 0) { |
289c0522 | 905 | pr_debug("%s: error %d reading JEDEC ID\n", |
0a32a102 | 906 | dev_name(&spi->dev), tmp); |
9d2c4f3f | 907 | return ERR_PTR(tmp); |
fa0a8c71 DB |
908 | } |
909 | jedec = id[0]; | |
910 | jedec = jedec << 8; | |
911 | jedec |= id[1]; | |
912 | jedec = jedec << 8; | |
913 | jedec |= id[2]; | |
914 | ||
d0e8c47c CG |
915 | ext_jedec = id[3] << 8 | id[4]; |
916 | ||
b34bc037 AV |
917 | for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) { |
918 | info = (void *)m25p_ids[tmp].driver_data; | |
a3d3f73c | 919 | if (info->jedec_id == jedec) { |
9168ab86 | 920 | if (info->ext_id != 0 && info->ext_id != ext_jedec) |
d0e8c47c | 921 | continue; |
b34bc037 | 922 | return &m25p_ids[tmp]; |
a3d3f73c | 923 | } |
fa0a8c71 | 924 | } |
f0dff9bd | 925 | dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); |
9d2c4f3f | 926 | return ERR_PTR(-ENODEV); |
fa0a8c71 DB |
927 | } |
928 | ||
929 | ||
2f9f7628 ML |
930 | /* |
931 | * board specific setup should have ensured the SPI clock used here | |
932 | * matches what the READ command supports, at least until this driver | |
933 | * understands FAST_READ (for clocks over 25 MHz). | |
934 | */ | |
06f25510 | 935 | static int m25p_probe(struct spi_device *spi) |
2f9f7628 | 936 | { |
18c6182b | 937 | const struct spi_device_id *id = spi_get_device_id(spi); |
2f9f7628 ML |
938 | struct flash_platform_data *data; |
939 | struct m25p *flash; | |
940 | struct flash_info *info; | |
941 | unsigned i; | |
ea6a4729 | 942 | struct mtd_part_parser_data ppdata; |
12ad2be9 | 943 | struct device_node __maybe_unused *np = spi->dev.of_node; |
2f9f7628 | 944 | |
5f949137 | 945 | #ifdef CONFIG_MTD_OF_PARTS |
12ad2be9 | 946 | if (!of_device_is_available(np)) |
5f949137 SX |
947 | return -ENODEV; |
948 | #endif | |
949 | ||
2f9f7628 | 950 | /* Platform data helps sort out which chip type we have, as |
fa0a8c71 DB |
951 | * well as how this board partitions it. If we don't have |
952 | * a chip ID, try the JEDEC id commands; they'll work for most | |
953 | * newer chips, even if we don't recognize the particular chip. | |
2f9f7628 | 954 | */ |
0278fd3f | 955 | data = dev_get_platdata(&spi->dev); |
fa0a8c71 | 956 | if (data && data->type) { |
18c6182b | 957 | const struct spi_device_id *plat_id; |
2f9f7628 | 958 | |
b34bc037 | 959 | for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) { |
18c6182b AV |
960 | plat_id = &m25p_ids[i]; |
961 | if (strcmp(data->type, plat_id->name)) | |
b34bc037 AV |
962 | continue; |
963 | break; | |
fa0a8c71 | 964 | } |
fa0a8c71 | 965 | |
f78ec6b2 | 966 | if (i < ARRAY_SIZE(m25p_ids) - 1) |
18c6182b AV |
967 | id = plat_id; |
968 | else | |
969 | dev_warn(&spi->dev, "unrecognized id %s\n", data->type); | |
b34bc037 | 970 | } |
fa0a8c71 | 971 | |
18c6182b AV |
972 | info = (void *)id->driver_data; |
973 | ||
974 | if (info->jedec_id) { | |
975 | const struct spi_device_id *jid; | |
976 | ||
977 | jid = jedec_probe(spi); | |
9d2c4f3f AV |
978 | if (IS_ERR(jid)) { |
979 | return PTR_ERR(jid); | |
18c6182b AV |
980 | } else if (jid != id) { |
981 | /* | |
982 | * JEDEC knows better, so overwrite platform ID. We | |
983 | * can't trust partitions any longer, but we'll let | |
984 | * mtd apply them anyway, since some partitions may be | |
985 | * marked read-only, and we don't want to lose that | |
986 | * information, even if it's not 100% accurate. | |
987 | */ | |
988 | dev_warn(&spi->dev, "found %s, expected %s\n", | |
989 | jid->name, id->name); | |
990 | id = jid; | |
991 | info = (void *)jid->driver_data; | |
992 | } | |
993 | } | |
2f9f7628 | 994 | |
e94b1766 | 995 | flash = kzalloc(sizeof *flash, GFP_KERNEL); |
2f9f7628 ML |
996 | if (!flash) |
997 | return -ENOMEM; | |
12ad2be9 MV |
998 | flash->command = kmalloc(MAX_CMD_SIZE + (flash->fast_read ? 1 : 0), |
999 | GFP_KERNEL); | |
61c3506c JS |
1000 | if (!flash->command) { |
1001 | kfree(flash); | |
1002 | return -ENOMEM; | |
1003 | } | |
2f9f7628 ML |
1004 | |
1005 | flash->spi = spi; | |
7d5230ea | 1006 | mutex_init(&flash->lock); |
975aefc9 | 1007 | spi_set_drvdata(spi, flash); |
2f9f7628 | 1008 | |
72289824 | 1009 | /* |
f80e521c | 1010 | * Atmel, SST and Intel/Numonyx serial flash tend to power |
ea60658a | 1011 | * up with the software protection bits set |
72289824 MH |
1012 | */ |
1013 | ||
aa084653 KC |
1014 | if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL || |
1015 | JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL || | |
1016 | JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) { | |
72289824 MH |
1017 | write_enable(flash); |
1018 | write_sr(flash, 0); | |
1019 | } | |
1020 | ||
fa0a8c71 | 1021 | if (data && data->name) |
2f9f7628 ML |
1022 | flash->mtd.name = data->name; |
1023 | else | |
160bbab3 | 1024 | flash->mtd.name = dev_name(&spi->dev); |
2f9f7628 ML |
1025 | |
1026 | flash->mtd.type = MTD_NORFLASH; | |
783ed81f | 1027 | flash->mtd.writesize = 1; |
2f9f7628 ML |
1028 | flash->mtd.flags = MTD_CAP_NORFLASH; |
1029 | flash->mtd.size = info->sector_size * info->n_sectors; | |
3c3c10bb AB |
1030 | flash->mtd._erase = m25p80_erase; |
1031 | flash->mtd._read = m25p80_read; | |
49aac4ae | 1032 | |
972e1b7b AB |
1033 | /* flash protection support for STmicro chips */ |
1034 | if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) { | |
1035 | flash->mtd._lock = m25p80_lock; | |
1036 | flash->mtd._unlock = m25p80_unlock; | |
1037 | } | |
1038 | ||
49aac4ae | 1039 | /* sst flash chips use AAI word program */ |
e534ee4f | 1040 | if (info->flags & SST_WRITE) |
3c3c10bb | 1041 | flash->mtd._write = sst_write; |
49aac4ae | 1042 | else |
3c3c10bb | 1043 | flash->mtd._write = m25p80_write; |
2f9f7628 | 1044 | |
fa0a8c71 DB |
1045 | /* prefer "small sector" erase if possible */ |
1046 | if (info->flags & SECT_4K) { | |
1047 | flash->erase_opcode = OPCODE_BE_4K; | |
1048 | flash->mtd.erasesize = 4096; | |
6c3b8897 MS |
1049 | } else if (info->flags & SECT_4K_PMC) { |
1050 | flash->erase_opcode = OPCODE_BE_4K_PMC; | |
1051 | flash->mtd.erasesize = 4096; | |
fa0a8c71 DB |
1052 | } else { |
1053 | flash->erase_opcode = OPCODE_SE; | |
1054 | flash->mtd.erasesize = info->sector_size; | |
1055 | } | |
1056 | ||
837479d2 AV |
1057 | if (info->flags & M25P_NO_ERASE) |
1058 | flash->mtd.flags |= MTD_NO_ERASE; | |
1059 | ||
ea6a4729 | 1060 | ppdata.of_node = spi->dev.of_node; |
87f39f04 | 1061 | flash->mtd.dev.parent = &spi->dev; |
837479d2 | 1062 | flash->page_size = info->page_size; |
b54f47c8 | 1063 | flash->mtd.writebufsize = flash->page_size; |
4b7f7422 | 1064 | |
12ad2be9 | 1065 | flash->fast_read = false; |
12ad2be9 MV |
1066 | if (np && of_property_read_bool(np, "m25p,fast-read")) |
1067 | flash->fast_read = true; | |
12ad2be9 MV |
1068 | |
1069 | #ifdef CONFIG_M25PXX_USE_FAST_READ | |
1070 | flash->fast_read = true; | |
1071 | #endif | |
58146992 SH |
1072 | if (info->flags & M25P_NO_FR) |
1073 | flash->fast_read = false; | |
12ad2be9 | 1074 | |
87c9511f BN |
1075 | /* Default commands */ |
1076 | if (flash->fast_read) | |
1077 | flash->read_opcode = OPCODE_FAST_READ; | |
1078 | else | |
1079 | flash->read_opcode = OPCODE_NORM_READ; | |
1080 | ||
1081 | flash->program_opcode = OPCODE_PP; | |
1082 | ||
4b7f7422 KC |
1083 | if (info->addr_width) |
1084 | flash->addr_width = info->addr_width; | |
87c9511f | 1085 | else if (flash->mtd.size > 0x1000000) { |
4b7f7422 | 1086 | /* enable 4-byte addressing if the device exceeds 16MiB */ |
87c9511f BN |
1087 | flash->addr_width = 4; |
1088 | if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) { | |
1089 | /* Dedicated 4-byte command set */ | |
1090 | flash->read_opcode = flash->fast_read ? | |
1091 | OPCODE_FAST_READ_4B : | |
1092 | OPCODE_NORM_READ_4B; | |
1093 | flash->program_opcode = OPCODE_PP_4B; | |
1094 | /* No small sector erase for 4-byte command set */ | |
1095 | flash->erase_opcode = OPCODE_SE_4B; | |
1096 | flash->mtd.erasesize = info->sector_size; | |
4b7f7422 | 1097 | } else |
87c9511f BN |
1098 | set_4byte(flash, info->jedec_id, 1); |
1099 | } else { | |
1100 | flash->addr_width = 3; | |
4b7f7422 | 1101 | } |
87f39f04 | 1102 | |
b34bc037 | 1103 | dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name, |
d85316ac | 1104 | (long long)flash->mtd.size >> 10); |
2f9f7628 | 1105 | |
289c0522 | 1106 | pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) " |
02d087db | 1107 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", |
2f9f7628 | 1108 | flash->mtd.name, |
d85316ac | 1109 | (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20), |
2f9f7628 ML |
1110 | flash->mtd.erasesize, flash->mtd.erasesize / 1024, |
1111 | flash->mtd.numeraseregions); | |
1112 | ||
1113 | if (flash->mtd.numeraseregions) | |
1114 | for (i = 0; i < flash->mtd.numeraseregions; i++) | |
289c0522 | 1115 | pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, " |
02d087db | 1116 | ".erasesize = 0x%.8x (%uKiB), " |
2f9f7628 | 1117 | ".numblocks = %d }\n", |
d85316ac | 1118 | i, (long long)flash->mtd.eraseregions[i].offset, |
2f9f7628 ML |
1119 | flash->mtd.eraseregions[i].erasesize, |
1120 | flash->mtd.eraseregions[i].erasesize / 1024, | |
1121 | flash->mtd.eraseregions[i].numblocks); | |
1122 | ||
1123 | ||
1124 | /* partitions should match sector boundaries; and it may be good to | |
1125 | * use readonly partitions for writeprotected sectors (BP2..BP0). | |
1126 | */ | |
871770b5 DES |
1127 | return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, |
1128 | data ? data->parts : NULL, | |
1129 | data ? data->nr_parts : 0); | |
2f9f7628 ML |
1130 | } |
1131 | ||
1132 | ||
810b7e06 | 1133 | static int m25p_remove(struct spi_device *spi) |
2f9f7628 | 1134 | { |
975aefc9 | 1135 | struct m25p *flash = spi_get_drvdata(spi); |
2f9f7628 ML |
1136 | int status; |
1137 | ||
1138 | /* Clean up MTD stuff. */ | |
ba52f3a2 | 1139 | status = mtd_device_unregister(&flash->mtd); |
61c3506c JS |
1140 | if (status == 0) { |
1141 | kfree(flash->command); | |
2f9f7628 | 1142 | kfree(flash); |
61c3506c | 1143 | } |
2f9f7628 ML |
1144 | return 0; |
1145 | } | |
1146 | ||
1147 | ||
1148 | static struct spi_driver m25p80_driver = { | |
1149 | .driver = { | |
1150 | .name = "m25p80", | |
2f9f7628 ML |
1151 | .owner = THIS_MODULE, |
1152 | }, | |
b34bc037 | 1153 | .id_table = m25p_ids, |
2f9f7628 | 1154 | .probe = m25p_probe, |
5153b88c | 1155 | .remove = m25p_remove, |
fa0a8c71 DB |
1156 | |
1157 | /* REVISIT: many of these chips have deep power-down modes, which | |
1158 | * should clearly be entered on suspend() to minimize power use. | |
1159 | * And also when they're otherwise idle... | |
1160 | */ | |
2f9f7628 ML |
1161 | }; |
1162 | ||
c9d1b752 | 1163 | module_spi_driver(m25p80_driver); |
2f9f7628 ML |
1164 | |
1165 | MODULE_LICENSE("GPL"); | |
1166 | MODULE_AUTHOR("Mike Lavender"); | |
1167 | MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips"); |